2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2013, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
51 /* un-comment DEBUG to enable pr_debug() statements */
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/tick.h>
59 #include <trace/events/power.h>
60 #include <linux/sched.h>
61 #include <linux/notifier.h>
62 #include <linux/cpu.h>
63 #include <linux/moduleparam.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/intel-family.h>
66 #include <asm/mwait.h>
69 #define INTEL_IDLE_VERSION "0.4.1"
71 static struct cpuidle_driver intel_idle_driver = {
75 /* intel_idle.max_cstate=0 disables driver */
76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
78 static unsigned int mwait_substates;
80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
82 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
85 struct cpuidle_state *state_table;
88 * Hardware C-state auto-demotion may not always be optimal.
89 * Indicate which enable bits to clear here.
91 unsigned long auto_demotion_disable_flags;
92 bool byt_auto_demotion_disable_flag;
93 bool disable_promotion_to_c1e;
96 static const struct idle_cpu *icpu;
97 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
98 static int intel_idle(struct cpuidle_device *dev,
99 struct cpuidle_driver *drv, int index);
100 static void intel_idle_s2idle(struct cpuidle_device *dev,
101 struct cpuidle_driver *drv, int index);
102 static struct cpuidle_state *cpuidle_state_table;
105 * Set this flag for states where the HW flushes the TLB for us
106 * and so we don't need cross-calls to keep it consistent.
107 * If this flag is set, SW flushes the TLB, so even if the
108 * HW doesn't do the flushing, this flag is safe to use.
110 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
113 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
114 * the C-state (top nibble) and sub-state (bottom nibble)
115 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
117 * We store the hint at the top of our "flags" for each state.
119 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
120 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
123 * States are indexed by the cstate number,
124 * which is also the index into the MWAIT hint array.
125 * Thus C0 is a dummy.
127 static struct cpuidle_state nehalem_cstates[] = {
130 .desc = "MWAIT 0x00",
131 .flags = MWAIT2flg(0x00),
133 .target_residency = 6,
134 .enter = &intel_idle,
135 .enter_s2idle = intel_idle_s2idle, },
138 .desc = "MWAIT 0x01",
139 .flags = MWAIT2flg(0x01),
141 .target_residency = 20,
142 .enter = &intel_idle,
143 .enter_s2idle = intel_idle_s2idle, },
146 .desc = "MWAIT 0x10",
147 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
149 .target_residency = 80,
150 .enter = &intel_idle,
151 .enter_s2idle = intel_idle_s2idle, },
154 .desc = "MWAIT 0x20",
155 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
157 .target_residency = 800,
158 .enter = &intel_idle,
159 .enter_s2idle = intel_idle_s2idle, },
164 static struct cpuidle_state snb_cstates[] = {
167 .desc = "MWAIT 0x00",
168 .flags = MWAIT2flg(0x00),
170 .target_residency = 2,
171 .enter = &intel_idle,
172 .enter_s2idle = intel_idle_s2idle, },
175 .desc = "MWAIT 0x01",
176 .flags = MWAIT2flg(0x01),
178 .target_residency = 20,
179 .enter = &intel_idle,
180 .enter_s2idle = intel_idle_s2idle, },
183 .desc = "MWAIT 0x10",
184 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
186 .target_residency = 211,
187 .enter = &intel_idle,
188 .enter_s2idle = intel_idle_s2idle, },
191 .desc = "MWAIT 0x20",
192 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
194 .target_residency = 345,
195 .enter = &intel_idle,
196 .enter_s2idle = intel_idle_s2idle, },
199 .desc = "MWAIT 0x30",
200 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
202 .target_residency = 345,
203 .enter = &intel_idle,
204 .enter_s2idle = intel_idle_s2idle, },
209 static struct cpuidle_state byt_cstates[] = {
212 .desc = "MWAIT 0x00",
213 .flags = MWAIT2flg(0x00),
215 .target_residency = 1,
216 .enter = &intel_idle,
217 .enter_s2idle = intel_idle_s2idle, },
220 .desc = "MWAIT 0x58",
221 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
223 .target_residency = 275,
224 .enter = &intel_idle,
225 .enter_s2idle = intel_idle_s2idle, },
228 .desc = "MWAIT 0x52",
229 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
231 .target_residency = 560,
232 .enter = &intel_idle,
233 .enter_s2idle = intel_idle_s2idle, },
236 .desc = "MWAIT 0x60",
237 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
238 .exit_latency = 1200,
239 .target_residency = 4000,
240 .enter = &intel_idle,
241 .enter_s2idle = intel_idle_s2idle, },
244 .desc = "MWAIT 0x64",
245 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
246 .exit_latency = 10000,
247 .target_residency = 20000,
248 .enter = &intel_idle,
249 .enter_s2idle = intel_idle_s2idle, },
254 static struct cpuidle_state cht_cstates[] = {
257 .desc = "MWAIT 0x00",
258 .flags = MWAIT2flg(0x00),
260 .target_residency = 1,
261 .enter = &intel_idle,
262 .enter_s2idle = intel_idle_s2idle, },
265 .desc = "MWAIT 0x58",
266 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
268 .target_residency = 275,
269 .enter = &intel_idle,
270 .enter_s2idle = intel_idle_s2idle, },
273 .desc = "MWAIT 0x52",
274 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
276 .target_residency = 560,
277 .enter = &intel_idle,
278 .enter_s2idle = intel_idle_s2idle, },
281 .desc = "MWAIT 0x60",
282 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
283 .exit_latency = 1200,
284 .target_residency = 4000,
285 .enter = &intel_idle,
286 .enter_s2idle = intel_idle_s2idle, },
289 .desc = "MWAIT 0x64",
290 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
291 .exit_latency = 10000,
292 .target_residency = 20000,
293 .enter = &intel_idle,
294 .enter_s2idle = intel_idle_s2idle, },
299 static struct cpuidle_state ivb_cstates[] = {
302 .desc = "MWAIT 0x00",
303 .flags = MWAIT2flg(0x00),
305 .target_residency = 1,
306 .enter = &intel_idle,
307 .enter_s2idle = intel_idle_s2idle, },
310 .desc = "MWAIT 0x01",
311 .flags = MWAIT2flg(0x01),
313 .target_residency = 20,
314 .enter = &intel_idle,
315 .enter_s2idle = intel_idle_s2idle, },
318 .desc = "MWAIT 0x10",
319 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
321 .target_residency = 156,
322 .enter = &intel_idle,
323 .enter_s2idle = intel_idle_s2idle, },
326 .desc = "MWAIT 0x20",
327 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
329 .target_residency = 300,
330 .enter = &intel_idle,
331 .enter_s2idle = intel_idle_s2idle, },
334 .desc = "MWAIT 0x30",
335 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
337 .target_residency = 300,
338 .enter = &intel_idle,
339 .enter_s2idle = intel_idle_s2idle, },
344 static struct cpuidle_state ivt_cstates[] = {
347 .desc = "MWAIT 0x00",
348 .flags = MWAIT2flg(0x00),
350 .target_residency = 1,
351 .enter = &intel_idle,
352 .enter_s2idle = intel_idle_s2idle, },
355 .desc = "MWAIT 0x01",
356 .flags = MWAIT2flg(0x01),
358 .target_residency = 80,
359 .enter = &intel_idle,
360 .enter_s2idle = intel_idle_s2idle, },
363 .desc = "MWAIT 0x10",
364 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
366 .target_residency = 156,
367 .enter = &intel_idle,
368 .enter_s2idle = intel_idle_s2idle, },
371 .desc = "MWAIT 0x20",
372 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
374 .target_residency = 300,
375 .enter = &intel_idle,
376 .enter_s2idle = intel_idle_s2idle, },
381 static struct cpuidle_state ivt_cstates_4s[] = {
384 .desc = "MWAIT 0x00",
385 .flags = MWAIT2flg(0x00),
387 .target_residency = 1,
388 .enter = &intel_idle,
389 .enter_s2idle = intel_idle_s2idle, },
392 .desc = "MWAIT 0x01",
393 .flags = MWAIT2flg(0x01),
395 .target_residency = 250,
396 .enter = &intel_idle,
397 .enter_s2idle = intel_idle_s2idle, },
400 .desc = "MWAIT 0x10",
401 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
403 .target_residency = 300,
404 .enter = &intel_idle,
405 .enter_s2idle = intel_idle_s2idle, },
408 .desc = "MWAIT 0x20",
409 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
411 .target_residency = 400,
412 .enter = &intel_idle,
413 .enter_s2idle = intel_idle_s2idle, },
418 static struct cpuidle_state ivt_cstates_8s[] = {
421 .desc = "MWAIT 0x00",
422 .flags = MWAIT2flg(0x00),
424 .target_residency = 1,
425 .enter = &intel_idle,
426 .enter_s2idle = intel_idle_s2idle, },
429 .desc = "MWAIT 0x01",
430 .flags = MWAIT2flg(0x01),
432 .target_residency = 500,
433 .enter = &intel_idle,
434 .enter_s2idle = intel_idle_s2idle, },
437 .desc = "MWAIT 0x10",
438 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
440 .target_residency = 600,
441 .enter = &intel_idle,
442 .enter_s2idle = intel_idle_s2idle, },
445 .desc = "MWAIT 0x20",
446 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
448 .target_residency = 700,
449 .enter = &intel_idle,
450 .enter_s2idle = intel_idle_s2idle, },
455 static struct cpuidle_state hsw_cstates[] = {
458 .desc = "MWAIT 0x00",
459 .flags = MWAIT2flg(0x00),
461 .target_residency = 2,
462 .enter = &intel_idle,
463 .enter_s2idle = intel_idle_s2idle, },
466 .desc = "MWAIT 0x01",
467 .flags = MWAIT2flg(0x01),
469 .target_residency = 20,
470 .enter = &intel_idle,
471 .enter_s2idle = intel_idle_s2idle, },
474 .desc = "MWAIT 0x10",
475 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
477 .target_residency = 100,
478 .enter = &intel_idle,
479 .enter_s2idle = intel_idle_s2idle, },
482 .desc = "MWAIT 0x20",
483 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
485 .target_residency = 400,
486 .enter = &intel_idle,
487 .enter_s2idle = intel_idle_s2idle, },
490 .desc = "MWAIT 0x32",
491 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
493 .target_residency = 500,
494 .enter = &intel_idle,
495 .enter_s2idle = intel_idle_s2idle, },
498 .desc = "MWAIT 0x40",
499 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
501 .target_residency = 900,
502 .enter = &intel_idle,
503 .enter_s2idle = intel_idle_s2idle, },
506 .desc = "MWAIT 0x50",
507 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
509 .target_residency = 1800,
510 .enter = &intel_idle,
511 .enter_s2idle = intel_idle_s2idle, },
514 .desc = "MWAIT 0x60",
515 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
516 .exit_latency = 2600,
517 .target_residency = 7700,
518 .enter = &intel_idle,
519 .enter_s2idle = intel_idle_s2idle, },
523 static struct cpuidle_state bdw_cstates[] = {
526 .desc = "MWAIT 0x00",
527 .flags = MWAIT2flg(0x00),
529 .target_residency = 2,
530 .enter = &intel_idle,
531 .enter_s2idle = intel_idle_s2idle, },
534 .desc = "MWAIT 0x01",
535 .flags = MWAIT2flg(0x01),
537 .target_residency = 20,
538 .enter = &intel_idle,
539 .enter_s2idle = intel_idle_s2idle, },
542 .desc = "MWAIT 0x10",
543 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
545 .target_residency = 100,
546 .enter = &intel_idle,
547 .enter_s2idle = intel_idle_s2idle, },
550 .desc = "MWAIT 0x20",
551 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
553 .target_residency = 400,
554 .enter = &intel_idle,
555 .enter_s2idle = intel_idle_s2idle, },
558 .desc = "MWAIT 0x32",
559 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
561 .target_residency = 500,
562 .enter = &intel_idle,
563 .enter_s2idle = intel_idle_s2idle, },
566 .desc = "MWAIT 0x40",
567 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
569 .target_residency = 900,
570 .enter = &intel_idle,
571 .enter_s2idle = intel_idle_s2idle, },
574 .desc = "MWAIT 0x50",
575 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
577 .target_residency = 1800,
578 .enter = &intel_idle,
579 .enter_s2idle = intel_idle_s2idle, },
582 .desc = "MWAIT 0x60",
583 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
584 .exit_latency = 2600,
585 .target_residency = 7700,
586 .enter = &intel_idle,
587 .enter_s2idle = intel_idle_s2idle, },
592 static struct cpuidle_state skl_cstates[] = {
595 .desc = "MWAIT 0x00",
596 .flags = MWAIT2flg(0x00),
598 .target_residency = 2,
599 .enter = &intel_idle,
600 .enter_s2idle = intel_idle_s2idle, },
603 .desc = "MWAIT 0x01",
604 .flags = MWAIT2flg(0x01),
606 .target_residency = 20,
607 .enter = &intel_idle,
608 .enter_s2idle = intel_idle_s2idle, },
611 .desc = "MWAIT 0x10",
612 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
614 .target_residency = 100,
615 .enter = &intel_idle,
616 .enter_s2idle = intel_idle_s2idle, },
619 .desc = "MWAIT 0x20",
620 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
622 .target_residency = 200,
623 .enter = &intel_idle,
624 .enter_s2idle = intel_idle_s2idle, },
627 .desc = "MWAIT 0x33",
628 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
630 .target_residency = 800,
631 .enter = &intel_idle,
632 .enter_s2idle = intel_idle_s2idle, },
635 .desc = "MWAIT 0x40",
636 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
638 .target_residency = 800,
639 .enter = &intel_idle,
640 .enter_s2idle = intel_idle_s2idle, },
643 .desc = "MWAIT 0x50",
644 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
646 .target_residency = 5000,
647 .enter = &intel_idle,
648 .enter_s2idle = intel_idle_s2idle, },
651 .desc = "MWAIT 0x60",
652 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
654 .target_residency = 5000,
655 .enter = &intel_idle,
656 .enter_s2idle = intel_idle_s2idle, },
661 static struct cpuidle_state skx_cstates[] = {
664 .desc = "MWAIT 0x00",
665 .flags = MWAIT2flg(0x00),
667 .target_residency = 2,
668 .enter = &intel_idle,
669 .enter_s2idle = intel_idle_s2idle, },
672 .desc = "MWAIT 0x01",
673 .flags = MWAIT2flg(0x01),
675 .target_residency = 20,
676 .enter = &intel_idle,
677 .enter_s2idle = intel_idle_s2idle, },
680 .desc = "MWAIT 0x20",
681 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
683 .target_residency = 600,
684 .enter = &intel_idle,
685 .enter_s2idle = intel_idle_s2idle, },
690 static struct cpuidle_state atom_cstates[] = {
693 .desc = "MWAIT 0x00",
694 .flags = MWAIT2flg(0x00),
696 .target_residency = 20,
697 .enter = &intel_idle,
698 .enter_s2idle = intel_idle_s2idle, },
701 .desc = "MWAIT 0x10",
702 .flags = MWAIT2flg(0x10),
704 .target_residency = 80,
705 .enter = &intel_idle,
706 .enter_s2idle = intel_idle_s2idle, },
709 .desc = "MWAIT 0x30",
710 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
712 .target_residency = 400,
713 .enter = &intel_idle,
714 .enter_s2idle = intel_idle_s2idle, },
717 .desc = "MWAIT 0x52",
718 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
720 .target_residency = 560,
721 .enter = &intel_idle,
722 .enter_s2idle = intel_idle_s2idle, },
726 static struct cpuidle_state tangier_cstates[] = {
729 .desc = "MWAIT 0x00",
730 .flags = MWAIT2flg(0x00),
732 .target_residency = 4,
733 .enter = &intel_idle,
734 .enter_s2idle = intel_idle_s2idle, },
737 .desc = "MWAIT 0x30",
738 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
740 .target_residency = 400,
741 .enter = &intel_idle,
742 .enter_s2idle = intel_idle_s2idle, },
745 .desc = "MWAIT 0x52",
746 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
748 .target_residency = 560,
749 .enter = &intel_idle,
750 .enter_s2idle = intel_idle_s2idle, },
753 .desc = "MWAIT 0x60",
754 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
755 .exit_latency = 1200,
756 .target_residency = 4000,
757 .enter = &intel_idle,
758 .enter_s2idle = intel_idle_s2idle, },
761 .desc = "MWAIT 0x64",
762 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
763 .exit_latency = 10000,
764 .target_residency = 20000,
765 .enter = &intel_idle,
766 .enter_s2idle = intel_idle_s2idle, },
770 static struct cpuidle_state avn_cstates[] = {
773 .desc = "MWAIT 0x00",
774 .flags = MWAIT2flg(0x00),
776 .target_residency = 2,
777 .enter = &intel_idle,
778 .enter_s2idle = intel_idle_s2idle, },
781 .desc = "MWAIT 0x51",
782 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
784 .target_residency = 45,
785 .enter = &intel_idle,
786 .enter_s2idle = intel_idle_s2idle, },
790 static struct cpuidle_state knl_cstates[] = {
793 .desc = "MWAIT 0x00",
794 .flags = MWAIT2flg(0x00),
796 .target_residency = 2,
797 .enter = &intel_idle,
798 .enter_s2idle = intel_idle_s2idle },
801 .desc = "MWAIT 0x10",
802 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
804 .target_residency = 500,
805 .enter = &intel_idle,
806 .enter_s2idle = intel_idle_s2idle },
811 static struct cpuidle_state bxt_cstates[] = {
814 .desc = "MWAIT 0x00",
815 .flags = MWAIT2flg(0x00),
817 .target_residency = 2,
818 .enter = &intel_idle,
819 .enter_s2idle = intel_idle_s2idle, },
822 .desc = "MWAIT 0x01",
823 .flags = MWAIT2flg(0x01),
825 .target_residency = 20,
826 .enter = &intel_idle,
827 .enter_s2idle = intel_idle_s2idle, },
830 .desc = "MWAIT 0x20",
831 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
833 .target_residency = 133,
834 .enter = &intel_idle,
835 .enter_s2idle = intel_idle_s2idle, },
838 .desc = "MWAIT 0x31",
839 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
841 .target_residency = 155,
842 .enter = &intel_idle,
843 .enter_s2idle = intel_idle_s2idle, },
846 .desc = "MWAIT 0x40",
847 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
848 .exit_latency = 1000,
849 .target_residency = 1000,
850 .enter = &intel_idle,
851 .enter_s2idle = intel_idle_s2idle, },
854 .desc = "MWAIT 0x50",
855 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
856 .exit_latency = 2000,
857 .target_residency = 2000,
858 .enter = &intel_idle,
859 .enter_s2idle = intel_idle_s2idle, },
862 .desc = "MWAIT 0x60",
863 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
864 .exit_latency = 10000,
865 .target_residency = 10000,
866 .enter = &intel_idle,
867 .enter_s2idle = intel_idle_s2idle, },
872 static struct cpuidle_state dnv_cstates[] = {
875 .desc = "MWAIT 0x00",
876 .flags = MWAIT2flg(0x00),
878 .target_residency = 2,
879 .enter = &intel_idle,
880 .enter_s2idle = intel_idle_s2idle, },
883 .desc = "MWAIT 0x01",
884 .flags = MWAIT2flg(0x01),
886 .target_residency = 20,
887 .enter = &intel_idle,
888 .enter_s2idle = intel_idle_s2idle, },
891 .desc = "MWAIT 0x20",
892 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
894 .target_residency = 500,
895 .enter = &intel_idle,
896 .enter_s2idle = intel_idle_s2idle, },
903 * @dev: cpuidle_device
904 * @drv: cpuidle driver
905 * @index: index of cpuidle state
907 * Must be called under local_irq_disable().
909 static __cpuidle int intel_idle(struct cpuidle_device *dev,
910 struct cpuidle_driver *drv, int index)
912 unsigned long ecx = 1; /* break on interrupt flag */
913 struct cpuidle_state *state = &drv->states[index];
914 unsigned long eax = flg2MWAIT(state->flags);
917 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
920 * NB: if CPUIDLE_FLAG_TLB_FLUSHED is set, this idle transition
921 * will probably flush the TLB. It's not guaranteed to flush
922 * the TLB, though, so it's not clear that we can do anything
923 * useful with this knowledge.
926 if (!(lapic_timer_reliable_states & (1 << (cstate))))
927 tick_broadcast_enter();
929 mwait_idle_with_hints(eax, ecx);
931 if (!(lapic_timer_reliable_states & (1 << (cstate))))
932 tick_broadcast_exit();
938 * intel_idle_s2idle - simplified "enter" callback routine for suspend-to-idle
939 * @dev: cpuidle_device
940 * @drv: cpuidle driver
941 * @index: state index
943 static void intel_idle_s2idle(struct cpuidle_device *dev,
944 struct cpuidle_driver *drv, int index)
946 unsigned long ecx = 1; /* break on interrupt flag */
947 unsigned long eax = flg2MWAIT(drv->states[index].flags);
949 mwait_idle_with_hints(eax, ecx);
952 static void __setup_broadcast_timer(bool on)
955 tick_broadcast_enable();
957 tick_broadcast_disable();
960 static void auto_demotion_disable(void)
962 unsigned long long msr_bits;
964 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
965 msr_bits &= ~(icpu->auto_demotion_disable_flags);
966 wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
968 static void c1e_promotion_disable(void)
970 unsigned long long msr_bits;
972 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
974 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
977 static const struct idle_cpu idle_cpu_nehalem = {
978 .state_table = nehalem_cstates,
979 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
980 .disable_promotion_to_c1e = true,
983 static const struct idle_cpu idle_cpu_atom = {
984 .state_table = atom_cstates,
987 static const struct idle_cpu idle_cpu_tangier = {
988 .state_table = tangier_cstates,
991 static const struct idle_cpu idle_cpu_lincroft = {
992 .state_table = atom_cstates,
993 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
996 static const struct idle_cpu idle_cpu_snb = {
997 .state_table = snb_cstates,
998 .disable_promotion_to_c1e = true,
1001 static const struct idle_cpu idle_cpu_byt = {
1002 .state_table = byt_cstates,
1003 .disable_promotion_to_c1e = true,
1004 .byt_auto_demotion_disable_flag = true,
1007 static const struct idle_cpu idle_cpu_cht = {
1008 .state_table = cht_cstates,
1009 .disable_promotion_to_c1e = true,
1010 .byt_auto_demotion_disable_flag = true,
1013 static const struct idle_cpu idle_cpu_ivb = {
1014 .state_table = ivb_cstates,
1015 .disable_promotion_to_c1e = true,
1018 static const struct idle_cpu idle_cpu_ivt = {
1019 .state_table = ivt_cstates,
1020 .disable_promotion_to_c1e = true,
1023 static const struct idle_cpu idle_cpu_hsw = {
1024 .state_table = hsw_cstates,
1025 .disable_promotion_to_c1e = true,
1028 static const struct idle_cpu idle_cpu_bdw = {
1029 .state_table = bdw_cstates,
1030 .disable_promotion_to_c1e = true,
1033 static const struct idle_cpu idle_cpu_skl = {
1034 .state_table = skl_cstates,
1035 .disable_promotion_to_c1e = true,
1038 static const struct idle_cpu idle_cpu_skx = {
1039 .state_table = skx_cstates,
1040 .disable_promotion_to_c1e = true,
1043 static const struct idle_cpu idle_cpu_avn = {
1044 .state_table = avn_cstates,
1045 .disable_promotion_to_c1e = true,
1048 static const struct idle_cpu idle_cpu_knl = {
1049 .state_table = knl_cstates,
1052 static const struct idle_cpu idle_cpu_bxt = {
1053 .state_table = bxt_cstates,
1054 .disable_promotion_to_c1e = true,
1057 static const struct idle_cpu idle_cpu_dnv = {
1058 .state_table = dnv_cstates,
1059 .disable_promotion_to_c1e = true,
1062 #define ICPU(model, cpu) \
1063 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
1065 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1066 ICPU(INTEL_FAM6_NEHALEM_EP, idle_cpu_nehalem),
1067 ICPU(INTEL_FAM6_NEHALEM, idle_cpu_nehalem),
1068 ICPU(INTEL_FAM6_NEHALEM_G, idle_cpu_nehalem),
1069 ICPU(INTEL_FAM6_WESTMERE, idle_cpu_nehalem),
1070 ICPU(INTEL_FAM6_WESTMERE_EP, idle_cpu_nehalem),
1071 ICPU(INTEL_FAM6_NEHALEM_EX, idle_cpu_nehalem),
1072 ICPU(INTEL_FAM6_ATOM_PINEVIEW, idle_cpu_atom),
1073 ICPU(INTEL_FAM6_ATOM_LINCROFT, idle_cpu_lincroft),
1074 ICPU(INTEL_FAM6_WESTMERE_EX, idle_cpu_nehalem),
1075 ICPU(INTEL_FAM6_SANDYBRIDGE, idle_cpu_snb),
1076 ICPU(INTEL_FAM6_SANDYBRIDGE_X, idle_cpu_snb),
1077 ICPU(INTEL_FAM6_ATOM_CEDARVIEW, idle_cpu_atom),
1078 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, idle_cpu_byt),
1079 ICPU(INTEL_FAM6_ATOM_MERRIFIELD, idle_cpu_tangier),
1080 ICPU(INTEL_FAM6_ATOM_AIRMONT, idle_cpu_cht),
1081 ICPU(INTEL_FAM6_IVYBRIDGE, idle_cpu_ivb),
1082 ICPU(INTEL_FAM6_IVYBRIDGE_X, idle_cpu_ivt),
1083 ICPU(INTEL_FAM6_HASWELL_CORE, idle_cpu_hsw),
1084 ICPU(INTEL_FAM6_HASWELL_X, idle_cpu_hsw),
1085 ICPU(INTEL_FAM6_HASWELL_ULT, idle_cpu_hsw),
1086 ICPU(INTEL_FAM6_HASWELL_GT3E, idle_cpu_hsw),
1087 ICPU(INTEL_FAM6_ATOM_SILVERMONT2, idle_cpu_avn),
1088 ICPU(INTEL_FAM6_BROADWELL_CORE, idle_cpu_bdw),
1089 ICPU(INTEL_FAM6_BROADWELL_GT3E, idle_cpu_bdw),
1090 ICPU(INTEL_FAM6_BROADWELL_X, idle_cpu_bdw),
1091 ICPU(INTEL_FAM6_BROADWELL_XEON_D, idle_cpu_bdw),
1092 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, idle_cpu_skl),
1093 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, idle_cpu_skl),
1094 ICPU(INTEL_FAM6_KABYLAKE_MOBILE, idle_cpu_skl),
1095 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, idle_cpu_skl),
1096 ICPU(INTEL_FAM6_SKYLAKE_X, idle_cpu_skx),
1097 ICPU(INTEL_FAM6_XEON_PHI_KNL, idle_cpu_knl),
1098 ICPU(INTEL_FAM6_XEON_PHI_KNM, idle_cpu_knl),
1099 ICPU(INTEL_FAM6_ATOM_GOLDMONT, idle_cpu_bxt),
1100 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, idle_cpu_bxt),
1101 ICPU(INTEL_FAM6_ATOM_DENVERTON, idle_cpu_dnv),
1106 * intel_idle_probe()
1108 static int __init intel_idle_probe(void)
1110 unsigned int eax, ebx, ecx;
1111 const struct x86_cpu_id *id;
1113 if (max_cstate == 0) {
1114 pr_debug("disabled\n");
1118 id = x86_match_cpu(intel_idle_ids);
1120 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
1121 boot_cpu_data.x86 == 6)
1122 pr_debug("does not run on family %d model %d\n",
1123 boot_cpu_data.x86, boot_cpu_data.x86_model);
1127 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1130 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1132 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1133 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1137 pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1139 icpu = (const struct idle_cpu *)id->driver_data;
1140 cpuidle_state_table = icpu->state_table;
1142 pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1143 boot_cpu_data.x86_model);
1149 * intel_idle_cpuidle_devices_uninit()
1150 * Unregisters the cpuidle devices.
1152 static void intel_idle_cpuidle_devices_uninit(void)
1155 struct cpuidle_device *dev;
1157 for_each_online_cpu(i) {
1158 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
1159 cpuidle_unregister_device(dev);
1164 * ivt_idle_state_table_update(void)
1166 * Tune IVT multi-socket targets
1167 * Assumption: num_sockets == (max_package_num + 1)
1169 static void ivt_idle_state_table_update(void)
1171 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1172 int cpu, package_num, num_sockets = 1;
1174 for_each_online_cpu(cpu) {
1175 package_num = topology_physical_package_id(cpu);
1176 if (package_num + 1 > num_sockets) {
1177 num_sockets = package_num + 1;
1179 if (num_sockets > 4) {
1180 cpuidle_state_table = ivt_cstates_8s;
1186 if (num_sockets > 2)
1187 cpuidle_state_table = ivt_cstates_4s;
1189 /* else, 1 and 2 socket systems use default ivt_cstates */
1193 * Translate IRTL (Interrupt Response Time Limit) MSR to usec
1196 static unsigned int irtl_ns_units[] = {
1197 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1199 static unsigned long long irtl_2_usec(unsigned long long irtl)
1201 unsigned long long ns;
1206 ns = irtl_ns_units[(irtl >> 10) & 0x7];
1208 return div64_u64((irtl & 0x3FF) * ns, 1000);
1211 * bxt_idle_state_table_update(void)
1213 * On BXT, we trust the IRTL to show the definitive maximum latency
1214 * We use the same value for target_residency.
1216 static void bxt_idle_state_table_update(void)
1218 unsigned long long msr;
1221 rdmsrl(MSR_PKGC6_IRTL, msr);
1222 usec = irtl_2_usec(msr);
1224 bxt_cstates[2].exit_latency = usec;
1225 bxt_cstates[2].target_residency = usec;
1228 rdmsrl(MSR_PKGC7_IRTL, msr);
1229 usec = irtl_2_usec(msr);
1231 bxt_cstates[3].exit_latency = usec;
1232 bxt_cstates[3].target_residency = usec;
1235 rdmsrl(MSR_PKGC8_IRTL, msr);
1236 usec = irtl_2_usec(msr);
1238 bxt_cstates[4].exit_latency = usec;
1239 bxt_cstates[4].target_residency = usec;
1242 rdmsrl(MSR_PKGC9_IRTL, msr);
1243 usec = irtl_2_usec(msr);
1245 bxt_cstates[5].exit_latency = usec;
1246 bxt_cstates[5].target_residency = usec;
1249 rdmsrl(MSR_PKGC10_IRTL, msr);
1250 usec = irtl_2_usec(msr);
1252 bxt_cstates[6].exit_latency = usec;
1253 bxt_cstates[6].target_residency = usec;
1258 * sklh_idle_state_table_update(void)
1260 * On SKL-H (model 0x5e) disable C8 and C9 if:
1261 * C10 is enabled and SGX disabled
1263 static void sklh_idle_state_table_update(void)
1265 unsigned long long msr;
1266 unsigned int eax, ebx, ecx, edx;
1269 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1270 if (max_cstate <= 7)
1273 /* if PC10 not present in CPUID.MWAIT.EDX */
1274 if ((mwait_substates & (0xF << 28)) == 0)
1277 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1279 /* PC10 is not enabled in PKG C-state limit */
1280 if ((msr & 0xF) != 8)
1284 cpuid(7, &eax, &ebx, &ecx, &edx);
1286 /* if SGX is present */
1287 if (ebx & (1 << 2)) {
1289 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1291 /* if SGX is enabled */
1292 if (msr & (1 << 18))
1296 skl_cstates[5].disabled = 1; /* C8-SKL */
1297 skl_cstates[6].disabled = 1; /* C9-SKL */
1300 * intel_idle_state_table_update()
1302 * Update the default state_table for this CPU-id
1305 static void intel_idle_state_table_update(void)
1307 switch (boot_cpu_data.x86_model) {
1309 case INTEL_FAM6_IVYBRIDGE_X:
1310 ivt_idle_state_table_update();
1312 case INTEL_FAM6_ATOM_GOLDMONT:
1313 case INTEL_FAM6_ATOM_GEMINI_LAKE:
1314 bxt_idle_state_table_update();
1316 case INTEL_FAM6_SKYLAKE_DESKTOP:
1317 sklh_idle_state_table_update();
1323 * intel_idle_cpuidle_driver_init()
1324 * allocate, initialize cpuidle_states
1326 static void __init intel_idle_cpuidle_driver_init(void)
1329 struct cpuidle_driver *drv = &intel_idle_driver;
1331 intel_idle_state_table_update();
1333 cpuidle_poll_state_init(drv);
1334 drv->state_count = 1;
1336 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1337 int num_substates, mwait_hint, mwait_cstate;
1339 if ((cpuidle_state_table[cstate].enter == NULL) &&
1340 (cpuidle_state_table[cstate].enter_s2idle == NULL))
1343 if (cstate + 1 > max_cstate) {
1344 pr_info("max_cstate %d reached\n", max_cstate);
1348 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1349 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
1351 /* number of sub-states for this state in CPUID.MWAIT */
1352 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
1353 & MWAIT_SUBSTATE_MASK;
1355 /* if NO sub-states for this state in CPUID, skip it */
1356 if (num_substates == 0)
1359 /* if state marked as disabled, skip it */
1360 if (cpuidle_state_table[cstate].disabled != 0) {
1361 pr_debug("state %s is disabled\n",
1362 cpuidle_state_table[cstate].name);
1367 if (((mwait_cstate + 1) > 2) &&
1368 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1369 mark_tsc_unstable("TSC halts in idle"
1370 " states deeper than C2");
1372 drv->states[drv->state_count] = /* structure copy */
1373 cpuidle_state_table[cstate];
1375 drv->state_count += 1;
1378 if (icpu->byt_auto_demotion_disable_flag) {
1379 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1380 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1386 * intel_idle_cpu_init()
1387 * allocate, initialize, register cpuidle_devices
1388 * @cpu: cpu/core to initialize
1390 static int intel_idle_cpu_init(unsigned int cpu)
1392 struct cpuidle_device *dev;
1394 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1397 if (cpuidle_register_device(dev)) {
1398 pr_debug("cpuidle_register_device %d failed!\n", cpu);
1402 if (icpu->auto_demotion_disable_flags)
1403 auto_demotion_disable();
1405 if (icpu->disable_promotion_to_c1e)
1406 c1e_promotion_disable();
1411 static int intel_idle_cpu_online(unsigned int cpu)
1413 struct cpuidle_device *dev;
1415 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
1416 __setup_broadcast_timer(true);
1419 * Some systems can hotplug a cpu at runtime after
1420 * the kernel has booted, we have to initialize the
1421 * driver in this case
1423 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1424 if (!dev->registered)
1425 return intel_idle_cpu_init(cpu);
1430 static int __init intel_idle_init(void)
1434 /* Do not load intel_idle at all for now if idle= is passed */
1435 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1438 retval = intel_idle_probe();
1442 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1443 if (intel_idle_cpuidle_devices == NULL)
1446 intel_idle_cpuidle_driver_init();
1447 retval = cpuidle_register_driver(&intel_idle_driver);
1449 struct cpuidle_driver *drv = cpuidle_get_driver();
1450 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1451 drv ? drv->name : "none");
1452 goto init_driver_fail;
1455 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
1456 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
1458 retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1459 intel_idle_cpu_online, NULL);
1463 pr_debug("lapic_timer_reliable_states 0x%x\n",
1464 lapic_timer_reliable_states);
1469 intel_idle_cpuidle_devices_uninit();
1470 cpuidle_unregister_driver(&intel_idle_driver);
1472 free_percpu(intel_idle_cpuidle_devices);
1476 device_initcall(intel_idle_init);
1479 * We are not really modular, but we used to support that. Meaning we also
1480 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1481 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1482 * is the easiest way (currently) to continue doing that.
1484 module_param(max_cstate, int, 0444);