1 // SPDX-License-Identifier: GPL-2.0
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
14 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
18 * TODO: orientation events
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
36 #define MMA8452_STATUS 0x00
37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38 #define MMA8452_OUT_X 0x01 /* MSB first */
39 #define MMA8452_OUT_Y 0x03
40 #define MMA8452_OUT_Z 0x05
41 #define MMA8452_INT_SRC 0x0c
42 #define MMA8452_WHO_AM_I 0x0d
43 #define MMA8452_DATA_CFG 0x0e
44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45 #define MMA8452_DATA_CFG_FS_2G 0
46 #define MMA8452_DATA_CFG_FS_4G 1
47 #define MMA8452_DATA_CFG_FS_8G 2
48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49 #define MMA8452_HP_FILTER_CUTOFF 0x0f
50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51 #define MMA8452_FF_MT_CFG 0x15
52 #define MMA8452_FF_MT_CFG_OAE BIT(6)
53 #define MMA8452_FF_MT_CFG_ELE BIT(7)
54 #define MMA8452_FF_MT_SRC 0x16
55 #define MMA8452_FF_MT_SRC_XHE BIT(1)
56 #define MMA8452_FF_MT_SRC_YHE BIT(3)
57 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
58 #define MMA8452_FF_MT_THS 0x17
59 #define MMA8452_FF_MT_THS_MASK 0x7f
60 #define MMA8452_FF_MT_COUNT 0x18
61 #define MMA8452_FF_MT_CHAN_SHIFT 3
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
66 #define MMA8452_TRANSIENT_SRC 0x1e
67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
70 #define MMA8452_TRANSIENT_THS 0x1f
71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
72 #define MMA8452_TRANSIENT_COUNT 0x20
73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
74 #define MMA8452_CTRL_REG1 0x2a
75 #define MMA8452_CTRL_ACTIVE BIT(0)
76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
77 #define MMA8452_CTRL_DR_SHIFT 3
78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
79 #define MMA8452_CTRL_REG2 0x2b
80 #define MMA8452_CTRL_REG2_RST BIT(6)
81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
83 #define MMA8452_CTRL_REG4 0x2d
84 #define MMA8452_CTRL_REG5 0x2e
85 #define MMA8452_OFF_X 0x2f
86 #define MMA8452_OFF_Y 0x30
87 #define MMA8452_OFF_Z 0x31
89 #define MMA8452_MAX_REG 0x31
91 #define MMA8452_INT_DRDY BIT(0)
92 #define MMA8452_INT_FF_MT BIT(2)
93 #define MMA8452_INT_TRANS BIT(5)
95 #define MMA8451_DEVICE_ID 0x1a
96 #define MMA8452_DEVICE_ID 0x2a
97 #define MMA8453_DEVICE_ID 0x3a
98 #define MMA8652_DEVICE_ID 0x4a
99 #define MMA8653_DEVICE_ID 0x5a
100 #define FXLS8471_DEVICE_ID 0x6a
102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
104 struct mma8452_data {
105 struct i2c_client *client;
109 const struct mma_chip_info *chip_info;
111 struct regulator *vdd_reg;
112 struct regulator *vddio_reg;
116 * struct mma8452_event_regs - chip specific data related to events
117 * @ev_cfg: event config register address
118 * @ev_cfg_ele: latch bit in event config register
119 * @ev_cfg_chan_shift: number of the bit to enable events in X
120 * direction; in event config register
121 * @ev_src: event source register address
122 * @ev_ths: event threshold register address
123 * @ev_ths_mask: mask for the threshold value
124 * @ev_count: event count (period) register address
126 * Since not all chips supported by the driver support comparing high pass
127 * filtered data for events (interrupts), different interrupt sources are
128 * used for different chips and the relevant registers are included here.
130 struct mma8452_event_regs {
133 u8 ev_cfg_chan_shift;
140 static const struct mma8452_event_regs ff_mt_ev_regs = {
141 .ev_cfg = MMA8452_FF_MT_CFG,
142 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
143 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
144 .ev_src = MMA8452_FF_MT_SRC,
145 .ev_ths = MMA8452_FF_MT_THS,
146 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
147 .ev_count = MMA8452_FF_MT_COUNT
150 static const struct mma8452_event_regs trans_ev_regs = {
151 .ev_cfg = MMA8452_TRANSIENT_CFG,
152 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
153 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
154 .ev_src = MMA8452_TRANSIENT_SRC,
155 .ev_ths = MMA8452_TRANSIENT_THS,
156 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
157 .ev_count = MMA8452_TRANSIENT_COUNT,
161 * struct mma_chip_info - chip specific data
162 * @chip_id: WHO_AM_I register's value
163 * @channels: struct iio_chan_spec matching the device's
165 * @num_channels: number of channels
166 * @mma_scales: scale factors for converting register values
167 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
168 * per mode: m/s^2 and micro m/s^2
169 * @all_events: all events supported by this chip
170 * @enabled_events: event flags enabled and handled by this driver
172 struct mma_chip_info {
174 const struct iio_chan_spec *channels;
176 const int mma_scales[3][2];
188 static int mma8452_drdy(struct mma8452_data *data)
192 while (tries-- > 0) {
193 int ret = i2c_smbus_read_byte_data(data->client,
197 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
200 if (data->sleep_val <= 20)
201 usleep_range(data->sleep_val * 250,
202 data->sleep_val * 500);
207 dev_err(&data->client->dev, "data not ready\n");
212 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
218 ret = pm_runtime_get_sync(&client->dev);
220 pm_runtime_mark_last_busy(&client->dev);
221 ret = pm_runtime_put_autosuspend(&client->dev);
225 dev_err(&client->dev,
226 "failed to change power state to %d\n", on);
228 pm_runtime_put_noidle(&client->dev);
237 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
239 int ret = mma8452_drdy(data);
244 ret = mma8452_set_runtime_pm_state(data->client, true);
248 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
249 3 * sizeof(__be16), (u8 *)buf);
251 ret = mma8452_set_runtime_pm_state(data->client, false);
256 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
262 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
263 vals[n][0], vals[n][1]);
265 /* replace trailing space by newline */
271 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
275 if (val == vals[n][0] && val2 == vals[n][1])
281 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
283 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
284 MMA8452_CTRL_DR_SHIFT;
287 static const int mma8452_samp_freq[8][2] = {
288 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
289 {6, 250000}, {1, 560000}
292 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
293 static const unsigned int mma8452_time_step_us[4][8] = {
294 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
295 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
296 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
297 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
300 /* Datasheet table "High-Pass Filter Cutoff Options" */
301 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
303 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
304 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
305 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
306 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
307 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
308 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
309 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
310 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
312 { /* low noise low power */
313 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
314 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
315 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
316 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
317 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
318 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
319 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
320 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
322 { /* high resolution */
323 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
324 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
325 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
326 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
327 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
328 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
335 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
336 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
337 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
338 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
339 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
340 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
344 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
345 static const u16 mma8452_os_ratio[4][8] = {
346 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
347 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
348 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
349 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
350 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
353 static int mma8452_get_power_mode(struct mma8452_data *data)
357 reg = i2c_smbus_read_byte_data(data->client,
362 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
363 MMA8452_CTRL_REG2_MODS_SHIFT);
366 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
367 struct device_attribute *attr,
370 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
371 ARRAY_SIZE(mma8452_samp_freq));
374 static ssize_t mma8452_show_scale_avail(struct device *dev,
375 struct device_attribute *attr,
378 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
379 to_i2c_client(dev)));
381 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
382 ARRAY_SIZE(data->chip_info->mma_scales));
385 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
386 struct device_attribute *attr,
389 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
390 struct mma8452_data *data = iio_priv(indio_dev);
393 i = mma8452_get_odr_index(data);
394 j = mma8452_get_power_mode(data);
398 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
399 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
402 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
403 struct device_attribute *attr,
406 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
407 struct mma8452_data *data = iio_priv(indio_dev);
408 int i = mma8452_get_odr_index(data);
413 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
414 if (val == mma8452_os_ratio[j][i])
417 val = mma8452_os_ratio[j][i];
419 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
426 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
427 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
428 mma8452_show_scale_avail, NULL, 0);
429 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
430 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
431 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
432 mma8452_show_os_ratio_avail, NULL, 0);
434 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
437 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
438 ARRAY_SIZE(mma8452_samp_freq),
442 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
444 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
445 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
448 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
453 i = mma8452_get_odr_index(data);
454 j = mma8452_get_power_mode(data);
458 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
459 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
462 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
466 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
470 i = mma8452_get_odr_index(data);
471 j = mma8452_get_power_mode(data);
475 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
476 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
477 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
482 static int mma8452_read_raw(struct iio_dev *indio_dev,
483 struct iio_chan_spec const *chan,
484 int *val, int *val2, long mask)
486 struct mma8452_data *data = iio_priv(indio_dev);
491 case IIO_CHAN_INFO_RAW:
492 ret = iio_device_claim_direct_mode(indio_dev);
496 mutex_lock(&data->lock);
497 ret = mma8452_read(data, buffer);
498 mutex_unlock(&data->lock);
499 iio_device_release_direct_mode(indio_dev);
503 *val = sign_extend32(be16_to_cpu(
504 buffer[chan->scan_index]) >> chan->scan_type.shift,
505 chan->scan_type.realbits - 1);
508 case IIO_CHAN_INFO_SCALE:
509 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
510 *val = data->chip_info->mma_scales[i][0];
511 *val2 = data->chip_info->mma_scales[i][1];
513 return IIO_VAL_INT_PLUS_MICRO;
514 case IIO_CHAN_INFO_SAMP_FREQ:
515 i = mma8452_get_odr_index(data);
516 *val = mma8452_samp_freq[i][0];
517 *val2 = mma8452_samp_freq[i][1];
519 return IIO_VAL_INT_PLUS_MICRO;
520 case IIO_CHAN_INFO_CALIBBIAS:
521 ret = i2c_smbus_read_byte_data(data->client,
527 *val = sign_extend32(ret, 7);
530 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
531 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
532 ret = mma8452_read_hp_filter(data, val, val2);
540 return IIO_VAL_INT_PLUS_MICRO;
541 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
542 ret = mma8452_get_power_mode(data);
546 i = mma8452_get_odr_index(data);
548 *val = mma8452_os_ratio[ret][i];
555 static int mma8452_calculate_sleep(struct mma8452_data *data)
557 int ret, i = mma8452_get_odr_index(data);
559 if (mma8452_samp_freq[i][0] > 0)
560 ret = 1000 / mma8452_samp_freq[i][0];
564 return ret == 0 ? 1 : ret;
567 static int mma8452_standby(struct mma8452_data *data)
569 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
570 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
573 static int mma8452_active(struct mma8452_data *data)
575 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
579 /* returns >0 if active, 0 if in standby and <0 on error */
580 static int mma8452_is_active(struct mma8452_data *data)
584 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
588 return reg & MMA8452_CTRL_ACTIVE;
591 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
596 mutex_lock(&data->lock);
598 is_active = mma8452_is_active(data);
604 /* config can only be changed when in standby */
606 ret = mma8452_standby(data);
611 ret = i2c_smbus_write_byte_data(data->client, reg, val);
616 ret = mma8452_active(data);
623 mutex_unlock(&data->lock);
628 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
632 reg = i2c_smbus_read_byte_data(data->client,
637 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
638 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
640 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
643 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
644 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
648 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
652 return !(val & MMA8452_FF_MT_CFG_OAE);
655 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
659 if ((state && mma8452_freefall_mode_enabled(data)) ||
660 (!state && !(mma8452_freefall_mode_enabled(data))))
663 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
668 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
669 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
670 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
671 val &= ~MMA8452_FF_MT_CFG_OAE;
673 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
674 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
675 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
676 val |= MMA8452_FF_MT_CFG_OAE;
679 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
682 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
687 i = mma8452_get_hp_filter_index(data, val, val2);
691 reg = i2c_smbus_read_byte_data(data->client,
692 MMA8452_HP_FILTER_CUTOFF);
696 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
699 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
702 static int mma8452_write_raw(struct iio_dev *indio_dev,
703 struct iio_chan_spec const *chan,
704 int val, int val2, long mask)
706 struct mma8452_data *data = iio_priv(indio_dev);
709 ret = iio_device_claim_direct_mode(indio_dev);
714 case IIO_CHAN_INFO_SAMP_FREQ:
715 i = mma8452_get_samp_freq_index(data, val, val2);
720 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
721 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
723 data->sleep_val = mma8452_calculate_sleep(data);
725 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
728 case IIO_CHAN_INFO_SCALE:
729 i = mma8452_get_scale_index(data, val, val2);
735 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
738 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
741 case IIO_CHAN_INFO_CALIBBIAS:
742 if (val < -128 || val > 127) {
747 ret = mma8452_change_config(data,
748 MMA8452_OFF_X + chan->scan_index,
752 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
753 if (val == 0 && val2 == 0) {
754 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
756 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
757 ret = mma8452_set_hp_filter_frequency(data, val, val2);
762 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
766 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
767 ret = mma8452_get_odr_index(data);
769 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
770 if (mma8452_os_ratio[i][ret] == val) {
771 ret = mma8452_set_power_mode(data, i);
781 iio_device_release_direct_mode(indio_dev);
785 static int mma8452_get_event_regs(struct mma8452_data *data,
786 const struct iio_chan_spec *chan, enum iio_event_direction dir,
787 const struct mma8452_event_regs **ev_reg)
792 switch (chan->type) {
795 case IIO_EV_DIR_RISING:
796 if ((data->chip_info->all_events
797 & MMA8452_INT_TRANS) &&
798 (data->chip_info->enabled_events
799 & MMA8452_INT_TRANS))
800 *ev_reg = &trans_ev_regs;
802 *ev_reg = &ff_mt_ev_regs;
804 case IIO_EV_DIR_FALLING:
805 *ev_reg = &ff_mt_ev_regs;
815 static int mma8452_read_event_value(struct iio_dev *indio_dev,
816 const struct iio_chan_spec *chan,
817 enum iio_event_type type,
818 enum iio_event_direction dir,
819 enum iio_event_info info,
822 struct mma8452_data *data = iio_priv(indio_dev);
823 int ret, us, power_mode;
824 const struct mma8452_event_regs *ev_regs;
826 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
831 case IIO_EV_INFO_VALUE:
832 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
836 *val = ret & ev_regs->ev_ths_mask;
840 case IIO_EV_INFO_PERIOD:
841 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
845 power_mode = mma8452_get_power_mode(data);
849 us = ret * mma8452_time_step_us[power_mode][
850 mma8452_get_odr_index(data)];
851 *val = us / USEC_PER_SEC;
852 *val2 = us % USEC_PER_SEC;
854 return IIO_VAL_INT_PLUS_MICRO;
856 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
857 ret = i2c_smbus_read_byte_data(data->client,
858 MMA8452_TRANSIENT_CFG);
862 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
866 ret = mma8452_read_hp_filter(data, val, val2);
871 return IIO_VAL_INT_PLUS_MICRO;
878 static int mma8452_write_event_value(struct iio_dev *indio_dev,
879 const struct iio_chan_spec *chan,
880 enum iio_event_type type,
881 enum iio_event_direction dir,
882 enum iio_event_info info,
885 struct mma8452_data *data = iio_priv(indio_dev);
887 const struct mma8452_event_regs *ev_regs;
889 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
894 case IIO_EV_INFO_VALUE:
895 if (val < 0 || val > ev_regs->ev_ths_mask)
898 return mma8452_change_config(data, ev_regs->ev_ths, val);
900 case IIO_EV_INFO_PERIOD:
901 ret = mma8452_get_power_mode(data);
905 steps = (val * USEC_PER_SEC + val2) /
906 mma8452_time_step_us[ret][
907 mma8452_get_odr_index(data)];
909 if (steps < 0 || steps > 0xff)
912 return mma8452_change_config(data, ev_regs->ev_count, steps);
914 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
915 reg = i2c_smbus_read_byte_data(data->client,
916 MMA8452_TRANSIENT_CFG);
920 if (val == 0 && val2 == 0) {
921 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
923 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
924 ret = mma8452_set_hp_filter_frequency(data, val, val2);
929 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
936 static int mma8452_read_event_config(struct iio_dev *indio_dev,
937 const struct iio_chan_spec *chan,
938 enum iio_event_type type,
939 enum iio_event_direction dir)
941 struct mma8452_data *data = iio_priv(indio_dev);
943 const struct mma8452_event_regs *ev_regs;
945 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
950 case IIO_EV_DIR_FALLING:
951 return mma8452_freefall_mode_enabled(data);
952 case IIO_EV_DIR_RISING:
953 ret = i2c_smbus_read_byte_data(data->client,
958 return !!(ret & BIT(chan->scan_index +
959 ev_regs->ev_cfg_chan_shift));
965 static int mma8452_write_event_config(struct iio_dev *indio_dev,
966 const struct iio_chan_spec *chan,
967 enum iio_event_type type,
968 enum iio_event_direction dir,
971 struct mma8452_data *data = iio_priv(indio_dev);
973 const struct mma8452_event_regs *ev_regs;
975 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
979 ret = mma8452_set_runtime_pm_state(data->client, state);
984 case IIO_EV_DIR_FALLING:
985 return mma8452_set_freefall_mode(data, state);
986 case IIO_EV_DIR_RISING:
987 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
992 if (mma8452_freefall_mode_enabled(data)) {
993 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
994 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
995 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
996 val |= MMA8452_FF_MT_CFG_OAE;
998 val |= BIT(chan->scan_index +
999 ev_regs->ev_cfg_chan_shift);
1001 if (mma8452_freefall_mode_enabled(data))
1004 val &= ~BIT(chan->scan_index +
1005 ev_regs->ev_cfg_chan_shift);
1008 val |= ev_regs->ev_cfg_ele;
1010 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1016 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1018 struct mma8452_data *data = iio_priv(indio_dev);
1019 s64 ts = iio_get_time_ns(indio_dev);
1022 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1026 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1027 iio_push_event(indio_dev,
1028 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1033 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1034 iio_push_event(indio_dev,
1035 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1040 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1041 iio_push_event(indio_dev,
1042 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1048 static irqreturn_t mma8452_interrupt(int irq, void *p)
1050 struct iio_dev *indio_dev = p;
1051 struct mma8452_data *data = iio_priv(indio_dev);
1055 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1059 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1062 if (src & MMA8452_INT_DRDY) {
1063 iio_trigger_poll_chained(indio_dev->trig);
1067 if (src & MMA8452_INT_FF_MT) {
1068 if (mma8452_freefall_mode_enabled(data)) {
1069 s64 ts = iio_get_time_ns(indio_dev);
1071 iio_push_event(indio_dev,
1072 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1073 IIO_MOD_X_AND_Y_AND_Z,
1075 IIO_EV_DIR_FALLING),
1081 if (src & MMA8452_INT_TRANS) {
1082 mma8452_transient_interrupt(indio_dev);
1089 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1091 struct iio_poll_func *pf = p;
1092 struct iio_dev *indio_dev = pf->indio_dev;
1093 struct mma8452_data *data = iio_priv(indio_dev);
1094 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
1097 ret = mma8452_read(data, (__be16 *)buffer);
1101 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1102 iio_get_time_ns(indio_dev));
1105 iio_trigger_notify_done(indio_dev->trig);
1110 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1111 unsigned int reg, unsigned int writeval,
1112 unsigned int *readval)
1115 struct mma8452_data *data = iio_priv(indio_dev);
1117 if (reg > MMA8452_MAX_REG)
1121 return mma8452_change_config(data, reg, writeval);
1123 ret = i2c_smbus_read_byte_data(data->client, reg);
1132 static const struct iio_event_spec mma8452_freefall_event[] = {
1134 .type = IIO_EV_TYPE_MAG,
1135 .dir = IIO_EV_DIR_FALLING,
1136 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1137 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1138 BIT(IIO_EV_INFO_PERIOD) |
1139 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1143 static const struct iio_event_spec mma8652_freefall_event[] = {
1145 .type = IIO_EV_TYPE_MAG,
1146 .dir = IIO_EV_DIR_FALLING,
1147 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1148 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1149 BIT(IIO_EV_INFO_PERIOD)
1153 static const struct iio_event_spec mma8452_transient_event[] = {
1155 .type = IIO_EV_TYPE_MAG,
1156 .dir = IIO_EV_DIR_RISING,
1157 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1158 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1159 BIT(IIO_EV_INFO_PERIOD) |
1160 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1164 static const struct iio_event_spec mma8452_motion_event[] = {
1166 .type = IIO_EV_TYPE_MAG,
1167 .dir = IIO_EV_DIR_RISING,
1168 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1169 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1170 BIT(IIO_EV_INFO_PERIOD)
1175 * Threshold is configured in fixed 8G/127 steps regardless of
1176 * currently selected scale for measurement.
1178 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1180 static struct attribute *mma8452_event_attributes[] = {
1181 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1185 static struct attribute_group mma8452_event_attribute_group = {
1186 .attrs = mma8452_event_attributes,
1189 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1190 .type = IIO_ACCEL, \
1192 .channel2 = modifier, \
1194 .event_spec = mma8452_freefall_event, \
1195 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1198 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1199 .type = IIO_ACCEL, \
1201 .channel2 = modifier, \
1203 .event_spec = mma8652_freefall_event, \
1204 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1207 #define MMA8452_CHANNEL(axis, idx, bits) { \
1208 .type = IIO_ACCEL, \
1210 .channel2 = IIO_MOD_##axis, \
1211 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1212 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1213 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1214 BIT(IIO_CHAN_INFO_SCALE) | \
1215 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1216 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1217 .scan_index = idx, \
1220 .realbits = (bits), \
1221 .storagebits = 16, \
1222 .shift = 16 - (bits), \
1223 .endianness = IIO_BE, \
1225 .event_spec = mma8452_transient_event, \
1226 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1229 #define MMA8652_CHANNEL(axis, idx, bits) { \
1230 .type = IIO_ACCEL, \
1232 .channel2 = IIO_MOD_##axis, \
1233 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1234 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1235 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1236 BIT(IIO_CHAN_INFO_SCALE) | \
1237 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1238 .scan_index = idx, \
1241 .realbits = (bits), \
1242 .storagebits = 16, \
1243 .shift = 16 - (bits), \
1244 .endianness = IIO_BE, \
1246 .event_spec = mma8452_motion_event, \
1247 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1250 static const struct iio_chan_spec mma8451_channels[] = {
1251 MMA8452_CHANNEL(X, idx_x, 14),
1252 MMA8452_CHANNEL(Y, idx_y, 14),
1253 MMA8452_CHANNEL(Z, idx_z, 14),
1254 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1255 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1258 static const struct iio_chan_spec mma8452_channels[] = {
1259 MMA8452_CHANNEL(X, idx_x, 12),
1260 MMA8452_CHANNEL(Y, idx_y, 12),
1261 MMA8452_CHANNEL(Z, idx_z, 12),
1262 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1263 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1266 static const struct iio_chan_spec mma8453_channels[] = {
1267 MMA8452_CHANNEL(X, idx_x, 10),
1268 MMA8452_CHANNEL(Y, idx_y, 10),
1269 MMA8452_CHANNEL(Z, idx_z, 10),
1270 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1271 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1274 static const struct iio_chan_spec mma8652_channels[] = {
1275 MMA8652_CHANNEL(X, idx_x, 12),
1276 MMA8652_CHANNEL(Y, idx_y, 12),
1277 MMA8652_CHANNEL(Z, idx_z, 12),
1278 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1279 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1282 static const struct iio_chan_spec mma8653_channels[] = {
1283 MMA8652_CHANNEL(X, idx_x, 10),
1284 MMA8652_CHANNEL(Y, idx_y, 10),
1285 MMA8652_CHANNEL(Z, idx_z, 10),
1286 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1287 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1299 static const struct mma_chip_info mma_chip_info_table[] = {
1301 .chip_id = MMA8451_DEVICE_ID,
1302 .channels = mma8451_channels,
1303 .num_channels = ARRAY_SIZE(mma8451_channels),
1305 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1306 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1308 * The userspace interface uses m/s^2 and we declare micro units
1309 * So scale factor for 12 bit here is given by:
1310 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1312 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1314 * Although we enable the interrupt sources once and for
1315 * all here the event detection itself is not enabled until
1316 * userspace asks for it by mma8452_write_event_config()
1318 .all_events = MMA8452_INT_DRDY |
1321 .enabled_events = MMA8452_INT_TRANS |
1325 .chip_id = MMA8452_DEVICE_ID,
1326 .channels = mma8452_channels,
1327 .num_channels = ARRAY_SIZE(mma8452_channels),
1328 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1330 * Although we enable the interrupt sources once and for
1331 * all here the event detection itself is not enabled until
1332 * userspace asks for it by mma8452_write_event_config()
1334 .all_events = MMA8452_INT_DRDY |
1337 .enabled_events = MMA8452_INT_TRANS |
1341 .chip_id = MMA8453_DEVICE_ID,
1342 .channels = mma8453_channels,
1343 .num_channels = ARRAY_SIZE(mma8453_channels),
1344 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1346 * Although we enable the interrupt sources once and for
1347 * all here the event detection itself is not enabled until
1348 * userspace asks for it by mma8452_write_event_config()
1350 .all_events = MMA8452_INT_DRDY |
1353 .enabled_events = MMA8452_INT_TRANS |
1357 .chip_id = MMA8652_DEVICE_ID,
1358 .channels = mma8652_channels,
1359 .num_channels = ARRAY_SIZE(mma8652_channels),
1360 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1361 .all_events = MMA8452_INT_DRDY |
1363 .enabled_events = MMA8452_INT_FF_MT,
1366 .chip_id = MMA8653_DEVICE_ID,
1367 .channels = mma8653_channels,
1368 .num_channels = ARRAY_SIZE(mma8653_channels),
1369 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1371 * Although we enable the interrupt sources once and for
1372 * all here the event detection itself is not enabled until
1373 * userspace asks for it by mma8452_write_event_config()
1375 .all_events = MMA8452_INT_DRDY |
1377 .enabled_events = MMA8452_INT_FF_MT,
1380 .chip_id = FXLS8471_DEVICE_ID,
1381 .channels = mma8451_channels,
1382 .num_channels = ARRAY_SIZE(mma8451_channels),
1383 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1385 * Although we enable the interrupt sources once and for
1386 * all here the event detection itself is not enabled until
1387 * userspace asks for it by mma8452_write_event_config()
1389 .all_events = MMA8452_INT_DRDY |
1392 .enabled_events = MMA8452_INT_TRANS |
1397 static struct attribute *mma8452_attributes[] = {
1398 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1399 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1400 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1401 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1405 static const struct attribute_group mma8452_group = {
1406 .attrs = mma8452_attributes,
1409 static const struct iio_info mma8452_info = {
1410 .attrs = &mma8452_group,
1411 .read_raw = &mma8452_read_raw,
1412 .write_raw = &mma8452_write_raw,
1413 .event_attrs = &mma8452_event_attribute_group,
1414 .read_event_value = &mma8452_read_event_value,
1415 .write_event_value = &mma8452_write_event_value,
1416 .read_event_config = &mma8452_read_event_config,
1417 .write_event_config = &mma8452_write_event_config,
1418 .debugfs_reg_access = &mma8452_reg_access_dbg,
1421 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1423 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1426 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1427 struct mma8452_data *data = iio_priv(indio_dev);
1430 ret = mma8452_set_runtime_pm_state(data->client, state);
1434 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1439 reg |= MMA8452_INT_DRDY;
1441 reg &= ~MMA8452_INT_DRDY;
1443 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1446 static const struct iio_trigger_ops mma8452_trigger_ops = {
1447 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1448 .validate_device = iio_trigger_validate_own_device,
1451 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1453 struct mma8452_data *data = iio_priv(indio_dev);
1454 struct iio_trigger *trig;
1457 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1463 trig->dev.parent = &data->client->dev;
1464 trig->ops = &mma8452_trigger_ops;
1465 iio_trigger_set_drvdata(trig, indio_dev);
1467 ret = iio_trigger_register(trig);
1471 indio_dev->trig = trig;
1476 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1478 if (indio_dev->trig)
1479 iio_trigger_unregister(indio_dev->trig);
1482 static int mma8452_reset(struct i2c_client *client)
1487 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1488 MMA8452_CTRL_REG2_RST);
1492 for (i = 0; i < 10; i++) {
1493 usleep_range(100, 200);
1494 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1496 continue; /* I2C comm reset */
1499 if (!(ret & MMA8452_CTRL_REG2_RST))
1506 static const struct of_device_id mma8452_dt_ids[] = {
1507 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1508 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1509 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1510 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1511 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1512 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1515 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1517 static int mma8452_probe(struct i2c_client *client,
1518 const struct i2c_device_id *id)
1520 struct mma8452_data *data;
1521 struct iio_dev *indio_dev;
1523 const struct of_device_id *match;
1525 match = of_match_device(mma8452_dt_ids, &client->dev);
1527 dev_err(&client->dev, "unknown device model\n");
1531 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1535 data = iio_priv(indio_dev);
1536 data->client = client;
1537 mutex_init(&data->lock);
1538 data->chip_info = match->data;
1540 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1541 if (IS_ERR(data->vdd_reg)) {
1542 if (PTR_ERR(data->vdd_reg) == -EPROBE_DEFER)
1543 return -EPROBE_DEFER;
1545 dev_err(&client->dev, "failed to get VDD regulator!\n");
1546 return PTR_ERR(data->vdd_reg);
1549 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1550 if (IS_ERR(data->vddio_reg)) {
1551 if (PTR_ERR(data->vddio_reg) == -EPROBE_DEFER)
1552 return -EPROBE_DEFER;
1554 dev_err(&client->dev, "failed to get VDDIO regulator!\n");
1555 return PTR_ERR(data->vddio_reg);
1558 ret = regulator_enable(data->vdd_reg);
1560 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1564 ret = regulator_enable(data->vddio_reg);
1566 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1567 goto disable_regulator_vdd;
1570 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1572 goto disable_regulators;
1575 case MMA8451_DEVICE_ID:
1576 case MMA8452_DEVICE_ID:
1577 case MMA8453_DEVICE_ID:
1578 case MMA8652_DEVICE_ID:
1579 case MMA8653_DEVICE_ID:
1580 case FXLS8471_DEVICE_ID:
1581 if (ret == data->chip_info->chip_id)
1586 goto disable_regulators;
1589 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1590 match->compatible, data->chip_info->chip_id);
1592 i2c_set_clientdata(client, indio_dev);
1593 indio_dev->info = &mma8452_info;
1594 indio_dev->name = id->name;
1595 indio_dev->dev.parent = &client->dev;
1596 indio_dev->modes = INDIO_DIRECT_MODE;
1597 indio_dev->channels = data->chip_info->channels;
1598 indio_dev->num_channels = data->chip_info->num_channels;
1599 indio_dev->available_scan_masks = mma8452_scan_masks;
1601 ret = mma8452_reset(client);
1603 goto disable_regulators;
1605 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1606 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1609 goto disable_regulators;
1612 * By default set transient threshold to max to avoid events if
1613 * enabling without configuring threshold.
1615 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1616 MMA8452_TRANSIENT_THS_MASK);
1618 goto disable_regulators;
1623 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1625 if (irq2 == client->irq) {
1626 dev_dbg(&client->dev, "using interrupt line INT2\n");
1628 ret = i2c_smbus_write_byte_data(client,
1630 data->chip_info->all_events);
1632 goto disable_regulators;
1634 dev_dbg(&client->dev, "using interrupt line INT1\n");
1637 ret = i2c_smbus_write_byte_data(client,
1639 data->chip_info->enabled_events);
1641 goto disable_regulators;
1643 ret = mma8452_trigger_setup(indio_dev);
1645 goto disable_regulators;
1648 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1649 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1651 data->sleep_val = mma8452_calculate_sleep(data);
1653 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1656 goto trigger_cleanup;
1658 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1659 mma8452_trigger_handler, NULL);
1661 goto trigger_cleanup;
1664 ret = devm_request_threaded_irq(&client->dev,
1666 NULL, mma8452_interrupt,
1667 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1668 client->name, indio_dev);
1670 goto buffer_cleanup;
1673 ret = pm_runtime_set_active(&client->dev);
1675 goto buffer_cleanup;
1677 pm_runtime_enable(&client->dev);
1678 pm_runtime_set_autosuspend_delay(&client->dev,
1679 MMA8452_AUTO_SUSPEND_DELAY_MS);
1680 pm_runtime_use_autosuspend(&client->dev);
1682 ret = iio_device_register(indio_dev);
1684 goto buffer_cleanup;
1686 ret = mma8452_set_freefall_mode(data, false);
1688 goto buffer_cleanup;
1693 iio_triggered_buffer_cleanup(indio_dev);
1696 mma8452_trigger_cleanup(indio_dev);
1699 regulator_disable(data->vddio_reg);
1701 disable_regulator_vdd:
1702 regulator_disable(data->vdd_reg);
1707 static int mma8452_remove(struct i2c_client *client)
1709 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1710 struct mma8452_data *data = iio_priv(indio_dev);
1712 iio_device_unregister(indio_dev);
1714 pm_runtime_disable(&client->dev);
1715 pm_runtime_set_suspended(&client->dev);
1716 pm_runtime_put_noidle(&client->dev);
1718 iio_triggered_buffer_cleanup(indio_dev);
1719 mma8452_trigger_cleanup(indio_dev);
1720 mma8452_standby(iio_priv(indio_dev));
1722 regulator_disable(data->vddio_reg);
1723 regulator_disable(data->vdd_reg);
1729 static int mma8452_runtime_suspend(struct device *dev)
1731 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1732 struct mma8452_data *data = iio_priv(indio_dev);
1735 mutex_lock(&data->lock);
1736 ret = mma8452_standby(data);
1737 mutex_unlock(&data->lock);
1739 dev_err(&data->client->dev, "powering off device failed\n");
1743 ret = regulator_disable(data->vddio_reg);
1745 dev_err(dev, "failed to disable VDDIO regulator\n");
1749 ret = regulator_disable(data->vdd_reg);
1751 dev_err(dev, "failed to disable VDD regulator\n");
1758 static int mma8452_runtime_resume(struct device *dev)
1760 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1761 struct mma8452_data *data = iio_priv(indio_dev);
1764 ret = regulator_enable(data->vdd_reg);
1766 dev_err(dev, "failed to enable VDD regulator\n");
1770 ret = regulator_enable(data->vddio_reg);
1772 dev_err(dev, "failed to enable VDDIO regulator\n");
1773 regulator_disable(data->vdd_reg);
1777 ret = mma8452_active(data);
1779 goto runtime_resume_failed;
1781 ret = mma8452_get_odr_index(data);
1782 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1784 usleep_range(sleep_val * 1000, 20000);
1786 msleep_interruptible(sleep_val);
1790 runtime_resume_failed:
1791 regulator_disable(data->vddio_reg);
1792 regulator_disable(data->vdd_reg);
1798 static const struct dev_pm_ops mma8452_pm_ops = {
1799 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1800 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1801 mma8452_runtime_resume, NULL)
1804 static const struct i2c_device_id mma8452_id[] = {
1805 { "mma8451", mma8451 },
1806 { "mma8452", mma8452 },
1807 { "mma8453", mma8453 },
1808 { "mma8652", mma8652 },
1809 { "mma8653", mma8653 },
1810 { "fxls8471", fxls8471 },
1813 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1815 static struct i2c_driver mma8452_driver = {
1818 .of_match_table = of_match_ptr(mma8452_dt_ids),
1819 .pm = &mma8452_pm_ops,
1821 .probe = mma8452_probe,
1822 .remove = mma8452_remove,
1823 .id_table = mma8452_id,
1825 module_i2c_driver(mma8452_driver);
1827 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1828 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1829 MODULE_LICENSE("GPL");