1 // SPDX-License-Identifier: GPL-2.0+
3 * AD7124 SPI ADC driver
5 * Copyright 2018 Analog Devices Inc.
7 #include <linux/bitfield.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/spi/spi.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/adc/ad_sigma_delta.h>
20 #include <linux/iio/sysfs.h>
22 /* AD7124 registers */
23 #define AD7124_COMMS 0x00
24 #define AD7124_STATUS 0x00
25 #define AD7124_ADC_CONTROL 0x01
26 #define AD7124_DATA 0x02
27 #define AD7124_IO_CONTROL_1 0x03
28 #define AD7124_IO_CONTROL_2 0x04
29 #define AD7124_ID 0x05
30 #define AD7124_ERROR 0x06
31 #define AD7124_ERROR_EN 0x07
32 #define AD7124_MCLK_COUNT 0x08
33 #define AD7124_CHANNEL(x) (0x09 + (x))
34 #define AD7124_CONFIG(x) (0x19 + (x))
35 #define AD7124_FILTER(x) (0x21 + (x))
36 #define AD7124_OFFSET(x) (0x29 + (x))
37 #define AD7124_GAIN(x) (0x31 + (x))
40 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
42 /* AD7124_ADC_CONTROL */
43 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
44 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
45 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
46 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
47 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
48 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
50 /* AD7124_CHANNEL_X */
51 #define AD7124_CHANNEL_EN_MSK BIT(15)
52 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
53 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
54 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
55 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
56 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
57 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
58 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
61 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
62 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
63 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
64 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
65 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
66 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
67 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(7, 6)
68 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
71 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
72 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
86 enum ad7124_power_mode {
92 static const unsigned int ad7124_gain[8] = {
93 1, 2, 4, 8, 16, 32, 64, 128
96 static const int ad7124_master_clk_freq_hz[3] = {
97 [AD7124_LOW_POWER] = 76800,
98 [AD7124_MID_POWER] = 153600,
99 [AD7124_FULL_POWER] = 614400,
102 static const char * const ad7124_ref_names[] = {
103 [AD7124_REFIN1] = "refin1",
104 [AD7124_REFIN2] = "refin2",
105 [AD7124_INT_REF] = "int",
106 [AD7124_AVDD_REF] = "avdd",
109 struct ad7124_chip_info {
110 unsigned int num_inputs;
113 struct ad7124_channel_config {
114 enum ad7124_ref_sel refsel;
119 unsigned int vref_mv;
120 unsigned int pga_bits;
124 struct ad7124_state {
125 const struct ad7124_chip_info *chip_info;
126 struct ad_sigma_delta sd;
127 struct ad7124_channel_config *channel_config;
128 struct regulator *vref[4];
130 unsigned int adc_control;
131 unsigned int num_channels;
134 static const struct iio_chan_spec ad7124_channel_template = {
138 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
139 BIT(IIO_CHAN_INFO_SCALE) |
140 BIT(IIO_CHAN_INFO_OFFSET) |
141 BIT(IIO_CHAN_INFO_SAMP_FREQ),
147 .endianness = IIO_BE,
151 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
160 static int ad7124_find_closest_match(const int *array,
161 unsigned int size, int val)
164 unsigned int diff_new, diff_old;
169 for (i = 0; i < size; i++) {
170 diff_new = abs(val - array[i]);
171 if (diff_new < diff_old) {
180 static int ad7124_spi_write_mask(struct ad7124_state *st,
186 unsigned int readval;
189 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
196 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
199 static int ad7124_set_mode(struct ad_sigma_delta *sd,
200 enum ad_sigma_delta_mode mode)
202 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
204 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
205 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
207 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
210 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
212 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
215 val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
216 AD7124_CHANNEL_SETUP(channel);
218 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
221 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
222 .set_channel = ad7124_set_channel,
223 .set_mode = ad7124_set_mode,
224 .has_registers = true,
227 .data_reg = AD7124_DATA,
228 .irq_flags = IRQF_TRIGGER_FALLING,
231 static int ad7124_set_channel_odr(struct ad7124_state *st,
232 unsigned int channel,
235 unsigned int fclk, odr_sel_bits;
238 fclk = clk_get_rate(st->mclk);
240 * FS[10:0] = fCLK / (fADC x 32) where:
241 * fADC is the output data rate
242 * fCLK is the master clock frequency
243 * FS[10:0] are the bits in the filter register
244 * FS[10:0] can have a value from 1 to 2047
246 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
247 if (odr_sel_bits < 1)
249 else if (odr_sel_bits > 2047)
252 ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
253 AD7124_FILTER_FS_MSK,
254 AD7124_FILTER_FS(odr_sel_bits), 3);
257 /* fADC = fCLK / (FS[10:0] x 32) */
258 st->channel_config[channel].odr =
259 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
264 static int ad7124_set_channel_gain(struct ad7124_state *st,
265 unsigned int channel,
271 res = ad7124_find_closest_match(ad7124_gain,
272 ARRAY_SIZE(ad7124_gain), gain);
273 ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
274 AD7124_CONFIG_PGA_MSK,
275 AD7124_CONFIG_PGA(res), 2);
279 st->channel_config[channel].pga_bits = res;
284 static int ad7124_read_raw(struct iio_dev *indio_dev,
285 struct iio_chan_spec const *chan,
286 int *val, int *val2, long info)
288 struct ad7124_state *st = iio_priv(indio_dev);
292 case IIO_CHAN_INFO_RAW:
293 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
297 /* After the conversion is performed, disable the channel */
298 ret = ad_sd_write_reg(&st->sd,
299 AD7124_CHANNEL(chan->address), 2,
300 st->channel_config[chan->address].ain |
301 AD7124_CHANNEL_EN(0));
306 case IIO_CHAN_INFO_SCALE:
307 idx = st->channel_config[chan->address].pga_bits;
308 *val = st->channel_config[chan->address].vref_mv;
309 if (st->channel_config[chan->address].bipolar)
310 *val2 = chan->scan_type.realbits - 1 + idx;
312 *val2 = chan->scan_type.realbits + idx;
314 return IIO_VAL_FRACTIONAL_LOG2;
315 case IIO_CHAN_INFO_OFFSET:
316 if (st->channel_config[chan->address].bipolar)
317 *val = -(1 << (chan->scan_type.realbits - 1));
322 case IIO_CHAN_INFO_SAMP_FREQ:
323 *val = st->channel_config[chan->address].odr;
331 static int ad7124_write_raw(struct iio_dev *indio_dev,
332 struct iio_chan_spec const *chan,
333 int val, int val2, long info)
335 struct ad7124_state *st = iio_priv(indio_dev);
336 unsigned int res, gain, full_scale, vref;
339 case IIO_CHAN_INFO_SAMP_FREQ:
343 return ad7124_set_channel_odr(st, chan->address, val);
344 case IIO_CHAN_INFO_SCALE:
348 if (st->channel_config[chan->address].bipolar)
349 full_scale = 1 << (chan->scan_type.realbits - 1);
351 full_scale = 1 << chan->scan_type.realbits;
353 vref = st->channel_config[chan->address].vref_mv * 1000000LL;
354 res = DIV_ROUND_CLOSEST(vref, full_scale);
355 gain = DIV_ROUND_CLOSEST(res, val2);
357 return ad7124_set_channel_gain(st, chan->address, gain);
363 static IIO_CONST_ATTR(in_voltage_scale_available,
364 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
366 static struct attribute *ad7124_attributes[] = {
367 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
371 static const struct attribute_group ad7124_attrs_group = {
372 .attrs = ad7124_attributes,
375 static const struct iio_info ad7124_info = {
376 .read_raw = ad7124_read_raw,
377 .write_raw = ad7124_write_raw,
378 .validate_trigger = ad_sd_validate_trigger,
379 .attrs = &ad7124_attrs_group,
382 static int ad7124_soft_reset(struct ad7124_state *st)
384 unsigned int readval, timeout;
387 ret = ad_sd_reset(&st->sd, 64);
393 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
397 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
400 /* The AD7124 requires typically 2ms to power up and settle */
401 usleep_range(100, 2000);
404 dev_err(&st->sd.spi->dev, "Soft reset failed\n");
409 static int ad7124_init_channel_vref(struct ad7124_state *st,
410 unsigned int channel_number)
412 unsigned int refsel = st->channel_config[channel_number].refsel;
417 case AD7124_AVDD_REF:
418 if (IS_ERR(st->vref[refsel])) {
419 dev_err(&st->sd.spi->dev,
420 "Error, trying to use external voltage reference without a %s regulator.\n",
421 ad7124_ref_names[refsel]);
422 return PTR_ERR(st->vref[refsel]);
424 st->channel_config[channel_number].vref_mv =
425 regulator_get_voltage(st->vref[refsel]);
426 /* Conversion from uV to mV */
427 st->channel_config[channel_number].vref_mv /= 1000;
430 st->channel_config[channel_number].vref_mv = 2500;
431 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
432 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
433 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
436 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
443 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
444 struct device_node *np)
446 struct ad7124_state *st = iio_priv(indio_dev);
447 struct device_node *child;
448 struct iio_chan_spec *chan;
449 struct ad7124_channel_config *chan_config;
450 unsigned int ain[2], channel = 0, tmp;
453 st->num_channels = of_get_available_child_count(np);
454 if (!st->num_channels) {
455 dev_err(indio_dev->dev.parent, "no channel children\n");
459 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
460 sizeof(*chan), GFP_KERNEL);
464 chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
465 sizeof(*chan_config), GFP_KERNEL);
469 indio_dev->channels = chan;
470 indio_dev->num_channels = st->num_channels;
471 st->channel_config = chan_config;
473 for_each_available_child_of_node(np, child) {
474 ret = of_property_read_u32(child, "reg", &channel);
478 ret = of_property_read_u32_array(child, "diff-channels",
483 st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
484 AD7124_CHANNEL_AINM(ain[1]);
485 st->channel_config[channel].bipolar =
486 of_property_read_bool(child, "bipolar");
488 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
490 st->channel_config[channel].refsel = AD7124_INT_REF;
492 st->channel_config[channel].refsel = tmp;
494 st->channel_config[channel].buf_positive =
495 of_property_read_bool(child, "adi,buffered-positive");
496 st->channel_config[channel].buf_negative =
497 of_property_read_bool(child, "adi,buffered-negative");
499 *chan = ad7124_channel_template;
500 chan->address = channel;
501 chan->scan_index = channel;
502 chan->channel = ain[0];
503 chan->channel2 = ain[1];
515 static int ad7124_setup(struct ad7124_state *st)
517 unsigned int val, fclk, power_mode;
520 fclk = clk_get_rate(st->mclk);
524 /* The power mode changes the master clock frequency */
525 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
526 ARRAY_SIZE(ad7124_master_clk_freq_hz),
528 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
529 ret = clk_set_rate(st->mclk, fclk);
534 /* Set the power mode */
535 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
536 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
537 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
541 for (i = 0; i < st->num_channels; i++) {
542 val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
543 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
547 ret = ad7124_init_channel_vref(st, i);
551 tmp = (st->channel_config[i].buf_positive << 1) +
552 st->channel_config[i].buf_negative;
554 val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
555 AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
556 AD7124_CONFIG_IN_BUFF(tmp);
557 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
561 * 9.38 SPS is the minimum output data rate supported
562 * regardless of the selected power mode. Round it up to 10 and
563 * set all the enabled channels to this default value.
565 ret = ad7124_set_channel_odr(st, i, 10);
571 static int ad7124_probe(struct spi_device *spi)
573 const struct spi_device_id *id;
574 struct ad7124_state *st;
575 struct iio_dev *indio_dev;
578 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
582 st = iio_priv(indio_dev);
584 id = spi_get_device_id(spi);
585 st->chip_info = &ad7124_chip_info_tbl[id->driver_data];
587 ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
589 spi_set_drvdata(spi, indio_dev);
591 indio_dev->dev.parent = &spi->dev;
592 indio_dev->name = spi_get_device_id(spi)->name;
593 indio_dev->modes = INDIO_DIRECT_MODE;
594 indio_dev->info = &ad7124_info;
596 ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
600 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
601 if (i == AD7124_INT_REF)
604 st->vref[i] = devm_regulator_get_optional(&spi->dev,
605 ad7124_ref_names[i]);
606 if (PTR_ERR(st->vref[i]) == -ENODEV)
608 else if (IS_ERR(st->vref[i]))
609 return PTR_ERR(st->vref[i]);
611 ret = regulator_enable(st->vref[i]);
616 st->mclk = devm_clk_get(&spi->dev, "mclk");
617 if (IS_ERR(st->mclk)) {
618 ret = PTR_ERR(st->mclk);
619 goto error_regulator_disable;
622 ret = clk_prepare_enable(st->mclk);
624 goto error_regulator_disable;
626 ret = ad7124_soft_reset(st);
628 goto error_clk_disable_unprepare;
630 ret = ad7124_setup(st);
632 goto error_clk_disable_unprepare;
634 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
636 goto error_clk_disable_unprepare;
638 ret = iio_device_register(indio_dev);
640 dev_err(&spi->dev, "Failed to register iio device\n");
641 goto error_remove_trigger;
646 error_remove_trigger:
647 ad_sd_cleanup_buffer_and_trigger(indio_dev);
648 error_clk_disable_unprepare:
649 clk_disable_unprepare(st->mclk);
650 error_regulator_disable:
651 for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
652 if (!IS_ERR_OR_NULL(st->vref[i]))
653 regulator_disable(st->vref[i]);
659 static int ad7124_remove(struct spi_device *spi)
661 struct iio_dev *indio_dev = spi_get_drvdata(spi);
662 struct ad7124_state *st = iio_priv(indio_dev);
665 iio_device_unregister(indio_dev);
666 ad_sd_cleanup_buffer_and_trigger(indio_dev);
667 clk_disable_unprepare(st->mclk);
669 for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
670 if (!IS_ERR_OR_NULL(st->vref[i]))
671 regulator_disable(st->vref[i]);
677 static const struct spi_device_id ad7124_id_table[] = {
678 { "ad7124-4", ID_AD7124_4 },
679 { "ad7124-8", ID_AD7124_8 },
682 MODULE_DEVICE_TABLE(spi, ad7124_id_table);
684 static const struct of_device_id ad7124_of_match[] = {
685 { .compatible = "adi,ad7124-4" },
686 { .compatible = "adi,ad7124-8" },
689 MODULE_DEVICE_TABLE(of, ad7124_of_match);
691 static struct spi_driver ad71124_driver = {
694 .of_match_table = ad7124_of_match,
696 .probe = ad7124_probe,
697 .remove = ad7124_remove,
698 .id_table = ad7124_id_table,
700 module_spi_driver(ad71124_driver);
702 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
703 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
704 MODULE_LICENSE("GPL");