drivers/iio/adc/ad7124.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AD7124 SPI ADC driver
   4  *
   5  * Copyright 2018 Analog Devices Inc.
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/spi/spi.h>
  17
  18 #include <linux/iio/iio.h>
  19 #include <linux/iio/adc/ad_sigma_delta.h>
  20 #include <linux/iio/sysfs.h>
  21
  22 /* AD7124 registers */
  23 #define AD7124_COMMS                    0x00
  24 #define AD7124_STATUS                   0x00
  25 #define AD7124_ADC_CONTROL              0x01
  26 #define AD7124_DATA                     0x02
  27 #define AD7124_IO_CONTROL_1             0x03
  28 #define AD7124_IO_CONTROL_2             0x04
  29 #define AD7124_ID                       0x05
  30 #define AD7124_ERROR                    0x06
  31 #define AD7124_ERROR_EN         0x07
  32 #define AD7124_MCLK_COUNT               0x08
  33 #define AD7124_CHANNEL(x)               (0x09 + (x))
  34 #define AD7124_CONFIG(x)                (0x19 + (x))
  35 #define AD7124_FILTER(x)                (0x21 + (x))
  36 #define AD7124_OFFSET(x)                (0x29 + (x))
  37 #define AD7124_GAIN(x)                  (0x31 + (x))
  38
  39 /* AD7124_STATUS */
  40 #define AD7124_STATUS_POR_FLAG_MSK      BIT(4)
  41
  42 /* AD7124_ADC_CONTROL */
  43 #define AD7124_ADC_CTRL_REF_EN_MSK      BIT(8)
  44 #define AD7124_ADC_CTRL_REF_EN(x)       FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
  45 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
  46 #define AD7124_ADC_CTRL_PWR(x)          FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
  47 #define AD7124_ADC_CTRL_MODE_MSK        GENMASK(5, 2)
  48 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
  49
  50 /* AD7124_CHANNEL_X */
  51 #define AD7124_CHANNEL_EN_MSK           BIT(15)
  52 #define AD7124_CHANNEL_EN(x)            FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
  53 #define AD7124_CHANNEL_SETUP_MSK        GENMASK(14, 12)
  54 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
  55 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
  56 #define AD7124_CHANNEL_AINP(x)          FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
  57 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
  58 #define AD7124_CHANNEL_AINM(x)          FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
  59
  60 /* AD7124_CONFIG_X */
  61 #define AD7124_CONFIG_BIPOLAR_MSK       BIT(11)
  62 #define AD7124_CONFIG_BIPOLAR(x)        FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
  63 #define AD7124_CONFIG_REF_SEL_MSK       GENMASK(4, 3)
  64 #define AD7124_CONFIG_REF_SEL(x)        FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
  65 #define AD7124_CONFIG_PGA_MSK           GENMASK(2, 0)
  66 #define AD7124_CONFIG_PGA(x)            FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
  67 #define AD7124_CONFIG_IN_BUFF_MSK       GENMASK(7, 6)
  68 #define AD7124_CONFIG_IN_BUFF(x)        FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
  69
  70 /* AD7124_FILTER_X */
  71 #define AD7124_FILTER_FS_MSK            GENMASK(10, 0)
  72 #define AD7124_FILTER_FS(x)             FIELD_PREP(AD7124_FILTER_FS_MSK, x)
  73
  74 enum ad7124_ids {
  75         ID_AD7124_4,
  76         ID_AD7124_8,
  77 };
  78
  79 enum ad7124_ref_sel {
  80         AD7124_REFIN1,
  81         AD7124_REFIN2,
  82         AD7124_INT_REF,
  83         AD7124_AVDD_REF,
  84 };
  85
  86 enum ad7124_power_mode {
  87         AD7124_LOW_POWER,
  88         AD7124_MID_POWER,
  89         AD7124_FULL_POWER,
  90 };
  91
  92 static const unsigned int ad7124_gain[8] = {
  93         1, 2, 4, 8, 16, 32, 64, 128
  94 };
  95
  96 static const int ad7124_master_clk_freq_hz[3] = {
  97         [AD7124_LOW_POWER] = 76800,
  98         [AD7124_MID_POWER] = 153600,
  99         [AD7124_FULL_POWER] = 614400,
 100 };
 101
 102 static const char * const ad7124_ref_names[] = {
 103         [AD7124_REFIN1] = "refin1",
 104         [AD7124_REFIN2] = "refin2",
 105         [AD7124_INT_REF] = "int",
 106         [AD7124_AVDD_REF] = "avdd",
 107 };
 108
 109 struct ad7124_chip_info {
 110         unsigned int num_inputs;
 111 };
 112
 113 struct ad7124_channel_config {
 114         enum ad7124_ref_sel refsel;
 115         bool bipolar;
 116         bool buf_positive;
 117         bool buf_negative;
 118         unsigned int ain;
 119         unsigned int vref_mv;
 120         unsigned int pga_bits;
 121         unsigned int odr;
 122 };
 123
 124 struct ad7124_state {
 125         const struct ad7124_chip_info *chip_info;
 126         struct ad_sigma_delta sd;
 127         struct ad7124_channel_config *channel_config;
 128         struct regulator *vref[4];
 129         struct clk *mclk;
 130         unsigned int adc_control;
 131         unsigned int num_channels;
 132 };
 133
 134 static const struct iio_chan_spec ad7124_channel_template = {
 135         .type = IIO_VOLTAGE,
 136         .indexed = 1,
 137         .differential = 1,
 138         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 139                 BIT(IIO_CHAN_INFO_SCALE) |
 140                 BIT(IIO_CHAN_INFO_OFFSET) |
 141                 BIT(IIO_CHAN_INFO_SAMP_FREQ),
 142         .scan_type = {
 143                 .sign = 'u',
 144                 .realbits = 24,
 145                 .storagebits = 32,
 146                 .shift = 8,
 147                 .endianness = IIO_BE,
 148         },
 149 };
 150
 151 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
 152         [ID_AD7124_4] = {
 153                 .num_inputs = 8,
 154         },
 155         [ID_AD7124_8] = {
 156                 .num_inputs = 16,
 157         },
 158 };
 159
 160 static int ad7124_find_closest_match(const int *array,
 161                                      unsigned int size, int val)
 162 {
 163         int i, idx;
 164         unsigned int diff_new, diff_old;
 165
 166         diff_old = U32_MAX;
 167         idx = 0;
 168
 169         for (i = 0; i < size; i++) {
 170                 diff_new = abs(val - array[i]);
 171                 if (diff_new < diff_old) {
 172                         diff_old = diff_new;
 173                         idx = i;
 174                 }
 175         }
 176
 177         return idx;
 178 }
 179
 180 static int ad7124_spi_write_mask(struct ad7124_state *st,
 181                                  unsigned int addr,
 182                                  unsigned long mask,
 183                                  unsigned int val,
 184                                  unsigned int bytes)
 185 {
 186         unsigned int readval;
 187         int ret;
 188
 189         ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
 190         if (ret < 0)
 191                 return ret;
 192
 193         readval &= ~mask;
 194         readval |= val;
 195
 196         return ad_sd_write_reg(&st->sd, addr, bytes, readval);
 197 }
 198
 199 static int ad7124_set_mode(struct ad_sigma_delta *sd,
 200                            enum ad_sigma_delta_mode mode)
 201 {
 202         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 203
 204         st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
 205         st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
 206
 207         return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 208 }
 209
 210 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
 211 {
 212         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 213         unsigned int val;
 214
 215         val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
 216               AD7124_CHANNEL_SETUP(channel);
 217
 218         return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
 219 }
 220
 221 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
 222         .set_channel = ad7124_set_channel,
 223         .set_mode = ad7124_set_mode,
 224         .has_registers = true,
 225         .addr_shift = 0,
 226         .read_mask = BIT(6),
 227         .data_reg = AD7124_DATA,
 228         .irq_flags = IRQF_TRIGGER_FALLING,
 229 };
 230
 231 static int ad7124_set_channel_odr(struct ad7124_state *st,
 232                                   unsigned int channel,
 233                                   unsigned int odr)
 234 {
 235         unsigned int fclk, odr_sel_bits;
 236         int ret;
 237
 238         fclk = clk_get_rate(st->mclk);
 239         /*
 240          * FS[10:0] = fCLK / (fADC x 32) where:
 241          * fADC is the output data rate
 242          * fCLK is the master clock frequency
 243          * FS[10:0] are the bits in the filter register
 244          * FS[10:0] can have a value from 1 to 2047
 245          */
 246         odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
 247         if (odr_sel_bits < 1)
 248                 odr_sel_bits = 1;
 249         else if (odr_sel_bits > 2047)
 250                 odr_sel_bits = 2047;
 251
 252         ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
 253                                     AD7124_FILTER_FS_MSK,
 254                                     AD7124_FILTER_FS(odr_sel_bits), 3);
 255         if (ret < 0)
 256                 return ret;
 257         /* fADC = fCLK / (FS[10:0] x 32) */
 258         st->channel_config[channel].odr =
 259                 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
 260
 261         return 0;
 262 }
 263
 264 static int ad7124_set_channel_gain(struct ad7124_state *st,
 265                                    unsigned int channel,
 266                                    unsigned int gain)
 267 {
 268         unsigned int res;
 269         int ret;
 270
 271         res = ad7124_find_closest_match(ad7124_gain,
 272                                         ARRAY_SIZE(ad7124_gain), gain);
 273         ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
 274                                     AD7124_CONFIG_PGA_MSK,
 275                                     AD7124_CONFIG_PGA(res), 2);
 276         if (ret < 0)
 277                 return ret;
 278
 279         st->channel_config[channel].pga_bits = res;
 280
 281         return 0;
 282 }
 283
 284 static int ad7124_read_raw(struct iio_dev *indio_dev,
 285                            struct iio_chan_spec const *chan,
 286                            int *val, int *val2, long info)
 287 {
 288         struct ad7124_state *st = iio_priv(indio_dev);
 289         int idx, ret;
 290
 291         switch (info) {
 292         case IIO_CHAN_INFO_RAW:
 293                 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
 294                 if (ret < 0)
 295                         return ret;
 296
 297                 /* After the conversion is performed, disable the channel */
 298                 ret = ad_sd_write_reg(&st->sd,
 299                                       AD7124_CHANNEL(chan->address), 2,
 300                                       st->channel_config[chan->address].ain |
 301                                       AD7124_CHANNEL_EN(0));
 302                 if (ret < 0)
 303                         return ret;
 304
 305                 return IIO_VAL_INT;
 306         case IIO_CHAN_INFO_SCALE:
 307                 idx = st->channel_config[chan->address].pga_bits;
 308                 *val = st->channel_config[chan->address].vref_mv;
 309                 if (st->channel_config[chan->address].bipolar)
 310                         *val2 = chan->scan_type.realbits - 1 + idx;
 311                 else
 312                         *val2 = chan->scan_type.realbits + idx;
 313
 314                 return IIO_VAL_FRACTIONAL_LOG2;
 315         case IIO_CHAN_INFO_OFFSET:
 316                 if (st->channel_config[chan->address].bipolar)
 317                         *val = -(1 << (chan->scan_type.realbits - 1));
 318                 else
 319                         *val = 0;
 320
 321                 return IIO_VAL_INT;
 322         case IIO_CHAN_INFO_SAMP_FREQ:
 323                 *val = st->channel_config[chan->address].odr;
 324
 325                 return IIO_VAL_INT;
 326         default:
 327                 return -EINVAL;
 328         }
 329 }
 330
 331 static int ad7124_write_raw(struct iio_dev *indio_dev,
 332                             struct iio_chan_spec const *chan,
 333                             int val, int val2, long info)
 334 {
 335         struct ad7124_state *st = iio_priv(indio_dev);
 336         unsigned int res, gain, full_scale, vref;
 337
 338         switch (info) {
 339         case IIO_CHAN_INFO_SAMP_FREQ:
 340                 if (val2 != 0)
 341                         return -EINVAL;
 342
 343                 return ad7124_set_channel_odr(st, chan->address, val);
 344         case IIO_CHAN_INFO_SCALE:
 345                 if (val != 0)
 346                         return -EINVAL;
 347
 348                 if (st->channel_config[chan->address].bipolar)
 349                         full_scale = 1 << (chan->scan_type.realbits - 1);
 350                 else
 351                         full_scale = 1 << chan->scan_type.realbits;
 352
 353                 vref = st->channel_config[chan->address].vref_mv * 1000000LL;
 354                 res = DIV_ROUND_CLOSEST(vref, full_scale);
 355                 gain = DIV_ROUND_CLOSEST(res, val2);
 356
 357                 return ad7124_set_channel_gain(st, chan->address, gain);
 358         default:
 359                 return -EINVAL;
 360         }
 361 }
 362
 363 static IIO_CONST_ATTR(in_voltage_scale_available,
 364         "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
 365
 366 static struct attribute *ad7124_attributes[] = {
 367         &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
 368         NULL,
 369 };
 370
 371 static const struct attribute_group ad7124_attrs_group = {
 372         .attrs = ad7124_attributes,
 373 };
 374
 375 static const struct iio_info ad7124_info = {
 376         .read_raw = ad7124_read_raw,
 377         .write_raw = ad7124_write_raw,
 378         .validate_trigger = ad_sd_validate_trigger,
 379         .attrs = &ad7124_attrs_group,
 380 };
 381
 382 static int ad7124_soft_reset(struct ad7124_state *st)
 383 {
 384         unsigned int readval, timeout;
 385         int ret;
 386
 387         ret = ad_sd_reset(&st->sd, 64);
 388         if (ret < 0)
 389                 return ret;
 390
 391         timeout = 100;
 392         do {
 393                 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
 394                 if (ret < 0)
 395                         return ret;
 396
 397                 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
 398                         return 0;
 399
 400                 /* The AD7124 requires typically 2ms to power up and settle */
 401                 usleep_range(100, 2000);
 402         } while (--timeout);
 403
 404         dev_err(&st->sd.spi->dev, "Soft reset failed\n");
 405
 406         return -EIO;
 407 }
 408
 409 static int ad7124_init_channel_vref(struct ad7124_state *st,
 410                                     unsigned int channel_number)
 411 {
 412         unsigned int refsel = st->channel_config[channel_number].refsel;
 413
 414         switch (refsel) {
 415         case AD7124_REFIN1:
 416         case AD7124_REFIN2:
 417         case AD7124_AVDD_REF:
 418                 if (IS_ERR(st->vref[refsel])) {
 419                         dev_err(&st->sd.spi->dev,
 420                                 "Error, trying to use external voltage reference without a %s regulator.\n",
 421                                 ad7124_ref_names[refsel]);
 422                         return PTR_ERR(st->vref[refsel]);
 423                 }
 424                 st->channel_config[channel_number].vref_mv =
 425                         regulator_get_voltage(st->vref[refsel]);
 426                 /* Conversion from uV to mV */
 427                 st->channel_config[channel_number].vref_mv /= 1000;
 428                 break;
 429         case AD7124_INT_REF:
 430                 st->channel_config[channel_number].vref_mv = 2500;
 431                 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
 432                 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
 433                 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
 434                                       2, st->adc_control);
 435         default:
 436                 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
 437                 return -EINVAL;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
 444                                           struct device_node *np)
 445 {
 446         struct ad7124_state *st = iio_priv(indio_dev);
 447         struct device_node *child;
 448         struct iio_chan_spec *chan;
 449         struct ad7124_channel_config *chan_config;
 450         unsigned int ain[2], channel = 0, tmp;
 451         int ret;
 452
 453         st->num_channels = of_get_available_child_count(np);
 454         if (!st->num_channels) {
 455                 dev_err(indio_dev->dev.parent, "no channel children\n");
 456                 return -ENODEV;
 457         }
 458
 459         chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 460                             sizeof(*chan), GFP_KERNEL);
 461         if (!chan)
 462                 return -ENOMEM;
 463
 464         chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 465                                    sizeof(*chan_config), GFP_KERNEL);
 466         if (!chan_config)
 467                 return -ENOMEM;
 468
 469         indio_dev->channels = chan;
 470         indio_dev->num_channels = st->num_channels;
 471         st->channel_config = chan_config;
 472
 473         for_each_available_child_of_node(np, child) {
 474                 ret = of_property_read_u32(child, "reg", &channel);
 475                 if (ret)
 476                         goto err;
 477
 478                 ret = of_property_read_u32_array(child, "diff-channels",
 479                                                  ain, 2);
 480                 if (ret)
 481                         goto err;
 482
 483                 st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
 484                                                   AD7124_CHANNEL_AINM(ain[1]);
 485                 st->channel_config[channel].bipolar =
 486                         of_property_read_bool(child, "bipolar");
 487
 488                 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
 489                 if (ret)
 490                         st->channel_config[channel].refsel = AD7124_INT_REF;
 491                 else
 492                         st->channel_config[channel].refsel = tmp;
 493
 494                 st->channel_config[channel].buf_positive =
 495                         of_property_read_bool(child, "adi,buffered-positive");
 496                 st->channel_config[channel].buf_negative =
 497                         of_property_read_bool(child, "adi,buffered-negative");
 498
 499                 chan[channel] = ad7124_channel_template;
 500                 chan[channel].address = channel;
 501                 chan[channel].scan_index = channel;
 502                 chan[channel].channel = ain[0];
 503                 chan[channel].channel2 = ain[1];
 504         }
 505
 506         return 0;
 507 err:
 508         of_node_put(child);
 509
 510         return ret;
 511 }
 512
 513 static int ad7124_setup(struct ad7124_state *st)
 514 {
 515         unsigned int val, fclk, power_mode;
 516         int i, ret, tmp;
 517
 518         fclk = clk_get_rate(st->mclk);
 519         if (!fclk)
 520                 return -EINVAL;
 521
 522         /* The power mode changes the master clock frequency */
 523         power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
 524                                         ARRAY_SIZE(ad7124_master_clk_freq_hz),
 525                                         fclk);
 526         if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
 527                 ret = clk_set_rate(st->mclk, fclk);
 528                 if (ret)
 529                         return ret;
 530         }
 531
 532         /* Set the power mode */
 533         st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
 534         st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
 535         ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 536         if (ret < 0)
 537                 return ret;
 538
 539         for (i = 0; i < st->num_channels; i++) {
 540                 val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
 541                 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
 542                 if (ret < 0)
 543                         return ret;
 544
 545                 ret = ad7124_init_channel_vref(st, i);
 546                 if (ret < 0)
 547                         return ret;
 548
 549                 tmp = (st->channel_config[i].buf_positive << 1)  +
 550                         st->channel_config[i].buf_negative;
 551
 552                 val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
 553                       AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
 554                       AD7124_CONFIG_IN_BUFF(tmp);
 555                 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
 556                 if (ret < 0)
 557                         return ret;
 558                 /*
 559                  * 9.38 SPS is the minimum output data rate supported
 560                  * regardless of the selected power mode. Round it up to 10 and
 561                  * set all the enabled channels to this default value.
 562                  */
 563                 ret = ad7124_set_channel_odr(st, i, 10);
 564         }
 565
 566         return ret;
 567 }
 568
 569 static int ad7124_probe(struct spi_device *spi)
 570 {
 571         const struct spi_device_id *id;
 572         struct ad7124_state *st;
 573         struct iio_dev *indio_dev;
 574         int i, ret;
 575
 576         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 577         if (!indio_dev)
 578                 return -ENOMEM;
 579
 580         st = iio_priv(indio_dev);
 581
 582         id = spi_get_device_id(spi);
 583         st->chip_info = &ad7124_chip_info_tbl[id->driver_data];
 584
 585         ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
 586
 587         spi_set_drvdata(spi, indio_dev);
 588
 589         indio_dev->dev.parent = &spi->dev;
 590         indio_dev->name = spi_get_device_id(spi)->name;
 591         indio_dev->modes = INDIO_DIRECT_MODE;
 592         indio_dev->info = &ad7124_info;
 593
 594         ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
 595         if (ret < 0)
 596                 return ret;
 597
 598         for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
 599                 if (i == AD7124_INT_REF)
 600                         continue;
 601
 602                 st->vref[i] = devm_regulator_get_optional(&spi->dev,
 603                                                 ad7124_ref_names[i]);
 604                 if (PTR_ERR(st->vref[i]) == -ENODEV)
 605                         continue;
 606                 else if (IS_ERR(st->vref[i]))
 607                         return PTR_ERR(st->vref[i]);
 608
 609                 ret = regulator_enable(st->vref[i]);
 610                 if (ret)
 611                         return ret;
 612         }
 613
 614         st->mclk = devm_clk_get(&spi->dev, "mclk");
 615         if (IS_ERR(st->mclk)) {
 616                 ret = PTR_ERR(st->mclk);
 617                 goto error_regulator_disable;
 618         }
 619
 620         ret = clk_prepare_enable(st->mclk);
 621         if (ret < 0)
 622                 goto error_regulator_disable;
 623
 624         ret = ad7124_soft_reset(st);
 625         if (ret < 0)
 626                 goto error_clk_disable_unprepare;
 627
 628         ret = ad7124_setup(st);
 629         if (ret < 0)
 630                 goto error_clk_disable_unprepare;
 631
 632         ret = ad_sd_setup_buffer_and_trigger(indio_dev);
 633         if (ret < 0)
 634                 goto error_clk_disable_unprepare;
 635
 636         ret = iio_device_register(indio_dev);
 637         if (ret < 0) {
 638                 dev_err(&spi->dev, "Failed to register iio device\n");
 639                 goto error_remove_trigger;
 640         }
 641
 642         return 0;
 643
 644 error_remove_trigger:
 645         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 646 error_clk_disable_unprepare:
 647         clk_disable_unprepare(st->mclk);
 648 error_regulator_disable:
 649         for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
 650                 if (!IS_ERR_OR_NULL(st->vref[i]))
 651                         regulator_disable(st->vref[i]);
 652         }
 653
 654         return ret;
 655 }
 656
 657 static int ad7124_remove(struct spi_device *spi)
 658 {
 659         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 660         struct ad7124_state *st = iio_priv(indio_dev);
 661         int i;
 662
 663         iio_device_unregister(indio_dev);
 664         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 665         clk_disable_unprepare(st->mclk);
 666
 667         for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
 668                 if (!IS_ERR_OR_NULL(st->vref[i]))
 669                         regulator_disable(st->vref[i]);
 670         }
 671
 672         return 0;
 673 }
 674
 675 static const struct spi_device_id ad7124_id_table[] = {
 676         { "ad7124-4", ID_AD7124_4 },
 677         { "ad7124-8", ID_AD7124_8 },
 678         {}
 679 };
 680 MODULE_DEVICE_TABLE(spi, ad7124_id_table);
 681
 682 static const struct of_device_id ad7124_of_match[] = {
 683         { .compatible = "adi,ad7124-4" },
 684         { .compatible = "adi,ad7124-8" },
 685         { },
 686 };
 687 MODULE_DEVICE_TABLE(of, ad7124_of_match);
 688
 689 static struct spi_driver ad71124_driver = {
 690         .driver = {
 691                 .name = "ad7124",
 692                 .of_match_table = ad7124_of_match,
 693         },
 694         .probe = ad7124_probe,
 695         .remove = ad7124_remove,
 696         .id_table = ad7124_id_table,
 697 };
 698 module_spi_driver(ad71124_driver);
 699
 700 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
 701 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
 702 MODULE_LICENSE("GPL");