drivers/iio/adc/max1027.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2  /*
   3   * iio/adc/max1027.c
   4   * Copyright (C) 2014 Philippe Reynes
   5   *
   6   * based on linux/drivers/iio/ad7923.c
   7   * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
   8   * Copyright 2012 CS Systemes d'Information
   9   *
  10   * max1027.c
  11   *
  12   * Partial support for max1027 and similar chips.
  13   */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/delay.h>
  19
  20 #include <linux/iio/iio.h>
  21 #include <linux/iio/buffer.h>
  22 #include <linux/iio/trigger.h>
  23 #include <linux/iio/trigger_consumer.h>
  24 #include <linux/iio/triggered_buffer.h>
  25
  26 #define MAX1027_CONV_REG  BIT(7)
  27 #define MAX1027_SETUP_REG BIT(6)
  28 #define MAX1027_AVG_REG   BIT(5)
  29 #define MAX1027_RST_REG   BIT(4)
  30
  31 /* conversion register */
  32 #define MAX1027_TEMP      BIT(0)
  33 #define MAX1027_SCAN_0_N  (0x00 << 1)
  34 #define MAX1027_SCAN_N_M  (0x01 << 1)
  35 #define MAX1027_SCAN_N    (0x02 << 1)
  36 #define MAX1027_NOSCAN    (0x03 << 1)
  37 #define MAX1027_CHAN(n)   ((n) << 3)
  38
  39 /* setup register */
  40 #define MAX1027_UNIPOLAR  0x02
  41 #define MAX1027_BIPOLAR   0x03
  42 #define MAX1027_REF_MODE0 (0x00 << 2)
  43 #define MAX1027_REF_MODE1 (0x01 << 2)
  44 #define MAX1027_REF_MODE2 (0x02 << 2)
  45 #define MAX1027_REF_MODE3 (0x03 << 2)
  46 #define MAX1027_CKS_MODE0 (0x00 << 4)
  47 #define MAX1027_CKS_MODE1 (0x01 << 4)
  48 #define MAX1027_CKS_MODE2 (0x02 << 4)
  49 #define MAX1027_CKS_MODE3 (0x03 << 4)
  50
  51 /* averaging register */
  52 #define MAX1027_NSCAN_4   0x00
  53 #define MAX1027_NSCAN_8   0x01
  54 #define MAX1027_NSCAN_12  0x02
  55 #define MAX1027_NSCAN_16  0x03
  56 #define MAX1027_NAVG_4    (0x00 << 2)
  57 #define MAX1027_NAVG_8    (0x01 << 2)
  58 #define MAX1027_NAVG_16   (0x02 << 2)
  59 #define MAX1027_NAVG_32   (0x03 << 2)
  60 #define MAX1027_AVG_EN    BIT(4)
  61
  62 enum max1027_id {
  63         max1027,
  64         max1029,
  65         max1031,
  66 };
  67
  68 static const struct spi_device_id max1027_id[] = {
  69         {"max1027", max1027},
  70         {"max1029", max1029},
  71         {"max1031", max1031},
  72         {}
  73 };
  74 MODULE_DEVICE_TABLE(spi, max1027_id);
  75
  76 #ifdef CONFIG_OF
  77 static const struct of_device_id max1027_adc_dt_ids[] = {
  78         { .compatible = "maxim,max1027" },
  79         { .compatible = "maxim,max1029" },
  80         { .compatible = "maxim,max1031" },
  81         {},
  82 };
  83 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
  84 #endif
  85
  86 #define MAX1027_V_CHAN(index, depth)                                    \
  87         {                                                               \
  88                 .type = IIO_VOLTAGE,                                    \
  89                 .indexed = 1,                                           \
  90                 .channel = index,                                       \
  91                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
  92                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
  93                 .scan_index = index + 1,                                \
  94                 .scan_type = {                                          \
  95                         .sign = 'u',                                    \
  96                         .realbits = depth,                              \
  97                         .storagebits = 16,                              \
  98                         .shift = 2,                                     \
  99                         .endianness = IIO_BE,                           \
 100                 },                                                      \
 101         }
 102
 103 #define MAX1027_T_CHAN                                                  \
 104         {                                                               \
 105                 .type = IIO_TEMP,                                       \
 106                 .channel = 0,                                           \
 107                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 108                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 109                 .scan_index = 0,                                        \
 110                 .scan_type = {                                          \
 111                         .sign = 'u',                                    \
 112                         .realbits = 12,                                 \
 113                         .storagebits = 16,                              \
 114                         .endianness = IIO_BE,                           \
 115                 },                                                      \
 116         }
 117
 118 #define MAX1X27_CHANNELS(depth)                 \
 119         MAX1027_T_CHAN,                         \
 120         MAX1027_V_CHAN(0, depth),               \
 121         MAX1027_V_CHAN(1, depth),               \
 122         MAX1027_V_CHAN(2, depth),               \
 123         MAX1027_V_CHAN(3, depth),               \
 124         MAX1027_V_CHAN(4, depth),               \
 125         MAX1027_V_CHAN(5, depth),               \
 126         MAX1027_V_CHAN(6, depth),               \
 127         MAX1027_V_CHAN(7, depth)
 128
 129 #define MAX1X29_CHANNELS(depth)                 \
 130         MAX1X27_CHANNELS(depth),                \
 131         MAX1027_V_CHAN(8, depth),               \
 132         MAX1027_V_CHAN(9, depth),               \
 133         MAX1027_V_CHAN(10, depth),              \
 134         MAX1027_V_CHAN(11, depth)
 135
 136 #define MAX1X31_CHANNELS(depth)                 \
 137         MAX1X27_CHANNELS(depth),                \
 138         MAX1X29_CHANNELS(depth),                \
 139         MAX1027_V_CHAN(12, depth),              \
 140         MAX1027_V_CHAN(13, depth),              \
 141         MAX1027_V_CHAN(14, depth),              \
 142         MAX1027_V_CHAN(15, depth)
 143
 144 static const struct iio_chan_spec max1027_channels[] = {
 145         MAX1X27_CHANNELS(10),
 146 };
 147
 148 static const struct iio_chan_spec max1029_channels[] = {
 149         MAX1X29_CHANNELS(10),
 150 };
 151
 152 static const struct iio_chan_spec max1031_channels[] = {
 153         MAX1X31_CHANNELS(10),
 154 };
 155
 156 static const unsigned long max1027_available_scan_masks[] = {
 157         0x000001ff,
 158         0x00000000,
 159 };
 160
 161 static const unsigned long max1029_available_scan_masks[] = {
 162         0x00001fff,
 163         0x00000000,
 164 };
 165
 166 static const unsigned long max1031_available_scan_masks[] = {
 167         0x0001ffff,
 168         0x00000000,
 169 };
 170
 171 struct max1027_chip_info {
 172         const struct iio_chan_spec *channels;
 173         unsigned int num_channels;
 174         const unsigned long *available_scan_masks;
 175 };
 176
 177 static const struct max1027_chip_info max1027_chip_info_tbl[] = {
 178         [max1027] = {
 179                 .channels = max1027_channels,
 180                 .num_channels = ARRAY_SIZE(max1027_channels),
 181                 .available_scan_masks = max1027_available_scan_masks,
 182         },
 183         [max1029] = {
 184                 .channels = max1029_channels,
 185                 .num_channels = ARRAY_SIZE(max1029_channels),
 186                 .available_scan_masks = max1029_available_scan_masks,
 187         },
 188         [max1031] = {
 189                 .channels = max1031_channels,
 190                 .num_channels = ARRAY_SIZE(max1031_channels),
 191                 .available_scan_masks = max1031_available_scan_masks,
 192         },
 193 };
 194
 195 struct max1027_state {
 196         const struct max1027_chip_info  *info;
 197         struct spi_device               *spi;
 198         struct iio_trigger              *trig;
 199         __be16                          *buffer;
 200         struct mutex                    lock;
 201
 202         u8                              reg ____cacheline_aligned;
 203 };
 204
 205 static int max1027_read_single_value(struct iio_dev *indio_dev,
 206                                      struct iio_chan_spec const *chan,
 207                                      int *val)
 208 {
 209         int ret;
 210         struct max1027_state *st = iio_priv(indio_dev);
 211
 212         if (iio_buffer_enabled(indio_dev)) {
 213                 dev_warn(&indio_dev->dev, "trigger mode already enabled");
 214                 return -EBUSY;
 215         }
 216
 217         /* Start acquisition on conversion register write */
 218         st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
 219         ret = spi_write(st->spi, &st->reg, 1);
 220         if (ret < 0) {
 221                 dev_err(&indio_dev->dev,
 222                         "Failed to configure setup register\n");
 223                 return ret;
 224         }
 225
 226         /* Configure conversion register with the requested chan */
 227         st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
 228                   MAX1027_NOSCAN;
 229         if (chan->type == IIO_TEMP)
 230                 st->reg |= MAX1027_TEMP;
 231         ret = spi_write(st->spi, &st->reg, 1);
 232         if (ret < 0) {
 233                 dev_err(&indio_dev->dev,
 234                         "Failed to configure conversion register\n");
 235                 return ret;
 236         }
 237
 238         /*
 239          * For an unknown reason, when we use the mode "10" (write
 240          * conversion register), the interrupt doesn't occur every time.
 241          * So we just wait 1 ms.
 242          */
 243         mdelay(1);
 244
 245         /* Read result */
 246         ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
 247         if (ret < 0)
 248                 return ret;
 249
 250         *val = be16_to_cpu(st->buffer[0]);
 251
 252         return IIO_VAL_INT;
 253 }
 254
 255 static int max1027_read_raw(struct iio_dev *indio_dev,
 256                             struct iio_chan_spec const *chan,
 257                             int *val, int *val2, long mask)
 258 {
 259         int ret = 0;
 260         struct max1027_state *st = iio_priv(indio_dev);
 261
 262         mutex_lock(&st->lock);
 263
 264         switch (mask) {
 265         case IIO_CHAN_INFO_RAW:
 266                 ret = max1027_read_single_value(indio_dev, chan, val);
 267                 break;
 268         case IIO_CHAN_INFO_SCALE:
 269                 switch (chan->type) {
 270                 case IIO_TEMP:
 271                         *val = 1;
 272                         *val2 = 8;
 273                         ret = IIO_VAL_FRACTIONAL;
 274                         break;
 275                 case IIO_VOLTAGE:
 276                         *val = 2500;
 277                         *val2 = chan->scan_type.realbits;
 278                         ret = IIO_VAL_FRACTIONAL_LOG2;
 279                         break;
 280                 default:
 281                         ret = -EINVAL;
 282                         break;
 283                 }
 284                 break;
 285         default:
 286                 ret = -EINVAL;
 287                 break;
 288         }
 289
 290         mutex_unlock(&st->lock);
 291
 292         return ret;
 293 }
 294
 295 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
 296                                       unsigned reg, unsigned writeval,
 297                                       unsigned *readval)
 298 {
 299         struct max1027_state *st = iio_priv(indio_dev);
 300         u8 *val = (u8 *)st->buffer;
 301
 302         if (readval) {
 303                 int ret = spi_read(st->spi, val, 2);
 304                 *readval = be16_to_cpu(st->buffer[0]);
 305                 return ret;
 306         }
 307
 308         *val = (u8)writeval;
 309         return spi_write(st->spi, val, 1);
 310 }
 311
 312 static int max1027_validate_trigger(struct iio_dev *indio_dev,
 313                                     struct iio_trigger *trig)
 314 {
 315         struct max1027_state *st = iio_priv(indio_dev);
 316
 317         if (st->trig != trig)
 318                 return -EINVAL;
 319
 320         return 0;
 321 }
 322
 323 static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
 324 {
 325         struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
 326         struct max1027_state *st = iio_priv(indio_dev);
 327         int ret;
 328
 329         if (state) {
 330                 /* Start acquisition on cnvst */
 331                 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
 332                           MAX1027_REF_MODE2;
 333                 ret = spi_write(st->spi, &st->reg, 1);
 334                 if (ret < 0)
 335                         return ret;
 336
 337                 /* Scan from 0 to max */
 338                 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
 339                           MAX1027_SCAN_N_M | MAX1027_TEMP;
 340                 ret = spi_write(st->spi, &st->reg, 1);
 341                 if (ret < 0)
 342                         return ret;
 343         } else {
 344                 /* Start acquisition on conversion register write */
 345                 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
 346                           MAX1027_REF_MODE2;
 347                 ret = spi_write(st->spi, &st->reg, 1);
 348                 if (ret < 0)
 349                         return ret;
 350         }
 351
 352         return 0;
 353 }
 354
 355 static irqreturn_t max1027_trigger_handler(int irq, void *private)
 356 {
 357         struct iio_poll_func *pf = private;
 358         struct iio_dev *indio_dev = pf->indio_dev;
 359         struct max1027_state *st = iio_priv(indio_dev);
 360
 361         pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
 362
 363         /* fill buffer with all channel */
 364         spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
 365
 366         iio_push_to_buffers(indio_dev, st->buffer);
 367
 368         iio_trigger_notify_done(indio_dev->trig);
 369
 370         return IRQ_HANDLED;
 371 }
 372
 373 static const struct iio_trigger_ops max1027_trigger_ops = {
 374         .validate_device = &iio_trigger_validate_own_device,
 375         .set_trigger_state = &max1027_set_trigger_state,
 376 };
 377
 378 static const struct iio_info max1027_info = {
 379         .read_raw = &max1027_read_raw,
 380         .validate_trigger = &max1027_validate_trigger,
 381         .debugfs_reg_access = &max1027_debugfs_reg_access,
 382 };
 383
 384 static int max1027_probe(struct spi_device *spi)
 385 {
 386         int ret;
 387         struct iio_dev *indio_dev;
 388         struct max1027_state *st;
 389
 390         pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
 391
 392         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 393         if (indio_dev == NULL) {
 394                 pr_err("Can't allocate iio device\n");
 395                 return -ENOMEM;
 396         }
 397
 398         spi_set_drvdata(spi, indio_dev);
 399
 400         st = iio_priv(indio_dev);
 401         st->spi = spi;
 402         st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
 403
 404         mutex_init(&st->lock);
 405
 406         indio_dev->name = spi_get_device_id(spi)->name;
 407         indio_dev->dev.parent = &spi->dev;
 408         indio_dev->dev.of_node = spi->dev.of_node;
 409         indio_dev->info = &max1027_info;
 410         indio_dev->modes = INDIO_DIRECT_MODE;
 411         indio_dev->channels = st->info->channels;
 412         indio_dev->num_channels = st->info->num_channels;
 413         indio_dev->available_scan_masks = st->info->available_scan_masks;
 414
 415         st->buffer = devm_kmalloc_array(&indio_dev->dev,
 416                                   indio_dev->num_channels, 2,
 417                                   GFP_KERNEL);
 418         if (st->buffer == NULL) {
 419                 dev_err(&indio_dev->dev, "Can't allocate buffer\n");
 420                 return -ENOMEM;
 421         }
 422
 423         if (spi->irq) {
 424                 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
 425                                                       &iio_pollfunc_store_time,
 426                                                       &max1027_trigger_handler,
 427                                                       NULL);
 428                 if (ret < 0) {
 429                         dev_err(&indio_dev->dev, "Failed to setup buffer\n");
 430                         return ret;
 431                 }
 432
 433                 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
 434                                                   indio_dev->name);
 435                 if (st->trig == NULL) {
 436                         ret = -ENOMEM;
 437                         dev_err(&indio_dev->dev,
 438                                 "Failed to allocate iio trigger\n");
 439                         return ret;
 440                 }
 441
 442                 st->trig->ops = &max1027_trigger_ops;
 443                 st->trig->dev.parent = &spi->dev;
 444                 iio_trigger_set_drvdata(st->trig, indio_dev);
 445                 iio_trigger_register(st->trig);
 446
 447                 ret = devm_request_threaded_irq(&spi->dev, spi->irq,
 448                                                 iio_trigger_generic_data_rdy_poll,
 449                                                 NULL,
 450                                                 IRQF_TRIGGER_FALLING,
 451                                                 spi->dev.driver->name,
 452                                                 st->trig);
 453                 if (ret < 0) {
 454                         dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
 455                         return ret;
 456                 }
 457         }
 458
 459         /* Internal reset */
 460         st->reg = MAX1027_RST_REG;
 461         ret = spi_write(st->spi, &st->reg, 1);
 462         if (ret < 0) {
 463                 dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
 464                 return ret;
 465         }
 466
 467         /* Disable averaging */
 468         st->reg = MAX1027_AVG_REG;
 469         ret = spi_write(st->spi, &st->reg, 1);
 470         if (ret < 0) {
 471                 dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
 472                 return ret;
 473         }
 474
 475         return devm_iio_device_register(&spi->dev, indio_dev);
 476 }
 477
 478 static struct spi_driver max1027_driver = {
 479         .driver = {
 480                 .name   = "max1027",
 481                 .of_match_table = of_match_ptr(max1027_adc_dt_ids),
 482         },
 483         .probe          = max1027_probe,
 484         .id_table       = max1027_id,
 485 };
 486 module_spi_driver(max1027_driver);
 487
 488 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
 489 MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
 490 MODULE_LICENSE("GPL v2");