drivers/iio/adc/max1027.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2  /*
   3   * iio/adc/max1027.c
   4   * Copyright (C) 2014 Philippe Reynes
   5   *
   6   * based on linux/drivers/iio/ad7923.c
   7   * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
   8   * Copyright 2012 CS Systemes d'Information
   9   *
  10   * max1027.c
  11   *
  12   * Partial support for max1027 and similar chips.
  13   */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/delay.h>
  19
  20 #include <linux/iio/iio.h>
  21 #include <linux/iio/buffer.h>
  22 #include <linux/iio/trigger.h>
  23 #include <linux/iio/trigger_consumer.h>
  24 #include <linux/iio/triggered_buffer.h>
  25
  26 #define MAX1027_CONV_REG  BIT(7)
  27 #define MAX1027_SETUP_REG BIT(6)
  28 #define MAX1027_AVG_REG   BIT(5)
  29 #define MAX1027_RST_REG   BIT(4)
  30
  31 /* conversion register */
  32 #define MAX1027_TEMP      BIT(0)
  33 #define MAX1027_SCAN_0_N  (0x00 << 1)
  34 #define MAX1027_SCAN_N_M  (0x01 << 1)
  35 #define MAX1027_SCAN_N    (0x02 << 1)
  36 #define MAX1027_NOSCAN    (0x03 << 1)
  37 #define MAX1027_CHAN(n)   ((n) << 3)
  38
  39 /* setup register */
  40 #define MAX1027_UNIPOLAR  0x02
  41 #define MAX1027_BIPOLAR   0x03
  42 #define MAX1027_REF_MODE0 (0x00 << 2)
  43 #define MAX1027_REF_MODE1 (0x01 << 2)
  44 #define MAX1027_REF_MODE2 (0x02 << 2)
  45 #define MAX1027_REF_MODE3 (0x03 << 2)
  46 #define MAX1027_CKS_MODE0 (0x00 << 4)
  47 #define MAX1027_CKS_MODE1 (0x01 << 4)
  48 #define MAX1027_CKS_MODE2 (0x02 << 4)
  49 #define MAX1027_CKS_MODE3 (0x03 << 4)
  50
  51 /* averaging register */
  52 #define MAX1027_NSCAN_4   0x00
  53 #define MAX1027_NSCAN_8   0x01
  54 #define MAX1027_NSCAN_12  0x02
  55 #define MAX1027_NSCAN_16  0x03
  56 #define MAX1027_NAVG_4    (0x00 << 2)
  57 #define MAX1027_NAVG_8    (0x01 << 2)
  58 #define MAX1027_NAVG_16   (0x02 << 2)
  59 #define MAX1027_NAVG_32   (0x03 << 2)
  60 #define MAX1027_AVG_EN    BIT(4)
  61
  62 enum max1027_id {
  63         max1027,
  64         max1029,
  65         max1031,
  66 };
  67
  68 static const struct spi_device_id max1027_id[] = {
  69         {"max1027", max1027},
  70         {"max1029", max1029},
  71         {"max1031", max1031},
  72         {}
  73 };
  74 MODULE_DEVICE_TABLE(spi, max1027_id);
  75
  76 #ifdef CONFIG_OF
  77 static const struct of_device_id max1027_adc_dt_ids[] = {
  78         { .compatible = "maxim,max1027" },
  79         { .compatible = "maxim,max1029" },
  80         { .compatible = "maxim,max1031" },
  81         {},
  82 };
  83 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
  84 #endif
  85
  86 #define MAX1027_V_CHAN(index)                                           \
  87         {                                                               \
  88                 .type = IIO_VOLTAGE,                                    \
  89                 .indexed = 1,                                           \
  90                 .channel = index,                                       \
  91                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
  92                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
  93                 .scan_index = index + 1,                                \
  94                 .scan_type = {                                          \
  95                         .sign = 'u',                                    \
  96                         .realbits = 10,                                 \
  97                         .storagebits = 16,                              \
  98                         .shift = 2,                                     \
  99                         .endianness = IIO_BE,                           \
 100                 },                                                      \
 101         }
 102
 103 #define MAX1027_T_CHAN                                                  \
 104         {                                                               \
 105                 .type = IIO_TEMP,                                       \
 106                 .channel = 0,                                           \
 107                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 108                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 109                 .scan_index = 0,                                        \
 110                 .scan_type = {                                          \
 111                         .sign = 'u',                                    \
 112                         .realbits = 12,                                 \
 113                         .storagebits = 16,                              \
 114                         .endianness = IIO_BE,                           \
 115                 },                                                      \
 116         }
 117
 118 static const struct iio_chan_spec max1027_channels[] = {
 119         MAX1027_T_CHAN,
 120         MAX1027_V_CHAN(0),
 121         MAX1027_V_CHAN(1),
 122         MAX1027_V_CHAN(2),
 123         MAX1027_V_CHAN(3),
 124         MAX1027_V_CHAN(4),
 125         MAX1027_V_CHAN(5),
 126         MAX1027_V_CHAN(6),
 127         MAX1027_V_CHAN(7)
 128 };
 129
 130 static const struct iio_chan_spec max1029_channels[] = {
 131         MAX1027_T_CHAN,
 132         MAX1027_V_CHAN(0),
 133         MAX1027_V_CHAN(1),
 134         MAX1027_V_CHAN(2),
 135         MAX1027_V_CHAN(3),
 136         MAX1027_V_CHAN(4),
 137         MAX1027_V_CHAN(5),
 138         MAX1027_V_CHAN(6),
 139         MAX1027_V_CHAN(7),
 140         MAX1027_V_CHAN(8),
 141         MAX1027_V_CHAN(9),
 142         MAX1027_V_CHAN(10),
 143         MAX1027_V_CHAN(11)
 144 };
 145
 146 static const struct iio_chan_spec max1031_channels[] = {
 147         MAX1027_T_CHAN,
 148         MAX1027_V_CHAN(0),
 149         MAX1027_V_CHAN(1),
 150         MAX1027_V_CHAN(2),
 151         MAX1027_V_CHAN(3),
 152         MAX1027_V_CHAN(4),
 153         MAX1027_V_CHAN(5),
 154         MAX1027_V_CHAN(6),
 155         MAX1027_V_CHAN(7),
 156         MAX1027_V_CHAN(8),
 157         MAX1027_V_CHAN(9),
 158         MAX1027_V_CHAN(10),
 159         MAX1027_V_CHAN(11),
 160         MAX1027_V_CHAN(12),
 161         MAX1027_V_CHAN(13),
 162         MAX1027_V_CHAN(14),
 163         MAX1027_V_CHAN(15)
 164 };
 165
 166 static const unsigned long max1027_available_scan_masks[] = {
 167         0x000001ff,
 168         0x00000000,
 169 };
 170
 171 static const unsigned long max1029_available_scan_masks[] = {
 172         0x00001fff,
 173         0x00000000,
 174 };
 175
 176 static const unsigned long max1031_available_scan_masks[] = {
 177         0x0001ffff,
 178         0x00000000,
 179 };
 180
 181 struct max1027_chip_info {
 182         const struct iio_chan_spec *channels;
 183         unsigned int num_channels;
 184         const unsigned long *available_scan_masks;
 185 };
 186
 187 static const struct max1027_chip_info max1027_chip_info_tbl[] = {
 188         [max1027] = {
 189                 .channels = max1027_channels,
 190                 .num_channels = ARRAY_SIZE(max1027_channels),
 191                 .available_scan_masks = max1027_available_scan_masks,
 192         },
 193         [max1029] = {
 194                 .channels = max1029_channels,
 195                 .num_channels = ARRAY_SIZE(max1029_channels),
 196                 .available_scan_masks = max1029_available_scan_masks,
 197         },
 198         [max1031] = {
 199                 .channels = max1031_channels,
 200                 .num_channels = ARRAY_SIZE(max1031_channels),
 201                 .available_scan_masks = max1031_available_scan_masks,
 202         },
 203 };
 204
 205 struct max1027_state {
 206         const struct max1027_chip_info  *info;
 207         struct spi_device               *spi;
 208         struct iio_trigger              *trig;
 209         __be16                          *buffer;
 210         struct mutex                    lock;
 211
 212         u8                              reg ____cacheline_aligned;
 213 };
 214
 215 static int max1027_read_single_value(struct iio_dev *indio_dev,
 216                                      struct iio_chan_spec const *chan,
 217                                      int *val)
 218 {
 219         int ret;
 220         struct max1027_state *st = iio_priv(indio_dev);
 221
 222         if (iio_buffer_enabled(indio_dev)) {
 223                 dev_warn(&indio_dev->dev, "trigger mode already enabled");
 224                 return -EBUSY;
 225         }
 226
 227         /* Start acquisition on conversion register write */
 228         st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
 229         ret = spi_write(st->spi, &st->reg, 1);
 230         if (ret < 0) {
 231                 dev_err(&indio_dev->dev,
 232                         "Failed to configure setup register\n");
 233                 return ret;
 234         }
 235
 236         /* Configure conversion register with the requested chan */
 237         st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
 238                   MAX1027_NOSCAN;
 239         if (chan->type == IIO_TEMP)
 240                 st->reg |= MAX1027_TEMP;
 241         ret = spi_write(st->spi, &st->reg, 1);
 242         if (ret < 0) {
 243                 dev_err(&indio_dev->dev,
 244                         "Failed to configure conversion register\n");
 245                 return ret;
 246         }
 247
 248         /*
 249          * For an unknown reason, when we use the mode "10" (write
 250          * conversion register), the interrupt doesn't occur every time.
 251          * So we just wait 1 ms.
 252          */
 253         mdelay(1);
 254
 255         /* Read result */
 256         ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
 257         if (ret < 0)
 258                 return ret;
 259
 260         *val = be16_to_cpu(st->buffer[0]);
 261
 262         return IIO_VAL_INT;
 263 }
 264
 265 static int max1027_read_raw(struct iio_dev *indio_dev,
 266                             struct iio_chan_spec const *chan,
 267                             int *val, int *val2, long mask)
 268 {
 269         int ret = 0;
 270         struct max1027_state *st = iio_priv(indio_dev);
 271
 272         mutex_lock(&st->lock);
 273
 274         switch (mask) {
 275         case IIO_CHAN_INFO_RAW:
 276                 ret = max1027_read_single_value(indio_dev, chan, val);
 277                 break;
 278         case IIO_CHAN_INFO_SCALE:
 279                 switch (chan->type) {
 280                 case IIO_TEMP:
 281                         *val = 1;
 282                         *val2 = 8;
 283                         ret = IIO_VAL_FRACTIONAL;
 284                         break;
 285                 case IIO_VOLTAGE:
 286                         *val = 2500;
 287                         *val2 = 10;
 288                         ret = IIO_VAL_FRACTIONAL_LOG2;
 289                         break;
 290                 default:
 291                         ret = -EINVAL;
 292                         break;
 293                 }
 294                 break;
 295         default:
 296                 ret = -EINVAL;
 297                 break;
 298         }
 299
 300         mutex_unlock(&st->lock);
 301
 302         return ret;
 303 }
 304
 305 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
 306                                       unsigned reg, unsigned writeval,
 307                                       unsigned *readval)
 308 {
 309         struct max1027_state *st = iio_priv(indio_dev);
 310         u8 *val = (u8 *)st->buffer;
 311
 312         if (readval) {
 313                 int ret = spi_read(st->spi, val, 2);
 314                 *readval = be16_to_cpu(st->buffer[0]);
 315                 return ret;
 316         }
 317
 318         *val = (u8)writeval;
 319         return spi_write(st->spi, val, 1);
 320 }
 321
 322 static int max1027_validate_trigger(struct iio_dev *indio_dev,
 323                                     struct iio_trigger *trig)
 324 {
 325         struct max1027_state *st = iio_priv(indio_dev);
 326
 327         if (st->trig != trig)
 328                 return -EINVAL;
 329
 330         return 0;
 331 }
 332
 333 static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
 334 {
 335         struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
 336         struct max1027_state *st = iio_priv(indio_dev);
 337         int ret;
 338
 339         if (state) {
 340                 /* Start acquisition on cnvst */
 341                 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
 342                           MAX1027_REF_MODE2;
 343                 ret = spi_write(st->spi, &st->reg, 1);
 344                 if (ret < 0)
 345                         return ret;
 346
 347                 /* Scan from 0 to max */
 348                 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
 349                           MAX1027_SCAN_N_M | MAX1027_TEMP;
 350                 ret = spi_write(st->spi, &st->reg, 1);
 351                 if (ret < 0)
 352                         return ret;
 353         } else {
 354                 /* Start acquisition on conversion register write */
 355                 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
 356                           MAX1027_REF_MODE2;
 357                 ret = spi_write(st->spi, &st->reg, 1);
 358                 if (ret < 0)
 359                         return ret;
 360         }
 361
 362         return 0;
 363 }
 364
 365 static irqreturn_t max1027_trigger_handler(int irq, void *private)
 366 {
 367         struct iio_poll_func *pf = private;
 368         struct iio_dev *indio_dev = pf->indio_dev;
 369         struct max1027_state *st = iio_priv(indio_dev);
 370
 371         pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
 372
 373         /* fill buffer with all channel */
 374         spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
 375
 376         iio_push_to_buffers(indio_dev, st->buffer);
 377
 378         iio_trigger_notify_done(indio_dev->trig);
 379
 380         return IRQ_HANDLED;
 381 }
 382
 383 static const struct iio_trigger_ops max1027_trigger_ops = {
 384         .validate_device = &iio_trigger_validate_own_device,
 385         .set_trigger_state = &max1027_set_trigger_state,
 386 };
 387
 388 static const struct iio_info max1027_info = {
 389         .read_raw = &max1027_read_raw,
 390         .validate_trigger = &max1027_validate_trigger,
 391         .debugfs_reg_access = &max1027_debugfs_reg_access,
 392 };
 393
 394 static int max1027_probe(struct spi_device *spi)
 395 {
 396         int ret;
 397         struct iio_dev *indio_dev;
 398         struct max1027_state *st;
 399
 400         pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
 401
 402         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 403         if (indio_dev == NULL) {
 404                 pr_err("Can't allocate iio device\n");
 405                 return -ENOMEM;
 406         }
 407
 408         spi_set_drvdata(spi, indio_dev);
 409
 410         st = iio_priv(indio_dev);
 411         st->spi = spi;
 412         st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
 413
 414         mutex_init(&st->lock);
 415
 416         indio_dev->name = spi_get_device_id(spi)->name;
 417         indio_dev->dev.parent = &spi->dev;
 418         indio_dev->dev.of_node = spi->dev.of_node;
 419         indio_dev->info = &max1027_info;
 420         indio_dev->modes = INDIO_DIRECT_MODE;
 421         indio_dev->channels = st->info->channels;
 422         indio_dev->num_channels = st->info->num_channels;
 423         indio_dev->available_scan_masks = st->info->available_scan_masks;
 424
 425         st->buffer = devm_kmalloc_array(&indio_dev->dev,
 426                                   indio_dev->num_channels, 2,
 427                                   GFP_KERNEL);
 428         if (st->buffer == NULL) {
 429                 dev_err(&indio_dev->dev, "Can't allocate buffer\n");
 430                 return -ENOMEM;
 431         }
 432
 433         if (spi->irq) {
 434                 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
 435                                                       &iio_pollfunc_store_time,
 436                                                       &max1027_trigger_handler,
 437                                                       NULL);
 438                 if (ret < 0) {
 439                         dev_err(&indio_dev->dev, "Failed to setup buffer\n");
 440                         return ret;
 441                 }
 442
 443                 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
 444                                                   indio_dev->name);
 445                 if (st->trig == NULL) {
 446                         ret = -ENOMEM;
 447                         dev_err(&indio_dev->dev,
 448                                 "Failed to allocate iio trigger\n");
 449                         return ret;
 450                 }
 451
 452                 st->trig->ops = &max1027_trigger_ops;
 453                 st->trig->dev.parent = &spi->dev;
 454                 iio_trigger_set_drvdata(st->trig, indio_dev);
 455                 iio_trigger_register(st->trig);
 456
 457                 ret = devm_request_threaded_irq(&spi->dev, spi->irq,
 458                                                 iio_trigger_generic_data_rdy_poll,
 459                                                 NULL,
 460                                                 IRQF_TRIGGER_FALLING,
 461                                                 spi->dev.driver->name,
 462                                                 st->trig);
 463                 if (ret < 0) {
 464                         dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
 465                         return ret;
 466                 }
 467         }
 468
 469         /* Internal reset */
 470         st->reg = MAX1027_RST_REG;
 471         ret = spi_write(st->spi, &st->reg, 1);
 472         if (ret < 0) {
 473                 dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
 474                 return ret;
 475         }
 476
 477         /* Disable averaging */
 478         st->reg = MAX1027_AVG_REG;
 479         ret = spi_write(st->spi, &st->reg, 1);
 480         if (ret < 0) {
 481                 dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
 482                 return ret;
 483         }
 484
 485         return devm_iio_device_register(&spi->dev, indio_dev);
 486 }
 487
 488 static struct spi_driver max1027_driver = {
 489         .driver = {
 490                 .name   = "max1027",
 491                 .of_match_table = of_match_ptr(max1027_adc_dt_ids),
 492         },
 493         .probe          = max1027_probe,
 494         .id_table       = max1027_id,
 495 };
 496 module_spi_driver(max1027_driver);
 497
 498 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
 499 MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
 500 MODULE_LICENSE("GPL v2");