1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2008-2010 Jonathan Cameron
6 * based on linux/drivers/i2c/chips/max123x
7 * Copyright (C) 2002-2004 Stefan Eletzhofer
9 * based on linux/drivers/acron/char/pcf8583.c
10 * Copyright (C) 2000 Russell King
12 * Driver for max1363 and similar chips.
15 #include <linux/interrupt.h>
16 #include <linux/device.h>
17 #include <linux/kernel.h>
18 #include <linux/sysfs.h>
19 #include <linux/list.h>
20 #include <linux/i2c.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <linux/err.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/events.h>
31 #include <linux/iio/buffer.h>
32 #include <linux/iio/driver.h>
33 #include <linux/iio/kfifo_buf.h>
34 #include <linux/iio/trigger_consumer.h>
35 #include <linux/iio/triggered_buffer.h>
37 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
39 /* There is a fair bit more defined here than currently
40 * used, but the intention is to support everything these
41 * chips do in the long run */
44 /* max1363 and max1236, max1237, max1238, max1239 */
45 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
46 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
47 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
48 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
49 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
50 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
52 /* think about including max11600 etc - more settings */
53 #define MAX1363_SETUP_EXT_CLOCK 0x08
54 #define MAX1363_SETUP_INT_CLOCK 0x00
55 #define MAX1363_SETUP_UNIPOLAR 0x00
56 #define MAX1363_SETUP_BIPOLAR 0x04
57 #define MAX1363_SETUP_RESET 0x00
58 #define MAX1363_SETUP_NORESET 0x02
59 /* max1363 only - though don't care on others.
60 * For now monitor modes are not implemented as the relevant
61 * line is not connected on my test board.
62 * The definitions are here as I intend to add this soon.
64 #define MAX1363_SETUP_MONITOR_SETUP 0x01
66 /* Specific to the max1363 */
67 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
68 #define MAX1363_MON_INT_ENABLE 0x01
70 /* defined for readability reasons */
72 #define MAX1363_CONFIG_BYTE(a) ((a))
74 #define MAX1363_CONFIG_SE 0x01
75 #define MAX1363_CONFIG_DE 0x00
76 #define MAX1363_CONFIG_SCAN_TO_CS 0x00
77 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
78 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
79 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
80 /* max123{6-9} only */
81 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
83 /* max1363 only - merely part of channel selects or don't care for others */
84 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
86 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
88 /* max1363 strictly 0x06 - but doesn't matter */
89 #define MAX1363_CHANNEL_SEL_MASK 0x1E
90 #define MAX1363_SCAN_MASK 0x60
91 #define MAX1363_SE_DE_MASK 0x01
93 #define MAX1363_MAX_CHANNELS 25
95 * struct max1363_mode - scan mode information
96 * @conf: The corresponding value of the configuration register
97 * @modemask: Bit mask corresponding to channels enabled in this mode
101 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
104 /* This must be maintained along side the max1363_mode_table in max1363_core */
106 /* Single read of a single channel */
107 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
108 /* Differential single read */
109 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
110 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
111 /* Scan to channel and mid to channel where overlapping */
112 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
113 s6to7, s0to7, s6to8, s0to8, s6to9,
114 s0to9, s6to10, s0to10, s6to11, s0to11,
115 /* Differential scan to channel and mid to channel where overlapping */
116 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
117 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
118 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
119 d7m6to11m10, d1m0to11m10,
123 * struct max1363_chip_info - chip specifc information
124 * @info: iio core function callbacks structure
125 * @channels: channel specification
126 * @num_channels: number of channels
127 * @mode_list: array of available scan modes
128 * @default_mode: the scan mode in which the chip starts up
129 * @int_vref_mv: the internal reference voltage
130 * @num_modes: number of modes
131 * @bits: accuracy of the adc in bits
133 struct max1363_chip_info {
134 const struct iio_info *info;
135 const struct iio_chan_spec *channels;
137 const enum max1363_modes *mode_list;
138 enum max1363_modes default_mode;
145 * struct max1363_state - driver instance specific data
146 * @client: i2c_client
147 * @setupbyte: cache of current device setup byte
148 * @configbyte: cache of current device config byte
149 * @chip_info: chip model specific constants, available modes, etc.
150 * @current_mode: the scan mode of this chip
151 * @requestedmask: a valid requested set of channels
152 * @reg: supply regulator
153 * @monitor_on: whether monitor mode is enabled
154 * @monitor_speed: parameter corresponding to device monitor speed setting
155 * @mask_high: bitmask for enabled high thresholds
156 * @mask_low: bitmask for enabled low thresholds
157 * @thresh_high: high threshold values
158 * @thresh_low: low threshold values
159 * @vref: Reference voltage regulator
160 * @vref_uv: Actual (external or internal) reference voltage
161 * @send: function used to send data to the chip
162 * @recv: function used to receive data from the chip
164 struct max1363_state {
165 struct i2c_client *client;
168 const struct max1363_chip_info *chip_info;
169 const struct max1363_mode *current_mode;
171 struct regulator *reg;
173 /* Using monitor modes and buffer at the same time is
174 currently not supported */
176 unsigned int monitor_speed:3;
179 /* 4x unipolar first then the fours bipolar ones */
182 struct regulator *vref;
184 int (*send)(const struct i2c_client *client,
185 const char *buf, int count);
186 int (*recv)(const struct i2c_client *client,
187 char *buf, int count);
190 #define MAX1363_MODE_SINGLE(_num, _mask) { \
191 .conf = MAX1363_CHANNEL_SEL(_num) \
192 | MAX1363_CONFIG_SCAN_SINGLE_1 \
193 | MAX1363_CONFIG_SE, \
194 .modemask[0] = _mask, \
197 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
198 .conf = MAX1363_CHANNEL_SEL(_num) \
199 | MAX1363_CONFIG_SCAN_TO_CS \
200 | MAX1363_CONFIG_SE, \
201 .modemask[0] = _mask, \
204 /* note not available for max1363 hence naming */
205 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
206 .conf = MAX1363_CHANNEL_SEL(_num) \
207 | MAX1236_SCAN_MID_TO_CHANNEL \
208 | MAX1363_CONFIG_SE, \
209 .modemask[0] = _mask \
212 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
213 .conf = MAX1363_CHANNEL_SEL(_nump) \
214 | MAX1363_CONFIG_SCAN_SINGLE_1 \
215 | MAX1363_CONFIG_DE, \
216 .modemask[0] = _mask \
219 /* Can't think how to automate naming so specify for now */
220 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
221 .conf = MAX1363_CHANNEL_SEL(_num) \
222 | MAX1363_CONFIG_SCAN_TO_CS \
223 | MAX1363_CONFIG_DE, \
224 .modemask[0] = _mask \
227 /* note only available for max1363 hence naming */
228 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
229 .conf = MAX1363_CHANNEL_SEL(_num) \
230 | MAX1236_SCAN_MID_TO_CHANNEL \
231 | MAX1363_CONFIG_SE, \
232 .modemask[0] = _mask \
235 static const struct max1363_mode max1363_mode_table[] = {
236 /* All of the single channel options first */
237 MAX1363_MODE_SINGLE(0, 1 << 0),
238 MAX1363_MODE_SINGLE(1, 1 << 1),
239 MAX1363_MODE_SINGLE(2, 1 << 2),
240 MAX1363_MODE_SINGLE(3, 1 << 3),
241 MAX1363_MODE_SINGLE(4, 1 << 4),
242 MAX1363_MODE_SINGLE(5, 1 << 5),
243 MAX1363_MODE_SINGLE(6, 1 << 6),
244 MAX1363_MODE_SINGLE(7, 1 << 7),
245 MAX1363_MODE_SINGLE(8, 1 << 8),
246 MAX1363_MODE_SINGLE(9, 1 << 9),
247 MAX1363_MODE_SINGLE(10, 1 << 10),
248 MAX1363_MODE_SINGLE(11, 1 << 11),
250 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
251 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
252 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
253 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
254 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
255 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
256 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
257 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
258 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
259 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
260 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
261 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
263 /* The multichannel scans next */
264 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
265 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
266 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
267 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
268 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
270 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
271 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
272 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
273 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
274 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
275 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
276 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
277 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
278 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
279 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
280 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
282 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
285 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
286 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
287 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
288 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
292 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
293 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
294 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
295 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
298 static const struct max1363_mode
299 *max1363_match_mode(const unsigned long *mask,
300 const struct max1363_chip_info *ci)
304 for (i = 0; i < ci->num_modes; i++)
305 if (bitmap_subset(mask,
306 max1363_mode_table[ci->mode_list[i]].
308 MAX1363_MAX_CHANNELS))
309 return &max1363_mode_table[ci->mode_list[i]];
313 static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
318 for (i = err = 0; err == 0 && i < count; ++i)
319 err = i2c_smbus_write_byte(client, buf[i]);
321 return err ? err : count;
324 static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
329 for (i = 0; i < count; ++i) {
330 ret = i2c_smbus_read_byte(client);
339 static int max1363_write_basic_config(struct max1363_state *st)
341 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
343 return st->send(st->client, tx_buf, 2);
346 static int max1363_set_scan_mode(struct max1363_state *st)
348 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
350 | MAX1363_SE_DE_MASK);
351 st->configbyte |= st->current_mode->conf;
353 return max1363_write_basic_config(st);
356 static int max1363_read_single_chan(struct iio_dev *indio_dev,
357 struct iio_chan_spec const *chan,
364 struct max1363_state *st = iio_priv(indio_dev);
365 struct i2c_client *client = st->client;
367 mutex_lock(&indio_dev->mlock);
369 * If monitor mode is enabled, the method for reading a single
370 * channel will have to be rather different and has not yet
373 * Also, cannot read directly if buffered capture enabled.
375 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
380 /* Check to see if current scan mode is correct */
381 if (st->current_mode != &max1363_mode_table[chan->address]) {
382 /* Update scan mode if needed */
383 st->current_mode = &max1363_mode_table[chan->address];
384 ret = max1363_set_scan_mode(st);
388 if (st->chip_info->bits != 8) {
390 data = st->recv(client, rxbuf, 2);
395 data = (rxbuf[1] | rxbuf[0] << 8) &
396 ((1 << st->chip_info->bits) - 1);
399 data = st->recv(client, rxbuf, 1);
408 mutex_unlock(&indio_dev->mlock);
413 static int max1363_read_raw(struct iio_dev *indio_dev,
414 struct iio_chan_spec const *chan,
419 struct max1363_state *st = iio_priv(indio_dev);
423 case IIO_CHAN_INFO_RAW:
424 ret = max1363_read_single_chan(indio_dev, chan, val, m);
428 case IIO_CHAN_INFO_SCALE:
429 *val = st->vref_uv / 1000;
430 *val2 = st->chip_info->bits;
431 return IIO_VAL_FRACTIONAL_LOG2;
438 /* Applies to max1363 */
439 static const enum max1363_modes max1363_mode_list[] = {
442 d0m1, d2m3, d1m0, d3m2,
443 d0m1to2m3, d1m0to3m2,
446 static const struct iio_event_spec max1363_events[] = {
448 .type = IIO_EV_TYPE_THRESH,
449 .dir = IIO_EV_DIR_RISING,
450 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
451 BIT(IIO_EV_INFO_ENABLE),
453 .type = IIO_EV_TYPE_THRESH,
454 .dir = IIO_EV_DIR_FALLING,
455 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
456 BIT(IIO_EV_INFO_ENABLE),
460 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
462 .type = IIO_VOLTAGE, \
466 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
467 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
468 .datasheet_name = "AIN"#num, \
472 .storagebits = (bits > 8) ? 16 : 8, \
473 .endianness = IIO_BE, \
476 .event_spec = ev_spec, \
477 .num_event_specs = num_ev_spec, \
480 /* bipolar channel */
481 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
483 .type = IIO_VOLTAGE, \
489 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
490 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
491 .datasheet_name = "AIN"#num"-AIN"#num2, \
495 .storagebits = (bits > 8) ? 16 : 8, \
496 .endianness = IIO_BE, \
499 .event_spec = ev_spec, \
500 .num_event_specs = num_ev_spec, \
503 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
504 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
505 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
506 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
507 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
511 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
512 IIO_CHAN_SOFT_TIMESTAMP(8) \
515 static const struct iio_chan_spec max1036_channels[] =
516 MAX1363_4X_CHANS(8, NULL, 0);
517 static const struct iio_chan_spec max1136_channels[] =
518 MAX1363_4X_CHANS(10, NULL, 0);
519 static const struct iio_chan_spec max1236_channels[] =
520 MAX1363_4X_CHANS(12, NULL, 0);
521 static const struct iio_chan_spec max1361_channels[] =
522 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
523 static const struct iio_chan_spec max1363_channels[] =
524 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
526 /* Applies to max1236, max1237 */
527 static const enum max1363_modes max1236_mode_list[] = {
530 d0m1, d2m3, d1m0, d3m2,
531 d0m1to2m3, d1m0to3m2,
535 /* Applies to max1238, max1239 */
536 static const enum max1363_modes max1238_mode_list[] = {
537 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
538 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
539 s0to7, s0to8, s0to9, s0to10, s0to11,
540 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
541 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
542 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
543 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
544 s6to7, s6to8, s6to9, s6to10, s6to11,
545 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
548 #define MAX1363_12X_CHANS(bits) { \
549 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
550 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
551 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
552 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
553 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
554 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
555 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
556 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
557 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
558 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
559 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
560 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
561 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
562 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
563 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
564 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
565 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
566 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
567 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
568 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
569 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
570 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
571 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
572 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
573 IIO_CHAN_SOFT_TIMESTAMP(24) \
575 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
576 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
577 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
579 static const enum max1363_modes max11607_mode_list[] = {
583 d0m1, d2m3, d1m0, d3m2,
584 d0m1to2m3, d1m0to3m2,
587 static const enum max1363_modes max11608_mode_list[] = {
588 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
589 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
591 d0m1, d2m3, d4m5, d6m7,
592 d1m0, d3m2, d5m4, d7m6,
593 d0m1to2m3, d0m1to4m5, d0m1to6m7,
594 d1m0to3m2, d1m0to5m4, d1m0to7m6,
597 #define MAX1363_8X_CHANS(bits) { \
598 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
599 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
600 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
601 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
602 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
603 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
604 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
605 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
606 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
607 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
608 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
609 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
610 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
611 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
612 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
613 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
614 IIO_CHAN_SOFT_TIMESTAMP(16) \
616 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
617 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
618 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
620 static const enum max1363_modes max11644_mode_list[] = {
621 _s0, _s1, s0to1, d0m1, d1m0,
624 #define MAX1363_2X_CHANS(bits) { \
625 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
626 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
627 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
628 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
629 IIO_CHAN_SOFT_TIMESTAMP(4) \
632 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
633 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
675 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
676 8300, 4200, 2000, 1000 };
678 static ssize_t max1363_monitor_show_freq(struct device *dev,
679 struct device_attribute *attr,
682 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
683 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
686 static ssize_t max1363_monitor_store_freq(struct device *dev,
687 struct device_attribute *attr,
691 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
692 struct max1363_state *st = iio_priv(indio_dev);
697 ret = kstrtoul(buf, 10, &val);
700 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
701 if (val == max1363_monitor_speeds[i]) {
708 mutex_lock(&indio_dev->mlock);
709 st->monitor_speed = i;
710 mutex_unlock(&indio_dev->mlock);
715 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
716 max1363_monitor_show_freq,
717 max1363_monitor_store_freq);
719 static IIO_CONST_ATTR(sampling_frequency_available,
720 "133000 665000 33300 16600 8300 4200 2000 1000");
722 static int max1363_read_thresh(struct iio_dev *indio_dev,
723 const struct iio_chan_spec *chan, enum iio_event_type type,
724 enum iio_event_direction dir, enum iio_event_info info, int *val,
727 struct max1363_state *st = iio_priv(indio_dev);
728 if (dir == IIO_EV_DIR_FALLING)
729 *val = st->thresh_low[chan->channel];
731 *val = st->thresh_high[chan->channel];
735 static int max1363_write_thresh(struct iio_dev *indio_dev,
736 const struct iio_chan_spec *chan, enum iio_event_type type,
737 enum iio_event_direction dir, enum iio_event_info info, int val,
740 struct max1363_state *st = iio_priv(indio_dev);
741 /* make it handle signed correctly as well */
742 switch (st->chip_info->bits) {
754 case IIO_EV_DIR_FALLING:
755 st->thresh_low[chan->channel] = val;
757 case IIO_EV_DIR_RISING:
758 st->thresh_high[chan->channel] = val;
767 static const u64 max1363_event_codes[] = {
768 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
769 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
770 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
771 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
772 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
773 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
774 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
775 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
776 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
777 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
778 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
779 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
780 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
781 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
782 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
783 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
786 static irqreturn_t max1363_event_handler(int irq, void *private)
788 struct iio_dev *indio_dev = private;
789 struct max1363_state *st = iio_priv(indio_dev);
790 s64 timestamp = iio_get_time_ns(indio_dev);
791 unsigned long mask, loc;
793 u8 tx[2] = { st->setupbyte,
794 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
796 st->recv(st->client, &rx, 1);
798 for_each_set_bit(loc, &mask, 8)
799 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
800 st->send(st->client, tx, 2);
805 static int max1363_read_event_config(struct iio_dev *indio_dev,
806 const struct iio_chan_spec *chan, enum iio_event_type type,
807 enum iio_event_direction dir)
809 struct max1363_state *st = iio_priv(indio_dev);
811 int number = chan->channel;
813 mutex_lock(&indio_dev->mlock);
814 if (dir == IIO_EV_DIR_FALLING)
815 val = (1 << number) & st->mask_low;
817 val = (1 << number) & st->mask_high;
818 mutex_unlock(&indio_dev->mlock);
823 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
827 unsigned long numelements;
829 const long *modemask;
832 /* transition to buffered capture is not currently supported */
833 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
834 st->configbyte &= ~MAX1363_SCAN_MASK;
835 st->monitor_on = false;
836 return max1363_write_basic_config(st);
839 /* Ensure we are in the relevant mode */
840 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
841 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
843 | MAX1363_SE_DE_MASK);
844 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
845 if ((st->mask_low | st->mask_high) & 0x0F) {
846 st->configbyte |= max1363_mode_table[s0to3].conf;
847 modemask = max1363_mode_table[s0to3].modemask;
848 } else if ((st->mask_low | st->mask_high) & 0x30) {
849 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
850 modemask = max1363_mode_table[d0m1to2m3].modemask;
852 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
853 modemask = max1363_mode_table[d1m0to3m2].modemask;
855 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
856 len = 3 * numelements + 3;
857 tx_buf = kmalloc(len, GFP_KERNEL);
862 tx_buf[0] = st->configbyte;
863 tx_buf[1] = st->setupbyte;
864 tx_buf[2] = (st->monitor_speed << 1);
867 * So we need to do yet another bit of nefarious scan mode
868 * setup to match what we need.
870 for (j = 0; j < 8; j++)
871 if (test_bit(j, modemask)) {
872 /* Establish the mode is in the scan */
873 if (st->mask_low & (1 << j)) {
874 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
875 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
883 if (st->mask_high & (1 << j)) {
885 (st->thresh_high[j] >> 8) & 0x0F;
886 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
888 tx_buf[i + 1] |= 0x0F;
889 tx_buf[i + 2] = 0xFF;
891 tx_buf[i + 1] |= 0x07;
892 tx_buf[i + 2] = 0xFF;
898 ret = st->send(st->client, tx_buf, len);
907 * Now that we hopefully have sensible thresholds in place it is
908 * time to turn the interrupts on.
909 * It is unclear from the data sheet if this should be necessary
910 * (i.e. whether monitor mode setup is atomic) but it appears to
913 tx_buf[0] = st->setupbyte;
914 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
915 ret = st->send(st->client, tx_buf, 2);
923 st->monitor_on = true;
932 * To keep this manageable we always use one of 3 scan modes.
933 * Scan 0...3, 0-1,2-3 and 1-0,3-2
936 static inline int __max1363_check_event_mask(int thismask, int checkmask)
941 if (checkmask & ~0x0F) {
945 } else if (thismask < 6) {
946 if (checkmask & ~0x30) {
950 } else if (checkmask & ~0xC0)
956 static int max1363_write_event_config(struct iio_dev *indio_dev,
957 const struct iio_chan_spec *chan, enum iio_event_type type,
958 enum iio_event_direction dir, int state)
961 struct max1363_state *st = iio_priv(indio_dev);
963 int number = chan->channel;
965 mutex_lock(&indio_dev->mlock);
966 unifiedmask = st->mask_low | st->mask_high;
967 if (dir == IIO_EV_DIR_FALLING) {
970 st->mask_low &= ~(1 << number);
972 ret = __max1363_check_event_mask((1 << number),
976 st->mask_low |= (1 << number);
980 st->mask_high &= ~(1 << number);
982 ret = __max1363_check_event_mask((1 << number),
986 st->mask_high |= (1 << number);
990 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
992 mutex_unlock(&indio_dev->mlock);
998 * As with scan_elements, only certain sets of these can
1001 static struct attribute *max1363_event_attributes[] = {
1002 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1003 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1007 static const struct attribute_group max1363_event_attribute_group = {
1008 .attrs = max1363_event_attributes,
1011 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1012 const unsigned long *scan_mask)
1014 struct max1363_state *st = iio_priv(indio_dev);
1017 * Need to figure out the current mode based upon the requested
1018 * scan mask in iio_dev
1020 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1021 if (!st->current_mode)
1023 max1363_set_scan_mode(st);
1027 static const struct iio_info max1238_info = {
1028 .read_raw = &max1363_read_raw,
1029 .update_scan_mode = &max1363_update_scan_mode,
1032 static const struct iio_info max1363_info = {
1033 .read_event_value = &max1363_read_thresh,
1034 .write_event_value = &max1363_write_thresh,
1035 .read_event_config = &max1363_read_event_config,
1036 .write_event_config = &max1363_write_event_config,
1037 .read_raw = &max1363_read_raw,
1038 .update_scan_mode = &max1363_update_scan_mode,
1039 .event_attrs = &max1363_event_attribute_group,
1042 /* max1363 and max1368 tested - rest from data sheet */
1043 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1046 .int_vref_mv = 2048,
1047 .mode_list = max1363_mode_list,
1048 .num_modes = ARRAY_SIZE(max1363_mode_list),
1049 .default_mode = s0to3,
1050 .channels = max1361_channels,
1051 .num_channels = ARRAY_SIZE(max1361_channels),
1052 .info = &max1363_info,
1056 .int_vref_mv = 4096,
1057 .mode_list = max1363_mode_list,
1058 .num_modes = ARRAY_SIZE(max1363_mode_list),
1059 .default_mode = s0to3,
1060 .channels = max1361_channels,
1061 .num_channels = ARRAY_SIZE(max1361_channels),
1062 .info = &max1363_info,
1066 .int_vref_mv = 2048,
1067 .mode_list = max1363_mode_list,
1068 .num_modes = ARRAY_SIZE(max1363_mode_list),
1069 .default_mode = s0to3,
1070 .channels = max1363_channels,
1071 .num_channels = ARRAY_SIZE(max1363_channels),
1072 .info = &max1363_info,
1076 .int_vref_mv = 4096,
1077 .mode_list = max1363_mode_list,
1078 .num_modes = ARRAY_SIZE(max1363_mode_list),
1079 .default_mode = s0to3,
1080 .channels = max1363_channels,
1081 .num_channels = ARRAY_SIZE(max1363_channels),
1082 .info = &max1363_info,
1086 .int_vref_mv = 4096,
1087 .mode_list = max1236_mode_list,
1088 .num_modes = ARRAY_SIZE(max1236_mode_list),
1089 .default_mode = s0to3,
1090 .info = &max1238_info,
1091 .channels = max1036_channels,
1092 .num_channels = ARRAY_SIZE(max1036_channels),
1096 .int_vref_mv = 2048,
1097 .mode_list = max1236_mode_list,
1098 .num_modes = ARRAY_SIZE(max1236_mode_list),
1099 .default_mode = s0to3,
1100 .info = &max1238_info,
1101 .channels = max1036_channels,
1102 .num_channels = ARRAY_SIZE(max1036_channels),
1106 .int_vref_mv = 4096,
1107 .mode_list = max1238_mode_list,
1108 .num_modes = ARRAY_SIZE(max1238_mode_list),
1109 .default_mode = s0to11,
1110 .info = &max1238_info,
1111 .channels = max1038_channels,
1112 .num_channels = ARRAY_SIZE(max1038_channels),
1116 .int_vref_mv = 2048,
1117 .mode_list = max1238_mode_list,
1118 .num_modes = ARRAY_SIZE(max1238_mode_list),
1119 .default_mode = s0to11,
1120 .info = &max1238_info,
1121 .channels = max1038_channels,
1122 .num_channels = ARRAY_SIZE(max1038_channels),
1126 .int_vref_mv = 4096,
1127 .mode_list = max1236_mode_list,
1128 .num_modes = ARRAY_SIZE(max1236_mode_list),
1129 .default_mode = s0to3,
1130 .info = &max1238_info,
1131 .channels = max1136_channels,
1132 .num_channels = ARRAY_SIZE(max1136_channels),
1136 .int_vref_mv = 2048,
1137 .mode_list = max1236_mode_list,
1138 .num_modes = ARRAY_SIZE(max1236_mode_list),
1139 .default_mode = s0to3,
1140 .info = &max1238_info,
1141 .channels = max1136_channels,
1142 .num_channels = ARRAY_SIZE(max1136_channels),
1146 .int_vref_mv = 4096,
1147 .mode_list = max1238_mode_list,
1148 .num_modes = ARRAY_SIZE(max1238_mode_list),
1149 .default_mode = s0to11,
1150 .info = &max1238_info,
1151 .channels = max1138_channels,
1152 .num_channels = ARRAY_SIZE(max1138_channels),
1156 .int_vref_mv = 2048,
1157 .mode_list = max1238_mode_list,
1158 .num_modes = ARRAY_SIZE(max1238_mode_list),
1159 .default_mode = s0to11,
1160 .info = &max1238_info,
1161 .channels = max1138_channels,
1162 .num_channels = ARRAY_SIZE(max1138_channels),
1166 .int_vref_mv = 4096,
1167 .mode_list = max1236_mode_list,
1168 .num_modes = ARRAY_SIZE(max1236_mode_list),
1169 .default_mode = s0to3,
1170 .info = &max1238_info,
1171 .channels = max1236_channels,
1172 .num_channels = ARRAY_SIZE(max1236_channels),
1176 .int_vref_mv = 2048,
1177 .mode_list = max1236_mode_list,
1178 .num_modes = ARRAY_SIZE(max1236_mode_list),
1179 .default_mode = s0to3,
1180 .info = &max1238_info,
1181 .channels = max1236_channels,
1182 .num_channels = ARRAY_SIZE(max1236_channels),
1186 .int_vref_mv = 4096,
1187 .mode_list = max1238_mode_list,
1188 .num_modes = ARRAY_SIZE(max1238_mode_list),
1189 .default_mode = s0to11,
1190 .info = &max1238_info,
1191 .channels = max1238_channels,
1192 .num_channels = ARRAY_SIZE(max1238_channels),
1196 .int_vref_mv = 2048,
1197 .mode_list = max1238_mode_list,
1198 .num_modes = ARRAY_SIZE(max1238_mode_list),
1199 .default_mode = s0to11,
1200 .info = &max1238_info,
1201 .channels = max1238_channels,
1202 .num_channels = ARRAY_SIZE(max1238_channels),
1206 .int_vref_mv = 4096,
1207 .mode_list = max11607_mode_list,
1208 .num_modes = ARRAY_SIZE(max11607_mode_list),
1209 .default_mode = s0to3,
1210 .info = &max1238_info,
1211 .channels = max1036_channels,
1212 .num_channels = ARRAY_SIZE(max1036_channels),
1216 .int_vref_mv = 2048,
1217 .mode_list = max11607_mode_list,
1218 .num_modes = ARRAY_SIZE(max11607_mode_list),
1219 .default_mode = s0to3,
1220 .info = &max1238_info,
1221 .channels = max1036_channels,
1222 .num_channels = ARRAY_SIZE(max1036_channels),
1226 .int_vref_mv = 4096,
1227 .mode_list = max11608_mode_list,
1228 .num_modes = ARRAY_SIZE(max11608_mode_list),
1229 .default_mode = s0to7,
1230 .info = &max1238_info,
1231 .channels = max11602_channels,
1232 .num_channels = ARRAY_SIZE(max11602_channels),
1236 .int_vref_mv = 2048,
1237 .mode_list = max11608_mode_list,
1238 .num_modes = ARRAY_SIZE(max11608_mode_list),
1239 .default_mode = s0to7,
1240 .info = &max1238_info,
1241 .channels = max11602_channels,
1242 .num_channels = ARRAY_SIZE(max11602_channels),
1246 .int_vref_mv = 4096,
1247 .mode_list = max1238_mode_list,
1248 .num_modes = ARRAY_SIZE(max1238_mode_list),
1249 .default_mode = s0to11,
1250 .info = &max1238_info,
1251 .channels = max1038_channels,
1252 .num_channels = ARRAY_SIZE(max1038_channels),
1256 .int_vref_mv = 2048,
1257 .mode_list = max1238_mode_list,
1258 .num_modes = ARRAY_SIZE(max1238_mode_list),
1259 .default_mode = s0to11,
1260 .info = &max1238_info,
1261 .channels = max1038_channels,
1262 .num_channels = ARRAY_SIZE(max1038_channels),
1266 .int_vref_mv = 4096,
1267 .mode_list = max11607_mode_list,
1268 .num_modes = ARRAY_SIZE(max11607_mode_list),
1269 .default_mode = s0to3,
1270 .info = &max1238_info,
1271 .channels = max1136_channels,
1272 .num_channels = ARRAY_SIZE(max1136_channels),
1276 .int_vref_mv = 2048,
1277 .mode_list = max11607_mode_list,
1278 .num_modes = ARRAY_SIZE(max11607_mode_list),
1279 .default_mode = s0to3,
1280 .info = &max1238_info,
1281 .channels = max1136_channels,
1282 .num_channels = ARRAY_SIZE(max1136_channels),
1286 .int_vref_mv = 4096,
1287 .mode_list = max11608_mode_list,
1288 .num_modes = ARRAY_SIZE(max11608_mode_list),
1289 .default_mode = s0to7,
1290 .info = &max1238_info,
1291 .channels = max11608_channels,
1292 .num_channels = ARRAY_SIZE(max11608_channels),
1296 .int_vref_mv = 2048,
1297 .mode_list = max11608_mode_list,
1298 .num_modes = ARRAY_SIZE(max11608_mode_list),
1299 .default_mode = s0to7,
1300 .info = &max1238_info,
1301 .channels = max11608_channels,
1302 .num_channels = ARRAY_SIZE(max11608_channels),
1306 .int_vref_mv = 4096,
1307 .mode_list = max1238_mode_list,
1308 .num_modes = ARRAY_SIZE(max1238_mode_list),
1309 .default_mode = s0to11,
1310 .info = &max1238_info,
1311 .channels = max1138_channels,
1312 .num_channels = ARRAY_SIZE(max1138_channels),
1316 .int_vref_mv = 2048,
1317 .mode_list = max1238_mode_list,
1318 .num_modes = ARRAY_SIZE(max1238_mode_list),
1319 .default_mode = s0to11,
1320 .info = &max1238_info,
1321 .channels = max1138_channels,
1322 .num_channels = ARRAY_SIZE(max1138_channels),
1326 .int_vref_mv = 4096,
1327 .mode_list = max11607_mode_list,
1328 .num_modes = ARRAY_SIZE(max11607_mode_list),
1329 .default_mode = s0to3,
1330 .info = &max1238_info,
1331 .channels = max1363_channels,
1332 .num_channels = ARRAY_SIZE(max1363_channels),
1336 .int_vref_mv = 2048,
1337 .mode_list = max11607_mode_list,
1338 .num_modes = ARRAY_SIZE(max11607_mode_list),
1339 .default_mode = s0to3,
1340 .info = &max1238_info,
1341 .channels = max1363_channels,
1342 .num_channels = ARRAY_SIZE(max1363_channels),
1346 .int_vref_mv = 4096,
1347 .mode_list = max11608_mode_list,
1348 .num_modes = ARRAY_SIZE(max11608_mode_list),
1349 .default_mode = s0to7,
1350 .info = &max1238_info,
1351 .channels = max11614_channels,
1352 .num_channels = ARRAY_SIZE(max11614_channels),
1356 .int_vref_mv = 2048,
1357 .mode_list = max11608_mode_list,
1358 .num_modes = ARRAY_SIZE(max11608_mode_list),
1359 .default_mode = s0to7,
1360 .info = &max1238_info,
1361 .channels = max11614_channels,
1362 .num_channels = ARRAY_SIZE(max11614_channels),
1366 .int_vref_mv = 4096,
1367 .mode_list = max1238_mode_list,
1368 .num_modes = ARRAY_SIZE(max1238_mode_list),
1369 .default_mode = s0to11,
1370 .info = &max1238_info,
1371 .channels = max1238_channels,
1372 .num_channels = ARRAY_SIZE(max1238_channels),
1376 .int_vref_mv = 2048,
1377 .mode_list = max1238_mode_list,
1378 .num_modes = ARRAY_SIZE(max1238_mode_list),
1379 .default_mode = s0to11,
1380 .info = &max1238_info,
1381 .channels = max1238_channels,
1382 .num_channels = ARRAY_SIZE(max1238_channels),
1386 .int_vref_mv = 4096,
1387 .mode_list = max11644_mode_list,
1388 .num_modes = ARRAY_SIZE(max11644_mode_list),
1389 .default_mode = s0to1,
1390 .info = &max1238_info,
1391 .channels = max11644_channels,
1392 .num_channels = ARRAY_SIZE(max11644_channels),
1396 .int_vref_mv = 2048,
1397 .mode_list = max11644_mode_list,
1398 .num_modes = ARRAY_SIZE(max11644_mode_list),
1399 .default_mode = s0to1,
1400 .info = &max1238_info,
1401 .channels = max11644_channels,
1402 .num_channels = ARRAY_SIZE(max11644_channels),
1406 .int_vref_mv = 4096,
1407 .mode_list = max11644_mode_list,
1408 .num_modes = ARRAY_SIZE(max11644_mode_list),
1409 .default_mode = s0to1,
1410 .info = &max1238_info,
1411 .channels = max11646_channels,
1412 .num_channels = ARRAY_SIZE(max11646_channels),
1416 .int_vref_mv = 2048,
1417 .mode_list = max11644_mode_list,
1418 .num_modes = ARRAY_SIZE(max11644_mode_list),
1419 .default_mode = s0to1,
1420 .info = &max1238_info,
1421 .channels = max11646_channels,
1422 .num_channels = ARRAY_SIZE(max11646_channels),
1426 static int max1363_initial_setup(struct max1363_state *st)
1428 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1429 | MAX1363_SETUP_UNIPOLAR
1430 | MAX1363_SETUP_NORESET;
1433 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1435 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1436 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1438 /* Set scan mode writes the config anyway so wait until then */
1439 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1440 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1441 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1443 return max1363_set_scan_mode(st);
1446 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1448 struct max1363_state *st = iio_priv(indio_dev);
1449 unsigned long *masks;
1452 masks = devm_kzalloc(&indio_dev->dev,
1453 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1455 st->chip_info->num_modes + 1),
1460 for (i = 0; i < st->chip_info->num_modes; i++)
1461 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1462 max1363_mode_table[st->chip_info->mode_list[i]]
1463 .modemask, MAX1363_MAX_CHANNELS);
1465 indio_dev->available_scan_masks = masks;
1470 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1472 struct iio_poll_func *pf = p;
1473 struct iio_dev *indio_dev = pf->indio_dev;
1474 struct max1363_state *st = iio_priv(indio_dev);
1478 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1479 MAX1363_MAX_CHANNELS);
1481 /* Ensure the timestamp is 8 byte aligned */
1482 if (st->chip_info->bits != 8)
1486 if (indio_dev->scan_timestamp) {
1487 d_size += sizeof(s64);
1488 if (d_size % sizeof(s64))
1489 d_size += sizeof(s64) - (d_size % sizeof(s64));
1491 /* Monitor mode prevents reading. Whilst not currently implemented
1492 * might as well have this test in here in the meantime as it does
1498 rxbuf = kmalloc(d_size, GFP_KERNEL);
1501 if (st->chip_info->bits != 8)
1502 b_sent = st->recv(st->client, rxbuf, numvals * 2);
1504 b_sent = st->recv(st->client, rxbuf, numvals);
1508 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1509 iio_get_time_ns(indio_dev));
1514 iio_trigger_notify_done(indio_dev->trig);
1521 #define MAX1363_COMPATIBLE(of_compatible, cfg) { \
1522 .compatible = of_compatible, \
1523 .data = &max1363_chip_info_tbl[cfg], \
1526 static const struct of_device_id max1363_of_match[] = {
1527 MAX1363_COMPATIBLE("maxim,max1361", max1361),
1528 MAX1363_COMPATIBLE("maxim,max1362", max1362),
1529 MAX1363_COMPATIBLE("maxim,max1363", max1363),
1530 MAX1363_COMPATIBLE("maxim,max1364", max1364),
1531 MAX1363_COMPATIBLE("maxim,max1036", max1036),
1532 MAX1363_COMPATIBLE("maxim,max1037", max1037),
1533 MAX1363_COMPATIBLE("maxim,max1038", max1038),
1534 MAX1363_COMPATIBLE("maxim,max1039", max1039),
1535 MAX1363_COMPATIBLE("maxim,max1136", max1136),
1536 MAX1363_COMPATIBLE("maxim,max1137", max1137),
1537 MAX1363_COMPATIBLE("maxim,max1138", max1138),
1538 MAX1363_COMPATIBLE("maxim,max1139", max1139),
1539 MAX1363_COMPATIBLE("maxim,max1236", max1236),
1540 MAX1363_COMPATIBLE("maxim,max1237", max1237),
1541 MAX1363_COMPATIBLE("maxim,max1238", max1238),
1542 MAX1363_COMPATIBLE("maxim,max1239", max1239),
1543 MAX1363_COMPATIBLE("maxim,max11600", max11600),
1544 MAX1363_COMPATIBLE("maxim,max11601", max11601),
1545 MAX1363_COMPATIBLE("maxim,max11602", max11602),
1546 MAX1363_COMPATIBLE("maxim,max11603", max11603),
1547 MAX1363_COMPATIBLE("maxim,max11604", max11604),
1548 MAX1363_COMPATIBLE("maxim,max11605", max11605),
1549 MAX1363_COMPATIBLE("maxim,max11606", max11606),
1550 MAX1363_COMPATIBLE("maxim,max11607", max11607),
1551 MAX1363_COMPATIBLE("maxim,max11608", max11608),
1552 MAX1363_COMPATIBLE("maxim,max11609", max11609),
1553 MAX1363_COMPATIBLE("maxim,max11610", max11610),
1554 MAX1363_COMPATIBLE("maxim,max11611", max11611),
1555 MAX1363_COMPATIBLE("maxim,max11612", max11612),
1556 MAX1363_COMPATIBLE("maxim,max11613", max11613),
1557 MAX1363_COMPATIBLE("maxim,max11614", max11614),
1558 MAX1363_COMPATIBLE("maxim,max11615", max11615),
1559 MAX1363_COMPATIBLE("maxim,max11616", max11616),
1560 MAX1363_COMPATIBLE("maxim,max11617", max11617),
1561 MAX1363_COMPATIBLE("maxim,max11644", max11644),
1562 MAX1363_COMPATIBLE("maxim,max11645", max11645),
1563 MAX1363_COMPATIBLE("maxim,max11646", max11646),
1564 MAX1363_COMPATIBLE("maxim,max11647", max11647),
1567 MODULE_DEVICE_TABLE(of, max1363_of_match);
1570 static int max1363_probe(struct i2c_client *client,
1571 const struct i2c_device_id *id)
1574 struct max1363_state *st;
1575 struct iio_dev *indio_dev;
1576 struct regulator *vref;
1578 indio_dev = devm_iio_device_alloc(&client->dev,
1579 sizeof(struct max1363_state));
1583 indio_dev->dev.of_node = client->dev.of_node;
1584 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1588 st = iio_priv(indio_dev);
1590 st->reg = devm_regulator_get(&client->dev, "vcc");
1591 if (IS_ERR(st->reg)) {
1592 ret = PTR_ERR(st->reg);
1593 goto error_unregister_map;
1596 ret = regulator_enable(st->reg);
1598 goto error_unregister_map;
1600 /* this is only used for device removal purposes */
1601 i2c_set_clientdata(client, indio_dev);
1603 st->chip_info = of_device_get_match_data(&client->dev);
1605 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1606 st->client = client;
1608 st->vref_uv = st->chip_info->int_vref_mv * 1000;
1609 vref = devm_regulator_get_optional(&client->dev, "vref");
1610 if (!IS_ERR(vref)) {
1613 ret = regulator_enable(vref);
1615 goto error_disable_reg;
1617 vref_uv = regulator_get_voltage(vref);
1620 goto error_disable_reg;
1622 st->vref_uv = vref_uv;
1625 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1626 st->send = i2c_master_send;
1627 st->recv = i2c_master_recv;
1628 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1629 && st->chip_info->bits == 8) {
1630 st->send = max1363_smbus_send;
1631 st->recv = max1363_smbus_recv;
1634 goto error_disable_reg;
1637 ret = max1363_alloc_scan_masks(indio_dev);
1639 goto error_disable_reg;
1641 /* Establish that the iio_dev is a child of the i2c device */
1642 indio_dev->dev.parent = &client->dev;
1643 indio_dev->dev.of_node = client->dev.of_node;
1644 indio_dev->name = id->name;
1645 indio_dev->channels = st->chip_info->channels;
1646 indio_dev->num_channels = st->chip_info->num_channels;
1647 indio_dev->info = st->chip_info->info;
1648 indio_dev->modes = INDIO_DIRECT_MODE;
1649 ret = max1363_initial_setup(st);
1651 goto error_disable_reg;
1653 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1654 &max1363_trigger_handler, NULL);
1656 goto error_disable_reg;
1659 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1661 &max1363_event_handler,
1662 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1667 goto error_uninit_buffer;
1670 ret = iio_device_register(indio_dev);
1672 goto error_uninit_buffer;
1676 error_uninit_buffer:
1677 iio_triggered_buffer_cleanup(indio_dev);
1680 regulator_disable(st->vref);
1681 regulator_disable(st->reg);
1682 error_unregister_map:
1683 iio_map_array_unregister(indio_dev);
1687 static int max1363_remove(struct i2c_client *client)
1689 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1690 struct max1363_state *st = iio_priv(indio_dev);
1692 iio_device_unregister(indio_dev);
1693 iio_triggered_buffer_cleanup(indio_dev);
1695 regulator_disable(st->vref);
1696 regulator_disable(st->reg);
1697 iio_map_array_unregister(indio_dev);
1702 static const struct i2c_device_id max1363_id[] = {
1703 { "max1361", max1361 },
1704 { "max1362", max1362 },
1705 { "max1363", max1363 },
1706 { "max1364", max1364 },
1707 { "max1036", max1036 },
1708 { "max1037", max1037 },
1709 { "max1038", max1038 },
1710 { "max1039", max1039 },
1711 { "max1136", max1136 },
1712 { "max1137", max1137 },
1713 { "max1138", max1138 },
1714 { "max1139", max1139 },
1715 { "max1236", max1236 },
1716 { "max1237", max1237 },
1717 { "max1238", max1238 },
1718 { "max1239", max1239 },
1719 { "max11600", max11600 },
1720 { "max11601", max11601 },
1721 { "max11602", max11602 },
1722 { "max11603", max11603 },
1723 { "max11604", max11604 },
1724 { "max11605", max11605 },
1725 { "max11606", max11606 },
1726 { "max11607", max11607 },
1727 { "max11608", max11608 },
1728 { "max11609", max11609 },
1729 { "max11610", max11610 },
1730 { "max11611", max11611 },
1731 { "max11612", max11612 },
1732 { "max11613", max11613 },
1733 { "max11614", max11614 },
1734 { "max11615", max11615 },
1735 { "max11616", max11616 },
1736 { "max11617", max11617 },
1737 { "max11644", max11644 },
1738 { "max11645", max11645 },
1739 { "max11646", max11646 },
1740 { "max11647", max11647 },
1744 MODULE_DEVICE_TABLE(i2c, max1363_id);
1746 static struct i2c_driver max1363_driver = {
1749 .of_match_table = of_match_ptr(max1363_of_match),
1751 .probe = max1363_probe,
1752 .remove = max1363_remove,
1753 .id_table = max1363_id,
1755 module_i2c_driver(max1363_driver);
1757 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1758 MODULE_DESCRIPTION("Maxim 1363 ADC");
1759 MODULE_LICENSE("GPL v2");