drivers/iio/adc/palmas_gpadc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * palmas-adc.c -- TI PALMAS GPADC.
   4  *
   5  * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
   6  *
   7  * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/err.h>
  12 #include <linux/irq.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/i2c.h>
  18 #include <linux/pm.h>
  19 #include <linux/mfd/palmas.h>
  20 #include <linux/completion.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/iio/iio.h>
  24 #include <linux/iio/machine.h>
  25 #include <linux/iio/driver.h>
  26
  27 #define MOD_NAME "palmas-gpadc"
  28 #define PALMAS_ADC_CONVERSION_TIMEOUT   (msecs_to_jiffies(5000))
  29 #define PALMAS_TO_BE_CALCULATED 0
  30 #define PALMAS_GPADC_TRIMINVALID        -1
  31
  32 struct palmas_gpadc_info {
  33 /* calibration codes and regs */
  34         int x1; /* lower ideal code */
  35         int x2; /* higher ideal code */
  36         int v1; /* expected lower volt reading */
  37         int v2; /* expected higher volt reading */
  38         u8 trim1_reg;   /* register number for lower trim */
  39         u8 trim2_reg;   /* register number for upper trim */
  40         int gain;       /* calculated from above (after reading trim regs) */
  41         int offset;     /* calculated from above (after reading trim regs) */
  42         int gain_error; /* calculated from above (after reading trim regs) */
  43         bool is_uncalibrated;   /* if channel has calibration data */
  44 };
  45
  46 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \
  47         [PALMAS_ADC_CH_##_chan] = { \
  48                 .x1 = _x1, \
  49                 .x2 = _x2, \
  50                 .v1 = _v1, \
  51                 .v2 = _v2, \
  52                 .gain = PALMAS_TO_BE_CALCULATED, \
  53                 .offset = PALMAS_TO_BE_CALCULATED, \
  54                 .gain_error = PALMAS_TO_BE_CALCULATED, \
  55                 .trim1_reg = PALMAS_GPADC_TRIM##_t1, \
  56                 .trim2_reg = PALMAS_GPADC_TRIM##_t2,  \
  57                 .is_uncalibrated = _is_uncalibrated \
  58         }
  59
  60 static struct palmas_gpadc_info palmas_gpadc_info[] = {
  61         PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false),
  62         PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false),
  63         PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false),
  64         PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false),
  65         PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false),
  66         PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false),
  67         PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false),
  68         PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false),
  69         PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false),
  70         PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false),
  71         PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false),
  72         PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true),
  73         PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true),
  74         PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true),
  75         PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false),
  76         PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true),
  77 };
  78
  79 /**
  80  * struct palmas_gpadc - the palmas_gpadc structure
  81  * @ch0_current:        channel 0 current source setting
  82  *                      0: 0 uA
  83  *                      1: 5 uA
  84  *                      2: 15 uA
  85  *                      3: 20 uA
  86  * @ch3_current:        channel 0 current source setting
  87  *                      0: 0 uA
  88  *                      1: 10 uA
  89  *                      2: 400 uA
  90  *                      3: 800 uA
  91  * @extended_delay:     enable the gpadc extended delay mode
  92  * @auto_conversion_period:     define the auto_conversion_period
  93  *
  94  * This is the palmas_gpadc structure to store run-time information
  95  * and pointers for this driver instance.
  96  */
  97
  98 struct palmas_gpadc {
  99         struct device                   *dev;
 100         struct palmas                   *palmas;
 101         u8                              ch0_current;
 102         u8                              ch3_current;
 103         bool                            extended_delay;
 104         int                             irq;
 105         int                             irq_auto_0;
 106         int                             irq_auto_1;
 107         struct palmas_gpadc_info        *adc_info;
 108         struct completion               conv_completion;
 109         struct palmas_adc_wakeup_property wakeup1_data;
 110         struct palmas_adc_wakeup_property wakeup2_data;
 111         bool                            wakeup1_enable;
 112         bool                            wakeup2_enable;
 113         int                             auto_conversion_period;
 114 };
 115
 116 /*
 117  * GPADC lock issue in AUTO mode.
 118  * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
 119  *         mode feature.
 120  * Details:
 121  *      When the AUTO mode is the only conversion mode enabled, if the AUTO
 122  *      mode feature is disabled with bit GPADC_AUTO_CTRL.  AUTO_CONV1_EN = 0
 123  *      or bit GPADC_AUTO_CTRL.  AUTO_CONV0_EN = 0 during a conversion, the
 124  *      conversion mechanism can be seen as locked meaning that all following
 125  *      conversion will give 0 as a result.  Bit GPADC_STATUS.GPADC_AVAILABLE
 126  *      will stay at 0 meaning that GPADC is busy.  An RT conversion can unlock
 127  *      the GPADC.
 128  *
 129  * Workaround(s):
 130  *      To avoid the lock mechanism, the workaround to follow before any stop
 131  *      conversion request is:
 132  *      Force the GPADC state machine to be ON by using the GPADC_CTRL1.
 133  *              GPADC_FORCE bit = 1
 134  *      Shutdown the GPADC AUTO conversion using
 135  *              GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
 136  *      After 100us, force the GPADC state machine to be OFF by using the
 137  *              GPADC_CTRL1.  GPADC_FORCE bit = 0
 138  */
 139
 140 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
 141 {
 142         int ret;
 143
 144         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 145                         PALMAS_GPADC_CTRL1,
 146                         PALMAS_GPADC_CTRL1_GPADC_FORCE,
 147                         PALMAS_GPADC_CTRL1_GPADC_FORCE);
 148         if (ret < 0) {
 149                 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
 150                 return ret;
 151         }
 152
 153         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 154                         PALMAS_GPADC_AUTO_CTRL,
 155                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
 156                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
 157                         0);
 158         if (ret < 0) {
 159                 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
 160                 return ret;
 161         }
 162
 163         udelay(100);
 164
 165         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 166                         PALMAS_GPADC_CTRL1,
 167                         PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
 168         if (ret < 0)
 169                 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
 170
 171         return ret;
 172 }
 173
 174 static irqreturn_t palmas_gpadc_irq(int irq, void *data)
 175 {
 176         struct palmas_gpadc *adc = data;
 177
 178         complete(&adc->conv_completion);
 179
 180         return IRQ_HANDLED;
 181 }
 182
 183 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
 184 {
 185         struct palmas_gpadc *adc = data;
 186
 187         dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq);
 188         palmas_disable_auto_conversion(adc);
 189
 190         return IRQ_HANDLED;
 191 }
 192
 193 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc,
 194                                                 bool mask)
 195 {
 196         int ret;
 197
 198         if (!mask)
 199                 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
 200                                         PALMAS_INT3_MASK,
 201                                         PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
 202         else
 203                 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
 204                                         PALMAS_INT3_MASK,
 205                                         PALMAS_INT3_MASK_GPADC_EOC_SW,
 206                                         PALMAS_INT3_MASK_GPADC_EOC_SW);
 207         if (ret < 0)
 208                 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
 209
 210         return ret;
 211 }
 212
 213 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
 214                                int enable)
 215 {
 216         unsigned int mask, val;
 217         int ret;
 218
 219         if (enable) {
 220                 val = (adc->extended_delay
 221                         << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
 222                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 223                                         PALMAS_GPADC_RT_CTRL,
 224                                         PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
 225                 if (ret < 0) {
 226                         dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
 227                         return ret;
 228                 }
 229
 230                 mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
 231                         PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
 232                         PALMAS_GPADC_CTRL1_GPADC_FORCE);
 233                 val = (adc->ch0_current
 234                         << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
 235                 val |= (adc->ch3_current
 236                         << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
 237                 val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
 238                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 239                                 PALMAS_GPADC_CTRL1, mask, val);
 240                 if (ret < 0) {
 241                         dev_err(adc->dev,
 242                                 "Failed to update current setting: %d\n", ret);
 243                         return ret;
 244                 }
 245
 246                 mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
 247                         PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
 248                 val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
 249                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 250                                 PALMAS_GPADC_SW_SELECT, mask, val);
 251                 if (ret < 0) {
 252                         dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
 253                         return ret;
 254                 }
 255         } else {
 256                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 257                                 PALMAS_GPADC_SW_SELECT, 0);
 258                 if (ret < 0)
 259                         dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
 260
 261                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 262                                 PALMAS_GPADC_CTRL1,
 263                                 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
 264                 if (ret < 0) {
 265                         dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
 266                         return ret;
 267                 }
 268         }
 269
 270         return ret;
 271 }
 272
 273 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
 274 {
 275         int ret;
 276
 277         ret = palmas_gpadc_enable(adc, adc_chan, true);
 278         if (ret < 0)
 279                 return ret;
 280
 281         return palmas_gpadc_start_mask_interrupt(adc, 0);
 282 }
 283
 284 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
 285 {
 286         palmas_gpadc_start_mask_interrupt(adc, 1);
 287         palmas_gpadc_enable(adc, adc_chan, false);
 288 }
 289
 290 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
 291 {
 292         int k;
 293         int d1;
 294         int d2;
 295         int ret;
 296         int gain;
 297         int x1 =  adc->adc_info[adc_chan].x1;
 298         int x2 =  adc->adc_info[adc_chan].x2;
 299         int v1 = adc->adc_info[adc_chan].v1;
 300         int v2 = adc->adc_info[adc_chan].v2;
 301
 302         ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
 303                                 adc->adc_info[adc_chan].trim1_reg, &d1);
 304         if (ret < 0) {
 305                 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
 306                 goto scrub;
 307         }
 308
 309         ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
 310                                 adc->adc_info[adc_chan].trim2_reg, &d2);
 311         if (ret < 0) {
 312                 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
 313                 goto scrub;
 314         }
 315
 316         /* gain error calculation */
 317         k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
 318
 319         /* gain calculation */
 320         gain = ((v2 - v1) * 1000) / (x2 - x1);
 321
 322         adc->adc_info[adc_chan].gain_error = k;
 323         adc->adc_info[adc_chan].gain = gain;
 324         /* offset Calculation */
 325         adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
 326
 327 scrub:
 328         return ret;
 329 }
 330
 331 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan)
 332 {
 333         unsigned int val;
 334         int ret;
 335
 336         init_completion(&adc->conv_completion);
 337         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 338                                 PALMAS_GPADC_SW_SELECT,
 339                                 PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
 340                                 PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
 341         if (ret < 0) {
 342                 dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret);
 343                 return ret;
 344         }
 345
 346         ret = wait_for_completion_timeout(&adc->conv_completion,
 347                                 PALMAS_ADC_CONVERSION_TIMEOUT);
 348         if (ret == 0) {
 349                 dev_err(adc->dev, "conversion not completed\n");
 350                 return -ETIMEDOUT;
 351         }
 352
 353         ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
 354                                 PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
 355         if (ret < 0) {
 356                 dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret);
 357                 return ret;
 358         }
 359
 360         ret = val & 0xFFF;
 361
 362         return ret;
 363 }
 364
 365 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
 366                                                 int adc_chan, int val)
 367 {
 368         if (!adc->adc_info[adc_chan].is_uncalibrated)
 369                 val  = (val*1000 - adc->adc_info[adc_chan].offset) /
 370                                         adc->adc_info[adc_chan].gain_error;
 371
 372         if (val < 0) {
 373                 dev_err(adc->dev, "Mismatch with calibration\n");
 374                 return 0;
 375         }
 376
 377         val = (val * adc->adc_info[adc_chan].gain) / 1000;
 378
 379         return val;
 380 }
 381
 382 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
 383         struct iio_chan_spec const *chan, int *val, int *val2, long mask)
 384 {
 385         struct  palmas_gpadc *adc = iio_priv(indio_dev);
 386         int adc_chan = chan->channel;
 387         int ret = 0;
 388
 389         if (adc_chan > PALMAS_ADC_CH_MAX)
 390                 return -EINVAL;
 391
 392         mutex_lock(&indio_dev->mlock);
 393
 394         switch (mask) {
 395         case IIO_CHAN_INFO_RAW:
 396         case IIO_CHAN_INFO_PROCESSED:
 397                 ret = palmas_gpadc_read_prepare(adc, adc_chan);
 398                 if (ret < 0)
 399                         goto out;
 400
 401                 ret = palmas_gpadc_start_conversion(adc, adc_chan);
 402                 if (ret < 0) {
 403                         dev_err(adc->dev,
 404                         "ADC start conversion failed\n");
 405                         goto out;
 406                 }
 407
 408                 if (mask == IIO_CHAN_INFO_PROCESSED)
 409                         ret = palmas_gpadc_get_calibrated_code(
 410                                                         adc, adc_chan, ret);
 411
 412                 *val = ret;
 413
 414                 ret = IIO_VAL_INT;
 415                 goto out;
 416         }
 417
 418         mutex_unlock(&indio_dev->mlock);
 419         return ret;
 420
 421 out:
 422         palmas_gpadc_read_done(adc, adc_chan);
 423         mutex_unlock(&indio_dev->mlock);
 424
 425         return ret;
 426 }
 427
 428 static const struct iio_info palmas_gpadc_iio_info = {
 429         .read_raw = palmas_gpadc_read_raw,
 430 };
 431
 432 #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info)     \
 433 {                                                       \
 434         .datasheet_name = PALMAS_DATASHEET_NAME(chan),  \
 435         .type = _type,                                  \
 436         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
 437                         BIT(chan_info),                 \
 438         .indexed = 1,                                   \
 439         .channel = PALMAS_ADC_CH_##chan,                \
 440 }
 441
 442 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
 443         PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 444         PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW),
 445         PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 446         PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW),
 447         PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 448         PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 449         PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 450         PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 451         PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 452         PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 453         PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 454         PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 455         PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW),
 456         PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW),
 457         PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 458         PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 459 };
 460
 461 static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev,
 462         struct palmas_gpadc_platform_data **gpadc_pdata)
 463 {
 464         struct device_node *np = pdev->dev.of_node;
 465         struct palmas_gpadc_platform_data *gp_data;
 466         int ret;
 467         u32 pval;
 468
 469         gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL);
 470         if (!gp_data)
 471                 return -ENOMEM;
 472
 473         ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval);
 474         if (!ret)
 475                 gp_data->ch0_current = pval;
 476
 477         ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval);
 478         if (!ret)
 479                 gp_data->ch3_current = pval;
 480
 481         gp_data->extended_delay = of_property_read_bool(np,
 482                                         "ti,enable-extended-delay");
 483
 484         *gpadc_pdata = gp_data;
 485
 486         return 0;
 487 }
 488
 489 static int palmas_gpadc_probe(struct platform_device *pdev)
 490 {
 491         struct palmas_gpadc *adc;
 492         struct palmas_platform_data *pdata;
 493         struct palmas_gpadc_platform_data *gpadc_pdata = NULL;
 494         struct iio_dev *indio_dev;
 495         int ret, i;
 496
 497         pdata = dev_get_platdata(pdev->dev.parent);
 498
 499         if (pdata && pdata->gpadc_pdata)
 500                 gpadc_pdata = pdata->gpadc_pdata;
 501
 502         if (!gpadc_pdata && pdev->dev.of_node) {
 503                 ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata);
 504                 if (ret < 0)
 505                         return ret;
 506         }
 507         if (!gpadc_pdata)
 508                 return -EINVAL;
 509
 510         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
 511         if (!indio_dev) {
 512                 dev_err(&pdev->dev, "iio_device_alloc failed\n");
 513                 return -ENOMEM;
 514         }
 515
 516         adc = iio_priv(indio_dev);
 517         adc->dev = &pdev->dev;
 518         adc->palmas = dev_get_drvdata(pdev->dev.parent);
 519         adc->adc_info = palmas_gpadc_info;
 520         init_completion(&adc->conv_completion);
 521         dev_set_drvdata(&pdev->dev, indio_dev);
 522
 523         adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms;
 524         adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
 525         if (adc->irq < 0) {
 526                 dev_err(adc->dev,
 527                         "get virq failed: %d\n", adc->irq);
 528                 ret = adc->irq;
 529                 goto out;
 530         }
 531         ret = request_threaded_irq(adc->irq, NULL,
 532                 palmas_gpadc_irq,
 533                 IRQF_ONESHOT, dev_name(adc->dev),
 534                 adc);
 535         if (ret < 0) {
 536                 dev_err(adc->dev,
 537                         "request irq %d failed: %d\n", adc->irq, ret);
 538                 goto out;
 539         }
 540
 541         if (gpadc_pdata->adc_wakeup1_data) {
 542                 memcpy(&adc->wakeup1_data, gpadc_pdata->adc_wakeup1_data,
 543                         sizeof(adc->wakeup1_data));
 544                 adc->wakeup1_enable = true;
 545                 adc->irq_auto_0 =  platform_get_irq(pdev, 1);
 546                 ret = request_threaded_irq(adc->irq_auto_0, NULL,
 547                                 palmas_gpadc_irq_auto,
 548                                 IRQF_ONESHOT,
 549                                 "palmas-adc-auto-0", adc);
 550                 if (ret < 0) {
 551                         dev_err(adc->dev, "request auto0 irq %d failed: %d\n",
 552                                 adc->irq_auto_0, ret);
 553                         goto out_irq_free;
 554                 }
 555         }
 556
 557         if (gpadc_pdata->adc_wakeup2_data) {
 558                 memcpy(&adc->wakeup2_data, gpadc_pdata->adc_wakeup2_data,
 559                                 sizeof(adc->wakeup2_data));
 560                 adc->wakeup2_enable = true;
 561                 adc->irq_auto_1 =  platform_get_irq(pdev, 2);
 562                 ret = request_threaded_irq(adc->irq_auto_1, NULL,
 563                                 palmas_gpadc_irq_auto,
 564                                 IRQF_ONESHOT,
 565                                 "palmas-adc-auto-1", adc);
 566                 if (ret < 0) {
 567                         dev_err(adc->dev, "request auto1 irq %d failed: %d\n",
 568                                 adc->irq_auto_1, ret);
 569                         goto out_irq_auto0_free;
 570                 }
 571         }
 572
 573         /* set the current source 0 (value 0/5/15/20 uA => 0..3) */
 574         if (gpadc_pdata->ch0_current <= 1)
 575                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
 576         else if (gpadc_pdata->ch0_current <= 5)
 577                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
 578         else if (gpadc_pdata->ch0_current <= 15)
 579                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
 580         else
 581                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
 582
 583         /* set the current source 3 (value 0/10/400/800 uA => 0..3) */
 584         if (gpadc_pdata->ch3_current <= 1)
 585                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
 586         else if (gpadc_pdata->ch3_current <= 10)
 587                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
 588         else if (gpadc_pdata->ch3_current <= 400)
 589                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
 590         else
 591                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
 592
 593         adc->extended_delay = gpadc_pdata->extended_delay;
 594
 595         indio_dev->name = MOD_NAME;
 596         indio_dev->dev.parent = &pdev->dev;
 597         indio_dev->info = &palmas_gpadc_iio_info;
 598         indio_dev->modes = INDIO_DIRECT_MODE;
 599         indio_dev->channels = palmas_gpadc_iio_channel;
 600         indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
 601
 602         ret = iio_device_register(indio_dev);
 603         if (ret < 0) {
 604                 dev_err(adc->dev, "iio_device_register() failed: %d\n", ret);
 605                 goto out_irq_auto1_free;
 606         }
 607
 608         device_set_wakeup_capable(&pdev->dev, 1);
 609         for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
 610                 if (!(adc->adc_info[i].is_uncalibrated))
 611                         palmas_gpadc_calibrate(adc, i);
 612         }
 613
 614         if (adc->wakeup1_enable || adc->wakeup2_enable)
 615                 device_wakeup_enable(&pdev->dev);
 616
 617         return 0;
 618
 619 out_irq_auto1_free:
 620         if (gpadc_pdata->adc_wakeup2_data)
 621                 free_irq(adc->irq_auto_1, adc);
 622 out_irq_auto0_free:
 623         if (gpadc_pdata->adc_wakeup1_data)
 624                 free_irq(adc->irq_auto_0, adc);
 625 out_irq_free:
 626         free_irq(adc->irq, adc);
 627 out:
 628         return ret;
 629 }
 630
 631 static int palmas_gpadc_remove(struct platform_device *pdev)
 632 {
 633         struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev);
 634         struct palmas_gpadc *adc = iio_priv(indio_dev);
 635
 636         if (adc->wakeup1_enable || adc->wakeup2_enable)
 637                 device_wakeup_disable(&pdev->dev);
 638         iio_device_unregister(indio_dev);
 639         free_irq(adc->irq, adc);
 640         if (adc->wakeup1_enable)
 641                 free_irq(adc->irq_auto_0, adc);
 642         if (adc->wakeup2_enable)
 643                 free_irq(adc->irq_auto_1, adc);
 644
 645         return 0;
 646 }
 647
 648 #ifdef CONFIG_PM_SLEEP
 649 static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc)
 650 {
 651         int adc_period, conv;
 652         int i;
 653         int ch0 = 0, ch1 = 0;
 654         int thres;
 655         int ret;
 656
 657         adc_period = adc->auto_conversion_period;
 658         for (i = 0; i < 16; ++i) {
 659                 if (((1000 * (1 << i)) / 32) < adc_period)
 660                         continue;
 661         }
 662         if (i > 0)
 663                 i--;
 664         adc_period = i;
 665         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 666                         PALMAS_GPADC_AUTO_CTRL,
 667                         PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
 668                         adc_period);
 669         if (ret < 0) {
 670                 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
 671                 return ret;
 672         }
 673
 674         conv = 0;
 675         if (adc->wakeup1_enable) {
 676                 int polarity;
 677
 678                 ch0 = adc->wakeup1_data.adc_channel_number;
 679                 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
 680                 if (adc->wakeup1_data.adc_high_threshold > 0) {
 681                         thres = adc->wakeup1_data.adc_high_threshold;
 682                         polarity = 0;
 683                 } else {
 684                         thres = adc->wakeup1_data.adc_low_threshold;
 685                         polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL;
 686                 }
 687
 688                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 689                                 PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
 690                 if (ret < 0) {
 691                         dev_err(adc->dev,
 692                                 "THRES_CONV0_LSB write failed: %d\n", ret);
 693                         return ret;
 694                 }
 695
 696                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 697                                 PALMAS_GPADC_THRES_CONV0_MSB,
 698                                 ((thres >> 8) & 0xF) | polarity);
 699                 if (ret < 0) {
 700                         dev_err(adc->dev,
 701                                 "THRES_CONV0_MSB write failed: %d\n", ret);
 702                         return ret;
 703                 }
 704         }
 705
 706         if (adc->wakeup2_enable) {
 707                 int polarity;
 708
 709                 ch1 = adc->wakeup2_data.adc_channel_number;
 710                 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
 711                 if (adc->wakeup2_data.adc_high_threshold > 0) {
 712                         thres = adc->wakeup2_data.adc_high_threshold;
 713                         polarity = 0;
 714                 } else {
 715                         thres = adc->wakeup2_data.adc_low_threshold;
 716                         polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL;
 717                 }
 718
 719                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 720                                 PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
 721                 if (ret < 0) {
 722                         dev_err(adc->dev,
 723                                 "THRES_CONV1_LSB write failed: %d\n", ret);
 724                         return ret;
 725                 }
 726
 727                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 728                                 PALMAS_GPADC_THRES_CONV1_MSB,
 729                                 ((thres >> 8) & 0xF) | polarity);
 730                 if (ret < 0) {
 731                         dev_err(adc->dev,
 732                                 "THRES_CONV1_MSB write failed: %d\n", ret);
 733                         return ret;
 734                 }
 735         }
 736
 737         ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 738                         PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
 739         if (ret < 0) {
 740                 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
 741                 return ret;
 742         }
 743
 744         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 745                         PALMAS_GPADC_AUTO_CTRL,
 746                         PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
 747                         PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
 748         if (ret < 0)
 749                 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
 750
 751         return ret;
 752 }
 753
 754 static int palmas_adc_wakeup_reset(struct palmas_gpadc *adc)
 755 {
 756         int ret;
 757
 758         ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 759                         PALMAS_GPADC_AUTO_SELECT, 0);
 760         if (ret < 0) {
 761                 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
 762                 return ret;
 763         }
 764
 765         ret = palmas_disable_auto_conversion(adc);
 766         if (ret < 0)
 767                 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
 768
 769         return ret;
 770 }
 771
 772 static int palmas_gpadc_suspend(struct device *dev)
 773 {
 774         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 775         struct palmas_gpadc *adc = iio_priv(indio_dev);
 776         int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
 777         int ret;
 778
 779         if (!device_may_wakeup(dev) || !wakeup)
 780                 return 0;
 781
 782         ret = palmas_adc_wakeup_configure(adc);
 783         if (ret < 0)
 784                 return ret;
 785
 786         if (adc->wakeup1_enable)
 787                 enable_irq_wake(adc->irq_auto_0);
 788
 789         if (adc->wakeup2_enable)
 790                 enable_irq_wake(adc->irq_auto_1);
 791
 792         return 0;
 793 }
 794
 795 static int palmas_gpadc_resume(struct device *dev)
 796 {
 797         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 798         struct palmas_gpadc *adc = iio_priv(indio_dev);
 799         int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
 800         int ret;
 801
 802         if (!device_may_wakeup(dev) || !wakeup)
 803                 return 0;
 804
 805         ret = palmas_adc_wakeup_reset(adc);
 806         if (ret < 0)
 807                 return ret;
 808
 809         if (adc->wakeup1_enable)
 810                 disable_irq_wake(adc->irq_auto_0);
 811
 812         if (adc->wakeup2_enable)
 813                 disable_irq_wake(adc->irq_auto_1);
 814
 815         return 0;
 816 };
 817 #endif
 818
 819 static const struct dev_pm_ops palmas_pm_ops = {
 820         SET_SYSTEM_SLEEP_PM_OPS(palmas_gpadc_suspend,
 821                                 palmas_gpadc_resume)
 822 };
 823
 824 static const struct of_device_id of_palmas_gpadc_match_tbl[] = {
 825         { .compatible = "ti,palmas-gpadc", },
 826         { /* end */ }
 827 };
 828 MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl);
 829
 830 static struct platform_driver palmas_gpadc_driver = {
 831         .probe = palmas_gpadc_probe,
 832         .remove = palmas_gpadc_remove,
 833         .driver = {
 834                 .name = MOD_NAME,
 835                 .pm = &palmas_pm_ops,
 836                 .of_match_table = of_palmas_gpadc_match_tbl,
 837         },
 838 };
 839
 840 static int __init palmas_gpadc_init(void)
 841 {
 842         return platform_driver_register(&palmas_gpadc_driver);
 843 }
 844 module_init(palmas_gpadc_init);
 845
 846 static void __exit palmas_gpadc_exit(void)
 847 {
 848         platform_driver_unregister(&palmas_gpadc_driver);
 849 }
 850 module_exit(palmas_gpadc_exit);
 851
 852 MODULE_DESCRIPTION("palmas GPADC driver");
 853 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>");
 854 MODULE_ALIAS("platform:palmas-gpadc");
 855 MODULE_LICENSE("GPL v2");