drivers/iio/adc/qcom-spmi-adc5.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/completion.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/iio/iio.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel.h>
  13 #include <linux/log2.h>
  14 #include <linux/math64.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19 #include <linux/slab.h>
  20
  21 #include <dt-bindings/iio/qcom,spmi-vadc.h>
  22 #include "qcom-vadc-common.h"
  23
  24 #define ADC5_USR_REVISION1                      0x0
  25 #define ADC5_USR_STATUS1                        0x8
  26 #define ADC5_USR_STATUS1_REQ_STS                BIT(1)
  27 #define ADC5_USR_STATUS1_EOC                    BIT(0)
  28 #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK       0x3
  29
  30 #define ADC5_USR_STATUS2                        0x9
  31 #define ADC5_USR_STATUS2_CONV_SEQ_MASK          0x70
  32 #define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT    0x5
  33
  34 #define ADC5_USR_IBAT_MEAS                      0xf
  35 #define ADC5_USR_IBAT_MEAS_SUPPORTED            BIT(0)
  36
  37 #define ADC5_USR_DIG_PARAM                      0x42
  38 #define ADC5_USR_DIG_PARAM_CAL_VAL              BIT(6)
  39 #define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT        6
  40 #define ADC5_USR_DIG_PARAM_CAL_SEL              0x30
  41 #define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT        4
  42 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL        0xc
  43 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT  2
  44
  45 #define ADC5_USR_FAST_AVG_CTL                   0x43
  46 #define ADC5_USR_FAST_AVG_CTL_EN                BIT(7)
  47 #define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK      0x7
  48
  49 #define ADC5_USR_CH_SEL_CTL                     0x44
  50
  51 #define ADC5_USR_DELAY_CTL                      0x45
  52 #define ADC5_USR_HW_SETTLE_DELAY_MASK           0xf
  53
  54 #define ADC5_USR_EN_CTL1                        0x46
  55 #define ADC5_USR_EN_CTL1_ADC_EN                 BIT(7)
  56
  57 #define ADC5_USR_CONV_REQ                       0x47
  58 #define ADC5_USR_CONV_REQ_REQ                   BIT(7)
  59
  60 #define ADC5_USR_DATA0                          0x50
  61
  62 #define ADC5_USR_DATA1                          0x51
  63
  64 #define ADC5_USR_IBAT_DATA0                     0x52
  65
  66 #define ADC5_USR_IBAT_DATA1                     0x53
  67
  68 /*
  69  * Conversion time varies based on the decimation, clock rate, fast average
  70  * samples and measurements queued across different VADC peripherals.
  71  * Set the timeout to a max of 100ms.
  72  */
  73 #define ADC5_CONV_TIME_MIN_US                   263
  74 #define ADC5_CONV_TIME_MAX_US                   264
  75 #define ADC5_CONV_TIME_RETRY                    400
  76 #define ADC5_CONV_TIMEOUT                       msecs_to_jiffies(100)
  77
  78 /* Digital version >= 5.3 supports hw_settle_2 */
  79 #define ADC5_HW_SETTLE_DIFF_MINOR               3
  80 #define ADC5_HW_SETTLE_DIFF_MAJOR               5
  81
  82 enum adc5_cal_method {
  83         ADC5_NO_CAL = 0,
  84         ADC5_RATIOMETRIC_CAL,
  85         ADC5_ABSOLUTE_CAL
  86 };
  87
  88 enum adc5_cal_val {
  89         ADC5_TIMER_CAL = 0,
  90         ADC5_NEW_CAL
  91 };
  92
  93 /**
  94  * struct adc5_channel_prop - ADC channel property.
  95  * @channel: channel number, refer to the channel list.
  96  * @cal_method: calibration method.
  97  * @cal_val: calibration value
  98  * @decimation: sampling rate supported for the channel.
  99  * @prescale: channel scaling performed on the input signal.
 100  * @hw_settle_time: the time between AMUX being configured and the
 101  *      start of conversion.
 102  * @avg_samples: ability to provide single result from the ADC
 103  *      that is an average of multiple measurements.
 104  * @scale_fn_type: Represents the scaling function to convert voltage
 105  *      physical units desired by the client for the channel.
 106  * @datasheet_name: Channel name used in device tree.
 107  */
 108 struct adc5_channel_prop {
 109         unsigned int            channel;
 110         enum adc5_cal_method    cal_method;
 111         enum adc5_cal_val       cal_val;
 112         unsigned int            decimation;
 113         unsigned int            prescale;
 114         unsigned int            hw_settle_time;
 115         unsigned int            avg_samples;
 116         enum vadc_scale_fn_type scale_fn_type;
 117         const char              *datasheet_name;
 118 };
 119
 120 /**
 121  * struct adc5_chip - ADC private structure.
 122  * @regmap: SPMI ADC5 peripheral register map field.
 123  * @dev: SPMI ADC5 device.
 124  * @base: base address for the ADC peripheral.
 125  * @nchannels: number of ADC channels.
 126  * @chan_props: array of ADC channel properties.
 127  * @iio_chans: array of IIO channels specification.
 128  * @poll_eoc: use polling instead of interrupt.
 129  * @complete: ADC result notification after interrupt is received.
 130  * @lock: ADC lock for access to the peripheral.
 131  * @data: software configuration data.
 132  */
 133 struct adc5_chip {
 134         struct regmap           *regmap;
 135         struct device           *dev;
 136         u16                     base;
 137         unsigned int            nchannels;
 138         struct adc5_channel_prop        *chan_props;
 139         struct iio_chan_spec    *iio_chans;
 140         bool                    poll_eoc;
 141         struct completion       complete;
 142         struct mutex            lock;
 143         const struct adc5_data  *data;
 144 };
 145
 146 static const struct vadc_prescale_ratio adc5_prescale_ratios[] = {
 147         {.num =  1, .den =  1},
 148         {.num =  1, .den =  3},
 149         {.num =  1, .den =  4},
 150         {.num =  1, .den =  6},
 151         {.num =  1, .den = 20},
 152         {.num =  1, .den =  8},
 153         {.num = 10, .den = 81},
 154         {.num =  1, .den = 10},
 155         {.num =  1, .den = 16}
 156 };
 157
 158 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
 159 {
 160         return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
 161 }
 162
 163 static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
 164 {
 165         return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
 166 }
 167
 168 static int adc5_prescaling_from_dt(u32 num, u32 den)
 169 {
 170         unsigned int pre;
 171
 172         for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++)
 173                 if (adc5_prescale_ratios[pre].num == num &&
 174                     adc5_prescale_ratios[pre].den == den)
 175                         break;
 176
 177         if (pre == ARRAY_SIZE(adc5_prescale_ratios))
 178                 return -EINVAL;
 179
 180         return pre;
 181 }
 182
 183 static int adc5_hw_settle_time_from_dt(u32 value,
 184                                         const unsigned int *hw_settle)
 185 {
 186         unsigned int i;
 187
 188         for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) {
 189                 if (value == hw_settle[i])
 190                         return i;
 191         }
 192
 193         return -EINVAL;
 194 }
 195
 196 static int adc5_avg_samples_from_dt(u32 value)
 197 {
 198         if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX)
 199                 return -EINVAL;
 200
 201         return __ffs(value);
 202 }
 203
 204 static int adc5_decimation_from_dt(u32 value,
 205                                         const unsigned int *decimation)
 206 {
 207         unsigned int i;
 208
 209         for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) {
 210                 if (value == decimation[i])
 211                         return i;
 212         }
 213
 214         return -EINVAL;
 215 }
 216
 217 static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
 218 {
 219         int ret;
 220         u8 rslt_lsb, rslt_msb;
 221
 222         ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
 223         if (ret)
 224                 return ret;
 225
 226         ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
 227         if (ret)
 228                 return ret;
 229
 230         *data = (rslt_msb << 8) | rslt_lsb;
 231
 232         if (*data == ADC5_USR_DATA_CHECK) {
 233                 pr_err("Invalid data:0x%x\n", *data);
 234                 return -EINVAL;
 235         }
 236
 237         pr_debug("voltage raw code:0x%x\n", *data);
 238
 239         return 0;
 240 }
 241
 242 static int adc5_poll_wait_eoc(struct adc5_chip *adc)
 243 {
 244         unsigned int count, retry = ADC5_CONV_TIME_RETRY;
 245         u8 status1;
 246         int ret;
 247
 248         for (count = 0; count < retry; count++) {
 249                 ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
 250                                                         sizeof(status1));
 251                 if (ret)
 252                         return ret;
 253
 254                 status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK;
 255                 if (status1 == ADC5_USR_STATUS1_EOC)
 256                         return 0;
 257
 258                 usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US);
 259         }
 260
 261         return -ETIMEDOUT;
 262 }
 263
 264 static void adc5_update_dig_param(struct adc5_chip *adc,
 265                         struct adc5_channel_prop *prop, u8 *data)
 266 {
 267         /* Update calibration value */
 268         *data &= ~ADC5_USR_DIG_PARAM_CAL_VAL;
 269         *data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT);
 270
 271         /* Update calibration select */
 272         *data &= ~ADC5_USR_DIG_PARAM_CAL_SEL;
 273         *data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT);
 274
 275         /* Update decimation ratio select */
 276         *data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL;
 277         *data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT);
 278 }
 279
 280 static int adc5_configure(struct adc5_chip *adc,
 281                         struct adc5_channel_prop *prop)
 282 {
 283         int ret;
 284         u8 buf[6];
 285
 286         /* Read registers 0x42 through 0x46 */
 287         ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
 288         if (ret < 0)
 289                 return ret;
 290
 291         /* Digital param selection */
 292         adc5_update_dig_param(adc, prop, &buf[0]);
 293
 294         /* Update fast average sample value */
 295         buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
 296         buf[1] |= prop->avg_samples;
 297
 298         /* Select ADC channel */
 299         buf[2] = prop->channel;
 300
 301         /* Select HW settle delay for channel */
 302         buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK;
 303         buf[3] |= prop->hw_settle_time;
 304
 305         /* Select ADC enable */
 306         buf[4] |= ADC5_USR_EN_CTL1_ADC_EN;
 307
 308         /* Select CONV request */
 309         buf[5] |= ADC5_USR_CONV_REQ_REQ;
 310
 311         if (!adc->poll_eoc)
 312                 reinit_completion(&adc->complete);
 313
 314         return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
 315 }
 316
 317 static int adc5_do_conversion(struct adc5_chip *adc,
 318                         struct adc5_channel_prop *prop,
 319                         struct iio_chan_spec const *chan,
 320                         u16 *data_volt, u16 *data_cur)
 321 {
 322         int ret;
 323
 324         mutex_lock(&adc->lock);
 325
 326         ret = adc5_configure(adc, prop);
 327         if (ret) {
 328                 pr_err("ADC configure failed with %d\n", ret);
 329                 goto unlock;
 330         }
 331
 332         if (adc->poll_eoc) {
 333                 ret = adc5_poll_wait_eoc(adc);
 334                 if (ret < 0) {
 335                         pr_err("EOC bit not set\n");
 336                         goto unlock;
 337                 }
 338         } else {
 339                 ret = wait_for_completion_timeout(&adc->complete,
 340                                                         ADC5_CONV_TIMEOUT);
 341                 if (!ret) {
 342                         pr_debug("Did not get completion timeout.\n");
 343                         ret = adc5_poll_wait_eoc(adc);
 344                         if (ret < 0) {
 345                                 pr_err("EOC bit not set\n");
 346                                 goto unlock;
 347                         }
 348                 }
 349         }
 350
 351         ret = adc5_read_voltage_data(adc, data_volt);
 352 unlock:
 353         mutex_unlock(&adc->lock);
 354
 355         return ret;
 356 }
 357
 358 static irqreturn_t adc5_isr(int irq, void *dev_id)
 359 {
 360         struct adc5_chip *adc = dev_id;
 361
 362         complete(&adc->complete);
 363
 364         return IRQ_HANDLED;
 365 }
 366
 367 static int adc5_of_xlate(struct iio_dev *indio_dev,
 368                                 const struct of_phandle_args *iiospec)
 369 {
 370         struct adc5_chip *adc = iio_priv(indio_dev);
 371         int i;
 372
 373         for (i = 0; i < adc->nchannels; i++)
 374                 if (adc->chan_props[i].channel == iiospec->args[0])
 375                         return i;
 376
 377         return -EINVAL;
 378 }
 379
 380 static int adc5_read_raw(struct iio_dev *indio_dev,
 381                          struct iio_chan_spec const *chan, int *val, int *val2,
 382                          long mask)
 383 {
 384         struct adc5_chip *adc = iio_priv(indio_dev);
 385         struct adc5_channel_prop *prop;
 386         u16 adc_code_volt, adc_code_cur;
 387         int ret;
 388
 389         prop = &adc->chan_props[chan->address];
 390
 391         switch (mask) {
 392         case IIO_CHAN_INFO_PROCESSED:
 393                 ret = adc5_do_conversion(adc, prop, chan,
 394                                 &adc_code_volt, &adc_code_cur);
 395                 if (ret)
 396                         return ret;
 397
 398                 ret = qcom_adc5_hw_scale(prop->scale_fn_type,
 399                         &adc5_prescale_ratios[prop->prescale],
 400                         adc->data,
 401                         adc_code_volt, val);
 402                 if (ret)
 403                         return ret;
 404
 405                 return IIO_VAL_INT;
 406         default:
 407                 return -EINVAL;
 408         }
 409
 410         return 0;
 411 }
 412
 413 static const struct iio_info adc5_info = {
 414         .read_raw = adc5_read_raw,
 415         .of_xlate = adc5_of_xlate,
 416 };
 417
 418 struct adc5_channels {
 419         const char *datasheet_name;
 420         unsigned int prescale_index;
 421         enum iio_chan_type type;
 422         long info_mask;
 423         enum vadc_scale_fn_type scale_fn_type;
 424 };
 425
 426 /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
 427 #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale)                   \
 428         {                                                               \
 429                 .datasheet_name = _dname,                               \
 430                 .prescale_index = _pre,                                 \
 431                 .type = _type,                                          \
 432                 .info_mask = _mask,                                     \
 433                 .scale_fn_type = _scale,                                \
 434         },                                                              \
 435
 436 #define ADC5_CHAN_TEMP(_dname, _pre, _scale)                            \
 437         ADC5_CHAN(_dname, IIO_TEMP,                                     \
 438                 BIT(IIO_CHAN_INFO_PROCESSED),                           \
 439                 _pre, _scale)                                           \
 440
 441 #define ADC5_CHAN_VOLT(_dname, _pre, _scale)                            \
 442         ADC5_CHAN(_dname, IIO_VOLTAGE,                                  \
 443                   BIT(IIO_CHAN_INFO_PROCESSED),                         \
 444                   _pre, _scale)                                         \
 445
 446 static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
 447         [ADC5_REF_GND]          = ADC5_CHAN_VOLT("ref_gnd", 0,
 448                                         SCALE_HW_CALIB_DEFAULT)
 449         [ADC5_1P25VREF]         = ADC5_CHAN_VOLT("vref_1p25", 0,
 450                                         SCALE_HW_CALIB_DEFAULT)
 451         [ADC5_VPH_PWR]          = ADC5_CHAN_VOLT("vph_pwr", 1,
 452                                         SCALE_HW_CALIB_DEFAULT)
 453         [ADC5_VBAT_SNS]         = ADC5_CHAN_VOLT("vbat_sns", 1,
 454                                         SCALE_HW_CALIB_DEFAULT)
 455         [ADC5_DIE_TEMP]         = ADC5_CHAN_TEMP("die_temp", 0,
 456                                         SCALE_HW_CALIB_PMIC_THERM)
 457         [ADC5_USB_IN_I]         = ADC5_CHAN_VOLT("usb_in_i_uv", 0,
 458                                         SCALE_HW_CALIB_DEFAULT)
 459         [ADC5_USB_IN_V_16]      = ADC5_CHAN_VOLT("usb_in_v_div_16", 8,
 460                                         SCALE_HW_CALIB_DEFAULT)
 461         [ADC5_CHG_TEMP]         = ADC5_CHAN_TEMP("chg_temp", 0,
 462                                         SCALE_HW_CALIB_PM5_CHG_TEMP)
 463         /* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */
 464         [ADC5_SBUx]             = ADC5_CHAN_VOLT("chg_sbux", 1,
 465                                         SCALE_HW_CALIB_DEFAULT)
 466         [ADC5_MID_CHG_DIV6]     = ADC5_CHAN_VOLT("chg_mid_chg", 3,
 467                                         SCALE_HW_CALIB_DEFAULT)
 468         [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0,
 469                                         SCALE_HW_CALIB_XOTHERM)
 470         [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
 471                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 472         [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
 473                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 474         [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
 475                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 476         [ADC5_AMUX_THM2]        = ADC5_CHAN_TEMP("amux_thm2", 0,
 477                                         SCALE_HW_CALIB_PM5_SMB_TEMP)
 478 };
 479
 480 static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
 481         [ADC5_REF_GND]          = ADC5_CHAN_VOLT("ref_gnd", 0,
 482                                         SCALE_HW_CALIB_DEFAULT)
 483         [ADC5_1P25VREF]         = ADC5_CHAN_VOLT("vref_1p25", 0,
 484                                         SCALE_HW_CALIB_DEFAULT)
 485         [ADC5_VPH_PWR]          = ADC5_CHAN_VOLT("vph_pwr", 1,
 486                                         SCALE_HW_CALIB_DEFAULT)
 487         [ADC5_VBAT_SNS]         = ADC5_CHAN_VOLT("vbat_sns", 1,
 488                                         SCALE_HW_CALIB_DEFAULT)
 489         [ADC5_VCOIN]            = ADC5_CHAN_VOLT("vcoin", 1,
 490                                         SCALE_HW_CALIB_DEFAULT)
 491         [ADC5_DIE_TEMP]         = ADC5_CHAN_TEMP("die_temp", 0,
 492                                         SCALE_HW_CALIB_PMIC_THERM)
 493         [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
 494                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 495         [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
 496                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 497         [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
 498                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 499         [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
 500                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 501         [ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 0,
 502                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 503         [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 0,
 504                                         SCALE_HW_CALIB_THERM_100K_PULLUP)
 505 };
 506
 507 static int adc5_get_dt_channel_data(struct adc5_chip *adc,
 508                                     struct adc5_channel_prop *prop,
 509                                     struct device_node *node,
 510                                     const struct adc5_data *data)
 511 {
 512         const char *name = node->name, *channel_name;
 513         u32 chan, value, varr[2];
 514         int ret;
 515         struct device *dev = adc->dev;
 516
 517         ret = of_property_read_u32(node, "reg", &chan);
 518         if (ret) {
 519                 dev_err(dev, "invalid channel number %s\n", name);
 520                 return ret;
 521         }
 522
 523         if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA ||
 524             !data->adc_chans[chan].datasheet_name) {
 525                 dev_err(dev, "%s invalid channel number %d\n", name, chan);
 526                 return -EINVAL;
 527         }
 528
 529         /* the channel has DT description */
 530         prop->channel = chan;
 531
 532         channel_name = of_get_property(node,
 533                                 "label", NULL) ? : node->name;
 534         if (!channel_name) {
 535                 pr_err("Invalid channel name\n");
 536                 return -EINVAL;
 537         }
 538         prop->datasheet_name = channel_name;
 539
 540         ret = of_property_read_u32(node, "qcom,decimation", &value);
 541         if (!ret) {
 542                 ret = adc5_decimation_from_dt(value, data->decimation);
 543                 if (ret < 0) {
 544                         dev_err(dev, "%02x invalid decimation %d\n",
 545                                 chan, value);
 546                         return ret;
 547                 }
 548                 prop->decimation = ret;
 549         } else {
 550                 prop->decimation = ADC5_DECIMATION_DEFAULT;
 551         }
 552
 553         ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
 554         if (!ret) {
 555                 ret = adc5_prescaling_from_dt(varr[0], varr[1]);
 556                 if (ret < 0) {
 557                         dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
 558                                 chan, varr[0], varr[1]);
 559                         return ret;
 560                 }
 561                 prop->prescale = ret;
 562         } else {
 563                 prop->prescale =
 564                         adc->data->adc_chans[prop->channel].prescale_index;
 565         }
 566
 567         ret = of_property_read_u32(node, "qcom,hw-settle-time", &value);
 568         if (!ret) {
 569                 u8 dig_version[2];
 570
 571                 ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
 572                                                         sizeof(dig_version));
 573                 if (ret < 0) {
 574                         dev_err(dev, "Invalid dig version read %d\n", ret);
 575                         return ret;
 576                 }
 577
 578                 pr_debug("dig_ver:minor:%d, major:%d\n", dig_version[0],
 579                                                 dig_version[1]);
 580                 /* Digital controller >= 5.3 have hw_settle_2 option */
 581                 if (dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
 582                         dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR)
 583                         ret = adc5_hw_settle_time_from_dt(value,
 584                                                         data->hw_settle_2);
 585                 else
 586                         ret = adc5_hw_settle_time_from_dt(value,
 587                                                         data->hw_settle_1);
 588
 589                 if (ret < 0) {
 590                         dev_err(dev, "%02x invalid hw-settle-time %d us\n",
 591                                 chan, value);
 592                         return ret;
 593                 }
 594                 prop->hw_settle_time = ret;
 595         } else {
 596                 prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
 597         }
 598
 599         ret = of_property_read_u32(node, "qcom,avg-samples", &value);
 600         if (!ret) {
 601                 ret = adc5_avg_samples_from_dt(value);
 602                 if (ret < 0) {
 603                         dev_err(dev, "%02x invalid avg-samples %d\n",
 604                                 chan, value);
 605                         return ret;
 606                 }
 607                 prop->avg_samples = ret;
 608         } else {
 609                 prop->avg_samples = VADC_DEF_AVG_SAMPLES;
 610         }
 611
 612         if (of_property_read_bool(node, "qcom,ratiometric"))
 613                 prop->cal_method = ADC5_RATIOMETRIC_CAL;
 614         else
 615                 prop->cal_method = ADC5_ABSOLUTE_CAL;
 616
 617         /*
 618          * Default to using timer calibration. Using a fresh calibration value
 619          * for every conversion will increase the overall time for a request.
 620          */
 621         prop->cal_val = ADC5_TIMER_CAL;
 622
 623         dev_dbg(dev, "%02x name %s\n", chan, name);
 624
 625         return 0;
 626 }
 627
 628 static const struct adc5_data adc5_data_pmic = {
 629         .full_scale_code_volt = 0x70e4,
 630         .full_scale_code_cur = 0x2710,
 631         .adc_chans = adc5_chans_pmic,
 632         .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
 633                                 {250, 420, 840},
 634         .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
 635                                 {15, 100, 200, 300, 400, 500, 600, 700,
 636                                 800, 900, 1, 2, 4, 6, 8, 10},
 637         .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
 638                                 {15, 100, 200, 300, 400, 500, 600, 700,
 639                                 1, 2, 4, 8, 16, 32, 64, 128},
 640 };
 641
 642 static const struct adc5_data adc5_data_pmic_rev2 = {
 643         .full_scale_code_volt = 0x4000,
 644         .full_scale_code_cur = 0x1800,
 645         .adc_chans = adc5_chans_rev2,
 646         .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
 647                                 {256, 512, 1024},
 648         .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
 649                                 {0, 100, 200, 300, 400, 500, 600, 700,
 650                                 800, 900, 1, 2, 4, 6, 8, 10},
 651         .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
 652                                 {15, 100, 200, 300, 400, 500, 600, 700,
 653                                 1, 2, 4, 8, 16, 32, 64, 128},
 654 };
 655
 656 static const struct of_device_id adc5_match_table[] = {
 657         {
 658                 .compatible = "qcom,spmi-adc5",
 659                 .data = &adc5_data_pmic,
 660         },
 661         {
 662                 .compatible = "qcom,spmi-adc-rev2",
 663                 .data = &adc5_data_pmic_rev2,
 664         },
 665         { }
 666 };
 667 MODULE_DEVICE_TABLE(of, adc5_match_table);
 668
 669 static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
 670 {
 671         const struct adc5_channels *adc_chan;
 672         struct iio_chan_spec *iio_chan;
 673         struct adc5_channel_prop prop, *chan_props;
 674         struct device_node *child;
 675         unsigned int index = 0;
 676         const struct of_device_id *id;
 677         const struct adc5_data *data;
 678         int ret;
 679
 680         adc->nchannels = of_get_available_child_count(node);
 681         if (!adc->nchannels)
 682                 return -EINVAL;
 683
 684         adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
 685                                        sizeof(*adc->iio_chans), GFP_KERNEL);
 686         if (!adc->iio_chans)
 687                 return -ENOMEM;
 688
 689         adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
 690                                         sizeof(*adc->chan_props), GFP_KERNEL);
 691         if (!adc->chan_props)
 692                 return -ENOMEM;
 693
 694         chan_props = adc->chan_props;
 695         iio_chan = adc->iio_chans;
 696         id = of_match_node(adc5_match_table, node);
 697         if (id)
 698                 data = id->data;
 699         else
 700                 data = &adc5_data_pmic;
 701         adc->data = data;
 702
 703         for_each_available_child_of_node(node, child) {
 704                 ret = adc5_get_dt_channel_data(adc, &prop, child, data);
 705                 if (ret) {
 706                         of_node_put(child);
 707                         return ret;
 708                 }
 709
 710                 prop.scale_fn_type =
 711                         data->adc_chans[prop.channel].scale_fn_type;
 712                 *chan_props = prop;
 713                 adc_chan = &data->adc_chans[prop.channel];
 714
 715                 iio_chan->channel = prop.channel;
 716                 iio_chan->datasheet_name = prop.datasheet_name;
 717                 iio_chan->extend_name = prop.datasheet_name;
 718                 iio_chan->info_mask_separate = adc_chan->info_mask;
 719                 iio_chan->type = adc_chan->type;
 720                 iio_chan->address = index;
 721                 iio_chan++;
 722                 chan_props++;
 723                 index++;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int adc5_probe(struct platform_device *pdev)
 730 {
 731         struct device_node *node = pdev->dev.of_node;
 732         struct device *dev = &pdev->dev;
 733         struct iio_dev *indio_dev;
 734         struct adc5_chip *adc;
 735         struct regmap *regmap;
 736         int ret, irq_eoc;
 737         u32 reg;
 738
 739         regmap = dev_get_regmap(dev->parent, NULL);
 740         if (!regmap)
 741                 return -ENODEV;
 742
 743         ret = of_property_read_u32(node, "reg", &reg);
 744         if (ret < 0)
 745                 return ret;
 746
 747         indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
 748         if (!indio_dev)
 749                 return -ENOMEM;
 750
 751         adc = iio_priv(indio_dev);
 752         adc->regmap = regmap;
 753         adc->dev = dev;
 754         adc->base = reg;
 755         init_completion(&adc->complete);
 756         mutex_init(&adc->lock);
 757
 758         ret = adc5_get_dt_data(adc, node);
 759         if (ret) {
 760                 pr_err("adc get dt data failed\n");
 761                 return ret;
 762         }
 763
 764         irq_eoc = platform_get_irq(pdev, 0);
 765         if (irq_eoc < 0) {
 766                 if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
 767                         return irq_eoc;
 768                 adc->poll_eoc = true;
 769         } else {
 770                 ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0,
 771                                        "pm-adc5", adc);
 772                 if (ret)
 773                         return ret;
 774         }
 775
 776         indio_dev->dev.parent = dev;
 777         indio_dev->dev.of_node = node;
 778         indio_dev->name = pdev->name;
 779         indio_dev->modes = INDIO_DIRECT_MODE;
 780         indio_dev->info = &adc5_info;
 781         indio_dev->channels = adc->iio_chans;
 782         indio_dev->num_channels = adc->nchannels;
 783
 784         return devm_iio_device_register(dev, indio_dev);
 785 }
 786
 787 static struct platform_driver adc5_driver = {
 788         .driver = {
 789                 .name = "qcom-spmi-adc5.c",
 790                 .of_match_table = adc5_match_table,
 791         },
 792         .probe = adc5_probe,
 793 };
 794 module_platform_driver(adc5_driver);
 795
 796 MODULE_ALIAS("platform:qcom-spmi-adc5");
 797 MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver");
 798 MODULE_LICENSE("GPL v2");