1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012 Stefan Roese <sr@denx.de>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/interrupt.h>
11 #include <linux/device.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/completion.h>
19 #include <linux/of_address.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
24 /* SPEAR registers definitions */
25 #define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF)
26 #define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF)
27 #define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0)
28 #define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4)
30 /* Bit definitions for SPEAR_ADC_STATUS */
31 #define SPEAR_ADC_STATUS_START_CONVERSION BIT(0)
32 #define SPEAR_ADC_STATUS_CHANNEL_NUM(x) ((x) << 1)
33 #define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4)
34 #define SPEAR_ADC_STATUS_AVG_SAMPLE(x) ((x) << 5)
35 #define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9)
37 #define SPEAR_ADC_DATA_MASK 0x03ff
38 #define SPEAR_ADC_DATA_BITS 10
40 #define SPEAR_ADC_MOD_NAME "spear-adc"
42 #define SPEAR_ADC_CHANNEL_NUM 8
44 #define SPEAR_ADC_CLK_MIN 2500000
45 #define SPEAR_ADC_CLK_MAX 20000000
47 struct adc_regs_spear3xx {
51 u32 clk; /* Not avail for 1340 & 1310 */
52 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
53 u32 ch_data[SPEAR_ADC_CHANNEL_NUM];
61 struct adc_regs_spear6xx {
65 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
66 struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM];
69 struct chan_data average;
72 struct spear_adc_state {
73 struct device_node *np;
74 struct adc_regs_spear3xx __iomem *adc_base_spear3xx;
75 struct adc_regs_spear6xx __iomem *adc_base_spear6xx;
77 struct completion completion;
86 * Functions to access some SPEAr ADC register. Abstracted into
87 * static inline functions, because of different register offsets
88 * on different SoC variants (SPEAr300 vs SPEAr600 etc).
90 static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
92 __raw_writel(val, &st->adc_base_spear6xx->status);
95 static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
97 u32 clk_high, clk_low, count;
98 u32 apb_clk = clk_get_rate(st->clk);
100 count = DIV_ROUND_UP(apb_clk, val);
102 clk_high = count - clk_low;
103 st->current_clk = apb_clk / count;
105 __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
106 &st->adc_base_spear6xx->clk);
109 static void spear_adc_set_ctrl(struct spear_adc_state *st, int n,
112 __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
115 static u32 spear_adc_get_average(struct spear_adc_state *st)
117 if (of_device_is_compatible(st->np, "st,spear600-adc")) {
118 return __raw_readl(&st->adc_base_spear6xx->average.msb) &
121 return __raw_readl(&st->adc_base_spear3xx->average) &
126 static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate)
128 if (of_device_is_compatible(st->np, "st,spear600-adc")) {
129 __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
130 &st->adc_base_spear6xx->scan_rate_lo);
131 __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
132 &st->adc_base_spear6xx->scan_rate_hi);
134 __raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
138 static int spear_adc_read_raw(struct iio_dev *indio_dev,
139 struct iio_chan_spec const *chan,
144 struct spear_adc_state *st = iio_priv(indio_dev);
148 case IIO_CHAN_INFO_RAW:
149 mutex_lock(&indio_dev->mlock);
151 status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) |
152 SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) |
153 SPEAR_ADC_STATUS_START_CONVERSION |
154 SPEAR_ADC_STATUS_ADC_ENABLE;
155 if (st->vref_external == 0)
156 status |= SPEAR_ADC_STATUS_VREF_INTERNAL;
158 spear_adc_set_status(st, status);
159 wait_for_completion(&st->completion); /* set by ISR */
162 mutex_unlock(&indio_dev->mlock);
166 case IIO_CHAN_INFO_SCALE:
167 *val = st->vref_external;
168 *val2 = SPEAR_ADC_DATA_BITS;
169 return IIO_VAL_FRACTIONAL_LOG2;
170 case IIO_CHAN_INFO_SAMP_FREQ:
171 *val = st->current_clk;
178 static int spear_adc_write_raw(struct iio_dev *indio_dev,
179 struct iio_chan_spec const *chan,
184 struct spear_adc_state *st = iio_priv(indio_dev);
187 if (mask != IIO_CHAN_INFO_SAMP_FREQ)
190 mutex_lock(&indio_dev->mlock);
192 if ((val < SPEAR_ADC_CLK_MIN) ||
193 (val > SPEAR_ADC_CLK_MAX) ||
199 spear_adc_set_clk(st, val);
202 mutex_unlock(&indio_dev->mlock);
206 #define SPEAR_ADC_CHAN(idx) { \
207 .type = IIO_VOLTAGE, \
209 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
210 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
211 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
215 static const struct iio_chan_spec spear_adc_iio_channels[] = {
226 static irqreturn_t spear_adc_isr(int irq, void *dev_id)
228 struct spear_adc_state *st = dev_id;
230 /* Read value to clear IRQ */
231 st->value = spear_adc_get_average(st);
232 complete(&st->completion);
237 static int spear_adc_configure(struct spear_adc_state *st)
242 spear_adc_set_status(st, 0);
243 __raw_writel(0, &st->adc_base_spear6xx->clk);
244 for (i = 0; i < 8; i++)
245 spear_adc_set_ctrl(st, i, 0);
246 spear_adc_set_scanrate(st, 0);
248 spear_adc_set_clk(st, st->sampling_freq);
253 static const struct iio_info spear_adc_info = {
254 .read_raw = &spear_adc_read_raw,
255 .write_raw = &spear_adc_write_raw,
258 static int spear_adc_probe(struct platform_device *pdev)
260 struct device_node *np = pdev->dev.of_node;
261 struct device *dev = &pdev->dev;
262 struct spear_adc_state *st;
263 struct iio_dev *indio_dev = NULL;
267 indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state));
269 dev_err(dev, "failed allocating iio device\n");
273 st = iio_priv(indio_dev);
277 * SPEAr600 has a different register layout than other SPEAr SoC's
278 * (e.g. SPEAr3xx). Let's provide two register base addresses
279 * to support multi-arch kernels.
281 st->adc_base_spear6xx = devm_platform_ioremap_resource(pdev, 0);
282 if (IS_ERR(st->adc_base_spear6xx))
283 return PTR_ERR(st->adc_base_spear6xx);
285 st->adc_base_spear3xx =
286 (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
288 st->clk = devm_clk_get(dev, NULL);
289 if (IS_ERR(st->clk)) {
290 dev_err(dev, "failed getting clock\n");
291 return PTR_ERR(st->clk);
294 ret = clk_prepare_enable(st->clk);
296 dev_err(dev, "failed enabling clock\n");
300 irq = platform_get_irq(pdev, 0);
306 ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
309 dev_err(dev, "failed requesting interrupt\n");
313 if (of_property_read_u32(np, "sampling-frequency",
314 &st->sampling_freq)) {
315 dev_err(dev, "sampling-frequency missing in DT\n");
321 * Optional avg_samples defaults to 0, resulting in single data
324 of_property_read_u32(np, "average-samples", &st->avg_samples);
327 * Optional vref_external defaults to 0, resulting in internal vref
330 of_property_read_u32(np, "vref-external", &st->vref_external);
332 spear_adc_configure(st);
334 platform_set_drvdata(pdev, indio_dev);
336 init_completion(&st->completion);
338 indio_dev->name = SPEAR_ADC_MOD_NAME;
339 indio_dev->dev.parent = dev;
340 indio_dev->info = &spear_adc_info;
341 indio_dev->modes = INDIO_DIRECT_MODE;
342 indio_dev->channels = spear_adc_iio_channels;
343 indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels);
345 ret = iio_device_register(indio_dev);
349 dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
354 clk_disable_unprepare(st->clk);
358 static int spear_adc_remove(struct platform_device *pdev)
360 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
361 struct spear_adc_state *st = iio_priv(indio_dev);
363 iio_device_unregister(indio_dev);
364 clk_disable_unprepare(st->clk);
370 static const struct of_device_id spear_adc_dt_ids[] = {
371 { .compatible = "st,spear600-adc", },
374 MODULE_DEVICE_TABLE(of, spear_adc_dt_ids);
377 static struct platform_driver spear_adc_driver = {
378 .probe = spear_adc_probe,
379 .remove = spear_adc_remove,
381 .name = SPEAR_ADC_MOD_NAME,
382 .of_match_table = of_match_ptr(spear_adc_dt_ids),
386 module_platform_driver(spear_adc_driver);
388 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
389 MODULE_DESCRIPTION("SPEAr ADC driver");
390 MODULE_LICENSE("GPL");