2 * This file is part of STM32 ADC driver
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 * Inspired from: fsl-imx25-tsadc
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 * or FITNESS FOR A PARTICULAR PURPOSE.
18 * See the GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <linux/clk.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/irqdesc.h>
28 #include <linux/irqdomain.h>
29 #include <linux/module.h>
30 #include <linux/of_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/slab.h>
34 #include "stm32-adc-core.h"
36 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
37 #define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
38 #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
40 /* STM32F4_ADC_CSR - bit fields */
41 #define STM32F4_EOC3 BIT(17)
42 #define STM32F4_EOC2 BIT(9)
43 #define STM32F4_EOC1 BIT(1)
45 /* STM32F4_ADC_CCR - bit fields */
46 #define STM32F4_ADC_ADCPRE_SHIFT 16
47 #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
49 /* STM32 F4 maximum analog clock rate (from datasheet) */
50 #define STM32F4_ADC_MAX_CLK_RATE 36000000
52 /* STM32H7 - common registers for all ADC instances */
53 #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
54 #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
56 /* STM32H7_ADC_CSR - bit fields */
57 #define STM32H7_EOC_SLV BIT(18)
58 #define STM32H7_EOC_MST BIT(2)
60 /* STM32H7_ADC_CCR - bit fields */
61 #define STM32H7_PRESC_SHIFT 18
62 #define STM32H7_PRESC_MASK GENMASK(21, 18)
63 #define STM32H7_CKMODE_SHIFT 16
64 #define STM32H7_CKMODE_MASK GENMASK(17, 16)
66 /* STM32 H7 maximum analog clock rate (from datasheet) */
67 #define STM32H7_ADC_MAX_CLK_RATE 36000000
70 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
71 * @csr: common status register offset
72 * @eoc1: adc1 end of conversion flag in @csr
73 * @eoc2: adc2 end of conversion flag in @csr
74 * @eoc3: adc3 end of conversion flag in @csr
76 struct stm32_adc_common_regs {
83 struct stm32_adc_priv;
86 * stm32_adc_priv_cfg - stm32 core compatible configuration data
87 * @regs: common registers for all instances
88 * @clk_sel: clock selection routine
90 struct stm32_adc_priv_cfg {
91 const struct stm32_adc_common_regs *regs;
92 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
96 * struct stm32_adc_priv - stm32 ADC core private data
97 * @irq: irq for ADC block
98 * @domain: irq domain reference
99 * @aclk: clock reference for the analog circuitry
100 * @bclk: bus clock common for all ADCs, depends on part used
101 * @vref: regulator reference
102 * @cfg: compatible configuration data
103 * @common: common data for all ADC instances
105 struct stm32_adc_priv {
107 struct irq_domain *domain;
110 struct regulator *vref;
111 const struct stm32_adc_priv_cfg *cfg;
112 struct stm32_adc_common common;
115 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
117 return container_of(com, struct stm32_adc_priv, common);
120 /* STM32F4 ADC internal common clock prescaler division ratios */
121 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
124 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
125 * @priv: stm32 ADC core private data
126 * Select clock prescaler used for analog conversions, before using ADC.
128 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
129 struct stm32_adc_priv *priv)
135 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
137 dev_err(&pdev->dev, "No 'adc' clock found\n");
141 rate = clk_get_rate(priv->aclk);
143 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
147 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
148 if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
151 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
152 dev_err(&pdev->dev, "adc clk selection failed\n");
156 priv->common.rate = rate / stm32f4_pclk_div[i];
157 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
158 val &= ~STM32F4_ADC_ADCPRE_MASK;
159 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
160 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
162 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
163 priv->common.rate / 1000);
169 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
170 * @ckmode: ADC clock mode, Async or sync with prescaler.
171 * @presc: prescaler bitfield for async clock mode
172 * @div: prescaler division ratio
174 struct stm32h7_adc_ck_spec {
180 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
181 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
194 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
200 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
201 struct stm32_adc_priv *priv)
203 u32 ckmode, presc, val;
207 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
209 dev_err(&pdev->dev, "No 'bus' clock found\n");
214 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
215 * So, choice is to have bus clock mandatory and adc clock optional.
216 * If optional 'adc' clock has been found, then try to use it first.
220 * Asynchronous clock modes (e.g. ckmode == 0)
221 * From spec: PLL output musn't exceed max rate
223 rate = clk_get_rate(priv->aclk);
225 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
229 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
230 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
231 presc = stm32h7_adc_ckmodes_spec[i].presc;
232 div = stm32h7_adc_ckmodes_spec[i].div;
237 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
242 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
243 rate = clk_get_rate(priv->bclk);
245 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
249 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
250 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
251 presc = stm32h7_adc_ckmodes_spec[i].presc;
252 div = stm32h7_adc_ckmodes_spec[i].div;
257 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
261 dev_err(&pdev->dev, "adc clk selection failed\n");
265 /* rate used later by each ADC instance to control BOOST mode */
266 priv->common.rate = rate / div;
268 /* Set common clock mode and prescaler */
269 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
270 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
271 val |= ckmode << STM32H7_CKMODE_SHIFT;
272 val |= presc << STM32H7_PRESC_SHIFT;
273 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
275 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
276 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
281 /* STM32F4 common registers definitions */
282 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
283 .csr = STM32F4_ADC_CSR,
284 .eoc1_msk = STM32F4_EOC1,
285 .eoc2_msk = STM32F4_EOC2,
286 .eoc3_msk = STM32F4_EOC3,
289 /* STM32H7 common registers definitions */
290 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
291 .csr = STM32H7_ADC_CSR,
292 .eoc1_msk = STM32H7_EOC_MST,
293 .eoc2_msk = STM32H7_EOC_SLV,
296 /* ADC common interrupt for all instances */
297 static void stm32_adc_irq_handler(struct irq_desc *desc)
299 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
300 struct irq_chip *chip = irq_desc_get_chip(desc);
303 chained_irq_enter(chip, desc);
304 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
306 if (status & priv->cfg->regs->eoc1_msk)
307 generic_handle_irq(irq_find_mapping(priv->domain, 0));
309 if (status & priv->cfg->regs->eoc2_msk)
310 generic_handle_irq(irq_find_mapping(priv->domain, 1));
312 if (status & priv->cfg->regs->eoc3_msk)
313 generic_handle_irq(irq_find_mapping(priv->domain, 2));
315 chained_irq_exit(chip, desc);
318 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
319 irq_hw_number_t hwirq)
321 irq_set_chip_data(irq, d->host_data);
322 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
327 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
329 irq_set_chip_and_handler(irq, NULL, NULL);
330 irq_set_chip_data(irq, NULL);
333 static const struct irq_domain_ops stm32_adc_domain_ops = {
334 .map = stm32_adc_domain_map,
335 .unmap = stm32_adc_domain_unmap,
336 .xlate = irq_domain_xlate_onecell,
339 static int stm32_adc_irq_probe(struct platform_device *pdev,
340 struct stm32_adc_priv *priv)
342 struct device_node *np = pdev->dev.of_node;
344 priv->irq = platform_get_irq(pdev, 0);
346 dev_err(&pdev->dev, "failed to get irq\n");
350 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
351 &stm32_adc_domain_ops,
354 dev_err(&pdev->dev, "Failed to add irq domain\n");
358 irq_set_chained_handler(priv->irq, stm32_adc_irq_handler);
359 irq_set_handler_data(priv->irq, priv);
364 static void stm32_adc_irq_remove(struct platform_device *pdev,
365 struct stm32_adc_priv *priv)
369 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
370 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
371 irq_domain_remove(priv->domain);
372 irq_set_chained_handler(priv->irq, NULL);
375 static int stm32_adc_probe(struct platform_device *pdev)
377 struct stm32_adc_priv *priv;
378 struct device *dev = &pdev->dev;
379 struct device_node *np = pdev->dev.of_node;
380 struct resource *res;
383 if (!pdev->dev.of_node)
386 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
390 priv->cfg = (const struct stm32_adc_priv_cfg *)
391 of_match_device(dev->driver->of_match_table, dev)->data;
393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
394 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
395 if (IS_ERR(priv->common.base))
396 return PTR_ERR(priv->common.base);
397 priv->common.phys_base = res->start;
399 priv->vref = devm_regulator_get(&pdev->dev, "vref");
400 if (IS_ERR(priv->vref)) {
401 ret = PTR_ERR(priv->vref);
402 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
406 ret = regulator_enable(priv->vref);
408 dev_err(&pdev->dev, "vref enable failed\n");
412 ret = regulator_get_voltage(priv->vref);
414 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
415 goto err_regulator_disable;
417 priv->common.vref_mv = ret / 1000;
418 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
420 priv->aclk = devm_clk_get(&pdev->dev, "adc");
421 if (IS_ERR(priv->aclk)) {
422 ret = PTR_ERR(priv->aclk);
423 if (ret == -ENOENT) {
426 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
427 goto err_regulator_disable;
432 ret = clk_prepare_enable(priv->aclk);
434 dev_err(&pdev->dev, "adc clk enable failed\n");
435 goto err_regulator_disable;
439 priv->bclk = devm_clk_get(&pdev->dev, "bus");
440 if (IS_ERR(priv->bclk)) {
441 ret = PTR_ERR(priv->bclk);
442 if (ret == -ENOENT) {
445 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
446 goto err_aclk_disable;
451 ret = clk_prepare_enable(priv->bclk);
453 dev_err(&pdev->dev, "adc clk enable failed\n");
454 goto err_aclk_disable;
458 ret = priv->cfg->clk_sel(pdev, priv);
460 goto err_bclk_disable;
462 ret = stm32_adc_irq_probe(pdev, priv);
464 goto err_bclk_disable;
466 platform_set_drvdata(pdev, &priv->common);
468 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
470 dev_err(&pdev->dev, "failed to populate DT children\n");
477 stm32_adc_irq_remove(pdev, priv);
481 clk_disable_unprepare(priv->bclk);
485 clk_disable_unprepare(priv->aclk);
487 err_regulator_disable:
488 regulator_disable(priv->vref);
493 static int stm32_adc_remove(struct platform_device *pdev)
495 struct stm32_adc_common *common = platform_get_drvdata(pdev);
496 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
498 of_platform_depopulate(&pdev->dev);
499 stm32_adc_irq_remove(pdev, priv);
501 clk_disable_unprepare(priv->bclk);
503 clk_disable_unprepare(priv->aclk);
504 regulator_disable(priv->vref);
509 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
510 .regs = &stm32f4_adc_common_regs,
511 .clk_sel = stm32f4_adc_clk_sel,
514 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
515 .regs = &stm32h7_adc_common_regs,
516 .clk_sel = stm32h7_adc_clk_sel,
519 static const struct of_device_id stm32_adc_of_match[] = {
521 .compatible = "st,stm32f4-adc-core",
522 .data = (void *)&stm32f4_adc_priv_cfg
524 .compatible = "st,stm32h7-adc-core",
525 .data = (void *)&stm32h7_adc_priv_cfg
529 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
531 static struct platform_driver stm32_adc_driver = {
532 .probe = stm32_adc_probe,
533 .remove = stm32_adc_remove,
535 .name = "stm32-adc-core",
536 .of_match_table = stm32_adc_of_match,
539 module_platform_driver(stm32_adc_driver);
541 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
542 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
543 MODULE_LICENSE("GPL v2");
544 MODULE_ALIAS("platform:stm32-adc-core");