1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part of STM32 ADC driver
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
8 * Inspired from: fsl-imx25-tsadc
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdesc.h>
16 #include <linux/irqdomain.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
25 #include "stm32-adc-core.h"
27 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
28 #define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
29 #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
31 /* STM32F4_ADC_CSR - bit fields */
32 #define STM32F4_EOC3 BIT(17)
33 #define STM32F4_EOC2 BIT(9)
34 #define STM32F4_EOC1 BIT(1)
36 /* STM32F4_ADC_CCR - bit fields */
37 #define STM32F4_ADC_ADCPRE_SHIFT 16
38 #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
40 /* STM32H7 - common registers for all ADC instances */
41 #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
42 #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
44 /* STM32H7_ADC_CSR - bit fields */
45 #define STM32H7_EOC_SLV BIT(18)
46 #define STM32H7_EOC_MST BIT(2)
48 /* STM32H7_ADC_CCR - bit fields */
49 #define STM32H7_PRESC_SHIFT 18
50 #define STM32H7_PRESC_MASK GENMASK(21, 18)
51 #define STM32H7_CKMODE_SHIFT 16
52 #define STM32H7_CKMODE_MASK GENMASK(17, 16)
54 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
56 /* SYSCFG registers */
57 #define STM32MP1_SYSCFG_PMCSETR 0x04
58 #define STM32MP1_SYSCFG_PMCCLRR 0x44
60 /* SYSCFG bit fields */
61 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
63 /* SYSCFG capability flags */
64 #define HAS_VBOOSTER BIT(0)
65 #define HAS_ANASWVDD BIT(1)
68 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
69 * @csr: common status register offset
70 * @ccr: common control register offset
71 * @eoc1: adc1 end of conversion flag in @csr
72 * @eoc2: adc2 end of conversion flag in @csr
73 * @eoc3: adc3 end of conversion flag in @csr
75 struct stm32_adc_common_regs {
83 struct stm32_adc_priv;
86 * stm32_adc_priv_cfg - stm32 core compatible configuration data
87 * @regs: common registers for all instances
88 * @clk_sel: clock selection routine
89 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
90 * @has_syscfg: SYSCFG capability flags
92 struct stm32_adc_priv_cfg {
93 const struct stm32_adc_common_regs *regs;
94 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
96 unsigned int has_syscfg;
100 * struct stm32_adc_priv - stm32 ADC core private data
101 * @irq: irq(s) for ADC block
102 * @domain: irq domain reference
103 * @aclk: clock reference for the analog circuitry
104 * @bclk: bus clock common for all ADCs, depends on part used
105 * @booster: booster supply reference
106 * @vdd: vdd supply reference
107 * @vdda: vdda analog supply reference
108 * @vref: regulator reference
109 * @vdd_uv: vdd supply voltage (microvolts)
110 * @vdda_uv: vdda supply voltage (microvolts)
111 * @cfg: compatible configuration data
112 * @common: common data for all ADC instances
113 * @ccr_bak: backup CCR in low power mode
114 * @syscfg: reference to syscon, system control registers
116 struct stm32_adc_priv {
117 int irq[STM32_ADC_MAX_ADCS];
118 struct irq_domain *domain;
121 struct regulator *booster;
122 struct regulator *vdd;
123 struct regulator *vdda;
124 struct regulator *vref;
127 const struct stm32_adc_priv_cfg *cfg;
128 struct stm32_adc_common common;
130 struct regmap *syscfg;
133 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
135 return container_of(com, struct stm32_adc_priv, common);
138 /* STM32F4 ADC internal common clock prescaler division ratios */
139 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
142 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
143 * @priv: stm32 ADC core private data
144 * Select clock prescaler used for analog conversions, before using ADC.
146 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
147 struct stm32_adc_priv *priv)
153 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
155 dev_err(&pdev->dev, "No 'adc' clock found\n");
159 rate = clk_get_rate(priv->aclk);
161 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
165 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
166 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
169 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
170 dev_err(&pdev->dev, "adc clk selection failed\n");
174 priv->common.rate = rate / stm32f4_pclk_div[i];
175 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
176 val &= ~STM32F4_ADC_ADCPRE_MASK;
177 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
178 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
180 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
181 priv->common.rate / 1000);
187 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
188 * @ckmode: ADC clock mode, Async or sync with prescaler.
189 * @presc: prescaler bitfield for async clock mode
190 * @div: prescaler division ratio
192 struct stm32h7_adc_ck_spec {
198 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
199 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
212 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
218 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
219 struct stm32_adc_priv *priv)
221 u32 ckmode, presc, val;
225 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
227 dev_err(&pdev->dev, "No 'bus' clock found\n");
232 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
233 * So, choice is to have bus clock mandatory and adc clock optional.
234 * If optional 'adc' clock has been found, then try to use it first.
238 * Asynchronous clock modes (e.g. ckmode == 0)
239 * From spec: PLL output musn't exceed max rate
241 rate = clk_get_rate(priv->aclk);
243 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
247 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
248 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
249 presc = stm32h7_adc_ckmodes_spec[i].presc;
250 div = stm32h7_adc_ckmodes_spec[i].div;
255 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
260 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
261 rate = clk_get_rate(priv->bclk);
263 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
267 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
268 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
269 presc = stm32h7_adc_ckmodes_spec[i].presc;
270 div = stm32h7_adc_ckmodes_spec[i].div;
275 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
279 dev_err(&pdev->dev, "adc clk selection failed\n");
283 /* rate used later by each ADC instance to control BOOST mode */
284 priv->common.rate = rate / div;
286 /* Set common clock mode and prescaler */
287 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
288 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
289 val |= ckmode << STM32H7_CKMODE_SHIFT;
290 val |= presc << STM32H7_PRESC_SHIFT;
291 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
293 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
294 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
299 /* STM32F4 common registers definitions */
300 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
301 .csr = STM32F4_ADC_CSR,
302 .ccr = STM32F4_ADC_CCR,
303 .eoc1_msk = STM32F4_EOC1,
304 .eoc2_msk = STM32F4_EOC2,
305 .eoc3_msk = STM32F4_EOC3,
308 /* STM32H7 common registers definitions */
309 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
310 .csr = STM32H7_ADC_CSR,
311 .ccr = STM32H7_ADC_CCR,
312 .eoc1_msk = STM32H7_EOC_MST,
313 .eoc2_msk = STM32H7_EOC_SLV,
316 /* ADC common interrupt for all instances */
317 static void stm32_adc_irq_handler(struct irq_desc *desc)
319 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
320 struct irq_chip *chip = irq_desc_get_chip(desc);
323 chained_irq_enter(chip, desc);
324 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
326 if (status & priv->cfg->regs->eoc1_msk)
327 generic_handle_irq(irq_find_mapping(priv->domain, 0));
329 if (status & priv->cfg->regs->eoc2_msk)
330 generic_handle_irq(irq_find_mapping(priv->domain, 1));
332 if (status & priv->cfg->regs->eoc3_msk)
333 generic_handle_irq(irq_find_mapping(priv->domain, 2));
335 chained_irq_exit(chip, desc);
338 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
339 irq_hw_number_t hwirq)
341 irq_set_chip_data(irq, d->host_data);
342 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
347 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
349 irq_set_chip_and_handler(irq, NULL, NULL);
350 irq_set_chip_data(irq, NULL);
353 static const struct irq_domain_ops stm32_adc_domain_ops = {
354 .map = stm32_adc_domain_map,
355 .unmap = stm32_adc_domain_unmap,
356 .xlate = irq_domain_xlate_onecell,
359 static int stm32_adc_irq_probe(struct platform_device *pdev,
360 struct stm32_adc_priv *priv)
362 struct device_node *np = pdev->dev.of_node;
365 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
366 priv->irq[i] = platform_get_irq(pdev, i);
367 if (priv->irq[i] < 0) {
369 * At least one interrupt must be provided, make others
371 * - stm32f4/h7 shares a common interrupt.
372 * - stm32mp1, has one line per ADC (either for ADC1,
375 if (i && priv->irq[i] == -ENXIO)
382 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
383 &stm32_adc_domain_ops,
386 dev_err(&pdev->dev, "Failed to add irq domain\n");
390 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
391 if (priv->irq[i] < 0)
393 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
394 irq_set_handler_data(priv->irq[i], priv);
400 static void stm32_adc_irq_remove(struct platform_device *pdev,
401 struct stm32_adc_priv *priv)
406 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
407 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
408 irq_domain_remove(priv->domain);
410 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
411 if (priv->irq[i] < 0)
413 irq_set_chained_handler(priv->irq[i], NULL);
417 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
423 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
424 * switches (via PCSEL) which have reduced performances when their
425 * supply is below 2.7V (vdda by default):
426 * - Voltage booster can be used, to get full ADC performances
427 * (increases power consumption).
428 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
430 * Recommended settings for ANASWVDD and EN_BOOSTER:
431 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
432 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
433 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
435 if (priv->vdda_uv < 2700000) {
436 if (priv->syscfg && priv->vdd_uv > 2700000) {
437 ret = regulator_enable(priv->vdd);
439 dev_err(dev, "vdd enable failed %d\n", ret);
443 ret = regmap_write(priv->syscfg,
444 STM32MP1_SYSCFG_PMCSETR,
445 STM32MP1_SYSCFG_ANASWVDD_MASK);
447 regulator_disable(priv->vdd);
448 dev_err(dev, "vdd select failed, %d\n", ret);
451 dev_dbg(dev, "analog switches supplied by vdd\n");
458 * This is optional, as this is a trade-off between
459 * analog performance and power consumption.
461 ret = regulator_enable(priv->booster);
463 dev_err(dev, "booster enable failed %d\n", ret);
466 dev_dbg(dev, "analog switches supplied by booster\n");
472 /* Fallback using vdda (default), nothing to do */
473 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
479 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
481 if (priv->vdda_uv < 2700000) {
482 if (priv->syscfg && priv->vdd_uv > 2700000) {
483 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
484 STM32MP1_SYSCFG_ANASWVDD_MASK);
485 regulator_disable(priv->vdd);
489 regulator_disable(priv->booster);
493 static int stm32_adc_core_hw_start(struct device *dev)
495 struct stm32_adc_common *common = dev_get_drvdata(dev);
496 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
499 ret = regulator_enable(priv->vdda);
501 dev_err(dev, "vdda enable failed %d\n", ret);
505 ret = regulator_get_voltage(priv->vdda);
507 dev_err(dev, "vdda get voltage failed, %d\n", ret);
508 goto err_vdda_disable;
512 ret = stm32_adc_core_switches_supply_en(priv, dev);
514 goto err_vdda_disable;
516 ret = regulator_enable(priv->vref);
518 dev_err(dev, "vref enable failed\n");
519 goto err_switches_dis;
523 ret = clk_prepare_enable(priv->bclk);
525 dev_err(dev, "bus clk enable failed\n");
526 goto err_regulator_disable;
531 ret = clk_prepare_enable(priv->aclk);
533 dev_err(dev, "adc clk enable failed\n");
534 goto err_bclk_disable;
538 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
544 clk_disable_unprepare(priv->bclk);
545 err_regulator_disable:
546 regulator_disable(priv->vref);
548 stm32_adc_core_switches_supply_dis(priv);
550 regulator_disable(priv->vdda);
555 static void stm32_adc_core_hw_stop(struct device *dev)
557 struct stm32_adc_common *common = dev_get_drvdata(dev);
558 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
560 /* Backup CCR that may be lost (depends on power state to achieve) */
561 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
563 clk_disable_unprepare(priv->aclk);
565 clk_disable_unprepare(priv->bclk);
566 regulator_disable(priv->vref);
567 stm32_adc_core_switches_supply_dis(priv);
568 regulator_disable(priv->vdda);
571 static int stm32_adc_core_switches_probe(struct device *dev,
572 struct stm32_adc_priv *priv)
574 struct device_node *np = dev->of_node;
577 /* Analog switches supply can be controlled by syscfg (optional) */
578 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
579 if (IS_ERR(priv->syscfg)) {
580 ret = PTR_ERR(priv->syscfg);
581 if (ret != -ENODEV) {
582 if (ret != -EPROBE_DEFER)
583 dev_err(dev, "Can't probe syscfg: %d\n", ret);
589 /* Booster can be used to supply analog switches (optional) */
590 if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
591 of_property_read_bool(np, "booster-supply")) {
592 priv->booster = devm_regulator_get_optional(dev, "booster");
593 if (IS_ERR(priv->booster)) {
594 ret = PTR_ERR(priv->booster);
595 if (ret != -ENODEV) {
596 if (ret != -EPROBE_DEFER)
597 dev_err(dev, "can't get booster %d\n",
601 priv->booster = NULL;
605 /* Vdd can be used to supply analog switches (optional) */
606 if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
607 of_property_read_bool(np, "vdd-supply")) {
608 priv->vdd = devm_regulator_get_optional(dev, "vdd");
609 if (IS_ERR(priv->vdd)) {
610 ret = PTR_ERR(priv->vdd);
611 if (ret != -ENODEV) {
612 if (ret != -EPROBE_DEFER)
613 dev_err(dev, "can't get vdd %d\n", ret);
621 ret = regulator_enable(priv->vdd);
623 dev_err(dev, "vdd enable failed %d\n", ret);
627 ret = regulator_get_voltage(priv->vdd);
629 dev_err(dev, "vdd get voltage failed %d\n", ret);
630 regulator_disable(priv->vdd);
635 regulator_disable(priv->vdd);
641 static int stm32_adc_probe(struct platform_device *pdev)
643 struct stm32_adc_priv *priv;
644 struct device *dev = &pdev->dev;
645 struct device_node *np = pdev->dev.of_node;
646 struct resource *res;
649 if (!pdev->dev.of_node)
652 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
655 platform_set_drvdata(pdev, &priv->common);
657 priv->cfg = (const struct stm32_adc_priv_cfg *)
658 of_match_device(dev->driver->of_match_table, dev)->data;
660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
661 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
662 if (IS_ERR(priv->common.base))
663 return PTR_ERR(priv->common.base);
664 priv->common.phys_base = res->start;
666 priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
667 if (IS_ERR(priv->vdda)) {
668 ret = PTR_ERR(priv->vdda);
669 if (ret != -EPROBE_DEFER)
670 dev_err(&pdev->dev, "vdda get failed, %d\n", ret);
674 priv->vref = devm_regulator_get(&pdev->dev, "vref");
675 if (IS_ERR(priv->vref)) {
676 ret = PTR_ERR(priv->vref);
677 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
681 priv->aclk = devm_clk_get(&pdev->dev, "adc");
682 if (IS_ERR(priv->aclk)) {
683 ret = PTR_ERR(priv->aclk);
684 if (ret != -ENOENT) {
685 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
691 priv->bclk = devm_clk_get(&pdev->dev, "bus");
692 if (IS_ERR(priv->bclk)) {
693 ret = PTR_ERR(priv->bclk);
694 if (ret != -ENOENT) {
695 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
701 ret = stm32_adc_core_switches_probe(dev, priv);
705 pm_runtime_get_noresume(dev);
706 pm_runtime_set_active(dev);
707 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
708 pm_runtime_use_autosuspend(dev);
709 pm_runtime_enable(dev);
711 ret = stm32_adc_core_hw_start(dev);
715 ret = regulator_get_voltage(priv->vref);
717 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
720 priv->common.vref_mv = ret / 1000;
721 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
723 ret = priv->cfg->clk_sel(pdev, priv);
727 ret = stm32_adc_irq_probe(pdev, priv);
731 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
733 dev_err(&pdev->dev, "failed to populate DT children\n");
737 pm_runtime_mark_last_busy(dev);
738 pm_runtime_put_autosuspend(dev);
743 stm32_adc_irq_remove(pdev, priv);
745 stm32_adc_core_hw_stop(dev);
747 pm_runtime_disable(dev);
748 pm_runtime_set_suspended(dev);
749 pm_runtime_put_noidle(dev);
754 static int stm32_adc_remove(struct platform_device *pdev)
756 struct stm32_adc_common *common = platform_get_drvdata(pdev);
757 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
759 pm_runtime_get_sync(&pdev->dev);
760 of_platform_depopulate(&pdev->dev);
761 stm32_adc_irq_remove(pdev, priv);
762 stm32_adc_core_hw_stop(&pdev->dev);
763 pm_runtime_disable(&pdev->dev);
764 pm_runtime_set_suspended(&pdev->dev);
765 pm_runtime_put_noidle(&pdev->dev);
770 #if defined(CONFIG_PM)
771 static int stm32_adc_core_runtime_suspend(struct device *dev)
773 stm32_adc_core_hw_stop(dev);
778 static int stm32_adc_core_runtime_resume(struct device *dev)
780 return stm32_adc_core_hw_start(dev);
784 static const struct dev_pm_ops stm32_adc_core_pm_ops = {
785 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
786 pm_runtime_force_resume)
787 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
788 stm32_adc_core_runtime_resume,
792 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
793 .regs = &stm32f4_adc_common_regs,
794 .clk_sel = stm32f4_adc_clk_sel,
795 .max_clk_rate_hz = 36000000,
798 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
799 .regs = &stm32h7_adc_common_regs,
800 .clk_sel = stm32h7_adc_clk_sel,
801 .max_clk_rate_hz = 36000000,
802 .has_syscfg = HAS_VBOOSTER,
805 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
806 .regs = &stm32h7_adc_common_regs,
807 .clk_sel = stm32h7_adc_clk_sel,
808 .max_clk_rate_hz = 40000000,
809 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
812 static const struct of_device_id stm32_adc_of_match[] = {
814 .compatible = "st,stm32f4-adc-core",
815 .data = (void *)&stm32f4_adc_priv_cfg
817 .compatible = "st,stm32h7-adc-core",
818 .data = (void *)&stm32h7_adc_priv_cfg
820 .compatible = "st,stm32mp1-adc-core",
821 .data = (void *)&stm32mp1_adc_priv_cfg
825 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
827 static struct platform_driver stm32_adc_driver = {
828 .probe = stm32_adc_probe,
829 .remove = stm32_adc_remove,
831 .name = "stm32-adc-core",
832 .of_match_table = stm32_adc_of_match,
833 .pm = &stm32_adc_core_pm_ops,
836 module_platform_driver(stm32_adc_driver);
838 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
839 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
840 MODULE_LICENSE("GPL v2");
841 MODULE_ALIAS("platform:stm32-adc-core");