1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part of STM32 ADC driver
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
8 * Inspired from: fsl-imx25-tsadc
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdesc.h>
16 #include <linux/irqdomain.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
25 #include "stm32-adc-core.h"
27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
29 /* SYSCFG registers */
30 #define STM32MP1_SYSCFG_PMCSETR 0x04
31 #define STM32MP1_SYSCFG_PMCCLRR 0x44
33 /* SYSCFG bit fields */
34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
36 /* SYSCFG capability flags */
37 #define HAS_VBOOSTER BIT(0)
38 #define HAS_ANASWVDD BIT(1)
41 * struct stm32_adc_common_regs - stm32 common registers
42 * @csr: common status register offset
43 * @ccr: common control register offset
44 * @eoc1_msk: adc1 end of conversion flag in @csr
45 * @eoc2_msk: adc2 end of conversion flag in @csr
46 * @eoc3_msk: adc3 end of conversion flag in @csr
47 * @ier: interrupt enable register offset for each adc
48 * @eocie_msk: end of conversion interrupt enable mask in @ier
50 struct stm32_adc_common_regs {
60 struct stm32_adc_priv;
63 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
64 * @regs: common registers for all instances
65 * @clk_sel: clock selection routine
66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
67 * @has_syscfg: SYSCFG capability flags
69 struct stm32_adc_priv_cfg {
70 const struct stm32_adc_common_regs *regs;
71 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
73 unsigned int has_syscfg;
77 * struct stm32_adc_priv - stm32 ADC core private data
78 * @irq: irq(s) for ADC block
79 * @domain: irq domain reference
80 * @aclk: clock reference for the analog circuitry
81 * @bclk: bus clock common for all ADCs, depends on part used
82 * @max_clk_rate: desired maximum clock rate
83 * @booster: booster supply reference
84 * @vdd: vdd supply reference
85 * @vdda: vdda analog supply reference
86 * @vref: regulator reference
87 * @vdd_uv: vdd supply voltage (microvolts)
88 * @vdda_uv: vdda supply voltage (microvolts)
89 * @cfg: compatible configuration data
90 * @common: common data for all ADC instances
91 * @ccr_bak: backup CCR in low power mode
92 * @syscfg: reference to syscon, system control registers
94 struct stm32_adc_priv {
95 int irq[STM32_ADC_MAX_ADCS];
96 struct irq_domain *domain;
100 struct regulator *booster;
101 struct regulator *vdd;
102 struct regulator *vdda;
103 struct regulator *vref;
106 const struct stm32_adc_priv_cfg *cfg;
107 struct stm32_adc_common common;
109 struct regmap *syscfg;
112 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
114 return container_of(com, struct stm32_adc_priv, common);
117 /* STM32F4 ADC internal common clock prescaler division ratios */
118 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
121 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
122 * @pdev: platform device
123 * @priv: stm32 ADC core private data
124 * Select clock prescaler used for analog conversions, before using ADC.
126 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
127 struct stm32_adc_priv *priv)
133 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
135 dev_err(&pdev->dev, "No 'adc' clock found\n");
139 rate = clk_get_rate(priv->aclk);
141 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
145 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
146 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
149 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
150 dev_err(&pdev->dev, "adc clk selection failed\n");
154 priv->common.rate = rate / stm32f4_pclk_div[i];
155 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
156 val &= ~STM32F4_ADC_ADCPRE_MASK;
157 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
158 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
160 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
161 priv->common.rate / 1000);
167 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
168 * @ckmode: ADC clock mode, Async or sync with prescaler.
169 * @presc: prescaler bitfield for async clock mode
170 * @div: prescaler division ratio
172 struct stm32h7_adc_ck_spec {
178 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
179 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
192 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
198 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
199 struct stm32_adc_priv *priv)
201 u32 ckmode, presc, val;
205 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
207 dev_err(&pdev->dev, "No 'bus' clock found\n");
212 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
213 * So, choice is to have bus clock mandatory and adc clock optional.
214 * If optional 'adc' clock has been found, then try to use it first.
218 * Asynchronous clock modes (e.g. ckmode == 0)
219 * From spec: PLL output musn't exceed max rate
221 rate = clk_get_rate(priv->aclk);
223 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
227 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
228 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
229 presc = stm32h7_adc_ckmodes_spec[i].presc;
230 div = stm32h7_adc_ckmodes_spec[i].div;
235 if ((rate / div) <= priv->max_clk_rate)
240 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
241 rate = clk_get_rate(priv->bclk);
243 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
247 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
248 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
249 presc = stm32h7_adc_ckmodes_spec[i].presc;
250 div = stm32h7_adc_ckmodes_spec[i].div;
255 if ((rate / div) <= priv->max_clk_rate)
259 dev_err(&pdev->dev, "adc clk selection failed\n");
263 /* rate used later by each ADC instance to control BOOST mode */
264 priv->common.rate = rate / div;
266 /* Set common clock mode and prescaler */
267 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
268 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
269 val |= ckmode << STM32H7_CKMODE_SHIFT;
270 val |= presc << STM32H7_PRESC_SHIFT;
271 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
273 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
274 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
279 /* STM32F4 common registers definitions */
280 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
281 .csr = STM32F4_ADC_CSR,
282 .ccr = STM32F4_ADC_CCR,
283 .eoc1_msk = STM32F4_EOC1 | STM32F4_OVR1,
284 .eoc2_msk = STM32F4_EOC2 | STM32F4_OVR2,
285 .eoc3_msk = STM32F4_EOC3 | STM32F4_OVR3,
286 .ier = STM32F4_ADC_CR1,
287 .eocie_msk = STM32F4_EOCIE | STM32F4_OVRIE,
290 /* STM32H7 common registers definitions */
291 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
292 .csr = STM32H7_ADC_CSR,
293 .ccr = STM32H7_ADC_CCR,
294 .eoc1_msk = STM32H7_EOC_MST | STM32H7_OVR_MST,
295 .eoc2_msk = STM32H7_EOC_SLV | STM32H7_OVR_SLV,
296 .ier = STM32H7_ADC_IER,
297 .eocie_msk = STM32H7_EOCIE | STM32H7_OVRIE,
300 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
301 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
304 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
307 u32 ier, offset = stm32_adc_offset[adc];
309 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
311 return ier & priv->cfg->regs->eocie_msk;
314 /* ADC common interrupt for all instances */
315 static void stm32_adc_irq_handler(struct irq_desc *desc)
317 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
318 struct irq_chip *chip = irq_desc_get_chip(desc);
321 chained_irq_enter(chip, desc);
322 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
325 * End of conversion may be handled by using IRQ or DMA. There may be a
326 * race here when two conversions complete at the same time on several
327 * ADCs. EOC may be read 'set' for several ADCs, with:
328 * - an ADC configured to use DMA (EOC triggers the DMA request, and
329 * is then automatically cleared by DR read in hardware)
330 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
331 * be called in this case)
332 * So both EOC status bit in CSR and EOCIE control bit must be checked
333 * before invoking the interrupt handler (e.g. call ISR only for
336 if (status & priv->cfg->regs->eoc1_msk &&
337 stm32_adc_eoc_enabled(priv, 0))
338 generic_handle_irq(irq_find_mapping(priv->domain, 0));
340 if (status & priv->cfg->regs->eoc2_msk &&
341 stm32_adc_eoc_enabled(priv, 1))
342 generic_handle_irq(irq_find_mapping(priv->domain, 1));
344 if (status & priv->cfg->regs->eoc3_msk &&
345 stm32_adc_eoc_enabled(priv, 2))
346 generic_handle_irq(irq_find_mapping(priv->domain, 2));
348 chained_irq_exit(chip, desc);
351 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
352 irq_hw_number_t hwirq)
354 irq_set_chip_data(irq, d->host_data);
355 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
360 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
362 irq_set_chip_and_handler(irq, NULL, NULL);
363 irq_set_chip_data(irq, NULL);
366 static const struct irq_domain_ops stm32_adc_domain_ops = {
367 .map = stm32_adc_domain_map,
368 .unmap = stm32_adc_domain_unmap,
369 .xlate = irq_domain_xlate_onecell,
372 static int stm32_adc_irq_probe(struct platform_device *pdev,
373 struct stm32_adc_priv *priv)
375 struct device_node *np = pdev->dev.of_node;
378 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
379 priv->irq[i] = platform_get_irq(pdev, i);
380 if (priv->irq[i] < 0) {
382 * At least one interrupt must be provided, make others
384 * - stm32f4/h7 shares a common interrupt.
385 * - stm32mp1, has one line per ADC (either for ADC1,
388 if (i && priv->irq[i] == -ENXIO)
395 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
396 &stm32_adc_domain_ops,
399 dev_err(&pdev->dev, "Failed to add irq domain\n");
403 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
404 if (priv->irq[i] < 0)
406 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
407 irq_set_handler_data(priv->irq[i], priv);
413 static void stm32_adc_irq_remove(struct platform_device *pdev,
414 struct stm32_adc_priv *priv)
419 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
420 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
421 irq_domain_remove(priv->domain);
423 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
424 if (priv->irq[i] < 0)
426 irq_set_chained_handler(priv->irq[i], NULL);
430 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
436 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
437 * switches (via PCSEL) which have reduced performances when their
438 * supply is below 2.7V (vdda by default):
439 * - Voltage booster can be used, to get full ADC performances
440 * (increases power consumption).
441 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
443 * Recommended settings for ANASWVDD and EN_BOOSTER:
444 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
445 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
446 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
448 if (priv->vdda_uv < 2700000) {
449 if (priv->syscfg && priv->vdd_uv > 2700000) {
450 ret = regulator_enable(priv->vdd);
452 dev_err(dev, "vdd enable failed %d\n", ret);
456 ret = regmap_write(priv->syscfg,
457 STM32MP1_SYSCFG_PMCSETR,
458 STM32MP1_SYSCFG_ANASWVDD_MASK);
460 regulator_disable(priv->vdd);
461 dev_err(dev, "vdd select failed, %d\n", ret);
464 dev_dbg(dev, "analog switches supplied by vdd\n");
471 * This is optional, as this is a trade-off between
472 * analog performance and power consumption.
474 ret = regulator_enable(priv->booster);
476 dev_err(dev, "booster enable failed %d\n", ret);
479 dev_dbg(dev, "analog switches supplied by booster\n");
485 /* Fallback using vdda (default), nothing to do */
486 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
492 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
494 if (priv->vdda_uv < 2700000) {
495 if (priv->syscfg && priv->vdd_uv > 2700000) {
496 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
497 STM32MP1_SYSCFG_ANASWVDD_MASK);
498 regulator_disable(priv->vdd);
502 regulator_disable(priv->booster);
506 static int stm32_adc_core_hw_start(struct device *dev)
508 struct stm32_adc_common *common = dev_get_drvdata(dev);
509 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
512 ret = regulator_enable(priv->vdda);
514 dev_err(dev, "vdda enable failed %d\n", ret);
518 ret = regulator_get_voltage(priv->vdda);
520 dev_err(dev, "vdda get voltage failed, %d\n", ret);
521 goto err_vdda_disable;
525 ret = stm32_adc_core_switches_supply_en(priv, dev);
527 goto err_vdda_disable;
529 ret = regulator_enable(priv->vref);
531 dev_err(dev, "vref enable failed\n");
532 goto err_switches_dis;
536 ret = clk_prepare_enable(priv->bclk);
538 dev_err(dev, "bus clk enable failed\n");
539 goto err_regulator_disable;
544 ret = clk_prepare_enable(priv->aclk);
546 dev_err(dev, "adc clk enable failed\n");
547 goto err_bclk_disable;
551 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
557 clk_disable_unprepare(priv->bclk);
558 err_regulator_disable:
559 regulator_disable(priv->vref);
561 stm32_adc_core_switches_supply_dis(priv);
563 regulator_disable(priv->vdda);
568 static void stm32_adc_core_hw_stop(struct device *dev)
570 struct stm32_adc_common *common = dev_get_drvdata(dev);
571 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
573 /* Backup CCR that may be lost (depends on power state to achieve) */
574 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
576 clk_disable_unprepare(priv->aclk);
578 clk_disable_unprepare(priv->bclk);
579 regulator_disable(priv->vref);
580 stm32_adc_core_switches_supply_dis(priv);
581 regulator_disable(priv->vdda);
584 static int stm32_adc_core_switches_probe(struct device *dev,
585 struct stm32_adc_priv *priv)
587 struct device_node *np = dev->of_node;
590 /* Analog switches supply can be controlled by syscfg (optional) */
591 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
592 if (IS_ERR(priv->syscfg)) {
593 ret = PTR_ERR(priv->syscfg);
594 if (ret != -ENODEV) {
595 if (ret != -EPROBE_DEFER)
596 dev_err(dev, "Can't probe syscfg: %d\n", ret);
602 /* Booster can be used to supply analog switches (optional) */
603 if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
604 of_property_read_bool(np, "booster-supply")) {
605 priv->booster = devm_regulator_get_optional(dev, "booster");
606 if (IS_ERR(priv->booster)) {
607 ret = PTR_ERR(priv->booster);
608 if (ret != -ENODEV) {
609 if (ret != -EPROBE_DEFER)
610 dev_err(dev, "can't get booster %d\n",
614 priv->booster = NULL;
618 /* Vdd can be used to supply analog switches (optional) */
619 if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
620 of_property_read_bool(np, "vdd-supply")) {
621 priv->vdd = devm_regulator_get_optional(dev, "vdd");
622 if (IS_ERR(priv->vdd)) {
623 ret = PTR_ERR(priv->vdd);
624 if (ret != -ENODEV) {
625 if (ret != -EPROBE_DEFER)
626 dev_err(dev, "can't get vdd %d\n", ret);
634 ret = regulator_enable(priv->vdd);
636 dev_err(dev, "vdd enable failed %d\n", ret);
640 ret = regulator_get_voltage(priv->vdd);
642 dev_err(dev, "vdd get voltage failed %d\n", ret);
643 regulator_disable(priv->vdd);
648 regulator_disable(priv->vdd);
654 static int stm32_adc_probe(struct platform_device *pdev)
656 struct stm32_adc_priv *priv;
657 struct device *dev = &pdev->dev;
658 struct device_node *np = pdev->dev.of_node;
659 struct resource *res;
663 if (!pdev->dev.of_node)
666 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
669 platform_set_drvdata(pdev, &priv->common);
671 priv->cfg = (const struct stm32_adc_priv_cfg *)
672 of_match_device(dev->driver->of_match_table, dev)->data;
674 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
675 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
676 if (IS_ERR(priv->common.base))
677 return PTR_ERR(priv->common.base);
678 priv->common.phys_base = res->start;
680 priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
681 if (IS_ERR(priv->vdda)) {
682 ret = PTR_ERR(priv->vdda);
683 if (ret != -EPROBE_DEFER)
684 dev_err(&pdev->dev, "vdda get failed, %d\n", ret);
688 priv->vref = devm_regulator_get(&pdev->dev, "vref");
689 if (IS_ERR(priv->vref)) {
690 ret = PTR_ERR(priv->vref);
691 if (ret != -EPROBE_DEFER)
692 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
696 priv->aclk = devm_clk_get(&pdev->dev, "adc");
697 if (IS_ERR(priv->aclk)) {
698 ret = PTR_ERR(priv->aclk);
699 if (ret != -ENOENT) {
700 if (ret != -EPROBE_DEFER)
701 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
707 priv->bclk = devm_clk_get(&pdev->dev, "bus");
708 if (IS_ERR(priv->bclk)) {
709 ret = PTR_ERR(priv->bclk);
710 if (ret != -ENOENT) {
711 if (ret != -EPROBE_DEFER)
712 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
718 ret = stm32_adc_core_switches_probe(dev, priv);
722 pm_runtime_get_noresume(dev);
723 pm_runtime_set_active(dev);
724 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
725 pm_runtime_use_autosuspend(dev);
726 pm_runtime_enable(dev);
728 ret = stm32_adc_core_hw_start(dev);
732 ret = regulator_get_voltage(priv->vref);
734 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
737 priv->common.vref_mv = ret / 1000;
738 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
740 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
743 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
745 priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
747 ret = priv->cfg->clk_sel(pdev, priv);
751 ret = stm32_adc_irq_probe(pdev, priv);
755 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
757 dev_err(&pdev->dev, "failed to populate DT children\n");
761 pm_runtime_mark_last_busy(dev);
762 pm_runtime_put_autosuspend(dev);
767 stm32_adc_irq_remove(pdev, priv);
769 stm32_adc_core_hw_stop(dev);
771 pm_runtime_disable(dev);
772 pm_runtime_set_suspended(dev);
773 pm_runtime_put_noidle(dev);
778 static int stm32_adc_remove(struct platform_device *pdev)
780 struct stm32_adc_common *common = platform_get_drvdata(pdev);
781 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
783 pm_runtime_get_sync(&pdev->dev);
784 of_platform_depopulate(&pdev->dev);
785 stm32_adc_irq_remove(pdev, priv);
786 stm32_adc_core_hw_stop(&pdev->dev);
787 pm_runtime_disable(&pdev->dev);
788 pm_runtime_set_suspended(&pdev->dev);
789 pm_runtime_put_noidle(&pdev->dev);
794 #if defined(CONFIG_PM)
795 static int stm32_adc_core_runtime_suspend(struct device *dev)
797 stm32_adc_core_hw_stop(dev);
802 static int stm32_adc_core_runtime_resume(struct device *dev)
804 return stm32_adc_core_hw_start(dev);
808 static const struct dev_pm_ops stm32_adc_core_pm_ops = {
809 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
810 pm_runtime_force_resume)
811 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
812 stm32_adc_core_runtime_resume,
816 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
817 .regs = &stm32f4_adc_common_regs,
818 .clk_sel = stm32f4_adc_clk_sel,
819 .max_clk_rate_hz = 36000000,
822 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
823 .regs = &stm32h7_adc_common_regs,
824 .clk_sel = stm32h7_adc_clk_sel,
825 .max_clk_rate_hz = 36000000,
826 .has_syscfg = HAS_VBOOSTER,
829 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
830 .regs = &stm32h7_adc_common_regs,
831 .clk_sel = stm32h7_adc_clk_sel,
832 .max_clk_rate_hz = 40000000,
833 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
836 static const struct of_device_id stm32_adc_of_match[] = {
838 .compatible = "st,stm32f4-adc-core",
839 .data = (void *)&stm32f4_adc_priv_cfg
841 .compatible = "st,stm32h7-adc-core",
842 .data = (void *)&stm32h7_adc_priv_cfg
844 .compatible = "st,stm32mp1-adc-core",
845 .data = (void *)&stm32mp1_adc_priv_cfg
849 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
851 static struct platform_driver stm32_adc_driver = {
852 .probe = stm32_adc_probe,
853 .remove = stm32_adc_remove,
855 .name = "stm32-adc-core",
856 .of_match_table = stm32_adc_of_match,
857 .pm = &stm32_adc_core_pm_ops,
860 module_platform_driver(stm32_adc_driver);
862 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
863 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
864 MODULE_LICENSE("GPL v2");
865 MODULE_ALIAS("platform:stm32-adc-core");