1 // SPDX-License-Identifier: GPL-2.0
3 * This file is the ADC part of the STM32 DFSDM driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
12 #include <linux/iio/buffer.h>
13 #include <linux/iio/hw-consumer.h>
14 #include <linux/iio/sysfs.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include "stm32-dfsdm.h"
29 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
31 /* Conversion timeout */
32 #define DFSDM_TIMEOUT_US 100000
33 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
35 /* Oversampling attribute default */
36 #define DFSDM_DEFAULT_OVERSAMPLING 100
38 /* Oversampling max values */
39 #define DFSDM_MAX_INT_OVERSAMPLING 256
40 #define DFSDM_MAX_FL_OVERSAMPLING 1024
42 /* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
43 #define DFSDM_DATA_MAX BIT(30)
45 * Data are output as two's complement data in a 24 bit field.
46 * Data from filters are in the range +/-2^(n-1)
47 * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
48 * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
49 * So, the resolution of samples from filter is actually limited to 23 bits
51 #define DFSDM_DATA_RES 24
53 /* Filter configuration */
54 #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
55 DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
58 enum sd_converter_type {
63 struct stm32_dfsdm_dev_data {
65 int (*init)(struct iio_dev *indio_dev);
66 unsigned int num_channels;
67 const struct regmap_config *regmap_cfg;
70 struct stm32_dfsdm_adc {
71 struct stm32_dfsdm *dfsdm;
72 const struct stm32_dfsdm_dev_data *dev_data;
78 unsigned int oversamp;
79 struct iio_hw_consumer *hwc;
80 struct completion completion;
84 unsigned int spi_freq; /* SPI bus clock frequency */
85 unsigned int sample_freq; /* Sample frequency after filter decimation */
86 int (*cb)(const void *data, size_t size, void *cb_priv);
91 unsigned int bufi; /* Buffer current position */
92 unsigned int buf_sz; /* Buffer size */
93 struct dma_chan *dma_chan;
97 struct stm32_dfsdm_str2field {
102 /* DFSDM channel serial interface type */
103 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
104 { "SPI_R", 0 }, /* SPI with data on rising edge */
105 { "SPI_F", 1 }, /* SPI with data on falling edge */
106 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
107 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
111 /* DFSDM channel clock source */
112 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
113 /* External SPI clock (CLKIN x) */
114 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
115 /* Internal SPI clock (CLKOUT) */
116 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
117 /* Internal SPI clock divided by 2 (falling edge) */
118 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
119 /* Internal SPI clock divided by 2 (falling edge) */
120 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
124 static int stm32_dfsdm_str2val(const char *str,
125 const struct stm32_dfsdm_str2field *list)
127 const struct stm32_dfsdm_str2field *p = list;
129 for (p = list; p && p->name; p++)
130 if (!strcmp(p->name, str))
137 * struct stm32_dfsdm_trig_info - DFSDM trigger info
138 * @name: name of the trigger, corresponding to its source
139 * @jextsel: trigger signal selection
141 struct stm32_dfsdm_trig_info {
143 unsigned int jextsel;
146 /* hardware injected trigger enable, edge selection */
147 enum stm32_dfsdm_jexten {
148 STM32_DFSDM_JEXTEN_DISABLED,
149 STM32_DFSDM_JEXTEN_RISING_EDGE,
150 STM32_DFSDM_JEXTEN_FALLING_EDGE,
151 STM32_DFSDM_EXTEN_BOTH_EDGES,
154 static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
170 static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
171 struct iio_trigger *trig)
175 /* lookup triggers registered by stm32 timer trigger driver */
176 for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
178 * Checking both stm32 timer trigger type and trig name
179 * should be safe against arbitrary trigger names.
181 if ((is_stm32_timer_trigger(trig) ||
182 is_stm32_lptim_trigger(trig)) &&
183 !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
184 return stm32_dfsdm_trigs[i].jextsel;
191 static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
192 unsigned int fast, unsigned int oversamp)
194 unsigned int i, d, fosr, iosr;
197 unsigned int m = 1; /* multiplication factor */
198 unsigned int p = fl->ford; /* filter order (ford) */
199 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
201 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
203 * This function tries to compute filter oversampling and integrator
204 * oversampling, base on oversampling ratio requested by user.
206 * Decimation d depends on the filter order and the oversampling ratios.
208 * fosr: filter over sampling ratio
209 * iosr: integrator over sampling ratio
211 if (fl->ford == DFSDM_FASTSINC_ORDER) {
217 * Look for filter and integrator oversampling ratios which allows
218 * to maximize data output resolution.
220 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
221 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
224 else if (fl->ford == DFSDM_FASTSINC_ORDER)
225 d = fosr * (iosr + 3) + 2;
227 d = fosr * (iosr - 1 + p) + p;
231 else if (d != oversamp)
234 * Check resolution (limited to signed 32 bits)
237 * res = m * fosr^p x iosr (with m=1, p=ford)
239 * res = m * fosr^p x iosr (with m=2, p=2)
242 for (i = p - 1; i > 0; i--) {
243 res = res * (u64)fosr;
244 if (res > DFSDM_DATA_MAX)
247 if (res > DFSDM_DATA_MAX)
250 res = res * (u64)m * (u64)iosr;
251 if (res > DFSDM_DATA_MAX)
254 if (res >= flo->res) {
259 bits = fls(flo->res);
260 /* 8 LBSs in data register contain chan info */
263 /* if resolution is not a power of two */
264 if (flo->res > BIT(bits - 1))
269 shift = DFSDM_DATA_RES - bits;
271 * Compute right/left shift
272 * Right shift is performed by hardware
273 * when transferring samples to data register.
274 * Left shift is done by software on buffer
277 /* Resolution is lower than 24 bits */
282 * If resolution is 24 bits or more,
283 * max positive value may be ambiguous
284 * (equal to max negative value as sign
286 * Reduce resolution to 23 bits (rshift)
287 * to keep the sign on bit 23 and treat
288 * saturation before rescaling on 24
291 flo->rshift = 1 - shift;
297 pr_debug("%s: fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
298 __func__, fast, flo->fosr, flo->iosr,
299 flo->res, bits, flo->rshift,
311 static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
312 unsigned int oversamp)
314 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
315 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
318 memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
319 memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
321 ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
322 ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
323 if (ret0 < 0 && ret1 < 0) {
324 dev_err(&indio_dev->dev,
325 "Filter parameters not found: errors %d/%d\n",
333 static int stm32_dfsdm_start_channel(struct stm32_dfsdm_adc *adc)
335 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
336 struct regmap *regmap = adc->dfsdm->regmap;
337 const struct iio_chan_spec *chan;
341 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
342 chan = indio_dev->channels + bit;
343 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
344 DFSDM_CHCFGR1_CHEN_MASK,
345 DFSDM_CHCFGR1_CHEN(1));
353 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm_adc *adc)
355 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
356 struct regmap *regmap = adc->dfsdm->regmap;
357 const struct iio_chan_spec *chan;
360 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
361 chan = indio_dev->channels + bit;
362 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
363 DFSDM_CHCFGR1_CHEN_MASK,
364 DFSDM_CHCFGR1_CHEN(0));
368 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
369 struct stm32_dfsdm_channel *ch)
371 unsigned int id = ch->id;
372 struct regmap *regmap = dfsdm->regmap;
375 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
376 DFSDM_CHCFGR1_SITP_MASK,
377 DFSDM_CHCFGR1_SITP(ch->type));
380 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
381 DFSDM_CHCFGR1_SPICKSEL_MASK,
382 DFSDM_CHCFGR1_SPICKSEL(ch->src));
385 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
386 DFSDM_CHCFGR1_CHINSEL_MASK,
387 DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
390 static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
392 struct iio_trigger *trig)
394 struct stm32_dfsdm *dfsdm = adc->dfsdm;
398 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
399 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
403 /* Nothing more to do for injected (scan mode/triggered) conversions */
404 if (adc->nconv > 1 || trig)
407 /* Software start (single or continuous) regular conversion */
408 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
409 DFSDM_CR1_RSWSTART_MASK,
410 DFSDM_CR1_RSWSTART(1));
413 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
416 /* Disable conversion */
417 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
418 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
421 static int stm32_dfsdm_filter_set_trig(struct stm32_dfsdm_adc *adc,
423 struct iio_trigger *trig)
425 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
426 struct regmap *regmap = adc->dfsdm->regmap;
427 u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
431 ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
435 /* set trigger source and polarity (default to rising edge) */
437 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
440 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
441 DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
442 DFSDM_CR1_JEXTSEL(jextsel) |
443 DFSDM_CR1_JEXTEN(jexten));
450 static int stm32_dfsdm_channels_configure(struct stm32_dfsdm_adc *adc,
452 struct iio_trigger *trig)
454 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
455 struct regmap *regmap = adc->dfsdm->regmap;
456 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
457 struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
458 const struct iio_chan_spec *chan;
465 * In continuous mode, use fast mode configuration,
466 * if it provides a better resolution.
468 if (adc->nconv == 1 && !trig &&
469 (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)) {
470 if (fl->flo[1].res >= fl->flo[0].res) {
479 for_each_set_bit(bit, &adc->smask,
480 sizeof(adc->smask) * BITS_PER_BYTE) {
481 chan = indio_dev->channels + bit;
483 ret = regmap_update_bits(regmap,
484 DFSDM_CHCFGR2(chan->channel),
485 DFSDM_CHCFGR2_DTRBS_MASK,
486 DFSDM_CHCFGR2_DTRBS(flo->rshift));
494 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc,
496 struct iio_trigger *trig)
498 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
499 struct regmap *regmap = adc->dfsdm->regmap;
500 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
501 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
503 const struct iio_chan_spec *chan;
504 unsigned int bit, jchg = 0;
507 /* Average integrator oversampling */
508 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
509 DFSDM_FCR_IOSR(flo->iosr - 1));
513 /* Filter order and Oversampling */
514 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
515 DFSDM_FCR_FOSR(flo->fosr - 1));
519 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
520 DFSDM_FCR_FORD(fl->ford));
524 ret = stm32_dfsdm_filter_set_trig(adc, fl_id, trig);
528 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
530 DFSDM_CR1_FAST(fl->fast));
535 * DFSDM modes configuration W.R.T audio/iio type modes
536 * ----------------------------------------------------------------
537 * Modes | regular | regular | injected | injected |
538 * | | continuous | | + scan |
539 * --------------|---------|--------------|----------|------------|
540 * single conv | x | | | |
542 * --------------|---------|--------------|----------|------------|
543 * 1 Audio chan | | sample freq | | |
544 * | | or sync_mode | | |
545 * --------------|---------|--------------|----------|------------|
546 * 1 IIO chan | | sample freq | trigger | |
547 * | | or sync_mode | | |
548 * --------------|---------|--------------|----------|------------|
549 * 2+ IIO chans | | | | trigger or |
550 * | | | | sync_mode |
551 * ----------------------------------------------------------------
553 if (adc->nconv == 1 && !trig) {
554 bit = __ffs(adc->smask);
555 chan = indio_dev->channels + bit;
557 /* Use regular conversion for single channel without trigger */
558 cr1 = DFSDM_CR1_RCH(chan->channel);
560 /* Continuous conversions triggered by SPI clk in buffer mode */
561 if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)
562 cr1 |= DFSDM_CR1_RCONT(1);
564 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
566 /* Use injected conversion for multiple channels */
567 for_each_set_bit(bit, &adc->smask,
568 sizeof(adc->smask) * BITS_PER_BYTE) {
569 chan = indio_dev->channels + bit;
570 jchg |= BIT(chan->channel);
572 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
576 /* Use scan mode for multiple channels */
577 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
580 * Continuous conversions not supported in injected mode,
582 * - conversions in sync with filter 0
583 * - triggered conversions
585 if (!fl->sync_mode && !trig)
587 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
590 return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
594 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
595 struct iio_dev *indio_dev,
596 struct iio_chan_spec *ch)
598 struct stm32_dfsdm_channel *df_ch;
600 int chan_idx = ch->scan_index;
603 ret = of_property_read_u32_index(indio_dev->dev.of_node,
604 "st,adc-channels", chan_idx,
607 dev_err(&indio_dev->dev,
608 " Error parsing 'st,adc-channels' for idx %d\n",
612 if (ch->channel >= dfsdm->num_chs) {
613 dev_err(&indio_dev->dev,
614 " Error bad channel number %d (max = %d)\n",
615 ch->channel, dfsdm->num_chs);
619 ret = of_property_read_string_index(indio_dev->dev.of_node,
620 "st,adc-channel-names", chan_idx,
621 &ch->datasheet_name);
623 dev_err(&indio_dev->dev,
624 " Error parsing 'st,adc-channel-names' for idx %d\n",
629 df_ch = &dfsdm->ch_list[ch->channel];
630 df_ch->id = ch->channel;
632 ret = of_property_read_string_index(indio_dev->dev.of_node,
633 "st,adc-channel-types", chan_idx,
636 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
644 ret = of_property_read_string_index(indio_dev->dev.of_node,
645 "st,adc-channel-clk-src", chan_idx,
648 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
656 ret = of_property_read_u32_index(indio_dev->dev.of_node,
657 "st,adc-alt-channel", chan_idx,
665 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
667 const struct iio_chan_spec *chan,
670 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
672 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
675 static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
676 unsigned int sample_freq,
677 unsigned int spi_freq)
679 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
680 unsigned int oversamp;
683 oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
684 if (spi_freq % sample_freq)
685 dev_dbg(&indio_dev->dev,
686 "Rate not accurate. requested (%u), actual (%u)\n",
687 sample_freq, spi_freq / oversamp);
689 ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
693 adc->sample_freq = spi_freq / oversamp;
694 adc->oversamp = oversamp;
699 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
701 const struct iio_chan_spec *chan,
702 const char *buf, size_t len)
704 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
705 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
706 unsigned int sample_freq = adc->sample_freq;
707 unsigned int spi_freq;
710 dev_err(&indio_dev->dev, "enter %s\n", __func__);
711 /* If DFSDM is master on SPI, SPI freq can not be updated */
712 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
715 ret = kstrtoint(buf, 0, &spi_freq);
723 ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
727 adc->spi_freq = spi_freq;
732 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
733 struct iio_trigger *trig)
735 struct regmap *regmap = adc->dfsdm->regmap;
738 ret = stm32_dfsdm_channels_configure(adc, adc->fl_id, trig);
742 ret = stm32_dfsdm_start_channel(adc);
746 ret = stm32_dfsdm_filter_configure(adc, adc->fl_id, trig);
750 ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
752 goto filter_unconfigure;
757 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
758 DFSDM_CR1_CFG_MASK, 0);
760 stm32_dfsdm_stop_channel(adc);
765 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc)
767 struct regmap *regmap = adc->dfsdm->regmap;
769 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
771 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
772 DFSDM_CR1_CFG_MASK, 0);
774 stm32_dfsdm_stop_channel(adc);
777 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
780 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
781 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
782 unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
785 * DMA cyclic transfers are used, buffer is split into two periods.
787 * - always one buffer (period) DMA is working on
788 * - one buffer (period) driver pushed to ASoC side.
790 watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
791 adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
796 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
798 struct dma_tx_state state;
799 enum dma_status status;
801 status = dmaengine_tx_status(adc->dma_chan,
802 adc->dma_chan->cookie,
804 if (status == DMA_IN_PROGRESS) {
805 /* Residue is size in bytes from end of buffer */
806 unsigned int i = adc->buf_sz - state.residue;
809 /* Return available bytes */
811 size = i - adc->bufi;
813 size = adc->buf_sz + i - adc->bufi;
821 static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
824 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
825 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
826 unsigned int i = adc->nconv;
830 /* Mask 8 LSB that contains the channel ID */
832 /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
836 * Samples from filter are retrieved with 23 bits resolution
837 * or less. Shift left to align MSB on 24 bits.
839 *ptr <<= flo->lshift;
845 static irqreturn_t stm32_dfsdm_adc_trigger_handler(int irq, void *p)
847 struct iio_poll_func *pf = p;
848 struct iio_dev *indio_dev = pf->indio_dev;
849 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
850 int available = stm32_dfsdm_adc_dma_residue(adc);
852 while (available >= indio_dev->scan_bytes) {
853 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
855 stm32_dfsdm_process_data(adc, buffer);
857 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
859 available -= indio_dev->scan_bytes;
860 adc->bufi += indio_dev->scan_bytes;
861 if (adc->bufi >= adc->buf_sz)
865 iio_trigger_notify_done(indio_dev->trig);
870 static void stm32_dfsdm_dma_buffer_done(void *data)
872 struct iio_dev *indio_dev = data;
873 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
874 int available = stm32_dfsdm_adc_dma_residue(adc);
877 if (indio_dev->currentmode & INDIO_BUFFER_TRIGGERED) {
878 iio_trigger_poll_chained(indio_dev->trig);
883 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
884 * offers only an interface to push data samples per samples.
885 * For this reason IIO buffer interface is not used and interface is
886 * bypassed using a private callback registered by ASoC.
887 * This should be a temporary solution waiting a cyclic DMA engine
891 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
892 adc->bufi, available);
895 while (available >= indio_dev->scan_bytes) {
896 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
898 stm32_dfsdm_process_data(adc, buffer);
900 available -= indio_dev->scan_bytes;
901 adc->bufi += indio_dev->scan_bytes;
902 if (adc->bufi >= adc->buf_sz) {
904 adc->cb(&adc->rx_buf[old_pos],
905 adc->buf_sz - old_pos, adc->cb_priv);
909 /* regular iio buffer without trigger */
910 if (adc->dev_data->type == DFSDM_IIO)
911 iio_push_to_buffers(indio_dev, buffer);
914 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
918 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
920 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
922 * The DFSDM supports half-word transfers. However, for 16 bits record,
923 * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
926 struct dma_slave_config config = {
927 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
928 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
930 struct dma_async_tx_descriptor *desc;
937 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
938 adc->buf_sz, adc->buf_sz / 2);
940 if (adc->nconv == 1 && !indio_dev->trig)
941 config.src_addr += DFSDM_RDATAR(adc->fl_id);
943 config.src_addr += DFSDM_JDATAR(adc->fl_id);
944 ret = dmaengine_slave_config(adc->dma_chan, &config);
948 /* Prepare a DMA cyclic transaction */
949 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
951 adc->buf_sz, adc->buf_sz / 2,
957 desc->callback = stm32_dfsdm_dma_buffer_done;
958 desc->callback_param = indio_dev;
960 cookie = dmaengine_submit(desc);
961 ret = dma_submit_error(cookie);
965 /* Issue pending DMA requests */
966 dma_async_issue_pending(adc->dma_chan);
968 if (adc->nconv == 1 && !indio_dev->trig) {
969 /* Enable regular DMA transfer*/
970 ret = regmap_update_bits(adc->dfsdm->regmap,
971 DFSDM_CR1(adc->fl_id),
972 DFSDM_CR1_RDMAEN_MASK,
973 DFSDM_CR1_RDMAEN_MASK);
975 /* Enable injected DMA transfer*/
976 ret = regmap_update_bits(adc->dfsdm->regmap,
977 DFSDM_CR1(adc->fl_id),
978 DFSDM_CR1_JDMAEN_MASK,
979 DFSDM_CR1_JDMAEN_MASK);
988 dmaengine_terminate_all(adc->dma_chan);
993 static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
995 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1000 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
1001 DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
1002 dmaengine_terminate_all(adc->dma_chan);
1005 static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
1006 const unsigned long *scan_mask)
1008 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1010 adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
1011 adc->smask = *scan_mask;
1013 dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
1018 static int __stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1020 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1023 /* Reset adc buffer index */
1027 ret = iio_hw_consumer_enable(adc->hwc);
1032 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1036 ret = stm32_dfsdm_adc_dma_start(indio_dev);
1038 dev_err(&indio_dev->dev, "Can't start DMA\n");
1042 ret = stm32_dfsdm_start_conv(adc, indio_dev->trig);
1044 dev_err(&indio_dev->dev, "Can't start conversion\n");
1051 stm32_dfsdm_adc_dma_stop(indio_dev);
1053 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1056 iio_hw_consumer_disable(adc->hwc);
1061 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1065 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
1066 ret = iio_triggered_buffer_postenable(indio_dev);
1071 ret = __stm32_dfsdm_postenable(indio_dev);
1073 goto err_predisable;
1078 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1079 iio_triggered_buffer_predisable(indio_dev);
1084 static void __stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1086 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1088 stm32_dfsdm_stop_conv(adc);
1090 stm32_dfsdm_adc_dma_stop(indio_dev);
1092 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1095 iio_hw_consumer_disable(adc->hwc);
1098 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1100 __stm32_dfsdm_predisable(indio_dev);
1102 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1103 iio_triggered_buffer_predisable(indio_dev);
1108 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
1109 .postenable = &stm32_dfsdm_postenable,
1110 .predisable = &stm32_dfsdm_predisable,
1114 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
1115 * DMA transfer period is achieved.
1117 * @iio_dev: Handle to IIO device.
1118 * @cb: Pointer to callback function:
1119 * - data: pointer to data buffer
1120 * - size: size in byte of the data buffer
1121 * - private: pointer to consumer private structure.
1122 * @private: Pointer to consumer private structure.
1124 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
1125 int (*cb)(const void *data, size_t size,
1129 struct stm32_dfsdm_adc *adc;
1133 adc = iio_priv(iio_dev);
1136 adc->cb_priv = private;
1140 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
1143 * stm32_dfsdm_release_buff_cb - unregister buffer callback
1145 * @iio_dev: Handle to IIO device.
1147 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1149 struct stm32_dfsdm_adc *adc;
1153 adc = iio_priv(iio_dev);
1156 adc->cb_priv = NULL;
1160 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1162 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1163 const struct iio_chan_spec *chan, int *res)
1165 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1169 reinit_completion(&adc->completion);
1173 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1177 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1178 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1183 adc->smask = BIT(chan->scan_index);
1184 ret = stm32_dfsdm_start_conv(adc, NULL);
1186 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1187 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1191 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
1194 /* Mask IRQ for regular conversion achievement*/
1195 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1196 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1200 else if (timeout < 0)
1205 stm32_dfsdm_stop_conv(adc);
1207 stm32_dfsdm_process_data(adc, res);
1210 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1215 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1216 struct iio_chan_spec const *chan,
1217 int val, int val2, long mask)
1219 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1220 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1221 unsigned int spi_freq;
1225 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1226 spi_freq = adc->dfsdm->spi_master_freq;
1228 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1229 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1230 spi_freq = adc->dfsdm->spi_master_freq / 2;
1233 spi_freq = adc->spi_freq;
1237 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1238 ret = iio_device_claim_direct_mode(indio_dev);
1242 ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
1244 dev_dbg(&indio_dev->dev,
1245 "Sampling rate changed from (%u) to (%u)\n",
1246 adc->sample_freq, spi_freq / val);
1247 adc->oversamp = val;
1248 adc->sample_freq = spi_freq / val;
1250 iio_device_release_direct_mode(indio_dev);
1253 case IIO_CHAN_INFO_SAMP_FREQ:
1257 ret = iio_device_claim_direct_mode(indio_dev);
1261 ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1262 iio_device_release_direct_mode(indio_dev);
1269 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1270 struct iio_chan_spec const *chan, int *val,
1271 int *val2, long mask)
1273 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1277 case IIO_CHAN_INFO_RAW:
1278 ret = iio_device_claim_direct_mode(indio_dev);
1281 ret = iio_hw_consumer_enable(adc->hwc);
1283 dev_err(&indio_dev->dev,
1284 "%s: IIO enable failed (channel %d)\n",
1285 __func__, chan->channel);
1286 iio_device_release_direct_mode(indio_dev);
1289 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1290 iio_hw_consumer_disable(adc->hwc);
1292 dev_err(&indio_dev->dev,
1293 "%s: Conversion failed (channel %d)\n",
1294 __func__, chan->channel);
1295 iio_device_release_direct_mode(indio_dev);
1298 iio_device_release_direct_mode(indio_dev);
1301 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1302 *val = adc->oversamp;
1306 case IIO_CHAN_INFO_SAMP_FREQ:
1307 *val = adc->sample_freq;
1315 static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1316 struct iio_trigger *trig)
1318 return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1321 static const struct iio_info stm32_dfsdm_info_audio = {
1322 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1323 .read_raw = stm32_dfsdm_read_raw,
1324 .write_raw = stm32_dfsdm_write_raw,
1325 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1328 static const struct iio_info stm32_dfsdm_info_adc = {
1329 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1330 .read_raw = stm32_dfsdm_read_raw,
1331 .write_raw = stm32_dfsdm_write_raw,
1332 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1333 .validate_trigger = stm32_dfsdm_validate_trigger,
1336 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1338 struct stm32_dfsdm_adc *adc = arg;
1339 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1340 struct regmap *regmap = adc->dfsdm->regmap;
1341 unsigned int status, int_en;
1343 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1344 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1346 if (status & DFSDM_ISR_REOCF_MASK) {
1347 /* Read the data register clean the IRQ status */
1348 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1349 complete(&adc->completion);
1352 if (status & DFSDM_ISR_ROVRF_MASK) {
1353 if (int_en & DFSDM_CR2_ROVRIE_MASK)
1354 dev_warn(&indio_dev->dev, "Overrun detected\n");
1355 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
1356 DFSDM_ICR_CLRROVRF_MASK,
1357 DFSDM_ICR_CLRROVRF_MASK);
1364 * Define external info for SPI Frequency and audio sampling rate that can be
1365 * configured by ASoC driver through consumer.h API
1367 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1368 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1370 .name = "spi_clk_freq",
1371 .shared = IIO_SHARED_BY_TYPE,
1372 .read = dfsdm_adc_audio_get_spiclk,
1373 .write = dfsdm_adc_audio_set_spiclk,
1378 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1380 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1382 if (adc->dma_chan) {
1383 dma_free_coherent(adc->dma_chan->device->dev,
1384 DFSDM_DMA_BUFFER_SIZE,
1385 adc->rx_buf, adc->dma_buf);
1386 dma_release_channel(adc->dma_chan);
1390 static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev)
1392 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1394 adc->dma_chan = dma_request_chan(&indio_dev->dev, "rx");
1395 if (IS_ERR(adc->dma_chan)) {
1396 int ret = PTR_ERR(adc->dma_chan);
1398 adc->dma_chan = NULL;
1402 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1403 DFSDM_DMA_BUFFER_SIZE,
1404 &adc->dma_buf, GFP_KERNEL);
1406 dma_release_channel(adc->dma_chan);
1410 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1411 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1416 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
1417 struct iio_chan_spec *ch)
1419 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1422 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1426 ch->type = IIO_VOLTAGE;
1430 * IIO_CHAN_INFO_RAW: used to compute regular conversion
1431 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1433 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1434 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1435 BIT(IIO_CHAN_INFO_SAMP_FREQ);
1437 if (adc->dev_data->type == DFSDM_AUDIO) {
1438 ch->ext_info = dfsdm_adc_audio_ext_info;
1440 ch->scan_type.shift = 8;
1442 ch->scan_type.sign = 's';
1443 ch->scan_type.realbits = 24;
1444 ch->scan_type.storagebits = 32;
1446 return stm32_dfsdm_chan_configure(adc->dfsdm,
1447 &adc->dfsdm->ch_list[ch->channel]);
1450 static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev)
1452 struct iio_chan_spec *ch;
1453 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1454 struct stm32_dfsdm_channel *d_ch;
1457 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1463 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1465 dev_err(&indio_dev->dev, "Channels init failed\n");
1468 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1470 d_ch = &adc->dfsdm->ch_list[ch->channel];
1471 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1472 adc->spi_freq = adc->dfsdm->spi_master_freq;
1474 indio_dev->num_channels = 1;
1475 indio_dev->channels = ch;
1477 return stm32_dfsdm_dma_request(indio_dev);
1480 static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
1482 struct iio_chan_spec *ch;
1483 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1487 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1488 ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1492 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1494 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1495 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1496 return num_ch < 0 ? num_ch : -EINVAL;
1499 /* Bind to SD modulator IIO device */
1500 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1501 if (IS_ERR(adc->hwc))
1502 return -EPROBE_DEFER;
1504 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1509 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1510 ch[chan_idx].scan_index = chan_idx;
1511 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1513 dev_err(&indio_dev->dev, "Channels init failed\n");
1518 indio_dev->num_channels = num_ch;
1519 indio_dev->channels = ch;
1521 init_completion(&adc->completion);
1523 /* Optionally request DMA */
1524 ret = stm32_dfsdm_dma_request(indio_dev);
1526 if (ret != -ENODEV) {
1527 if (ret != -EPROBE_DEFER)
1528 dev_err(&indio_dev->dev,
1529 "DMA channel request failed with %d\n",
1534 dev_dbg(&indio_dev->dev, "No DMA support\n");
1538 ret = iio_triggered_buffer_setup(indio_dev,
1539 &iio_pollfunc_store_time,
1540 &stm32_dfsdm_adc_trigger_handler,
1541 &stm32_dfsdm_buffer_setup_ops);
1543 stm32_dfsdm_dma_release(indio_dev);
1544 dev_err(&indio_dev->dev, "buffer setup failed\n");
1548 /* lptimer/timer hardware triggers */
1549 indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1554 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1556 .init = stm32_dfsdm_adc_init,
1559 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1560 .type = DFSDM_AUDIO,
1561 .init = stm32_dfsdm_audio_init,
1564 static const struct of_device_id stm32_dfsdm_adc_match[] = {
1566 .compatible = "st,stm32-dfsdm-adc",
1567 .data = &stm32h7_dfsdm_adc_data,
1570 .compatible = "st,stm32-dfsdm-dmic",
1571 .data = &stm32h7_dfsdm_audio_data,
1576 static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1578 struct device *dev = &pdev->dev;
1579 struct stm32_dfsdm_adc *adc;
1580 struct device_node *np = dev->of_node;
1581 const struct stm32_dfsdm_dev_data *dev_data;
1582 struct iio_dev *iio;
1586 dev_data = of_device_get_match_data(dev);
1587 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1589 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1593 adc = iio_priv(iio);
1594 adc->dfsdm = dev_get_drvdata(dev->parent);
1596 iio->dev.parent = dev;
1597 iio->dev.of_node = np;
1598 iio->modes = INDIO_DIRECT_MODE;
1600 platform_set_drvdata(pdev, adc);
1602 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1603 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1604 dev_err(dev, "Missing or bad reg property\n");
1608 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1611 if (dev_data->type == DFSDM_AUDIO) {
1612 iio->info = &stm32_dfsdm_info_audio;
1613 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1615 iio->info = &stm32_dfsdm_info_adc;
1616 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1621 * In a first step IRQs generated for channels are not treated.
1622 * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1624 irq = platform_get_irq(pdev, 0);
1628 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1629 0, pdev->name, adc);
1631 dev_err(dev, "Failed to request IRQ\n");
1635 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1637 dev_err(dev, "Failed to set filter order\n");
1641 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1643 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1645 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1647 adc->dev_data = dev_data;
1648 ret = dev_data->init(iio);
1652 ret = iio_device_register(iio);
1656 if (dev_data->type == DFSDM_AUDIO) {
1657 ret = of_platform_populate(np, NULL, NULL, dev);
1659 dev_err(dev, "Failed to find an audio DAI\n");
1660 goto err_unregister;
1667 iio_device_unregister(iio);
1669 stm32_dfsdm_dma_release(iio);
1674 static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1676 struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
1677 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1679 if (adc->dev_data->type == DFSDM_AUDIO)
1680 of_platform_depopulate(&pdev->dev);
1681 iio_device_unregister(indio_dev);
1682 stm32_dfsdm_dma_release(indio_dev);
1687 static int __maybe_unused stm32_dfsdm_adc_suspend(struct device *dev)
1689 struct stm32_dfsdm_adc *adc = dev_get_drvdata(dev);
1690 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1692 if (iio_buffer_enabled(indio_dev))
1693 __stm32_dfsdm_predisable(indio_dev);
1698 static int __maybe_unused stm32_dfsdm_adc_resume(struct device *dev)
1700 struct stm32_dfsdm_adc *adc = dev_get_drvdata(dev);
1701 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1702 const struct iio_chan_spec *chan;
1703 struct stm32_dfsdm_channel *ch;
1706 /* restore channels configuration */
1707 for (i = 0; i < indio_dev->num_channels; i++) {
1708 chan = indio_dev->channels + i;
1709 ch = &adc->dfsdm->ch_list[chan->channel];
1710 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1715 if (iio_buffer_enabled(indio_dev))
1716 __stm32_dfsdm_postenable(indio_dev);
1721 static SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1722 stm32_dfsdm_adc_suspend, stm32_dfsdm_adc_resume);
1724 static struct platform_driver stm32_dfsdm_adc_driver = {
1726 .name = "stm32-dfsdm-adc",
1727 .of_match_table = stm32_dfsdm_adc_match,
1728 .pm = &stm32_dfsdm_adc_pm_ops,
1730 .probe = stm32_dfsdm_adc_probe,
1731 .remove = stm32_dfsdm_adc_remove,
1733 module_platform_driver(stm32_dfsdm_adc_driver);
1735 MODULE_DESCRIPTION("STM32 sigma delta ADC");
1736 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1737 MODULE_LICENSE("GPL v2");