drivers/iio/adc/ti-ads1015.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ADS1015 - Texas Instruments Analog-to-Digital Converter
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  *
   7  * IIO driver for ADS1015 ADC 7-bit I2C slave address:
   8  *      * 0x48 - ADDR connected to Ground
   9  *      * 0x49 - ADDR connected to Vdd
  10  *      * 0x4A - ADDR connected to SDA
  11  *      * 0x4B - ADDR connected to SCL
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/i2c.h>
  18 #include <linux/property.h>
  19 #include <linux/regmap.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/mutex.h>
  22 #include <linux/delay.h>
  23
  24 #include <linux/iio/iio.h>
  25 #include <linux/iio/types.h>
  26 #include <linux/iio/sysfs.h>
  27 #include <linux/iio/events.h>
  28 #include <linux/iio/buffer.h>
  29 #include <linux/iio/triggered_buffer.h>
  30 #include <linux/iio/trigger_consumer.h>
  31
  32 #define ADS1015_DRV_NAME "ads1015"
  33
  34 #define ADS1015_CHANNELS 8
  35
  36 #define ADS1015_CONV_REG        0x00
  37 #define ADS1015_CFG_REG         0x01
  38 #define ADS1015_LO_THRESH_REG   0x02
  39 #define ADS1015_HI_THRESH_REG   0x03
  40
  41 #define ADS1015_CFG_COMP_QUE_SHIFT      0
  42 #define ADS1015_CFG_COMP_LAT_SHIFT      2
  43 #define ADS1015_CFG_COMP_POL_SHIFT      3
  44 #define ADS1015_CFG_COMP_MODE_SHIFT     4
  45 #define ADS1015_CFG_DR_SHIFT    5
  46 #define ADS1015_CFG_MOD_SHIFT   8
  47 #define ADS1015_CFG_PGA_SHIFT   9
  48 #define ADS1015_CFG_MUX_SHIFT   12
  49
  50 #define ADS1015_CFG_COMP_QUE_MASK       GENMASK(1, 0)
  51 #define ADS1015_CFG_COMP_LAT_MASK       BIT(2)
  52 #define ADS1015_CFG_COMP_POL_MASK       BIT(3)
  53 #define ADS1015_CFG_COMP_MODE_MASK      BIT(4)
  54 #define ADS1015_CFG_DR_MASK     GENMASK(7, 5)
  55 #define ADS1015_CFG_MOD_MASK    BIT(8)
  56 #define ADS1015_CFG_PGA_MASK    GENMASK(11, 9)
  57 #define ADS1015_CFG_MUX_MASK    GENMASK(14, 12)
  58
  59 /* Comparator queue and disable field */
  60 #define ADS1015_CFG_COMP_DISABLE        3
  61
  62 /* Comparator polarity field */
  63 #define ADS1015_CFG_COMP_POL_LOW        0
  64 #define ADS1015_CFG_COMP_POL_HIGH       1
  65
  66 /* Comparator mode field */
  67 #define ADS1015_CFG_COMP_MODE_TRAD      0
  68 #define ADS1015_CFG_COMP_MODE_WINDOW    1
  69
  70 /* device operating modes */
  71 #define ADS1015_CONTINUOUS      0
  72 #define ADS1015_SINGLESHOT      1
  73
  74 #define ADS1015_SLEEP_DELAY_MS          2000
  75 #define ADS1015_DEFAULT_PGA             2
  76 #define ADS1015_DEFAULT_DATA_RATE       4
  77 #define ADS1015_DEFAULT_CHAN            0
  78
  79 enum chip_ids {
  80         ADSXXXX = 0,
  81         ADS1015,
  82         ADS1115,
  83 };
  84
  85 enum ads1015_channels {
  86         ADS1015_AIN0_AIN1 = 0,
  87         ADS1015_AIN0_AIN3,
  88         ADS1015_AIN1_AIN3,
  89         ADS1015_AIN2_AIN3,
  90         ADS1015_AIN0,
  91         ADS1015_AIN1,
  92         ADS1015_AIN2,
  93         ADS1015_AIN3,
  94         ADS1015_TIMESTAMP,
  95 };
  96
  97 static const unsigned int ads1015_data_rate[] = {
  98         128, 250, 490, 920, 1600, 2400, 3300, 3300
  99 };
 100
 101 static const unsigned int ads1115_data_rate[] = {
 102         8, 16, 32, 64, 128, 250, 475, 860
 103 };
 104
 105 /*
 106  * Translation from PGA bits to full-scale positive and negative input voltage
 107  * range in mV
 108  */
 109 static int ads1015_fullscale_range[] = {
 110         6144, 4096, 2048, 1024, 512, 256, 256, 256
 111 };
 112
 113 /*
 114  * Translation from COMP_QUE field value to the number of successive readings
 115  * exceed the threshold values before an interrupt is generated
 116  */
 117 static const int ads1015_comp_queue[] = { 1, 2, 4 };
 118
 119 static const struct iio_event_spec ads1015_events[] = {
 120         {
 121                 .type = IIO_EV_TYPE_THRESH,
 122                 .dir = IIO_EV_DIR_RISING,
 123                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 124                                 BIT(IIO_EV_INFO_ENABLE),
 125         }, {
 126                 .type = IIO_EV_TYPE_THRESH,
 127                 .dir = IIO_EV_DIR_FALLING,
 128                 .mask_separate = BIT(IIO_EV_INFO_VALUE),
 129         }, {
 130                 .type = IIO_EV_TYPE_THRESH,
 131                 .dir = IIO_EV_DIR_EITHER,
 132                 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
 133                                 BIT(IIO_EV_INFO_PERIOD),
 134         },
 135 };
 136
 137 #define ADS1015_V_CHAN(_chan, _addr) {                          \
 138         .type = IIO_VOLTAGE,                                    \
 139         .indexed = 1,                                           \
 140         .address = _addr,                                       \
 141         .channel = _chan,                                       \
 142         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 143                                 BIT(IIO_CHAN_INFO_SCALE) |      \
 144                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 145         .scan_index = _addr,                                    \
 146         .scan_type = {                                          \
 147                 .sign = 's',                                    \
 148                 .realbits = 12,                                 \
 149                 .storagebits = 16,                              \
 150                 .shift = 4,                                     \
 151                 .endianness = IIO_CPU,                          \
 152         },                                                      \
 153         .event_spec = ads1015_events,                           \
 154         .num_event_specs = ARRAY_SIZE(ads1015_events),          \
 155         .datasheet_name = "AIN"#_chan,                          \
 156 }
 157
 158 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) {             \
 159         .type = IIO_VOLTAGE,                                    \
 160         .differential = 1,                                      \
 161         .indexed = 1,                                           \
 162         .address = _addr,                                       \
 163         .channel = _chan,                                       \
 164         .channel2 = _chan2,                                     \
 165         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 166                                 BIT(IIO_CHAN_INFO_SCALE) |      \
 167                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 168         .scan_index = _addr,                                    \
 169         .scan_type = {                                          \
 170                 .sign = 's',                                    \
 171                 .realbits = 12,                                 \
 172                 .storagebits = 16,                              \
 173                 .shift = 4,                                     \
 174                 .endianness = IIO_CPU,                          \
 175         },                                                      \
 176         .event_spec = ads1015_events,                           \
 177         .num_event_specs = ARRAY_SIZE(ads1015_events),          \
 178         .datasheet_name = "AIN"#_chan"-AIN"#_chan2,             \
 179 }
 180
 181 #define ADS1115_V_CHAN(_chan, _addr) {                          \
 182         .type = IIO_VOLTAGE,                                    \
 183         .indexed = 1,                                           \
 184         .address = _addr,                                       \
 185         .channel = _chan,                                       \
 186         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 187                                 BIT(IIO_CHAN_INFO_SCALE) |      \
 188                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 189         .scan_index = _addr,                                    \
 190         .scan_type = {                                          \
 191                 .sign = 's',                                    \
 192                 .realbits = 16,                                 \
 193                 .storagebits = 16,                              \
 194                 .endianness = IIO_CPU,                          \
 195         },                                                      \
 196         .event_spec = ads1015_events,                           \
 197         .num_event_specs = ARRAY_SIZE(ads1015_events),          \
 198         .datasheet_name = "AIN"#_chan,                          \
 199 }
 200
 201 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) {             \
 202         .type = IIO_VOLTAGE,                                    \
 203         .differential = 1,                                      \
 204         .indexed = 1,                                           \
 205         .address = _addr,                                       \
 206         .channel = _chan,                                       \
 207         .channel2 = _chan2,                                     \
 208         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 209                                 BIT(IIO_CHAN_INFO_SCALE) |      \
 210                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 211         .scan_index = _addr,                                    \
 212         .scan_type = {                                          \
 213                 .sign = 's',                                    \
 214                 .realbits = 16,                                 \
 215                 .storagebits = 16,                              \
 216                 .endianness = IIO_CPU,                          \
 217         },                                                      \
 218         .event_spec = ads1015_events,                           \
 219         .num_event_specs = ARRAY_SIZE(ads1015_events),          \
 220         .datasheet_name = "AIN"#_chan"-AIN"#_chan2,             \
 221 }
 222
 223 struct ads1015_channel_data {
 224         bool enabled;
 225         unsigned int pga;
 226         unsigned int data_rate;
 227 };
 228
 229 struct ads1015_thresh_data {
 230         unsigned int comp_queue;
 231         int high_thresh;
 232         int low_thresh;
 233 };
 234
 235 struct ads1015_data {
 236         struct regmap *regmap;
 237         /*
 238          * Protects ADC ops, e.g: concurrent sysfs/buffered
 239          * data reads, configuration updates
 240          */
 241         struct mutex lock;
 242         struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
 243
 244         unsigned int event_channel;
 245         unsigned int comp_mode;
 246         struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
 247
 248         unsigned int *data_rate;
 249         /*
 250          * Set to true when the ADC is switched to the continuous-conversion
 251          * mode and exits from a power-down state.  This flag is used to avoid
 252          * getting the stale result from the conversion register.
 253          */
 254         bool conv_invalid;
 255 };
 256
 257 static bool ads1015_event_channel_enabled(struct ads1015_data *data)
 258 {
 259         return (data->event_channel != ADS1015_CHANNELS);
 260 }
 261
 262 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
 263                                          int comp_mode)
 264 {
 265         WARN_ON(ads1015_event_channel_enabled(data));
 266
 267         data->event_channel = chan;
 268         data->comp_mode = comp_mode;
 269 }
 270
 271 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
 272 {
 273         data->event_channel = ADS1015_CHANNELS;
 274 }
 275
 276 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
 277 {
 278         switch (reg) {
 279         case ADS1015_CFG_REG:
 280         case ADS1015_LO_THRESH_REG:
 281         case ADS1015_HI_THRESH_REG:
 282                 return true;
 283         default:
 284                 return false;
 285         }
 286 }
 287
 288 static const struct regmap_config ads1015_regmap_config = {
 289         .reg_bits = 8,
 290         .val_bits = 16,
 291         .max_register = ADS1015_HI_THRESH_REG,
 292         .writeable_reg = ads1015_is_writeable_reg,
 293 };
 294
 295 static const struct iio_chan_spec ads1015_channels[] = {
 296         ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
 297         ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
 298         ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
 299         ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
 300         ADS1015_V_CHAN(0, ADS1015_AIN0),
 301         ADS1015_V_CHAN(1, ADS1015_AIN1),
 302         ADS1015_V_CHAN(2, ADS1015_AIN2),
 303         ADS1015_V_CHAN(3, ADS1015_AIN3),
 304         IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
 305 };
 306
 307 static const struct iio_chan_spec ads1115_channels[] = {
 308         ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
 309         ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
 310         ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
 311         ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
 312         ADS1115_V_CHAN(0, ADS1015_AIN0),
 313         ADS1115_V_CHAN(1, ADS1015_AIN1),
 314         ADS1115_V_CHAN(2, ADS1015_AIN2),
 315         ADS1115_V_CHAN(3, ADS1015_AIN3),
 316         IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
 317 };
 318
 319 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
 320 {
 321         int ret;
 322         struct device *dev = regmap_get_device(data->regmap);
 323
 324         if (on) {
 325                 ret = pm_runtime_get_sync(dev);
 326                 if (ret < 0)
 327                         pm_runtime_put_noidle(dev);
 328         } else {
 329                 pm_runtime_mark_last_busy(dev);
 330                 ret = pm_runtime_put_autosuspend(dev);
 331         }
 332
 333         return ret < 0 ? ret : 0;
 334 }
 335
 336 static
 337 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
 338 {
 339         int ret, pga, dr, dr_old, conv_time;
 340         unsigned int old, mask, cfg;
 341
 342         if (chan < 0 || chan >= ADS1015_CHANNELS)
 343                 return -EINVAL;
 344
 345         ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
 346         if (ret)
 347                 return ret;
 348
 349         pga = data->channel_data[chan].pga;
 350         dr = data->channel_data[chan].data_rate;
 351         mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
 352                 ADS1015_CFG_DR_MASK;
 353         cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
 354                 dr << ADS1015_CFG_DR_SHIFT;
 355
 356         if (ads1015_event_channel_enabled(data)) {
 357                 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
 358                 cfg |= data->thresh_data[chan].comp_queue <<
 359                                 ADS1015_CFG_COMP_QUE_SHIFT |
 360                         data->comp_mode <<
 361                                 ADS1015_CFG_COMP_MODE_SHIFT;
 362         }
 363
 364         cfg = (old & ~mask) | (cfg & mask);
 365         if (old != cfg) {
 366                 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
 367                 if (ret)
 368                         return ret;
 369                 data->conv_invalid = true;
 370         }
 371         if (data->conv_invalid) {
 372                 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
 373                 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
 374                 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
 375                 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
 376                 usleep_range(conv_time, conv_time + 1);
 377                 data->conv_invalid = false;
 378         }
 379
 380         return regmap_read(data->regmap, ADS1015_CONV_REG, val);
 381 }
 382
 383 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
 384 {
 385         struct iio_poll_func *pf = p;
 386         struct iio_dev *indio_dev = pf->indio_dev;
 387         struct ads1015_data *data = iio_priv(indio_dev);
 388         s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding +  4x s16 timestamp */
 389         int chan, ret, res;
 390
 391         memset(buf, 0, sizeof(buf));
 392
 393         mutex_lock(&data->lock);
 394         chan = find_first_bit(indio_dev->active_scan_mask,
 395                               indio_dev->masklength);
 396         ret = ads1015_get_adc_result(data, chan, &res);
 397         if (ret < 0) {
 398                 mutex_unlock(&data->lock);
 399                 goto err;
 400         }
 401
 402         buf[0] = res;
 403         mutex_unlock(&data->lock);
 404
 405         iio_push_to_buffers_with_timestamp(indio_dev, buf,
 406                                            iio_get_time_ns(indio_dev));
 407
 408 err:
 409         iio_trigger_notify_done(indio_dev->trig);
 410
 411         return IRQ_HANDLED;
 412 }
 413
 414 static int ads1015_set_scale(struct ads1015_data *data,
 415                              struct iio_chan_spec const *chan,
 416                              int scale, int uscale)
 417 {
 418         int i;
 419         int fullscale = div_s64((scale * 1000000LL + uscale) <<
 420                                 (chan->scan_type.realbits - 1), 1000000);
 421
 422         for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
 423                 if (ads1015_fullscale_range[i] == fullscale) {
 424                         data->channel_data[chan->address].pga = i;
 425                         return 0;
 426                 }
 427         }
 428
 429         return -EINVAL;
 430 }
 431
 432 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
 433 {
 434         int i;
 435
 436         for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
 437                 if (data->data_rate[i] == rate) {
 438                         data->channel_data[chan].data_rate = i;
 439                         return 0;
 440                 }
 441         }
 442
 443         return -EINVAL;
 444 }
 445
 446 static int ads1015_read_raw(struct iio_dev *indio_dev,
 447                             struct iio_chan_spec const *chan, int *val,
 448                             int *val2, long mask)
 449 {
 450         int ret, idx;
 451         struct ads1015_data *data = iio_priv(indio_dev);
 452
 453         mutex_lock(&data->lock);
 454         switch (mask) {
 455         case IIO_CHAN_INFO_RAW: {
 456                 int shift = chan->scan_type.shift;
 457
 458                 ret = iio_device_claim_direct_mode(indio_dev);
 459                 if (ret)
 460                         break;
 461
 462                 if (ads1015_event_channel_enabled(data) &&
 463                                 data->event_channel != chan->address) {
 464                         ret = -EBUSY;
 465                         goto release_direct;
 466                 }
 467
 468                 ret = ads1015_set_power_state(data, true);
 469                 if (ret < 0)
 470                         goto release_direct;
 471
 472                 ret = ads1015_get_adc_result(data, chan->address, val);
 473                 if (ret < 0) {
 474                         ads1015_set_power_state(data, false);
 475                         goto release_direct;
 476                 }
 477
 478                 *val = sign_extend32(*val >> shift, 15 - shift);
 479
 480                 ret = ads1015_set_power_state(data, false);
 481                 if (ret < 0)
 482                         goto release_direct;
 483
 484                 ret = IIO_VAL_INT;
 485 release_direct:
 486                 iio_device_release_direct_mode(indio_dev);
 487                 break;
 488         }
 489         case IIO_CHAN_INFO_SCALE:
 490                 idx = data->channel_data[chan->address].pga;
 491                 *val = ads1015_fullscale_range[idx];
 492                 *val2 = chan->scan_type.realbits - 1;
 493                 ret = IIO_VAL_FRACTIONAL_LOG2;
 494                 break;
 495         case IIO_CHAN_INFO_SAMP_FREQ:
 496                 idx = data->channel_data[chan->address].data_rate;
 497                 *val = data->data_rate[idx];
 498                 ret = IIO_VAL_INT;
 499                 break;
 500         default:
 501                 ret = -EINVAL;
 502                 break;
 503         }
 504         mutex_unlock(&data->lock);
 505
 506         return ret;
 507 }
 508
 509 static int ads1015_write_raw(struct iio_dev *indio_dev,
 510                              struct iio_chan_spec const *chan, int val,
 511                              int val2, long mask)
 512 {
 513         struct ads1015_data *data = iio_priv(indio_dev);
 514         int ret;
 515
 516         mutex_lock(&data->lock);
 517         switch (mask) {
 518         case IIO_CHAN_INFO_SCALE:
 519                 ret = ads1015_set_scale(data, chan, val, val2);
 520                 break;
 521         case IIO_CHAN_INFO_SAMP_FREQ:
 522                 ret = ads1015_set_data_rate(data, chan->address, val);
 523                 break;
 524         default:
 525                 ret = -EINVAL;
 526                 break;
 527         }
 528         mutex_unlock(&data->lock);
 529
 530         return ret;
 531 }
 532
 533 static int ads1015_read_event(struct iio_dev *indio_dev,
 534         const struct iio_chan_spec *chan, enum iio_event_type type,
 535         enum iio_event_direction dir, enum iio_event_info info, int *val,
 536         int *val2)
 537 {
 538         struct ads1015_data *data = iio_priv(indio_dev);
 539         int ret;
 540         unsigned int comp_queue;
 541         int period;
 542         int dr;
 543
 544         mutex_lock(&data->lock);
 545
 546         switch (info) {
 547         case IIO_EV_INFO_VALUE:
 548                 *val = (dir == IIO_EV_DIR_RISING) ?
 549                         data->thresh_data[chan->address].high_thresh :
 550                         data->thresh_data[chan->address].low_thresh;
 551                 ret = IIO_VAL_INT;
 552                 break;
 553         case IIO_EV_INFO_PERIOD:
 554                 dr = data->channel_data[chan->address].data_rate;
 555                 comp_queue = data->thresh_data[chan->address].comp_queue;
 556                 period = ads1015_comp_queue[comp_queue] *
 557                         USEC_PER_SEC / data->data_rate[dr];
 558
 559                 *val = period / USEC_PER_SEC;
 560                 *val2 = period % USEC_PER_SEC;
 561                 ret = IIO_VAL_INT_PLUS_MICRO;
 562                 break;
 563         default:
 564                 ret = -EINVAL;
 565                 break;
 566         }
 567
 568         mutex_unlock(&data->lock);
 569
 570         return ret;
 571 }
 572
 573 static int ads1015_write_event(struct iio_dev *indio_dev,
 574         const struct iio_chan_spec *chan, enum iio_event_type type,
 575         enum iio_event_direction dir, enum iio_event_info info, int val,
 576         int val2)
 577 {
 578         struct ads1015_data *data = iio_priv(indio_dev);
 579         int realbits = chan->scan_type.realbits;
 580         int ret = 0;
 581         long long period;
 582         int i;
 583         int dr;
 584
 585         mutex_lock(&data->lock);
 586
 587         switch (info) {
 588         case IIO_EV_INFO_VALUE:
 589                 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
 590                         ret = -EINVAL;
 591                         break;
 592                 }
 593                 if (dir == IIO_EV_DIR_RISING)
 594                         data->thresh_data[chan->address].high_thresh = val;
 595                 else
 596                         data->thresh_data[chan->address].low_thresh = val;
 597                 break;
 598         case IIO_EV_INFO_PERIOD:
 599                 dr = data->channel_data[chan->address].data_rate;
 600                 period = val * USEC_PER_SEC + val2;
 601
 602                 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
 603                         if (period <= ads1015_comp_queue[i] *
 604                                         USEC_PER_SEC / data->data_rate[dr])
 605                                 break;
 606                 }
 607                 data->thresh_data[chan->address].comp_queue = i;
 608                 break;
 609         default:
 610                 ret = -EINVAL;
 611                 break;
 612         }
 613
 614         mutex_unlock(&data->lock);
 615
 616         return ret;
 617 }
 618
 619 static int ads1015_read_event_config(struct iio_dev *indio_dev,
 620         const struct iio_chan_spec *chan, enum iio_event_type type,
 621         enum iio_event_direction dir)
 622 {
 623         struct ads1015_data *data = iio_priv(indio_dev);
 624         int ret = 0;
 625
 626         mutex_lock(&data->lock);
 627         if (data->event_channel == chan->address) {
 628                 switch (dir) {
 629                 case IIO_EV_DIR_RISING:
 630                         ret = 1;
 631                         break;
 632                 case IIO_EV_DIR_EITHER:
 633                         ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
 634                         break;
 635                 default:
 636                         ret = -EINVAL;
 637                         break;
 638                 }
 639         }
 640         mutex_unlock(&data->lock);
 641
 642         return ret;
 643 }
 644
 645 static int ads1015_enable_event_config(struct ads1015_data *data,
 646         const struct iio_chan_spec *chan, int comp_mode)
 647 {
 648         int low_thresh = data->thresh_data[chan->address].low_thresh;
 649         int high_thresh = data->thresh_data[chan->address].high_thresh;
 650         int ret;
 651         unsigned int val;
 652
 653         if (ads1015_event_channel_enabled(data)) {
 654                 if (data->event_channel != chan->address ||
 655                         (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
 656                                 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
 657                         return -EBUSY;
 658
 659                 return 0;
 660         }
 661
 662         if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
 663                 low_thresh = max(-1 << (chan->scan_type.realbits - 1),
 664                                 high_thresh - 1);
 665         }
 666         ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
 667                         low_thresh << chan->scan_type.shift);
 668         if (ret)
 669                 return ret;
 670
 671         ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
 672                         high_thresh << chan->scan_type.shift);
 673         if (ret)
 674                 return ret;
 675
 676         ret = ads1015_set_power_state(data, true);
 677         if (ret < 0)
 678                 return ret;
 679
 680         ads1015_event_channel_enable(data, chan->address, comp_mode);
 681
 682         ret = ads1015_get_adc_result(data, chan->address, &val);
 683         if (ret) {
 684                 ads1015_event_channel_disable(data, chan->address);
 685                 ads1015_set_power_state(data, false);
 686         }
 687
 688         return ret;
 689 }
 690
 691 static int ads1015_disable_event_config(struct ads1015_data *data,
 692         const struct iio_chan_spec *chan, int comp_mode)
 693 {
 694         int ret;
 695
 696         if (!ads1015_event_channel_enabled(data))
 697                 return 0;
 698
 699         if (data->event_channel != chan->address)
 700                 return 0;
 701
 702         if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
 703                         comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
 704                 return 0;
 705
 706         ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
 707                                 ADS1015_CFG_COMP_QUE_MASK,
 708                                 ADS1015_CFG_COMP_DISABLE <<
 709                                         ADS1015_CFG_COMP_QUE_SHIFT);
 710         if (ret)
 711                 return ret;
 712
 713         ads1015_event_channel_disable(data, chan->address);
 714
 715         return ads1015_set_power_state(data, false);
 716 }
 717
 718 static int ads1015_write_event_config(struct iio_dev *indio_dev,
 719         const struct iio_chan_spec *chan, enum iio_event_type type,
 720         enum iio_event_direction dir, int state)
 721 {
 722         struct ads1015_data *data = iio_priv(indio_dev);
 723         int ret;
 724         int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
 725                 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
 726
 727         mutex_lock(&data->lock);
 728
 729         /* Prevent from enabling both buffer and event at a time */
 730         ret = iio_device_claim_direct_mode(indio_dev);
 731         if (ret) {
 732                 mutex_unlock(&data->lock);
 733                 return ret;
 734         }
 735
 736         if (state)
 737                 ret = ads1015_enable_event_config(data, chan, comp_mode);
 738         else
 739                 ret = ads1015_disable_event_config(data, chan, comp_mode);
 740
 741         iio_device_release_direct_mode(indio_dev);
 742         mutex_unlock(&data->lock);
 743
 744         return ret;
 745 }
 746
 747 static irqreturn_t ads1015_event_handler(int irq, void *priv)
 748 {
 749         struct iio_dev *indio_dev = priv;
 750         struct ads1015_data *data = iio_priv(indio_dev);
 751         int val;
 752         int ret;
 753
 754         /* Clear the latched ALERT/RDY pin */
 755         ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
 756         if (ret)
 757                 return IRQ_HANDLED;
 758
 759         if (ads1015_event_channel_enabled(data)) {
 760                 enum iio_event_direction dir;
 761                 u64 code;
 762
 763                 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
 764                                         IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
 765                 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
 766                                         IIO_EV_TYPE_THRESH, dir);
 767                 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
 768         }
 769
 770         return IRQ_HANDLED;
 771 }
 772
 773 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
 774 {
 775         struct ads1015_data *data = iio_priv(indio_dev);
 776
 777         /* Prevent from enabling both buffer and event at a time */
 778         if (ads1015_event_channel_enabled(data))
 779                 return -EBUSY;
 780
 781         return ads1015_set_power_state(iio_priv(indio_dev), true);
 782 }
 783
 784 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
 785 {
 786         return ads1015_set_power_state(iio_priv(indio_dev), false);
 787 }
 788
 789 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
 790         .preenable      = ads1015_buffer_preenable,
 791         .postenable     = iio_triggered_buffer_postenable,
 792         .predisable     = iio_triggered_buffer_predisable,
 793         .postdisable    = ads1015_buffer_postdisable,
 794         .validate_scan_mask = &iio_validate_scan_mask_onehot,
 795 };
 796
 797 static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
 798         "3 2 1 0.5 0.25 0.125");
 799 static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
 800         "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
 801
 802 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
 803         sampling_frequency_available, "128 250 490 920 1600 2400 3300");
 804 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
 805         sampling_frequency_available, "8 16 32 64 128 250 475 860");
 806
 807 static struct attribute *ads1015_attributes[] = {
 808         &iio_const_attr_ads1015_scale_available.dev_attr.attr,
 809         &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
 810         NULL,
 811 };
 812
 813 static const struct attribute_group ads1015_attribute_group = {
 814         .attrs = ads1015_attributes,
 815 };
 816
 817 static struct attribute *ads1115_attributes[] = {
 818         &iio_const_attr_ads1115_scale_available.dev_attr.attr,
 819         &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
 820         NULL,
 821 };
 822
 823 static const struct attribute_group ads1115_attribute_group = {
 824         .attrs = ads1115_attributes,
 825 };
 826
 827 static const struct iio_info ads1015_info = {
 828         .read_raw       = ads1015_read_raw,
 829         .write_raw      = ads1015_write_raw,
 830         .read_event_value = ads1015_read_event,
 831         .write_event_value = ads1015_write_event,
 832         .read_event_config = ads1015_read_event_config,
 833         .write_event_config = ads1015_write_event_config,
 834         .attrs          = &ads1015_attribute_group,
 835 };
 836
 837 static const struct iio_info ads1115_info = {
 838         .read_raw       = ads1015_read_raw,
 839         .write_raw      = ads1015_write_raw,
 840         .read_event_value = ads1015_read_event,
 841         .write_event_value = ads1015_write_event,
 842         .read_event_config = ads1015_read_event_config,
 843         .write_event_config = ads1015_write_event_config,
 844         .attrs          = &ads1115_attribute_group,
 845 };
 846
 847 static int ads1015_client_get_channels_config(struct i2c_client *client)
 848 {
 849         struct iio_dev *indio_dev = i2c_get_clientdata(client);
 850         struct ads1015_data *data = iio_priv(indio_dev);
 851         struct device *dev = &client->dev;
 852         struct fwnode_handle *node;
 853         int i = -1;
 854
 855         device_for_each_child_node(dev, node) {
 856                 u32 pval;
 857                 unsigned int channel;
 858                 unsigned int pga = ADS1015_DEFAULT_PGA;
 859                 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
 860
 861                 if (fwnode_property_read_u32(node, "reg", &pval)) {
 862                         dev_err(dev, "invalid reg on %pfw\n", node);
 863                         continue;
 864                 }
 865
 866                 channel = pval;
 867                 if (channel >= ADS1015_CHANNELS) {
 868                         dev_err(dev, "invalid channel index %d on %pfw\n",
 869                                 channel, node);
 870                         continue;
 871                 }
 872
 873                 if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
 874                         pga = pval;
 875                         if (pga > 6) {
 876                                 dev_err(dev, "invalid gain on %pfw\n", node);
 877                                 fwnode_handle_put(node);
 878                                 return -EINVAL;
 879                         }
 880                 }
 881
 882                 if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
 883                         data_rate = pval;
 884                         if (data_rate > 7) {
 885                                 dev_err(dev, "invalid data_rate on %pfw\n", node);
 886                                 fwnode_handle_put(node);
 887                                 return -EINVAL;
 888                         }
 889                 }
 890
 891                 data->channel_data[channel].pga = pga;
 892                 data->channel_data[channel].data_rate = data_rate;
 893
 894                 i++;
 895         }
 896
 897         return i < 0 ? -EINVAL : 0;
 898 }
 899
 900 static void ads1015_get_channels_config(struct i2c_client *client)
 901 {
 902         unsigned int k;
 903
 904         struct iio_dev *indio_dev = i2c_get_clientdata(client);
 905         struct ads1015_data *data = iio_priv(indio_dev);
 906
 907         if (!ads1015_client_get_channels_config(client))
 908                 return;
 909
 910         /* fallback on default configuration */
 911         for (k = 0; k < ADS1015_CHANNELS; ++k) {
 912                 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
 913                 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
 914         }
 915 }
 916
 917 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
 918 {
 919         return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
 920                                   ADS1015_CFG_MOD_MASK,
 921                                   mode << ADS1015_CFG_MOD_SHIFT);
 922 }
 923
 924 static int ads1015_probe(struct i2c_client *client,
 925                          const struct i2c_device_id *id)
 926 {
 927         struct iio_dev *indio_dev;
 928         struct ads1015_data *data;
 929         int ret;
 930         enum chip_ids chip;
 931         int i;
 932
 933         indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
 934         if (!indio_dev)
 935                 return -ENOMEM;
 936
 937         data = iio_priv(indio_dev);
 938         i2c_set_clientdata(client, indio_dev);
 939
 940         mutex_init(&data->lock);
 941
 942         indio_dev->dev.parent = &client->dev;
 943         indio_dev->dev.of_node = client->dev.of_node;
 944         indio_dev->name = ADS1015_DRV_NAME;
 945         indio_dev->modes = INDIO_DIRECT_MODE;
 946
 947         chip = (enum chip_ids)device_get_match_data(&client->dev);
 948         if (chip == ADSXXXX)
 949                 chip = id->driver_data;
 950         switch (chip) {
 951         case ADS1015:
 952                 indio_dev->channels = ads1015_channels;
 953                 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
 954                 indio_dev->info = &ads1015_info;
 955                 data->data_rate = (unsigned int *) &ads1015_data_rate;
 956                 break;
 957         case ADS1115:
 958                 indio_dev->channels = ads1115_channels;
 959                 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
 960                 indio_dev->info = &ads1115_info;
 961                 data->data_rate = (unsigned int *) &ads1115_data_rate;
 962                 break;
 963         default:
 964                 dev_err(&client->dev, "Unknown chip %d\n", chip);
 965                 return -EINVAL;
 966         }
 967
 968         data->event_channel = ADS1015_CHANNELS;
 969         /*
 970          * Set default lower and upper threshold to min and max value
 971          * respectively.
 972          */
 973         for (i = 0; i < ADS1015_CHANNELS; i++) {
 974                 int realbits = indio_dev->channels[i].scan_type.realbits;
 975
 976                 data->thresh_data[i].low_thresh = -1 << (realbits - 1);
 977                 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
 978         }
 979
 980         /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
 981         ads1015_get_channels_config(client);
 982
 983         data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
 984         if (IS_ERR(data->regmap)) {
 985                 dev_err(&client->dev, "Failed to allocate register map\n");
 986                 return PTR_ERR(data->regmap);
 987         }
 988
 989         ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
 990                                               ads1015_trigger_handler,
 991                                               &ads1015_buffer_setup_ops);
 992         if (ret < 0) {
 993                 dev_err(&client->dev, "iio triggered buffer setup failed\n");
 994                 return ret;
 995         }
 996
 997         if (client->irq) {
 998                 unsigned long irq_trig =
 999                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1000                 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
1001                         ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
1002                 unsigned int cfg_comp =
1003                         ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1004                         1 << ADS1015_CFG_COMP_LAT_SHIFT;
1005
1006                 switch (irq_trig) {
1007                 case IRQF_TRIGGER_LOW:
1008                         cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1009                                         ADS1015_CFG_COMP_POL_SHIFT;
1010                         break;
1011                 case IRQF_TRIGGER_HIGH:
1012                         cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1013                                         ADS1015_CFG_COMP_POL_SHIFT;
1014                         break;
1015                 default:
1016                         return -EINVAL;
1017                 }
1018
1019                 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1020                                         cfg_comp_mask, cfg_comp);
1021                 if (ret)
1022                         return ret;
1023
1024                 ret = devm_request_threaded_irq(&client->dev, client->irq,
1025                                                 NULL, ads1015_event_handler,
1026                                                 irq_trig | IRQF_ONESHOT,
1027                                                 client->name, indio_dev);
1028                 if (ret)
1029                         return ret;
1030         }
1031
1032         ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1033         if (ret)
1034                 return ret;
1035
1036         data->conv_invalid = true;
1037
1038         ret = pm_runtime_set_active(&client->dev);
1039         if (ret)
1040                 return ret;
1041         pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1042         pm_runtime_use_autosuspend(&client->dev);
1043         pm_runtime_enable(&client->dev);
1044
1045         ret = iio_device_register(indio_dev);
1046         if (ret < 0) {
1047                 dev_err(&client->dev, "Failed to register IIO device\n");
1048                 return ret;
1049         }
1050
1051         return 0;
1052 }
1053
1054 static int ads1015_remove(struct i2c_client *client)
1055 {
1056         struct iio_dev *indio_dev = i2c_get_clientdata(client);
1057         struct ads1015_data *data = iio_priv(indio_dev);
1058
1059         iio_device_unregister(indio_dev);
1060
1061         pm_runtime_disable(&client->dev);
1062         pm_runtime_set_suspended(&client->dev);
1063         pm_runtime_put_noidle(&client->dev);
1064
1065         /* power down single shot mode */
1066         return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1067 }
1068
1069 #ifdef CONFIG_PM
1070 static int ads1015_runtime_suspend(struct device *dev)
1071 {
1072         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1073         struct ads1015_data *data = iio_priv(indio_dev);
1074
1075         return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1076 }
1077
1078 static int ads1015_runtime_resume(struct device *dev)
1079 {
1080         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1081         struct ads1015_data *data = iio_priv(indio_dev);
1082         int ret;
1083
1084         ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1085         if (!ret)
1086                 data->conv_invalid = true;
1087
1088         return ret;
1089 }
1090 #endif
1091
1092 static const struct dev_pm_ops ads1015_pm_ops = {
1093         SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1094                            ads1015_runtime_resume, NULL)
1095 };
1096
1097 static const struct i2c_device_id ads1015_id[] = {
1098         {"ads1015", ADS1015},
1099         {"ads1115", ADS1115},
1100         {}
1101 };
1102 MODULE_DEVICE_TABLE(i2c, ads1015_id);
1103
1104 static const struct of_device_id ads1015_of_match[] = {
1105         {
1106                 .compatible = "ti,ads1015",
1107                 .data = (void *)ADS1015
1108         },
1109         {
1110                 .compatible = "ti,ads1115",
1111                 .data = (void *)ADS1115
1112         },
1113         {}
1114 };
1115 MODULE_DEVICE_TABLE(of, ads1015_of_match);
1116
1117 static struct i2c_driver ads1015_driver = {
1118         .driver = {
1119                 .name = ADS1015_DRV_NAME,
1120                 .of_match_table = ads1015_of_match,
1121                 .pm = &ads1015_pm_ops,
1122         },
1123         .probe          = ads1015_probe,
1124         .remove         = ads1015_remove,
1125         .id_table       = ads1015_id,
1126 };
1127
1128 module_i2c_driver(ads1015_driver);
1129
1130 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1131 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1132 MODULE_LICENSE("GPL v2");