1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog devices AD5360, AD5361, AD5362, AD5363, AD5370, AD5371, AD5373
4 * multi-channel Digital to Analog Converters driver
6 * Copyright 2011 Analog Devices Inc.
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spi/spi.h>
14 #include <linux/slab.h>
15 #include <linux/sysfs.h>
16 #include <linux/regulator/consumer.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
21 #define AD5360_CMD(x) ((x) << 22)
22 #define AD5360_ADDR(x) ((x) << 16)
24 #define AD5360_READBACK_TYPE(x) ((x) << 13)
25 #define AD5360_READBACK_ADDR(x) ((x) << 7)
27 #define AD5360_CHAN_ADDR(chan) ((chan) + 0x8)
29 #define AD5360_CMD_WRITE_DATA 0x3
30 #define AD5360_CMD_WRITE_OFFSET 0x2
31 #define AD5360_CMD_WRITE_GAIN 0x1
32 #define AD5360_CMD_SPECIAL_FUNCTION 0x0
34 /* Special function register addresses */
35 #define AD5360_REG_SF_NOP 0x0
36 #define AD5360_REG_SF_CTRL 0x1
37 #define AD5360_REG_SF_OFS(x) (0x2 + (x))
38 #define AD5360_REG_SF_READBACK 0x5
40 #define AD5360_SF_CTRL_PWR_DOWN BIT(0)
42 #define AD5360_READBACK_X1A 0x0
43 #define AD5360_READBACK_X1B 0x1
44 #define AD5360_READBACK_OFFSET 0x2
45 #define AD5360_READBACK_GAIN 0x3
46 #define AD5360_READBACK_SF 0x4
50 * struct ad5360_chip_info - chip specific information
51 * @channel_template: channel specification template
52 * @num_channels: number of channels
53 * @channels_per_group: number of channels per group
54 * @num_vrefs: number of vref supplies for the chip
57 struct ad5360_chip_info {
58 struct iio_chan_spec channel_template;
59 unsigned int num_channels;
60 unsigned int channels_per_group;
61 unsigned int num_vrefs;
65 * struct ad5360_state - driver instance specific data
67 * @chip_info: chip model specific constants, available modes etc
68 * @vref_reg: vref supply regulators
69 * @ctrl: control register cache
70 * @data: spi transfer buffers
74 struct spi_device *spi;
75 const struct ad5360_chip_info *chip_info;
76 struct regulator_bulk_data vref_reg[3];
80 * DMA (thus cache coherency maintenance) requires the
81 * transfer buffers to live in their own cache lines.
86 } data[2] ____cacheline_aligned;
100 #define AD5360_CHANNEL(bits) { \
101 .type = IIO_VOLTAGE, \
104 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
105 BIT(IIO_CHAN_INFO_SCALE) | \
106 BIT(IIO_CHAN_INFO_OFFSET) | \
107 BIT(IIO_CHAN_INFO_CALIBSCALE) | \
108 BIT(IIO_CHAN_INFO_CALIBBIAS), \
111 .realbits = (bits), \
113 .shift = 16 - (bits), \
117 static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
119 .channel_template = AD5360_CHANNEL(16),
121 .channels_per_group = 8,
125 .channel_template = AD5360_CHANNEL(14),
127 .channels_per_group = 8,
131 .channel_template = AD5360_CHANNEL(16),
133 .channels_per_group = 4,
137 .channel_template = AD5360_CHANNEL(14),
139 .channels_per_group = 4,
143 .channel_template = AD5360_CHANNEL(16),
145 .channels_per_group = 8,
149 .channel_template = AD5360_CHANNEL(14),
151 .channels_per_group = 8,
155 .channel_template = AD5360_CHANNEL(16),
157 .channels_per_group = 8,
161 .channel_template = AD5360_CHANNEL(14),
163 .channels_per_group = 8,
168 static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
169 unsigned int channel)
173 /* The first groups have their own vref, while the remaining groups
174 * share the last vref */
175 i = channel / st->chip_info->channels_per_group;
176 if (i >= st->chip_info->num_vrefs)
177 i = st->chip_info->num_vrefs - 1;
182 static int ad5360_get_channel_vref(struct ad5360_state *st,
183 unsigned int channel)
185 unsigned int i = ad5360_get_channel_vref_index(st, channel);
187 return regulator_get_voltage(st->vref_reg[i].consumer);
191 static int ad5360_write_unlocked(struct iio_dev *indio_dev,
192 unsigned int cmd, unsigned int addr, unsigned int val,
195 struct ad5360_state *st = iio_priv(indio_dev);
198 val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
199 st->data[0].d32 = cpu_to_be32(val);
201 return spi_write(st->spi, &st->data[0].d8[1], 3);
204 static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
205 unsigned int addr, unsigned int val, unsigned int shift)
209 mutex_lock(&indio_dev->mlock);
210 ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
211 mutex_unlock(&indio_dev->mlock);
216 static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
219 struct ad5360_state *st = iio_priv(indio_dev);
221 struct spi_transfer t[] = {
223 .tx_buf = &st->data[0].d8[1],
227 .rx_buf = &st->data[1].d8[1],
232 mutex_lock(&indio_dev->mlock);
234 st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
235 AD5360_ADDR(AD5360_REG_SF_READBACK) |
236 AD5360_READBACK_TYPE(type) |
237 AD5360_READBACK_ADDR(addr));
239 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
241 ret = be32_to_cpu(st->data[1].d32) & 0xffff;
243 mutex_unlock(&indio_dev->mlock);
248 static ssize_t ad5360_read_dac_powerdown(struct device *dev,
249 struct device_attribute *attr,
252 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
253 struct ad5360_state *st = iio_priv(indio_dev);
255 return sprintf(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
258 static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
261 struct ad5360_state *st = iio_priv(indio_dev);
264 mutex_lock(&indio_dev->mlock);
269 ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
270 AD5360_REG_SF_CTRL, st->ctrl, 0);
272 mutex_unlock(&indio_dev->mlock);
277 static ssize_t ad5360_write_dac_powerdown(struct device *dev,
278 struct device_attribute *attr, const char *buf, size_t len)
280 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
284 ret = strtobool(buf, &pwr_down);
289 ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
291 ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
293 return ret ? ret : len;
296 static IIO_DEVICE_ATTR(out_voltage_powerdown,
298 ad5360_read_dac_powerdown,
299 ad5360_write_dac_powerdown, 0);
301 static struct attribute *ad5360_attributes[] = {
302 &iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
306 static const struct attribute_group ad5360_attribute_group = {
307 .attrs = ad5360_attributes,
310 static int ad5360_write_raw(struct iio_dev *indio_dev,
311 struct iio_chan_spec const *chan,
316 struct ad5360_state *st = iio_priv(indio_dev);
317 int max_val = (1 << chan->scan_type.realbits);
318 unsigned int ofs_index;
321 case IIO_CHAN_INFO_RAW:
322 if (val >= max_val || val < 0)
325 return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
326 chan->address, val, chan->scan_type.shift);
328 case IIO_CHAN_INFO_CALIBBIAS:
329 if (val >= max_val || val < 0)
332 return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
333 chan->address, val, chan->scan_type.shift);
335 case IIO_CHAN_INFO_CALIBSCALE:
336 if (val >= max_val || val < 0)
339 return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
340 chan->address, val, chan->scan_type.shift);
342 case IIO_CHAN_INFO_OFFSET:
343 if (val <= -max_val || val > 0)
348 /* offset is supposed to have the same scale as raw, but it
349 * is always 14bits wide, so on a chip where the raw value has
350 * more bits, we need to shift offset. */
351 val >>= (chan->scan_type.realbits - 14);
353 /* There is one DAC offset register per vref. Changing one
354 * channels offset will also change the offset for all other
355 * channels which share the same vref supply. */
356 ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
357 return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
358 AD5360_REG_SF_OFS(ofs_index), val, 0);
366 static int ad5360_read_raw(struct iio_dev *indio_dev,
367 struct iio_chan_spec const *chan,
372 struct ad5360_state *st = iio_priv(indio_dev);
373 unsigned int ofs_index;
378 case IIO_CHAN_INFO_RAW:
379 ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
383 *val = ret >> chan->scan_type.shift;
385 case IIO_CHAN_INFO_SCALE:
386 scale_uv = ad5360_get_channel_vref(st, chan->channel);
390 /* vout = 4 * vref * dac_code */
391 *val = scale_uv * 4 / 1000;
392 *val2 = chan->scan_type.realbits;
393 return IIO_VAL_FRACTIONAL_LOG2;
394 case IIO_CHAN_INFO_CALIBBIAS:
395 ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
401 case IIO_CHAN_INFO_CALIBSCALE:
402 ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
408 case IIO_CHAN_INFO_OFFSET:
409 ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
410 ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
411 AD5360_REG_SF_OFS(ofs_index));
415 ret <<= (chan->scan_type.realbits - 14);
423 static const struct iio_info ad5360_info = {
424 .read_raw = ad5360_read_raw,
425 .write_raw = ad5360_write_raw,
426 .attrs = &ad5360_attribute_group,
429 static const char * const ad5360_vref_name[] = {
430 "vref0", "vref1", "vref2"
433 static int ad5360_alloc_channels(struct iio_dev *indio_dev)
435 struct ad5360_state *st = iio_priv(indio_dev);
436 struct iio_chan_spec *channels;
439 channels = kcalloc(st->chip_info->num_channels,
440 sizeof(struct iio_chan_spec), GFP_KERNEL);
445 for (i = 0; i < st->chip_info->num_channels; ++i) {
446 channels[i] = st->chip_info->channel_template;
447 channels[i].channel = i;
448 channels[i].address = AD5360_CHAN_ADDR(i);
451 indio_dev->channels = channels;
456 static int ad5360_probe(struct spi_device *spi)
458 enum ad5360_type type = spi_get_device_id(spi)->driver_data;
459 struct iio_dev *indio_dev;
460 struct ad5360_state *st;
464 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
465 if (indio_dev == NULL) {
466 dev_err(&spi->dev, "Failed to allocate iio device\n");
470 st = iio_priv(indio_dev);
471 spi_set_drvdata(spi, indio_dev);
473 st->chip_info = &ad5360_chip_info_tbl[type];
476 indio_dev->dev.parent = &spi->dev;
477 indio_dev->name = spi_get_device_id(spi)->name;
478 indio_dev->info = &ad5360_info;
479 indio_dev->modes = INDIO_DIRECT_MODE;
480 indio_dev->num_channels = st->chip_info->num_channels;
482 ret = ad5360_alloc_channels(indio_dev);
484 dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
488 for (i = 0; i < st->chip_info->num_vrefs; ++i)
489 st->vref_reg[i].supply = ad5360_vref_name[i];
491 ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
494 dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
495 goto error_free_channels;
498 ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
500 dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
501 goto error_free_channels;
504 ret = iio_device_register(indio_dev);
506 dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
507 goto error_disable_reg;
513 regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
515 kfree(indio_dev->channels);
520 static int ad5360_remove(struct spi_device *spi)
522 struct iio_dev *indio_dev = spi_get_drvdata(spi);
523 struct ad5360_state *st = iio_priv(indio_dev);
525 iio_device_unregister(indio_dev);
527 kfree(indio_dev->channels);
529 regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
534 static const struct spi_device_id ad5360_ids[] = {
535 { "ad5360", ID_AD5360 },
536 { "ad5361", ID_AD5361 },
537 { "ad5362", ID_AD5362 },
538 { "ad5363", ID_AD5363 },
539 { "ad5370", ID_AD5370 },
540 { "ad5371", ID_AD5371 },
541 { "ad5372", ID_AD5372 },
542 { "ad5373", ID_AD5373 },
545 MODULE_DEVICE_TABLE(spi, ad5360_ids);
547 static struct spi_driver ad5360_driver = {
551 .probe = ad5360_probe,
552 .remove = ad5360_remove,
553 .id_table = ad5360_ids,
555 module_spi_driver(ad5360_driver);
557 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
558 MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
559 MODULE_LICENSE("GPL v2");