1 // SPDX-License-Identifier: GPL-2.0-only
3 * BMG160 Gyro Sensor driver
4 * Copyright (c) 2014, Intel Corporation.
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/acpi.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/iio/buffer.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/events.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/regmap.h>
24 #define BMG160_IRQ_NAME "bmg160_event"
26 #define BMG160_REG_CHIP_ID 0x00
27 #define BMG160_CHIP_ID_VAL 0x0F
29 #define BMG160_REG_PMU_LPW 0x11
30 #define BMG160_MODE_NORMAL 0x00
31 #define BMG160_MODE_DEEP_SUSPEND 0x20
32 #define BMG160_MODE_SUSPEND 0x80
34 #define BMG160_REG_RANGE 0x0F
36 #define BMG160_RANGE_2000DPS 0
37 #define BMG160_RANGE_1000DPS 1
38 #define BMG160_RANGE_500DPS 2
39 #define BMG160_RANGE_250DPS 3
40 #define BMG160_RANGE_125DPS 4
42 #define BMG160_REG_PMU_BW 0x10
43 #define BMG160_NO_FILTER 0
44 #define BMG160_DEF_BW 100
45 #define BMG160_REG_PMU_BW_RES BIT(7)
47 #define BMG160_GYRO_REG_RESET 0x14
48 #define BMG160_GYRO_RESET_VAL 0xb6
50 #define BMG160_REG_INT_MAP_0 0x17
51 #define BMG160_INT_MAP_0_BIT_ANY BIT(1)
53 #define BMG160_REG_INT_MAP_1 0x18
54 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
56 #define BMG160_REG_INT_RST_LATCH 0x21
57 #define BMG160_INT_MODE_LATCH_RESET 0x80
58 #define BMG160_INT_MODE_LATCH_INT 0x0F
59 #define BMG160_INT_MODE_NON_LATCH_INT 0x00
61 #define BMG160_REG_INT_EN_0 0x15
62 #define BMG160_DATA_ENABLE_INT BIT(7)
64 #define BMG160_REG_INT_EN_1 0x16
65 #define BMG160_INT1_BIT_OD BIT(1)
67 #define BMG160_REG_XOUT_L 0x02
68 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
70 #define BMG160_REG_SLOPE_THRES 0x1B
71 #define BMG160_SLOPE_THRES_MASK 0x0F
73 #define BMG160_REG_MOTION_INTR 0x1C
74 #define BMG160_INT_MOTION_X BIT(0)
75 #define BMG160_INT_MOTION_Y BIT(1)
76 #define BMG160_INT_MOTION_Z BIT(2)
77 #define BMG160_ANY_DUR_MASK 0x30
78 #define BMG160_ANY_DUR_SHIFT 4
80 #define BMG160_REG_INT_STATUS_2 0x0B
81 #define BMG160_ANY_MOTION_MASK 0x07
82 #define BMG160_ANY_MOTION_BIT_X BIT(0)
83 #define BMG160_ANY_MOTION_BIT_Y BIT(1)
84 #define BMG160_ANY_MOTION_BIT_Z BIT(2)
86 #define BMG160_REG_TEMP 0x08
87 #define BMG160_TEMP_CENTER_VAL 23
89 #define BMG160_MAX_STARTUP_TIME_MS 80
91 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000
94 struct regmap *regmap;
95 struct iio_trigger *dready_trig;
96 struct iio_trigger *motion_trig;
97 struct iio_mount_matrix orientation;
103 bool dready_trigger_on;
104 bool motion_trigger_on;
115 static const struct {
119 } bmg160_samp_freq_table[] = { {100, 32, 0x07},
127 static const struct {
130 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
131 { 532, BMG160_RANGE_1000DPS},
132 { 266, BMG160_RANGE_500DPS},
133 { 133, BMG160_RANGE_250DPS},
134 { 66, BMG160_RANGE_125DPS} };
136 static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
138 struct device *dev = regmap_get_device(data->regmap);
141 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
143 dev_err(dev, "Error writing reg_pmu_lpw\n");
150 static int bmg160_convert_freq_to_bit(int val)
154 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
155 if (bmg160_samp_freq_table[i].odr == val)
156 return bmg160_samp_freq_table[i].bw_bits;
162 static int bmg160_set_bw(struct bmg160_data *data, int val)
164 struct device *dev = regmap_get_device(data->regmap);
168 bw_bits = bmg160_convert_freq_to_bit(val);
172 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
174 dev_err(dev, "Error writing reg_pmu_bw\n");
181 static int bmg160_get_filter(struct bmg160_data *data, int *val)
183 struct device *dev = regmap_get_device(data->regmap);
186 unsigned int bw_bits;
188 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
190 dev_err(dev, "Error reading reg_pmu_bw\n");
194 /* Ignore the readonly reserved bit. */
195 bw_bits &= ~BMG160_REG_PMU_BW_RES;
197 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
198 if (bmg160_samp_freq_table[i].bw_bits == bw_bits)
202 *val = bmg160_samp_freq_table[i].filter;
204 return ret ? ret : IIO_VAL_INT;
208 static int bmg160_set_filter(struct bmg160_data *data, int val)
210 struct device *dev = regmap_get_device(data->regmap);
214 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
215 if (bmg160_samp_freq_table[i].filter == val)
219 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW,
220 bmg160_samp_freq_table[i].bw_bits);
222 dev_err(dev, "Error writing reg_pmu_bw\n");
229 static int bmg160_chip_init(struct bmg160_data *data)
231 struct device *dev = regmap_get_device(data->regmap);
236 * Reset chip to get it in a known good state. A delay of 30ms after
237 * reset is required according to the datasheet.
239 regmap_write(data->regmap, BMG160_GYRO_REG_RESET,
240 BMG160_GYRO_RESET_VAL);
241 usleep_range(30000, 30700);
243 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
245 dev_err(dev, "Error reading reg_chip_id\n");
249 dev_dbg(dev, "Chip Id %x\n", val);
250 if (val != BMG160_CHIP_ID_VAL) {
251 dev_err(dev, "invalid chip %x\n", val);
255 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
259 /* Wait upto 500 ms to be ready after changing mode */
260 usleep_range(500, 1000);
263 ret = bmg160_set_bw(data, BMG160_DEF_BW);
267 /* Set Default Range */
268 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
270 dev_err(dev, "Error writing reg_range\n");
273 data->dps_range = BMG160_RANGE_500DPS;
275 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
277 dev_err(dev, "Error reading reg_slope_thres\n");
280 data->slope_thres = val;
282 /* Set default interrupt mode */
283 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
284 BMG160_INT1_BIT_OD, 0);
286 dev_err(dev, "Error updating bits in reg_int_en_1\n");
290 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
291 BMG160_INT_MODE_LATCH_INT |
292 BMG160_INT_MODE_LATCH_RESET);
295 "Error writing reg_motion_intr\n");
302 static int bmg160_set_power_state(struct bmg160_data *data, bool on)
305 struct device *dev = regmap_get_device(data->regmap);
309 ret = pm_runtime_get_sync(dev);
311 pm_runtime_mark_last_busy(dev);
312 ret = pm_runtime_put_autosuspend(dev);
316 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on);
319 pm_runtime_put_noidle(dev);
328 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
331 struct device *dev = regmap_get_device(data->regmap);
334 /* Enable/Disable INT_MAP0 mapping */
335 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
336 BMG160_INT_MAP_0_BIT_ANY,
337 (status ? BMG160_INT_MAP_0_BIT_ANY : 0));
339 dev_err(dev, "Error updating bits reg_int_map0\n");
343 /* Enable/Disable slope interrupts */
345 /* Update slope thres */
346 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
349 dev_err(dev, "Error writing reg_slope_thres\n");
353 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
354 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
355 BMG160_INT_MOTION_Z);
357 dev_err(dev, "Error writing reg_motion_intr\n");
362 * New data interrupt is always non-latched,
363 * which will have higher priority, so no need
364 * to set latched mode, we will be flooded anyway with INTR
366 if (!data->dready_trigger_on) {
367 ret = regmap_write(data->regmap,
368 BMG160_REG_INT_RST_LATCH,
369 BMG160_INT_MODE_LATCH_INT |
370 BMG160_INT_MODE_LATCH_RESET);
372 dev_err(dev, "Error writing reg_rst_latch\n");
377 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
378 BMG160_DATA_ENABLE_INT);
381 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
385 dev_err(dev, "Error writing reg_int_en0\n");
392 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
395 struct device *dev = regmap_get_device(data->regmap);
398 /* Enable/Disable INT_MAP1 mapping */
399 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
400 BMG160_INT_MAP_1_BIT_NEW_DATA,
401 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
403 dev_err(dev, "Error updating bits in reg_int_map1\n");
408 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
409 BMG160_INT_MODE_NON_LATCH_INT |
410 BMG160_INT_MODE_LATCH_RESET);
412 dev_err(dev, "Error writing reg_rst_latch\n");
416 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
417 BMG160_DATA_ENABLE_INT);
420 /* Restore interrupt mode */
421 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
422 BMG160_INT_MODE_LATCH_INT |
423 BMG160_INT_MODE_LATCH_RESET);
425 dev_err(dev, "Error writing reg_rst_latch\n");
429 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
433 dev_err(dev, "Error writing reg_int_en0\n");
440 static int bmg160_get_bw(struct bmg160_data *data, int *val)
442 struct device *dev = regmap_get_device(data->regmap);
444 unsigned int bw_bits;
447 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
449 dev_err(dev, "Error reading reg_pmu_bw\n");
453 /* Ignore the readonly reserved bit. */
454 bw_bits &= ~BMG160_REG_PMU_BW_RES;
456 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
457 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) {
458 *val = bmg160_samp_freq_table[i].odr;
466 static int bmg160_set_scale(struct bmg160_data *data, int val)
468 struct device *dev = regmap_get_device(data->regmap);
471 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
472 if (bmg160_scale_table[i].scale == val) {
473 ret = regmap_write(data->regmap, BMG160_REG_RANGE,
474 bmg160_scale_table[i].dps_range);
476 dev_err(dev, "Error writing reg_range\n");
479 data->dps_range = bmg160_scale_table[i].dps_range;
487 static int bmg160_get_temp(struct bmg160_data *data, int *val)
489 struct device *dev = regmap_get_device(data->regmap);
491 unsigned int raw_val;
493 mutex_lock(&data->mutex);
494 ret = bmg160_set_power_state(data, true);
496 mutex_unlock(&data->mutex);
500 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
502 dev_err(dev, "Error reading reg_temp\n");
503 bmg160_set_power_state(data, false);
504 mutex_unlock(&data->mutex);
508 *val = sign_extend32(raw_val, 7);
509 ret = bmg160_set_power_state(data, false);
510 mutex_unlock(&data->mutex);
517 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
519 struct device *dev = regmap_get_device(data->regmap);
523 mutex_lock(&data->mutex);
524 ret = bmg160_set_power_state(data, true);
526 mutex_unlock(&data->mutex);
530 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
533 dev_err(dev, "Error reading axis %d\n", axis);
534 bmg160_set_power_state(data, false);
535 mutex_unlock(&data->mutex);
539 *val = sign_extend32(le16_to_cpu(raw_val), 15);
540 ret = bmg160_set_power_state(data, false);
541 mutex_unlock(&data->mutex);
548 static int bmg160_read_raw(struct iio_dev *indio_dev,
549 struct iio_chan_spec const *chan,
550 int *val, int *val2, long mask)
552 struct bmg160_data *data = iio_priv(indio_dev);
556 case IIO_CHAN_INFO_RAW:
557 switch (chan->type) {
559 return bmg160_get_temp(data, val);
561 if (iio_buffer_enabled(indio_dev))
564 return bmg160_get_axis(data, chan->scan_index,
569 case IIO_CHAN_INFO_OFFSET:
570 if (chan->type == IIO_TEMP) {
571 *val = BMG160_TEMP_CENTER_VAL;
575 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
576 return bmg160_get_filter(data, val);
577 case IIO_CHAN_INFO_SCALE:
578 switch (chan->type) {
586 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
587 if (bmg160_scale_table[i].dps_range ==
590 *val2 = bmg160_scale_table[i].scale;
591 return IIO_VAL_INT_PLUS_MICRO;
599 case IIO_CHAN_INFO_SAMP_FREQ:
601 mutex_lock(&data->mutex);
602 ret = bmg160_get_bw(data, val);
603 mutex_unlock(&data->mutex);
610 static int bmg160_write_raw(struct iio_dev *indio_dev,
611 struct iio_chan_spec const *chan,
612 int val, int val2, long mask)
614 struct bmg160_data *data = iio_priv(indio_dev);
618 case IIO_CHAN_INFO_SAMP_FREQ:
619 mutex_lock(&data->mutex);
621 * Section 4.2 of spec
622 * In suspend mode, the only supported operations are reading
623 * registers as well as writing to the (0x14) softreset
624 * register. Since we will be in suspend mode by default, change
625 * mode to power on for other writes.
627 ret = bmg160_set_power_state(data, true);
629 mutex_unlock(&data->mutex);
632 ret = bmg160_set_bw(data, val);
634 bmg160_set_power_state(data, false);
635 mutex_unlock(&data->mutex);
638 ret = bmg160_set_power_state(data, false);
639 mutex_unlock(&data->mutex);
641 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
645 mutex_lock(&data->mutex);
646 ret = bmg160_set_power_state(data, true);
648 bmg160_set_power_state(data, false);
649 mutex_unlock(&data->mutex);
652 ret = bmg160_set_filter(data, val);
654 bmg160_set_power_state(data, false);
655 mutex_unlock(&data->mutex);
658 ret = bmg160_set_power_state(data, false);
659 mutex_unlock(&data->mutex);
661 case IIO_CHAN_INFO_SCALE:
665 mutex_lock(&data->mutex);
666 /* Refer to comments above for the suspend mode ops */
667 ret = bmg160_set_power_state(data, true);
669 mutex_unlock(&data->mutex);
672 ret = bmg160_set_scale(data, val2);
674 bmg160_set_power_state(data, false);
675 mutex_unlock(&data->mutex);
678 ret = bmg160_set_power_state(data, false);
679 mutex_unlock(&data->mutex);
688 static int bmg160_read_event(struct iio_dev *indio_dev,
689 const struct iio_chan_spec *chan,
690 enum iio_event_type type,
691 enum iio_event_direction dir,
692 enum iio_event_info info,
695 struct bmg160_data *data = iio_priv(indio_dev);
699 case IIO_EV_INFO_VALUE:
700 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
709 static int bmg160_write_event(struct iio_dev *indio_dev,
710 const struct iio_chan_spec *chan,
711 enum iio_event_type type,
712 enum iio_event_direction dir,
713 enum iio_event_info info,
716 struct bmg160_data *data = iio_priv(indio_dev);
719 case IIO_EV_INFO_VALUE:
720 if (data->ev_enable_state)
722 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
723 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
732 static int bmg160_read_event_config(struct iio_dev *indio_dev,
733 const struct iio_chan_spec *chan,
734 enum iio_event_type type,
735 enum iio_event_direction dir)
738 struct bmg160_data *data = iio_priv(indio_dev);
740 return data->ev_enable_state;
743 static int bmg160_write_event_config(struct iio_dev *indio_dev,
744 const struct iio_chan_spec *chan,
745 enum iio_event_type type,
746 enum iio_event_direction dir,
749 struct bmg160_data *data = iio_priv(indio_dev);
752 if (state && data->ev_enable_state)
755 mutex_lock(&data->mutex);
757 if (!state && data->motion_trigger_on) {
758 data->ev_enable_state = 0;
759 mutex_unlock(&data->mutex);
763 * We will expect the enable and disable to do operation in
764 * in reverse order. This will happen here anyway as our
765 * resume operation uses sync mode runtime pm calls, the
766 * suspend operation will be delayed by autosuspend delay
767 * So the disable operation will still happen in reverse of
768 * enable operation. When runtime pm is disabled the mode
769 * is always on so sequence doesn't matter
771 ret = bmg160_set_power_state(data, state);
773 mutex_unlock(&data->mutex);
777 ret = bmg160_setup_any_motion_interrupt(data, state);
779 bmg160_set_power_state(data, false);
780 mutex_unlock(&data->mutex);
784 data->ev_enable_state = state;
785 mutex_unlock(&data->mutex);
790 static const struct iio_mount_matrix *
791 bmg160_get_mount_matrix(const struct iio_dev *indio_dev,
792 const struct iio_chan_spec *chan)
794 struct bmg160_data *data = iio_priv(indio_dev);
796 return &data->orientation;
799 static const struct iio_chan_spec_ext_info bmg160_ext_info[] = {
800 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix),
804 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
806 static IIO_CONST_ATTR(in_anglvel_scale_available,
807 "0.001065 0.000532 0.000266 0.000133 0.000066");
809 static struct attribute *bmg160_attributes[] = {
810 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
811 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
815 static const struct attribute_group bmg160_attrs_group = {
816 .attrs = bmg160_attributes,
819 static const struct iio_event_spec bmg160_event = {
820 .type = IIO_EV_TYPE_ROC,
821 .dir = IIO_EV_DIR_EITHER,
822 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
823 BIT(IIO_EV_INFO_ENABLE)
826 #define BMG160_CHANNEL(_axis) { \
827 .type = IIO_ANGL_VEL, \
829 .channel2 = IIO_MOD_##_axis, \
830 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
831 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
832 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
833 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
834 .scan_index = AXIS_##_axis, \
839 .endianness = IIO_LE, \
841 .ext_info = bmg160_ext_info, \
842 .event_spec = &bmg160_event, \
843 .num_event_specs = 1 \
846 static const struct iio_chan_spec bmg160_channels[] = {
849 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
850 BIT(IIO_CHAN_INFO_SCALE) |
851 BIT(IIO_CHAN_INFO_OFFSET),
857 IIO_CHAN_SOFT_TIMESTAMP(3),
860 static const struct iio_info bmg160_info = {
861 .attrs = &bmg160_attrs_group,
862 .read_raw = bmg160_read_raw,
863 .write_raw = bmg160_write_raw,
864 .read_event_value = bmg160_read_event,
865 .write_event_value = bmg160_write_event,
866 .write_event_config = bmg160_write_event_config,
867 .read_event_config = bmg160_read_event_config,
870 static const unsigned long bmg160_accel_scan_masks[] = {
871 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
874 static irqreturn_t bmg160_trigger_handler(int irq, void *p)
876 struct iio_poll_func *pf = p;
877 struct iio_dev *indio_dev = pf->indio_dev;
878 struct bmg160_data *data = iio_priv(indio_dev);
881 mutex_lock(&data->mutex);
882 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L,
883 data->buffer, AXIS_MAX * 2);
884 mutex_unlock(&data->mutex);
888 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
891 iio_trigger_notify_done(indio_dev->trig);
896 static int bmg160_trig_try_reen(struct iio_trigger *trig)
898 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
899 struct bmg160_data *data = iio_priv(indio_dev);
900 struct device *dev = regmap_get_device(data->regmap);
903 /* new data interrupts don't need ack */
904 if (data->dready_trigger_on)
907 /* Set latched mode interrupt and clear any latched interrupt */
908 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
909 BMG160_INT_MODE_LATCH_INT |
910 BMG160_INT_MODE_LATCH_RESET);
912 dev_err(dev, "Error writing reg_rst_latch\n");
919 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
922 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
923 struct bmg160_data *data = iio_priv(indio_dev);
926 mutex_lock(&data->mutex);
928 if (!state && data->ev_enable_state && data->motion_trigger_on) {
929 data->motion_trigger_on = false;
930 mutex_unlock(&data->mutex);
935 * Refer to comment in bmg160_write_event_config for
936 * enable/disable operation order
938 ret = bmg160_set_power_state(data, state);
940 mutex_unlock(&data->mutex);
943 if (data->motion_trig == trig)
944 ret = bmg160_setup_any_motion_interrupt(data, state);
946 ret = bmg160_setup_new_data_interrupt(data, state);
948 bmg160_set_power_state(data, false);
949 mutex_unlock(&data->mutex);
952 if (data->motion_trig == trig)
953 data->motion_trigger_on = state;
955 data->dready_trigger_on = state;
957 mutex_unlock(&data->mutex);
962 static const struct iio_trigger_ops bmg160_trigger_ops = {
963 .set_trigger_state = bmg160_data_rdy_trigger_set_state,
964 .try_reenable = bmg160_trig_try_reen,
967 static irqreturn_t bmg160_event_handler(int irq, void *private)
969 struct iio_dev *indio_dev = private;
970 struct bmg160_data *data = iio_priv(indio_dev);
971 struct device *dev = regmap_get_device(data->regmap);
976 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
978 dev_err(dev, "Error reading reg_int_status2\n");
979 goto ack_intr_status;
983 dir = IIO_EV_DIR_RISING;
985 dir = IIO_EV_DIR_FALLING;
987 if (val & BMG160_ANY_MOTION_BIT_X)
988 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
993 iio_get_time_ns(indio_dev));
994 if (val & BMG160_ANY_MOTION_BIT_Y)
995 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
1000 iio_get_time_ns(indio_dev));
1001 if (val & BMG160_ANY_MOTION_BIT_Z)
1002 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
1007 iio_get_time_ns(indio_dev));
1010 if (!data->dready_trigger_on) {
1011 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
1012 BMG160_INT_MODE_LATCH_INT |
1013 BMG160_INT_MODE_LATCH_RESET);
1015 dev_err(dev, "Error writing reg_rst_latch\n");
1021 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
1023 struct iio_dev *indio_dev = private;
1024 struct bmg160_data *data = iio_priv(indio_dev);
1026 if (data->dready_trigger_on)
1027 iio_trigger_poll(data->dready_trig);
1028 else if (data->motion_trigger_on)
1029 iio_trigger_poll(data->motion_trig);
1031 if (data->ev_enable_state)
1032 return IRQ_WAKE_THREAD;
1038 static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
1040 struct bmg160_data *data = iio_priv(indio_dev);
1042 return bmg160_set_power_state(data, true);
1045 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
1047 struct bmg160_data *data = iio_priv(indio_dev);
1049 return bmg160_set_power_state(data, false);
1052 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
1053 .preenable = bmg160_buffer_preenable,
1054 .postenable = iio_triggered_buffer_postenable,
1055 .predisable = iio_triggered_buffer_predisable,
1056 .postdisable = bmg160_buffer_postdisable,
1059 static const char *bmg160_match_acpi_device(struct device *dev)
1061 const struct acpi_device_id *id;
1063 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1067 return dev_name(dev);
1070 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
1073 struct bmg160_data *data;
1074 struct iio_dev *indio_dev;
1077 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1081 data = iio_priv(indio_dev);
1082 dev_set_drvdata(dev, indio_dev);
1084 data->regmap = regmap;
1086 ret = iio_read_mount_matrix(dev, "mount-matrix",
1087 &data->orientation);
1091 ret = bmg160_chip_init(data);
1095 mutex_init(&data->mutex);
1097 if (ACPI_HANDLE(dev))
1098 name = bmg160_match_acpi_device(dev);
1100 indio_dev->dev.parent = dev;
1101 indio_dev->channels = bmg160_channels;
1102 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
1103 indio_dev->name = name;
1104 indio_dev->available_scan_masks = bmg160_accel_scan_masks;
1105 indio_dev->modes = INDIO_DIRECT_MODE;
1106 indio_dev->info = &bmg160_info;
1108 if (data->irq > 0) {
1109 ret = devm_request_threaded_irq(dev,
1111 bmg160_data_rdy_trig_poll,
1112 bmg160_event_handler,
1113 IRQF_TRIGGER_RISING,
1119 data->dready_trig = devm_iio_trigger_alloc(dev,
1123 if (!data->dready_trig)
1126 data->motion_trig = devm_iio_trigger_alloc(dev,
1127 "%s-any-motion-dev%d",
1130 if (!data->motion_trig)
1133 data->dready_trig->dev.parent = dev;
1134 data->dready_trig->ops = &bmg160_trigger_ops;
1135 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1136 ret = iio_trigger_register(data->dready_trig);
1140 data->motion_trig->dev.parent = dev;
1141 data->motion_trig->ops = &bmg160_trigger_ops;
1142 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1143 ret = iio_trigger_register(data->motion_trig);
1145 data->motion_trig = NULL;
1146 goto err_trigger_unregister;
1150 ret = iio_triggered_buffer_setup(indio_dev,
1151 iio_pollfunc_store_time,
1152 bmg160_trigger_handler,
1153 &bmg160_buffer_setup_ops);
1156 "iio triggered buffer setup failed\n");
1157 goto err_trigger_unregister;
1160 ret = pm_runtime_set_active(dev);
1162 goto err_buffer_cleanup;
1164 pm_runtime_enable(dev);
1165 pm_runtime_set_autosuspend_delay(dev,
1166 BMG160_AUTO_SUSPEND_DELAY_MS);
1167 pm_runtime_use_autosuspend(dev);
1169 ret = iio_device_register(indio_dev);
1171 dev_err(dev, "unable to register iio device\n");
1172 goto err_buffer_cleanup;
1178 iio_triggered_buffer_cleanup(indio_dev);
1179 err_trigger_unregister:
1180 if (data->dready_trig)
1181 iio_trigger_unregister(data->dready_trig);
1182 if (data->motion_trig)
1183 iio_trigger_unregister(data->motion_trig);
1187 EXPORT_SYMBOL_GPL(bmg160_core_probe);
1189 void bmg160_core_remove(struct device *dev)
1191 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1192 struct bmg160_data *data = iio_priv(indio_dev);
1194 iio_device_unregister(indio_dev);
1196 pm_runtime_disable(dev);
1197 pm_runtime_set_suspended(dev);
1198 pm_runtime_put_noidle(dev);
1200 iio_triggered_buffer_cleanup(indio_dev);
1202 if (data->dready_trig) {
1203 iio_trigger_unregister(data->dready_trig);
1204 iio_trigger_unregister(data->motion_trig);
1207 mutex_lock(&data->mutex);
1208 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
1209 mutex_unlock(&data->mutex);
1211 EXPORT_SYMBOL_GPL(bmg160_core_remove);
1213 #ifdef CONFIG_PM_SLEEP
1214 static int bmg160_suspend(struct device *dev)
1216 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1217 struct bmg160_data *data = iio_priv(indio_dev);
1219 mutex_lock(&data->mutex);
1220 bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1221 mutex_unlock(&data->mutex);
1226 static int bmg160_resume(struct device *dev)
1228 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1229 struct bmg160_data *data = iio_priv(indio_dev);
1231 mutex_lock(&data->mutex);
1232 if (data->dready_trigger_on || data->motion_trigger_on ||
1233 data->ev_enable_state)
1234 bmg160_set_mode(data, BMG160_MODE_NORMAL);
1235 mutex_unlock(&data->mutex);
1242 static int bmg160_runtime_suspend(struct device *dev)
1244 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1245 struct bmg160_data *data = iio_priv(indio_dev);
1248 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1250 dev_err(dev, "set mode failed\n");
1257 static int bmg160_runtime_resume(struct device *dev)
1259 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1260 struct bmg160_data *data = iio_priv(indio_dev);
1263 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
1267 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
1273 const struct dev_pm_ops bmg160_pm_ops = {
1274 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
1275 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
1276 bmg160_runtime_resume, NULL)
1278 EXPORT_SYMBOL_GPL(bmg160_pm_ops);
1280 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1281 MODULE_LICENSE("GPL v2");
1282 MODULE_DESCRIPTION("BMG160 Gyro driver");