1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2016
5 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
9 #include <linux/iio/iio.h>
10 #include <linux/iio/sysfs.h>
11 #include <linux/iio/timer/stm32-timer-trigger.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/mfd/stm32-timers.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_device.h>
18 #define MAX_TRIGGERS 7
21 /* List the triggers created by each timer */
22 static const void *triggers_table[][MAX_TRIGGERS] = {
23 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
24 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
25 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
26 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
27 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
30 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
31 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
34 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
42 /* List the triggers accepted by each timer */
43 static const void *valids_table[][MAX_VALIDS] = {
44 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
45 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
46 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
47 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
48 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
51 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
52 { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
55 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
58 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
59 { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
60 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
61 { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
62 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
63 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
66 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
70 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
73 { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
78 struct stm32_timer_trigger {
80 struct regmap *regmap;
88 struct stm32_timer_trigger_cfg {
89 const void *(*valids_table)[MAX_VALIDS];
90 const unsigned int num_valids_table;
93 static bool stm32_timer_is_trgo2_name(const char *name)
95 return !!strstr(name, "trgo2");
98 static bool stm32_timer_is_trgo_name(const char *name)
100 return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
103 static int stm32_timer_start(struct stm32_timer_trigger *priv,
104 struct iio_trigger *trig,
105 unsigned int frequency)
107 unsigned long long prd, div;
111 /* Period and prescaler values depends of clock rate */
112 div = (unsigned long long)clk_get_rate(priv->clk);
114 do_div(div, frequency);
119 * Increase prescaler value until we get a result that fit
120 * with auto reload register maximum value.
122 while (div > priv->max_arr) {
125 do_div(div, (prescaler + 1));
129 if (prescaler > MAX_TIM_PSC) {
130 dev_err(priv->dev, "prescaler exceeds the maximum value\n");
134 /* Check if nobody else use the timer */
135 regmap_read(priv->regmap, TIM_CCER, &ccer);
136 if (ccer & TIM_CCER_CCXE)
139 regmap_read(priv->regmap, TIM_CR1, &cr1);
140 if (!(cr1 & TIM_CR1_CEN))
141 clk_enable(priv->clk);
143 regmap_write(priv->regmap, TIM_PSC, prescaler);
144 regmap_write(priv->regmap, TIM_ARR, prd - 1);
145 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
147 /* Force master mode to update mode */
148 if (stm32_timer_is_trgo2_name(trig->name))
149 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
150 0x2 << TIM_CR2_MMS2_SHIFT);
152 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
153 0x2 << TIM_CR2_MMS_SHIFT);
155 /* Make sure that registers are updated */
156 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
158 /* Enable controller */
159 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
164 static void stm32_timer_stop(struct stm32_timer_trigger *priv,
165 struct iio_trigger *trig)
169 regmap_read(priv->regmap, TIM_CCER, &ccer);
170 if (ccer & TIM_CCER_CCXE)
173 regmap_read(priv->regmap, TIM_CR1, &cr1);
174 if (cr1 & TIM_CR1_CEN)
175 clk_disable(priv->clk);
178 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
179 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
180 regmap_write(priv->regmap, TIM_PSC, 0);
181 regmap_write(priv->regmap, TIM_ARR, 0);
183 /* Force disable master mode */
184 if (stm32_timer_is_trgo2_name(trig->name))
185 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
187 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
189 /* Make sure that registers are updated */
190 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
193 static ssize_t stm32_tt_store_frequency(struct device *dev,
194 struct device_attribute *attr,
195 const char *buf, size_t len)
197 struct iio_trigger *trig = to_iio_trigger(dev);
198 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
202 ret = kstrtouint(buf, 10, &freq);
207 stm32_timer_stop(priv, trig);
209 ret = stm32_timer_start(priv, trig, freq);
217 static ssize_t stm32_tt_read_frequency(struct device *dev,
218 struct device_attribute *attr, char *buf)
220 struct iio_trigger *trig = to_iio_trigger(dev);
221 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
223 unsigned long long freq = 0;
225 regmap_read(priv->regmap, TIM_CR1, &cr1);
226 regmap_read(priv->regmap, TIM_PSC, &psc);
227 regmap_read(priv->regmap, TIM_ARR, &arr);
229 if (cr1 & TIM_CR1_CEN) {
230 freq = (unsigned long long)clk_get_rate(priv->clk);
231 do_div(freq, psc + 1);
232 do_div(freq, arr + 1);
235 return sprintf(buf, "%d\n", (unsigned int)freq);
238 static IIO_DEV_ATTR_SAMP_FREQ(0660,
239 stm32_tt_read_frequency,
240 stm32_tt_store_frequency);
242 #define MASTER_MODE_MAX 7
243 #define MASTER_MODE2_MAX 15
245 static char *master_mode_table[] = {
254 /* Master mode selection 2 only */
257 "compare_pulse_OC4REF",
258 "compare_pulse_OC6REF",
259 "compare_pulse_OC4REF_r_or_OC6REF_r",
260 "compare_pulse_OC4REF_r_or_OC6REF_f",
261 "compare_pulse_OC5REF_r_or_OC6REF_r",
262 "compare_pulse_OC5REF_r_or_OC6REF_f",
265 static ssize_t stm32_tt_show_master_mode(struct device *dev,
266 struct device_attribute *attr,
269 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
270 struct iio_trigger *trig = to_iio_trigger(dev);
273 regmap_read(priv->regmap, TIM_CR2, &cr2);
275 if (stm32_timer_is_trgo2_name(trig->name))
276 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
278 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
280 return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
283 static ssize_t stm32_tt_store_master_mode(struct device *dev,
284 struct device_attribute *attr,
285 const char *buf, size_t len)
287 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
288 struct iio_trigger *trig = to_iio_trigger(dev);
289 u32 mask, shift, master_mode_max;
292 if (stm32_timer_is_trgo2_name(trig->name)) {
294 shift = TIM_CR2_MMS2_SHIFT;
295 master_mode_max = MASTER_MODE2_MAX;
298 shift = TIM_CR2_MMS_SHIFT;
299 master_mode_max = MASTER_MODE_MAX;
302 for (i = 0; i <= master_mode_max; i++) {
303 if (!strncmp(master_mode_table[i], buf,
304 strlen(master_mode_table[i]))) {
305 regmap_update_bits(priv->regmap, TIM_CR2, mask,
314 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
315 struct device_attribute *attr,
318 struct iio_trigger *trig = to_iio_trigger(dev);
319 unsigned int i, master_mode_max;
322 if (stm32_timer_is_trgo2_name(trig->name))
323 master_mode_max = MASTER_MODE2_MAX;
325 master_mode_max = MASTER_MODE_MAX;
327 for (i = 0; i <= master_mode_max; i++)
328 len += scnprintf(buf + len, PAGE_SIZE - len,
329 "%s ", master_mode_table[i]);
331 /* replace trailing space by newline */
337 static IIO_DEVICE_ATTR(master_mode_available, 0444,
338 stm32_tt_show_master_mode_avail, NULL, 0);
340 static IIO_DEVICE_ATTR(master_mode, 0660,
341 stm32_tt_show_master_mode,
342 stm32_tt_store_master_mode,
345 static struct attribute *stm32_trigger_attrs[] = {
346 &iio_dev_attr_sampling_frequency.dev_attr.attr,
347 &iio_dev_attr_master_mode.dev_attr.attr,
348 &iio_dev_attr_master_mode_available.dev_attr.attr,
352 static const struct attribute_group stm32_trigger_attr_group = {
353 .attrs = stm32_trigger_attrs,
356 static const struct attribute_group *stm32_trigger_attr_groups[] = {
357 &stm32_trigger_attr_group,
361 static const struct iio_trigger_ops timer_trigger_ops = {
364 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
367 const char * const *cur = priv->triggers;
369 while (cur && *cur) {
370 struct iio_trigger *trig;
371 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
372 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
374 if (cur_is_trgo2 && !priv->has_trgo2) {
379 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
383 trig->dev.parent = priv->dev->parent;
384 trig->ops = &timer_trigger_ops;
387 * sampling frequency and master mode attributes
388 * should only be available on trgo/trgo2 triggers
390 if (cur_is_trgo || cur_is_trgo2)
391 trig->dev.groups = stm32_trigger_attr_groups;
393 iio_trigger_set_drvdata(trig, priv);
395 ret = devm_iio_trigger_register(priv->dev, trig);
404 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
405 struct iio_chan_spec const *chan,
406 int *val, int *val2, long mask)
408 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
412 case IIO_CHAN_INFO_RAW:
413 regmap_read(priv->regmap, TIM_CNT, &dat);
417 case IIO_CHAN_INFO_ENABLE:
418 regmap_read(priv->regmap, TIM_CR1, &dat);
419 *val = (dat & TIM_CR1_CEN) ? 1 : 0;
422 case IIO_CHAN_INFO_SCALE:
423 regmap_read(priv->regmap, TIM_SMCR, &dat);
429 /* in quadrature case scale = 0.25 */
433 return IIO_VAL_FRACTIONAL_LOG2;
439 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
440 struct iio_chan_spec const *chan,
441 int val, int val2, long mask)
443 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
447 case IIO_CHAN_INFO_RAW:
448 return regmap_write(priv->regmap, TIM_CNT, val);
450 case IIO_CHAN_INFO_SCALE:
454 case IIO_CHAN_INFO_ENABLE:
456 regmap_read(priv->regmap, TIM_CR1, &dat);
457 if (!(dat & TIM_CR1_CEN))
458 clk_enable(priv->clk);
459 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
462 regmap_read(priv->regmap, TIM_CR1, &dat);
463 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
465 if (dat & TIM_CR1_CEN)
466 clk_disable(priv->clk);
474 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
475 struct iio_trigger *trig)
477 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
478 const char * const *cur = priv->valids;
481 if (!is_stm32_timer_trigger(trig))
484 while (cur && *cur) {
485 if (!strncmp(trig->name, *cur, strlen(trig->name))) {
486 regmap_update_bits(priv->regmap,
487 TIM_SMCR, TIM_SMCR_TS,
488 i << TIM_SMCR_TS_SHIFT);
498 static const struct iio_info stm32_trigger_info = {
499 .validate_trigger = stm32_counter_validate_trigger,
500 .read_raw = stm32_counter_read_raw,
501 .write_raw = stm32_counter_write_raw
504 static const char *const stm32_trigger_modes[] = {
508 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
509 const struct iio_chan_spec *chan,
512 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
514 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
519 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
520 const struct iio_chan_spec *chan)
522 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
525 regmap_read(priv->regmap, TIM_SMCR, &smcr);
527 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
530 static const struct iio_enum stm32_trigger_mode_enum = {
531 .items = stm32_trigger_modes,
532 .num_items = ARRAY_SIZE(stm32_trigger_modes),
533 .set = stm32_set_trigger_mode,
534 .get = stm32_get_trigger_mode
537 static const char *const stm32_enable_modes[] = {
543 static int stm32_enable_mode2sms(int mode)
557 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
558 const struct iio_chan_spec *chan,
561 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
562 int sms = stm32_enable_mode2sms(mode);
568 * Triggered mode sets CEN bit automatically by hardware. So, first
569 * enable counter clock, so it can use it. Keeps it in sync with CEN.
572 regmap_read(priv->regmap, TIM_CR1, &val);
573 if (!(val & TIM_CR1_CEN))
574 clk_enable(priv->clk);
577 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
582 static int stm32_sms2enable_mode(int mode)
596 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
597 const struct iio_chan_spec *chan)
599 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
602 regmap_read(priv->regmap, TIM_SMCR, &smcr);
603 smcr &= TIM_SMCR_SMS;
605 return stm32_sms2enable_mode(smcr);
608 static const struct iio_enum stm32_enable_mode_enum = {
609 .items = stm32_enable_modes,
610 .num_items = ARRAY_SIZE(stm32_enable_modes),
611 .set = stm32_set_enable_mode,
612 .get = stm32_get_enable_mode
615 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
617 const struct iio_chan_spec *chan,
620 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
623 regmap_read(priv->regmap, TIM_ARR, &arr);
625 return snprintf(buf, PAGE_SIZE, "%u\n", arr);
628 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
630 const struct iio_chan_spec *chan,
631 const char *buf, size_t len)
633 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
637 ret = kstrtouint(buf, 0, &preset);
641 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
642 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
643 regmap_write(priv->regmap, TIM_ARR, preset);
648 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
651 .shared = IIO_SEPARATE,
652 .read = stm32_count_get_preset,
653 .write = stm32_count_set_preset
655 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
656 IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
657 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
658 IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
662 static const struct iio_chan_spec stm32_trigger_channel = {
665 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
666 BIT(IIO_CHAN_INFO_ENABLE) |
667 BIT(IIO_CHAN_INFO_SCALE),
668 .ext_info = stm32_trigger_count_info,
672 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
674 struct iio_dev *indio_dev;
677 indio_dev = devm_iio_device_alloc(dev,
678 sizeof(struct stm32_timer_trigger));
682 indio_dev->name = dev_name(dev);
683 indio_dev->dev.parent = dev;
684 indio_dev->info = &stm32_trigger_info;
685 indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
686 indio_dev->num_channels = 1;
687 indio_dev->channels = &stm32_trigger_channel;
688 indio_dev->dev.of_node = dev->of_node;
690 ret = devm_iio_device_register(dev, indio_dev);
694 return iio_priv(indio_dev);
698 * is_stm32_timer_trigger
699 * @trig: trigger to be checked
701 * return true if the trigger is a valid stm32 iio timer trigger
702 * either return false
704 bool is_stm32_timer_trigger(struct iio_trigger *trig)
706 return (trig->ops == &timer_trigger_ops);
708 EXPORT_SYMBOL(is_stm32_timer_trigger);
710 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
715 * Master mode selection 2 bits can only be written and read back when
718 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
719 regmap_read(priv->regmap, TIM_CR2, &val);
720 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
721 priv->has_trgo2 = !!val;
724 static int stm32_timer_trigger_probe(struct platform_device *pdev)
726 struct device *dev = &pdev->dev;
727 struct stm32_timer_trigger *priv;
728 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
729 const struct stm32_timer_trigger_cfg *cfg;
733 if (of_property_read_u32(dev->of_node, "reg", &index))
736 cfg = (const struct stm32_timer_trigger_cfg *)
737 of_match_device(dev->driver->of_match_table, dev)->data;
739 if (index >= ARRAY_SIZE(triggers_table) ||
740 index >= cfg->num_valids_table)
743 /* Create an IIO device only if we have triggers to be validated */
744 if (*cfg->valids_table[index])
745 priv = stm32_setup_counter_device(dev);
747 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
753 priv->regmap = ddata->regmap;
754 priv->clk = ddata->clk;
755 priv->max_arr = ddata->max_arr;
756 priv->triggers = triggers_table[index];
757 priv->valids = cfg->valids_table[index];
758 stm32_timer_detect_trgo2(priv);
760 ret = stm32_setup_iio_triggers(priv);
764 platform_set_drvdata(pdev, priv);
769 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
770 .valids_table = valids_table,
771 .num_valids_table = ARRAY_SIZE(valids_table),
774 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
775 .valids_table = stm32h7_valids_table,
776 .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
779 static const struct of_device_id stm32_trig_of_match[] = {
781 .compatible = "st,stm32-timer-trigger",
782 .data = (void *)&stm32_timer_trg_cfg,
784 .compatible = "st,stm32h7-timer-trigger",
785 .data = (void *)&stm32h7_timer_trg_cfg,
789 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
791 static struct platform_driver stm32_timer_trigger_driver = {
792 .probe = stm32_timer_trigger_probe,
794 .name = "stm32-timer-trigger",
795 .of_match_table = stm32_trig_of_match,
798 module_platform_driver(stm32_timer_trigger_driver);
800 MODULE_ALIAS("platform: stm32-timer-trigger");
801 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
802 MODULE_LICENSE("GPL v2");