2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
70 spin_unlock_irq(&dev->lock);
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
79 static void free_ird(struct c4iw_dev *dev, int ird)
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
110 dealloc_host_sq(rdev, sq);
113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
143 ret = alloc_oc_sq(rdev, sq);
145 ret = alloc_host_sq(rdev, sq);
149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx)
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
156 dma_free_coherent(&(rdev->lldi.pdev->dev),
157 wq->rq.memsize, wq->rq.queue,
158 dma_unmap_addr(&wq->rq, mapping));
159 dealloc_sq(rdev, &wq->sq);
160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
163 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
164 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
174 enum cxgb4_bar2_qtype qtype,
175 unsigned int *pbar2_qid, u64 *pbar2_pa)
180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
182 &bar2_qoffset, pbar2_qid);
187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
189 if (is_t4(rdev->lldi.adapter_type))
192 return rdev->bar2_kva + bar2_qoffset;
195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
196 struct t4_cq *rcq, struct t4_cq *scq,
197 struct c4iw_dev_ucontext *uctx)
199 int user = (uctx != &rdev->uctx);
200 struct fw_ri_res_wr *res_wr;
201 struct fw_ri_res *res;
203 struct c4iw_wr_wait wr_wait;
208 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
212 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
235 * RQT must be a power of 2 and at least 16 deep.
237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
239 if (!wq->rq.rqt_hwaddr) {
244 ret = alloc_sq(rdev, &wq->sq, user);
247 memset(wq->sq.queue, 0, wq->sq.memsize);
248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
251 wq->rq.memsize, &(wq->rq.dma_addr),
257 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
258 __func__, wq->sq.queue,
259 (unsigned long long)virt_to_phys(wq->sq.queue),
261 (unsigned long long)virt_to_phys(wq->rq.queue));
262 memset(wq->rq.queue, 0, wq->rq.memsize);
263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
265 wq->db = rdev->lldi.db_reg;
267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
269 user ? &wq->sq.bar2_pa : NULL);
270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
272 user ? &wq->rq.bar2_pa : NULL);
275 * User mode must have bar2 access.
277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) {
278 pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n",
279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
286 /* build fw_ri_res_wr */
287 wr_len = sizeof *res_wr + 2 * sizeof *res;
289 skb = alloc_skb(wr_len, GFP_KERNEL);
294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
296 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
297 memset(res_wr, 0, wr_len);
298 res_wr->op_nres = cpu_to_be32(
299 FW_WR_OP_V(FW_RI_RES_WR) |
300 FW_RI_RES_WR_NRES_V(2) |
302 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
303 res_wr->cookie = (uintptr_t)&wr_wait;
305 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
306 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
309 * eqsize is the number of 64B entries plus the status page size.
311 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
312 rdev->hw_queue.t4_eq_status_entries;
314 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
318 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
319 FW_RI_RES_WR_IQID_V(scq->cqid));
320 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
321 FW_RI_RES_WR_DCAEN_V(0) |
322 FW_RI_RES_WR_DCACPU_V(0) |
323 FW_RI_RES_WR_FBMIN_V(2) |
324 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) :
325 FW_RI_RES_WR_FBMAX_V(3)) |
326 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
327 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
328 FW_RI_RES_WR_EQSIZE_V(eqsize));
329 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
330 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
332 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
333 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
336 * eqsize is the number of 64B entries plus the status page size.
338 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
339 rdev->hw_queue.t4_eq_status_entries;
340 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
341 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
342 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
343 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
344 FW_RI_RES_WR_IQID_V(rcq->cqid));
345 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
346 FW_RI_RES_WR_DCAEN_V(0) |
347 FW_RI_RES_WR_DCACPU_V(0) |
348 FW_RI_RES_WR_FBMIN_V(2) |
349 FW_RI_RES_WR_FBMAX_V(3) |
350 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
351 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
352 FW_RI_RES_WR_EQSIZE_V(eqsize));
353 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
354 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
356 c4iw_init_wr_wait(&wr_wait);
358 ret = c4iw_ofld_send(rdev, skb);
361 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
365 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
366 __func__, wq->sq.qid, wq->rq.qid, wq->db,
367 wq->sq.bar2_va, wq->rq.bar2_va);
371 dma_free_coherent(&(rdev->lldi.pdev->dev),
372 wq->rq.memsize, wq->rq.queue,
373 dma_unmap_addr(&wq->rq, mapping));
375 dealloc_sq(rdev, &wq->sq);
377 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
383 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
385 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
389 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
390 struct ib_send_wr *wr, int max, u32 *plenp)
397 dstp = (u8 *)immdp->data;
398 for (i = 0; i < wr->num_sge; i++) {
399 if ((plen + wr->sg_list[i].length) > max)
401 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
402 plen += wr->sg_list[i].length;
403 rem = wr->sg_list[i].length;
405 if (dstp == (u8 *)&sq->queue[sq->size])
406 dstp = (u8 *)sq->queue;
407 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
410 len = (u8 *)&sq->queue[sq->size] - dstp;
411 memcpy(dstp, srcp, len);
417 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
419 memset(dstp, 0, len);
420 immdp->op = FW_RI_DATA_IMMD;
423 immdp->immdlen = cpu_to_be32(plen);
428 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
429 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
430 int num_sge, u32 *plenp)
435 __be64 *flitp = (__be64 *)isglp->sge;
437 for (i = 0; i < num_sge; i++) {
438 if ((plen + sg_list[i].length) < plen)
440 plen += sg_list[i].length;
441 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
443 if (++flitp == queue_end)
445 *flitp = cpu_to_be64(sg_list[i].addr);
446 if (++flitp == queue_end)
449 *flitp = (__force __be64)0;
450 isglp->op = FW_RI_DATA_ISGL;
452 isglp->nsge = cpu_to_be16(num_sge);
459 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
460 struct ib_send_wr *wr, u8 *len16)
466 if (wr->num_sge > T4_MAX_SEND_SGE)
468 switch (wr->opcode) {
470 if (wr->send_flags & IB_SEND_SOLICITED)
471 wqe->send.sendop_pkd = cpu_to_be32(
472 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
474 wqe->send.sendop_pkd = cpu_to_be32(
475 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
476 wqe->send.stag_inv = 0;
478 case IB_WR_SEND_WITH_INV:
479 if (wr->send_flags & IB_SEND_SOLICITED)
480 wqe->send.sendop_pkd = cpu_to_be32(
481 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
483 wqe->send.sendop_pkd = cpu_to_be32(
484 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
485 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
496 if (wr->send_flags & IB_SEND_INLINE) {
497 ret = build_immd(sq, wqe->send.u.immd_src, wr,
498 T4_MAX_SEND_INLINE, &plen);
501 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
504 ret = build_isgl((__be64 *)sq->queue,
505 (__be64 *)&sq->queue[sq->size],
506 wqe->send.u.isgl_src,
507 wr->sg_list, wr->num_sge, &plen);
510 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
511 wr->num_sge * sizeof(struct fw_ri_sge);
514 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
515 wqe->send.u.immd_src[0].r1 = 0;
516 wqe->send.u.immd_src[0].r2 = 0;
517 wqe->send.u.immd_src[0].immdlen = 0;
518 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
521 *len16 = DIV_ROUND_UP(size, 16);
522 wqe->send.plen = cpu_to_be32(plen);
526 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
527 struct ib_send_wr *wr, u8 *len16)
533 if (wr->num_sge > T4_MAX_SEND_SGE)
536 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
537 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
539 if (wr->send_flags & IB_SEND_INLINE) {
540 ret = build_immd(sq, wqe->write.u.immd_src, wr,
541 T4_MAX_WRITE_INLINE, &plen);
544 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
547 ret = build_isgl((__be64 *)sq->queue,
548 (__be64 *)&sq->queue[sq->size],
549 wqe->write.u.isgl_src,
550 wr->sg_list, wr->num_sge, &plen);
553 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
554 wr->num_sge * sizeof(struct fw_ri_sge);
557 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
558 wqe->write.u.immd_src[0].r1 = 0;
559 wqe->write.u.immd_src[0].r2 = 0;
560 wqe->write.u.immd_src[0].immdlen = 0;
561 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
564 *len16 = DIV_ROUND_UP(size, 16);
565 wqe->write.plen = cpu_to_be32(plen);
569 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
574 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
575 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
577 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
578 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
579 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
580 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
582 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
584 wqe->read.stag_src = cpu_to_be32(2);
585 wqe->read.to_src_hi = 0;
586 wqe->read.to_src_lo = 0;
587 wqe->read.stag_sink = cpu_to_be32(2);
589 wqe->read.to_sink_hi = 0;
590 wqe->read.to_sink_lo = 0;
594 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
598 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
599 struct ib_recv_wr *wr, u8 *len16)
603 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
604 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
605 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
608 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
609 wr->num_sge * sizeof(struct fw_ri_sge), 16);
613 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
614 struct ib_reg_wr *wr, struct c4iw_mr *mhp,
617 __be64 *p = (__be64 *)fr->pbl;
619 fr->r2 = cpu_to_be32(0);
620 fr->stag = cpu_to_be32(mhp->ibmr.rkey);
622 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
623 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) |
624 FW_RI_TPTE_STAGSTATE_V(1) |
625 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) |
626 FW_RI_TPTE_PDID_V(mhp->attr.pdid));
627 fr->tpte.locread_to_qpid = cpu_to_be32(
628 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) |
629 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) |
630 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12));
631 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V(
632 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
633 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
634 fr->tpte.len_hi = cpu_to_be32(0);
635 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length);
636 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
637 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
639 p[0] = cpu_to_be64((u64)mhp->mpl[0]);
640 p[1] = cpu_to_be64((u64)mhp->mpl[1]);
642 *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
645 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
646 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16,
649 struct fw_ri_immd *imdp;
652 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
655 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
658 wqe->fr.qpbinde_to_dcacpu = 0;
659 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
660 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
661 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
663 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
664 wqe->fr.stag = cpu_to_be32(wr->key);
665 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
666 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
669 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
670 struct fw_ri_dsgl *sglp;
672 for (i = 0; i < mhp->mpl_len; i++)
673 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
675 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
676 sglp->op = FW_RI_DATA_DSGL;
678 sglp->nsge = cpu_to_be16(1);
679 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
680 sglp->len0 = cpu_to_be32(pbllen);
682 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
684 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
685 imdp->op = FW_RI_DATA_IMMD;
688 imdp->immdlen = cpu_to_be32(pbllen);
689 p = (__be64 *)(imdp + 1);
691 for (i = 0; i < mhp->mpl_len; i++) {
692 *p = cpu_to_be64((u64)mhp->mpl[i]);
694 if (++p == (__be64 *)&sq->queue[sq->size])
695 p = (__be64 *)sq->queue;
701 if (++p == (__be64 *)&sq->queue[sq->size])
702 p = (__be64 *)sq->queue;
704 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
710 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
712 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
714 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
718 static void _free_qp(struct kref *kref)
722 qhp = container_of(kref, struct c4iw_qp, kref);
723 PDBG("%s qhp %p\n", __func__, qhp);
727 void c4iw_qp_add_ref(struct ib_qp *qp)
729 PDBG("%s ib_qp %p\n", __func__, qp);
730 kref_get(&to_c4iw_qp(qp)->kref);
733 void c4iw_qp_rem_ref(struct ib_qp *qp)
735 PDBG("%s ib_qp %p\n", __func__, qp);
736 kref_put(&to_c4iw_qp(qp)->kref, _free_qp);
739 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
741 if (list_empty(entry))
742 list_add_tail(entry, head);
745 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
749 spin_lock_irqsave(&qhp->rhp->lock, flags);
750 spin_lock(&qhp->lock);
751 if (qhp->rhp->db_state == NORMAL)
752 t4_ring_sq_db(&qhp->wq, inc, NULL);
754 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
755 qhp->wq.sq.wq_pidx_inc += inc;
757 spin_unlock(&qhp->lock);
758 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
762 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
766 spin_lock_irqsave(&qhp->rhp->lock, flags);
767 spin_lock(&qhp->lock);
768 if (qhp->rhp->db_state == NORMAL)
769 t4_ring_rq_db(&qhp->wq, inc, NULL);
771 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
772 qhp->wq.rq.wq_pidx_inc += inc;
774 spin_unlock(&qhp->lock);
775 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
779 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
780 struct ib_send_wr **bad_wr)
784 enum fw_wr_opcodes fw_opcode = 0;
785 enum fw_ri_wr_flags fw_flags;
787 union t4_wr *wqe = NULL;
789 struct t4_swsqe *swsqe;
793 qhp = to_c4iw_qp(ibqp);
794 spin_lock_irqsave(&qhp->lock, flag);
795 if (t4_wq_in_error(&qhp->wq)) {
796 spin_unlock_irqrestore(&qhp->lock, flag);
800 num_wrs = t4_sq_avail(&qhp->wq);
802 spin_unlock_irqrestore(&qhp->lock, flag);
812 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
813 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
816 if (wr->send_flags & IB_SEND_SOLICITED)
817 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
818 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
819 fw_flags |= FW_RI_COMPLETION_FLAG;
820 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
821 switch (wr->opcode) {
822 case IB_WR_SEND_WITH_INV:
824 if (wr->send_flags & IB_SEND_FENCE)
825 fw_flags |= FW_RI_READ_FENCE_FLAG;
826 fw_opcode = FW_RI_SEND_WR;
827 if (wr->opcode == IB_WR_SEND)
828 swsqe->opcode = FW_RI_SEND;
830 swsqe->opcode = FW_RI_SEND_WITH_INV;
831 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
833 case IB_WR_RDMA_WRITE:
834 fw_opcode = FW_RI_RDMA_WRITE_WR;
835 swsqe->opcode = FW_RI_RDMA_WRITE;
836 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
838 case IB_WR_RDMA_READ:
839 case IB_WR_RDMA_READ_WITH_INV:
840 fw_opcode = FW_RI_RDMA_READ_WR;
841 swsqe->opcode = FW_RI_READ_REQ;
842 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
843 c4iw_invalidate_mr(qhp->rhp,
844 wr->sg_list[0].lkey);
845 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
849 err = build_rdma_read(wqe, wr, &len16);
852 swsqe->read_len = wr->sg_list[0].length;
853 if (!qhp->wq.sq.oldest_read)
854 qhp->wq.sq.oldest_read = swsqe;
857 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
859 swsqe->opcode = FW_RI_FAST_REGISTER;
860 if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support &&
861 !mhp->attr.state && mhp->mpl_len <= 2) {
862 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
863 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
866 fw_opcode = FW_RI_FR_NSMR_WR;
867 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
869 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
876 case IB_WR_LOCAL_INV:
877 if (wr->send_flags & IB_SEND_FENCE)
878 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
879 fw_opcode = FW_RI_INV_LSTAG_WR;
880 swsqe->opcode = FW_RI_LOCAL_INV;
881 err = build_inv_stag(wqe, wr, &len16);
882 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
885 PDBG("%s post of type=%d TBD!\n", __func__,
893 swsqe->idx = qhp->wq.sq.pidx;
895 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
898 swsqe->wr_id = wr->wr_id;
900 swsqe->sge_ts = cxgb4_read_sge_timestamp(
901 qhp->rhp->rdev.lldi.ports[0]);
902 getnstimeofday(&swsqe->host_ts);
905 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
907 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
908 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
909 swsqe->opcode, swsqe->read_len);
912 t4_sq_produce(&qhp->wq, len16);
913 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
915 if (!qhp->rhp->rdev.status_page->db_off) {
916 t4_ring_sq_db(&qhp->wq, idx, wqe);
917 spin_unlock_irqrestore(&qhp->lock, flag);
919 spin_unlock_irqrestore(&qhp->lock, flag);
920 ring_kernel_sq_db(qhp, idx);
925 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
926 struct ib_recv_wr **bad_wr)
930 union t4_recv_wr *wqe = NULL;
936 qhp = to_c4iw_qp(ibqp);
937 spin_lock_irqsave(&qhp->lock, flag);
938 if (t4_wq_in_error(&qhp->wq)) {
939 spin_unlock_irqrestore(&qhp->lock, flag);
943 num_wrs = t4_rq_avail(&qhp->wq);
945 spin_unlock_irqrestore(&qhp->lock, flag);
950 if (wr->num_sge > T4_MAX_RECV_SGE) {
955 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
959 err = build_rdma_recv(qhp, wqe, wr, &len16);
967 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
969 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
970 cxgb4_read_sge_timestamp(
971 qhp->rhp->rdev.lldi.ports[0]);
973 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
976 wqe->recv.opcode = FW_RI_RECV_WR;
978 wqe->recv.wrid = qhp->wq.rq.pidx;
982 wqe->recv.len16 = len16;
983 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
984 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
985 t4_rq_produce(&qhp->wq, len16);
986 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
990 if (!qhp->rhp->rdev.status_page->db_off) {
991 t4_ring_rq_db(&qhp->wq, idx, wqe);
992 spin_unlock_irqrestore(&qhp->lock, flag);
994 spin_unlock_irqrestore(&qhp->lock, flag);
995 ring_kernel_rq_db(qhp, idx);
1000 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
1010 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1015 status = CQE_STATUS(err_cqe);
1016 opcode = CQE_OPCODE(err_cqe);
1017 rqtype = RQ_TYPE(err_cqe);
1018 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
1019 (opcode == FW_RI_SEND_WITH_SE_INV);
1020 tagged = (opcode == FW_RI_RDMA_WRITE) ||
1021 (rqtype && (opcode == FW_RI_READ_RESP));
1026 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1027 *ecode = RDMAP_CANT_INV_STAG;
1029 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1030 *ecode = RDMAP_INV_STAG;
1034 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1035 if ((opcode == FW_RI_SEND_WITH_INV) ||
1036 (opcode == FW_RI_SEND_WITH_SE_INV))
1037 *ecode = RDMAP_CANT_INV_STAG;
1039 *ecode = RDMAP_STAG_NOT_ASSOC;
1042 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1043 *ecode = RDMAP_STAG_NOT_ASSOC;
1046 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1047 *ecode = RDMAP_ACC_VIOL;
1050 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1051 *ecode = RDMAP_TO_WRAP;
1055 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1056 *ecode = DDPT_BASE_BOUNDS;
1058 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1059 *ecode = RDMAP_BASE_BOUNDS;
1062 case T4_ERR_INVALIDATE_SHARED_MR:
1063 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1064 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1065 *ecode = RDMAP_CANT_INV_STAG;
1068 case T4_ERR_ECC_PSTAG:
1069 case T4_ERR_INTERNAL_ERR:
1070 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1073 case T4_ERR_OUT_OF_RQE:
1074 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1075 *ecode = DDPU_INV_MSN_NOBUF;
1077 case T4_ERR_PBL_ADDR_BOUND:
1078 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1079 *ecode = DDPT_BASE_BOUNDS;
1082 *layer_type = LAYER_MPA|DDP_LLP;
1083 *ecode = MPA_CRC_ERR;
1086 *layer_type = LAYER_MPA|DDP_LLP;
1087 *ecode = MPA_MARKER_ERR;
1089 case T4_ERR_PDU_LEN_ERR:
1090 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1091 *ecode = DDPU_MSG_TOOBIG;
1093 case T4_ERR_DDP_VERSION:
1095 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1096 *ecode = DDPT_INV_VERS;
1098 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1099 *ecode = DDPU_INV_VERS;
1102 case T4_ERR_RDMA_VERSION:
1103 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1104 *ecode = RDMAP_INV_VERS;
1107 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1108 *ecode = RDMAP_INV_OPCODE;
1110 case T4_ERR_DDP_QUEUE_NUM:
1111 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1112 *ecode = DDPU_INV_QN;
1115 case T4_ERR_MSN_GAP:
1116 case T4_ERR_MSN_RANGE:
1117 case T4_ERR_IRD_OVERFLOW:
1118 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1119 *ecode = DDPU_INV_MSN_RANGE;
1122 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1126 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1127 *ecode = DDPU_INV_MO;
1130 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1136 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1139 struct fw_ri_wr *wqe;
1140 struct sk_buff *skb;
1141 struct terminate_message *term;
1143 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1146 skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
1150 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1152 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1153 memset(wqe, 0, sizeof *wqe);
1154 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1155 wqe->flowid_len16 = cpu_to_be32(
1156 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1157 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1159 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1160 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1161 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1162 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1163 term->layer_etype = qhp->attr.layer_etype;
1164 term->ecode = qhp->attr.ecode;
1166 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1167 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1171 * Assumes qhp lock is held.
1173 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1174 struct c4iw_cq *schp)
1177 int rq_flushed, sq_flushed;
1180 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1182 /* locking hierarchy: cq lock first, then qp lock. */
1183 spin_lock_irqsave(&rchp->lock, flag);
1184 spin_lock(&qhp->lock);
1186 if (qhp->wq.flushed) {
1187 spin_unlock(&qhp->lock);
1188 spin_unlock_irqrestore(&rchp->lock, flag);
1191 qhp->wq.flushed = 1;
1193 c4iw_flush_hw_cq(rchp);
1194 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1195 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1196 spin_unlock(&qhp->lock);
1197 spin_unlock_irqrestore(&rchp->lock, flag);
1199 /* locking hierarchy: cq lock first, then qp lock. */
1200 spin_lock_irqsave(&schp->lock, flag);
1201 spin_lock(&qhp->lock);
1203 c4iw_flush_hw_cq(schp);
1204 sq_flushed = c4iw_flush_sq(qhp);
1205 spin_unlock(&qhp->lock);
1206 spin_unlock_irqrestore(&schp->lock, flag);
1209 if (t4_clear_cq_armed(&rchp->cq) &&
1210 (rq_flushed || sq_flushed)) {
1211 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1212 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1213 rchp->ibcq.cq_context);
1214 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1217 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
1218 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1219 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1220 rchp->ibcq.cq_context);
1221 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1223 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
1224 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1225 (*schp->ibcq.comp_handler)(&schp->ibcq,
1226 schp->ibcq.cq_context);
1227 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1232 static void flush_qp(struct c4iw_qp *qhp)
1234 struct c4iw_cq *rchp, *schp;
1237 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1238 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1240 t4_set_wq_in_error(&qhp->wq);
1241 if (qhp->ibqp.uobject) {
1242 t4_set_cq_in_error(&rchp->cq);
1243 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1244 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1245 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1247 t4_set_cq_in_error(&schp->cq);
1248 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1249 (*schp->ibcq.comp_handler)(&schp->ibcq,
1250 schp->ibcq.cq_context);
1251 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1255 __flush_qp(qhp, rchp, schp);
1258 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1261 struct fw_ri_wr *wqe;
1263 struct sk_buff *skb;
1265 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1268 skb = skb_dequeue(&ep->com.ep_skb_list);
1272 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1274 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1275 memset(wqe, 0, sizeof *wqe);
1276 wqe->op_compl = cpu_to_be32(
1277 FW_WR_OP_V(FW_RI_INIT_WR) |
1279 wqe->flowid_len16 = cpu_to_be32(
1280 FW_WR_FLOWID_V(ep->hwtid) |
1281 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1282 wqe->cookie = (uintptr_t)&ep->com.wr_wait;
1284 wqe->u.fini.type = FW_RI_TYPE_FINI;
1285 ret = c4iw_ofld_send(&rhp->rdev, skb);
1289 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1290 qhp->wq.sq.qid, __func__);
1292 PDBG("%s ret %d\n", __func__, ret);
1296 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1298 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1299 memset(&init->u, 0, sizeof init->u);
1301 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1302 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1303 init->u.write.stag_sink = cpu_to_be32(1);
1304 init->u.write.to_sink = cpu_to_be64(1);
1305 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1306 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1307 sizeof(struct fw_ri_immd),
1310 case FW_RI_INIT_P2PTYPE_READ_REQ:
1311 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1312 init->u.read.stag_src = cpu_to_be32(1);
1313 init->u.read.to_src_lo = cpu_to_be32(1);
1314 init->u.read.stag_sink = cpu_to_be32(1);
1315 init->u.read.to_sink_lo = cpu_to_be32(1);
1316 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1321 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1323 struct fw_ri_wr *wqe;
1325 struct sk_buff *skb;
1327 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp,
1328 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1330 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1335 ret = alloc_ird(rhp, qhp->attr.max_ird);
1337 qhp->attr.max_ird = 0;
1341 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1343 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1344 memset(wqe, 0, sizeof *wqe);
1345 wqe->op_compl = cpu_to_be32(
1346 FW_WR_OP_V(FW_RI_INIT_WR) |
1348 wqe->flowid_len16 = cpu_to_be32(
1349 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1350 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1352 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait;
1354 wqe->u.init.type = FW_RI_TYPE_INIT;
1355 wqe->u.init.mpareqbit_p2ptype =
1356 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1357 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1358 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1359 if (qhp->attr.mpa_attr.recv_marker_enabled)
1360 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1361 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1362 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1363 if (qhp->attr.mpa_attr.crc_enabled)
1364 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1366 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1367 FW_RI_QP_RDMA_WRITE_ENABLE |
1368 FW_RI_QP_BIND_ENABLE;
1369 if (!qhp->ibqp.uobject)
1370 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1371 FW_RI_QP_STAG0_ENABLE;
1372 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1373 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1374 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1375 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1376 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1377 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1378 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1379 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1380 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1381 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1382 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1383 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1384 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1385 rhp->rdev.lldi.vr->rq.start);
1386 if (qhp->attr.mpa_attr.initiator)
1387 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1389 ret = c4iw_ofld_send(&rhp->rdev, skb);
1393 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1394 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1398 free_ird(rhp, qhp->attr.max_ird);
1400 PDBG("%s ret %d\n", __func__, ret);
1404 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1405 enum c4iw_qp_attr_mask mask,
1406 struct c4iw_qp_attributes *attrs,
1410 struct c4iw_qp_attributes newattr = qhp->attr;
1415 struct c4iw_ep *ep = NULL;
1417 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1418 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1419 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1421 mutex_lock(&qhp->mutex);
1423 /* Process attr changes if in IDLE */
1424 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1425 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1429 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1430 newattr.enable_rdma_read = attrs->enable_rdma_read;
1431 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1432 newattr.enable_rdma_write = attrs->enable_rdma_write;
1433 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1434 newattr.enable_bind = attrs->enable_bind;
1435 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1436 if (attrs->max_ord > c4iw_max_read_depth) {
1440 newattr.max_ord = attrs->max_ord;
1442 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1443 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1447 newattr.max_ird = attrs->max_ird;
1449 qhp->attr = newattr;
1452 if (mask & C4IW_QP_ATTR_SQ_DB) {
1453 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1456 if (mask & C4IW_QP_ATTR_RQ_DB) {
1457 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1461 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1463 if (qhp->attr.state == attrs->next_state)
1466 switch (qhp->attr.state) {
1467 case C4IW_QP_STATE_IDLE:
1468 switch (attrs->next_state) {
1469 case C4IW_QP_STATE_RTS:
1470 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1474 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1478 qhp->attr.mpa_attr = attrs->mpa_attr;
1479 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1480 qhp->ep = qhp->attr.llp_stream_handle;
1481 set_state(qhp, C4IW_QP_STATE_RTS);
1484 * Ref the endpoint here and deref when we
1485 * disassociate the endpoint from the QP. This
1486 * happens in CLOSING->IDLE transition or *->ERROR
1489 c4iw_get_ep(&qhp->ep->com);
1490 ret = rdma_init(rhp, qhp);
1494 case C4IW_QP_STATE_ERROR:
1495 set_state(qhp, C4IW_QP_STATE_ERROR);
1503 case C4IW_QP_STATE_RTS:
1504 switch (attrs->next_state) {
1505 case C4IW_QP_STATE_CLOSING:
1506 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1507 t4_set_wq_in_error(&qhp->wq);
1508 set_state(qhp, C4IW_QP_STATE_CLOSING);
1513 c4iw_get_ep(&qhp->ep->com);
1515 ret = rdma_fini(rhp, qhp, ep);
1519 case C4IW_QP_STATE_TERMINATE:
1520 t4_set_wq_in_error(&qhp->wq);
1521 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1522 qhp->attr.layer_etype = attrs->layer_etype;
1523 qhp->attr.ecode = attrs->ecode;
1526 c4iw_get_ep(&qhp->ep->com);
1530 terminate = qhp->attr.send_term;
1531 ret = rdma_fini(rhp, qhp, ep);
1536 case C4IW_QP_STATE_ERROR:
1537 t4_set_wq_in_error(&qhp->wq);
1538 set_state(qhp, C4IW_QP_STATE_ERROR);
1543 c4iw_get_ep(&qhp->ep->com);
1552 case C4IW_QP_STATE_CLOSING:
1557 switch (attrs->next_state) {
1558 case C4IW_QP_STATE_IDLE:
1560 set_state(qhp, C4IW_QP_STATE_IDLE);
1561 qhp->attr.llp_stream_handle = NULL;
1562 c4iw_put_ep(&qhp->ep->com);
1564 wake_up(&qhp->wait);
1566 case C4IW_QP_STATE_ERROR:
1573 case C4IW_QP_STATE_ERROR:
1574 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1578 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1582 set_state(qhp, C4IW_QP_STATE_IDLE);
1584 case C4IW_QP_STATE_TERMINATE:
1592 printk(KERN_ERR "%s in a bad state %d\n",
1593 __func__, qhp->attr.state);
1600 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1603 /* disassociate the LLP connection */
1604 qhp->attr.llp_stream_handle = NULL;
1608 set_state(qhp, C4IW_QP_STATE_ERROR);
1613 wake_up(&qhp->wait);
1615 mutex_unlock(&qhp->mutex);
1618 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1621 * If disconnect is 1, then we need to initiate a disconnect
1622 * on the EP. This can be a normal close (RTS->CLOSING) or
1623 * an abnormal close (RTS/CLOSING->ERROR).
1626 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1628 c4iw_put_ep(&ep->com);
1632 * If free is 1, then we've disassociated the EP from the QP
1633 * and we need to dereference the EP.
1636 c4iw_put_ep(&ep->com);
1637 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1641 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1643 struct c4iw_dev *rhp;
1644 struct c4iw_qp *qhp;
1645 struct c4iw_qp_attributes attrs;
1646 struct c4iw_ucontext *ucontext;
1648 qhp = to_c4iw_qp(ib_qp);
1651 attrs.next_state = C4IW_QP_STATE_ERROR;
1652 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1653 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1655 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1656 wait_event(qhp->wait, !qhp->ep);
1658 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1660 spin_lock_irq(&rhp->lock);
1661 if (!list_empty(&qhp->db_fc_entry))
1662 list_del_init(&qhp->db_fc_entry);
1663 spin_unlock_irq(&rhp->lock);
1664 free_ird(rhp, qhp->attr.max_ird);
1666 ucontext = ib_qp->uobject ?
1667 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1668 destroy_qp(&rhp->rdev, &qhp->wq,
1669 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1671 c4iw_qp_rem_ref(ib_qp);
1673 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1677 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1678 struct ib_udata *udata)
1680 struct c4iw_dev *rhp;
1681 struct c4iw_qp *qhp;
1682 struct c4iw_pd *php;
1683 struct c4iw_cq *schp;
1684 struct c4iw_cq *rchp;
1685 struct c4iw_create_qp_resp uresp;
1686 unsigned int sqsize, rqsize;
1687 struct c4iw_ucontext *ucontext;
1689 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1690 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1692 PDBG("%s ib_pd %p\n", __func__, pd);
1694 if (attrs->qp_type != IB_QPT_RC)
1695 return ERR_PTR(-EINVAL);
1697 php = to_c4iw_pd(pd);
1699 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1700 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1702 return ERR_PTR(-EINVAL);
1704 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1705 return ERR_PTR(-EINVAL);
1707 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1708 return ERR_PTR(-E2BIG);
1709 rqsize = attrs->cap.max_recv_wr + 1;
1713 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1714 return ERR_PTR(-E2BIG);
1715 sqsize = attrs->cap.max_send_wr + 1;
1719 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1721 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1723 return ERR_PTR(-ENOMEM);
1724 qhp->wq.sq.size = sqsize;
1725 qhp->wq.sq.memsize =
1726 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1727 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1728 qhp->wq.sq.flush_cidx = -1;
1729 qhp->wq.rq.size = rqsize;
1730 qhp->wq.rq.memsize =
1731 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1732 sizeof(*qhp->wq.rq.queue);
1735 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1736 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1739 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1740 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1744 attrs->cap.max_recv_wr = rqsize - 1;
1745 attrs->cap.max_send_wr = sqsize - 1;
1746 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1749 qhp->attr.pd = php->pdid;
1750 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1751 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1752 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1753 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1754 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1755 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1756 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1757 qhp->attr.state = C4IW_QP_STATE_IDLE;
1758 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1759 qhp->attr.enable_rdma_read = 1;
1760 qhp->attr.enable_rdma_write = 1;
1761 qhp->attr.enable_bind = 1;
1762 qhp->attr.max_ord = 0;
1763 qhp->attr.max_ird = 0;
1764 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1765 spin_lock_init(&qhp->lock);
1766 init_completion(&qhp->sq_drained);
1767 init_completion(&qhp->rq_drained);
1768 mutex_init(&qhp->mutex);
1769 init_waitqueue_head(&qhp->wait);
1770 kref_init(&qhp->kref);
1772 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1777 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1782 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1787 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1788 if (!sq_db_key_mm) {
1792 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1793 if (!rq_db_key_mm) {
1797 if (t4_sq_onchip(&qhp->wq.sq)) {
1798 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
1800 if (!ma_sync_key_mm) {
1804 uresp.flags = C4IW_QPF_ONCHIP;
1807 uresp.qid_mask = rhp->rdev.qpmask;
1808 uresp.sqid = qhp->wq.sq.qid;
1809 uresp.sq_size = qhp->wq.sq.size;
1810 uresp.sq_memsize = qhp->wq.sq.memsize;
1811 uresp.rqid = qhp->wq.rq.qid;
1812 uresp.rq_size = qhp->wq.rq.size;
1813 uresp.rq_memsize = qhp->wq.rq.memsize;
1814 spin_lock(&ucontext->mmap_lock);
1815 if (ma_sync_key_mm) {
1816 uresp.ma_sync_key = ucontext->key;
1817 ucontext->key += PAGE_SIZE;
1819 uresp.ma_sync_key = 0;
1821 uresp.sq_key = ucontext->key;
1822 ucontext->key += PAGE_SIZE;
1823 uresp.rq_key = ucontext->key;
1824 ucontext->key += PAGE_SIZE;
1825 uresp.sq_db_gts_key = ucontext->key;
1826 ucontext->key += PAGE_SIZE;
1827 uresp.rq_db_gts_key = ucontext->key;
1828 ucontext->key += PAGE_SIZE;
1829 spin_unlock(&ucontext->mmap_lock);
1830 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1833 sq_key_mm->key = uresp.sq_key;
1834 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1835 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1836 insert_mmap(ucontext, sq_key_mm);
1837 rq_key_mm->key = uresp.rq_key;
1838 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
1839 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1840 insert_mmap(ucontext, rq_key_mm);
1841 sq_db_key_mm->key = uresp.sq_db_gts_key;
1842 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
1843 sq_db_key_mm->len = PAGE_SIZE;
1844 insert_mmap(ucontext, sq_db_key_mm);
1845 rq_db_key_mm->key = uresp.rq_db_gts_key;
1846 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa;
1847 rq_db_key_mm->len = PAGE_SIZE;
1848 insert_mmap(ucontext, rq_db_key_mm);
1849 if (ma_sync_key_mm) {
1850 ma_sync_key_mm->key = uresp.ma_sync_key;
1851 ma_sync_key_mm->addr =
1852 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
1853 PCIE_MA_SYNC_A) & PAGE_MASK;
1854 ma_sync_key_mm->len = PAGE_SIZE;
1855 insert_mmap(ucontext, ma_sync_key_mm);
1858 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1859 init_timer(&(qhp->timer));
1860 INIT_LIST_HEAD(&qhp->db_fc_entry);
1861 PDBG("%s sq id %u size %u memsize %zu num_entries %u "
1862 "rq id %u size %u memsize %zu num_entries %u\n", __func__,
1863 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
1864 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
1865 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1868 kfree(ma_sync_key_mm);
1870 kfree(rq_db_key_mm);
1872 kfree(sq_db_key_mm);
1878 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1880 destroy_qp(&rhp->rdev, &qhp->wq,
1881 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1884 return ERR_PTR(ret);
1887 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1888 int attr_mask, struct ib_udata *udata)
1890 struct c4iw_dev *rhp;
1891 struct c4iw_qp *qhp;
1892 enum c4iw_qp_attr_mask mask = 0;
1893 struct c4iw_qp_attributes attrs;
1895 PDBG("%s ib_qp %p\n", __func__, ibqp);
1897 /* iwarp does not support the RTR state */
1898 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1899 attr_mask &= ~IB_QP_STATE;
1901 /* Make sure we still have something left to do */
1905 memset(&attrs, 0, sizeof attrs);
1906 qhp = to_c4iw_qp(ibqp);
1909 attrs.next_state = c4iw_convert_state(attr->qp_state);
1910 attrs.enable_rdma_read = (attr->qp_access_flags &
1911 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1912 attrs.enable_rdma_write = (attr->qp_access_flags &
1913 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1914 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1917 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1918 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1919 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1920 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1921 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1924 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1925 * ringing the queue db when we're in DB_FULL mode.
1926 * Only allow this on T4 devices.
1928 attrs.sq_db_inc = attr->sq_psn;
1929 attrs.rq_db_inc = attr->rq_psn;
1930 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1931 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1932 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
1933 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
1936 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1939 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1941 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1942 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1945 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1946 int attr_mask, struct ib_qp_init_attr *init_attr)
1948 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1950 memset(attr, 0, sizeof *attr);
1951 memset(init_attr, 0, sizeof *init_attr);
1952 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1953 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
1954 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
1955 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
1956 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
1957 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
1958 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
1962 static void move_qp_to_err(struct c4iw_qp *qp)
1964 struct c4iw_qp_attributes attrs = { .next_state = C4IW_QP_STATE_ERROR };
1966 (void)c4iw_modify_qp(qp->rhp, qp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1969 void c4iw_drain_sq(struct ib_qp *ibqp)
1971 struct c4iw_qp *qp = to_c4iw_qp(ibqp);
1976 spin_lock_irqsave(&qp->lock, flag);
1977 need_to_wait = !t4_sq_empty(&qp->wq);
1978 spin_unlock_irqrestore(&qp->lock, flag);
1981 wait_for_completion(&qp->sq_drained);
1984 void c4iw_drain_rq(struct ib_qp *ibqp)
1986 struct c4iw_qp *qp = to_c4iw_qp(ibqp);
1991 spin_lock_irqsave(&qp->lock, flag);
1992 need_to_wait = !t4_rq_empty(&qp->wq);
1993 spin_unlock_irqrestore(&qp->lock, flag);
1996 wait_for_completion(&qp->rq_drained);