4 * Copyright(c) 2015, 2016 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
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23 * modification, are permitted provided that the following conditions
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27 * notice, this list of conditions and the following disclaimer.
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29 * notice, this list of conditions and the following disclaimer in
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50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
59 #include <linux/completion.h>
60 #include <linux/kref.h>
61 #include <linux/sched.h>
62 #include <linux/cdev.h>
63 #include <linux/delay.h>
64 #include <linux/kthread.h>
65 #include <linux/i2c.h>
66 #include <linux/i2c-algo-bit.h>
67 #include <rdma/ib_hdrs.h>
68 #include <linux/rhashtable.h>
69 #include <rdma/rdma_vt.h>
71 #include "chip_registers.h"
81 /* bumped 1 from s/w major version of TrueScale */
82 #define HFI1_CHIP_VERS_MAJ 3U
84 /* don't care about this except printing */
85 #define HFI1_CHIP_VERS_MIN 0U
87 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
88 #define HFI1_OUI 0x001175
89 #define HFI1_OUI_LSB 40
91 #define DROP_PACKET_OFF 0
92 #define DROP_PACKET_ON 1
94 extern unsigned long hfi1_cap_mask;
95 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
96 #define HFI1_CAP_UGET_MASK(mask, cap) \
97 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
98 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
99 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
100 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
101 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
102 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
104 /* Offline Disabled Reason is 4-bits */
105 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
108 * Control context is always 0 and handles the error packets.
109 * It also handles the VL15 and multicast packets.
111 #define HFI1_CTRL_CTXT 0
114 * Driver context will store software counters for each of the events
115 * associated with these status registers
117 #define NUM_CCE_ERR_STATUS_COUNTERS 41
118 #define NUM_RCV_ERR_STATUS_COUNTERS 64
119 #define NUM_MISC_ERR_STATUS_COUNTERS 13
120 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
121 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
122 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
123 #define NUM_SEND_ERR_STATUS_COUNTERS 3
124 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
125 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
128 * per driver stats, either not device nor port-specific, or
129 * summed over all of the devices and ports.
130 * They are described by name via ipathfs filesystem, so layout
131 * and number of elements can change without breaking compatibility.
132 * If members are added or deleted hfi1_statnames[] in debugfs.c must
135 struct hfi1_ib_stats {
136 __u64 sps_ints; /* number of interrupts handled */
137 __u64 sps_errints; /* number of error interrupts */
138 __u64 sps_txerrs; /* tx-related packet errors */
139 __u64 sps_rcverrs; /* non-crc rcv packet errors */
140 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
141 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
142 __u64 sps_ctxts; /* number of contexts currently open */
143 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
148 extern struct hfi1_ib_stats hfi1_stats;
149 extern const struct pci_error_handlers hfi1_pci_err_handler;
152 * First-cut criterion for "device is active" is
153 * two thousand dwords combined Tx, Rx traffic per
154 * 5-second interval. SMA packets are 64 dwords,
155 * and occur "a few per second", presumably each way.
157 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
160 * Below contains all data related to a single context (formerly called port).
163 #ifdef CONFIG_DEBUG_FS
164 struct hfi1_opcode_stats_perctx;
167 struct ctxt_eager_bufs {
168 ssize_t size; /* total size of eager buffers */
169 u32 count; /* size of buffers array */
170 u32 numbufs; /* number of buffers allocated */
171 u32 alloced; /* number of rcvarray entries used */
172 u32 rcvtid_size; /* size of each eager rcv tid */
173 u32 threshold; /* head update threshold */
174 struct eager_buffer {
186 struct list_head list;
190 struct hfi1_ctxtdata {
191 /* shadow the ctxt's RcvCtrl register */
193 /* rcvhdrq base, needs mmap before useful */
195 /* kernel virtual address where hdrqtail is updated */
196 volatile __le64 *rcvhdrtail_kvaddr;
198 * Shared page for kernel to signal user processes that send buffers
199 * need disarming. The process should call HFI1_CMD_DISARM_BUFS
200 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
202 unsigned long *user_event_mask;
203 /* when waiting for rcv or pioavail */
204 wait_queue_head_t wait;
205 /* rcvhdrq size (for freeing) */
207 /* number of rcvhdrq entries */
209 /* size of each of the rcvhdrq entries */
211 /* mmap of hdrq, must fit in 44 bits */
212 dma_addr_t rcvhdrq_dma;
213 dma_addr_t rcvhdrqtailaddr_dma;
214 struct ctxt_eager_bufs egrbufs;
215 /* this receive context's assigned PIO ACK send context */
216 struct send_context *sc;
218 /* dynamic receive available interrupt timeout */
219 u32 rcvavail_timeout;
221 * number of opens (including slave sub-contexts) on this instance
222 * (ignoring forks, dup, etc. for now)
226 * how much space to leave at start of eager TID entries for
227 * protocol use, on each TID
229 /* instead of calculating it */
231 /* non-zero if ctxt is being shared. */
233 /* non-zero if ctxt is being shared. */
238 /* number of RcvArray groups for this context. */
239 u32 rcv_array_groups;
240 /* index of first eager TID entry. */
242 /* number of expected TID entries */
244 /* index of first expected TID entry. */
247 struct exp_tid_set tid_group_list;
248 struct exp_tid_set tid_used_list;
249 struct exp_tid_set tid_full_list;
251 /* lock protecting all Expected TID data */
252 struct mutex exp_lock;
253 /* number of pio bufs for this ctxt (all procs, if shared) */
255 /* first pio buffer for this ctxt */
257 /* chip offset of PIO buffers for this ctxt */
259 /* per-context configuration flags */
261 /* per-context event flags for fileops/intr communication */
262 unsigned long event_flags;
263 /* WAIT_RCV that timed out, no interrupt */
265 /* WAIT_PIO that timed out, no interrupt */
267 /* WAIT_RCV already happened, no wait */
269 /* WAIT_PIO already happened, no wait */
271 /* total number of polled urgent packets */
273 /* saved total number of polled urgent packets for poll edge trigger */
275 /* same size as task_struct .comm[], command that opened context */
276 char comm[TASK_COMM_LEN];
277 /* so file ops can get at unit */
278 struct hfi1_devdata *dd;
279 /* so functions that need physical port can get it easily */
280 struct hfi1_pportdata *ppd;
281 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
282 void *subctxt_uregbase;
283 /* An array of pages for the eager receive buffers * N */
284 void *subctxt_rcvegrbuf;
285 /* An array of pages for the eager header queue entries * N */
286 void *subctxt_rcvhdr_base;
287 /* The version of the library which opened this ctxt */
289 /* Bitmask of active slaves */
291 /* Type of packets or conditions we want to poll for */
293 /* receive packet sequence counter */
296 /* ctxt rcvhdrq head offset */
299 /* QPs waiting for context processing */
300 struct list_head qp_wait_list;
301 /* interrupt handling */
302 u64 imask; /* clear interrupt mask */
303 int ireg; /* clear interrupt register */
304 unsigned numa_id; /* numa node of this context */
305 /* verbs stats per CTX */
306 struct hfi1_opcode_stats_perctx *opstats;
308 * This is the kernel thread that will keep making
309 * progress on the user sdma requests behind the scenes.
310 * There is one per context (shared contexts use the master's).
312 struct task_struct *progress;
313 struct list_head sdma_queues;
314 /* protect sdma queues */
315 spinlock_t sdma_qlock;
317 /* Is ASPM interrupt supported for this context */
318 bool aspm_intr_supported;
319 /* ASPM state (enabled/disabled) for this context */
321 /* Timer for re-enabling ASPM if interrupt activity quietens down */
322 struct timer_list aspm_timer;
323 /* Lock to serialize between intr, timer intr and user threads */
324 spinlock_t aspm_lock;
325 /* Is ASPM processing enabled for this context (in intr context) */
326 bool aspm_intr_enable;
327 /* Last interrupt timestamp */
328 ktime_t aspm_ts_last_intr;
329 /* Last timestamp at which we scheduled a timer for this context */
330 ktime_t aspm_ts_timer_sched;
333 * The interrupt handler for a particular receive context can vary
334 * throughout it's lifetime. This is not a lock protected data member so
335 * it must be updated atomically and the prev and new value must always
336 * be valid. Worst case is we process an extra interrupt and up to 64
337 * packets with the wrong interrupt handler.
339 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
343 * Represents a single packet at a high level. Put commonly computed things in
344 * here so we do not have to keep doing them over and over. The rule of thumb is
345 * if something is used one time to derive some value, store that something in
346 * here. If it is used multiple times, then store the result of that derivation
352 struct hfi1_ctxtdata *rcd;
355 struct ib_other_headers *ohdr;
370 struct rvt_sge_state;
373 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
374 * Mostly for MADs that set or query link parameters, also ipath
377 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
378 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
379 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
380 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
381 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
382 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
383 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
384 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
385 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
386 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
387 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
388 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
389 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
390 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
391 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
392 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
393 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
394 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
395 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
396 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
397 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
400 * HFI or Host Link States
402 * These describe the states the driver thinks the logical and physical
403 * states are in. Used as an argument to set_link_state(). Implemented
404 * as bits for easy multi-state checking. The actual state can only be
407 #define __HLS_UP_INIT_BP 0
408 #define __HLS_UP_ARMED_BP 1
409 #define __HLS_UP_ACTIVE_BP 2
410 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
411 #define __HLS_DN_POLL_BP 4
412 #define __HLS_DN_DISABLE_BP 5
413 #define __HLS_DN_OFFLINE_BP 6
414 #define __HLS_VERIFY_CAP_BP 7
415 #define __HLS_GOING_UP_BP 8
416 #define __HLS_GOING_OFFLINE_BP 9
417 #define __HLS_LINK_COOLDOWN_BP 10
419 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
420 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
421 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
422 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
423 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
424 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
425 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
426 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
427 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
428 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
429 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
431 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
432 #define HLS_DOWN ~(HLS_UP)
434 /* use this MTU size if none other is given */
435 #define HFI1_DEFAULT_ACTIVE_MTU 10240
436 /* use this MTU size as the default maximum */
437 #define HFI1_DEFAULT_MAX_MTU 10240
438 /* default partition key */
439 #define DEFAULT_PKEY 0xffff
442 * Possible fabric manager config parameters for fm_{get,set}_table()
444 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
445 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
446 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
447 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
448 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
449 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
452 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
453 * these are bits so they can be combined, e.g.
454 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
456 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
457 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
458 #define HFI1_RCVCTRL_CTXT_ENB 0x04
459 #define HFI1_RCVCTRL_CTXT_DIS 0x08
460 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
461 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
462 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
463 #define HFI1_RCVCTRL_PKEY_DIS 0x80
464 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
465 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
466 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
467 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
468 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
469 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
470 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
471 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
473 /* partition enforcement flags */
474 #define HFI1_PART_ENFORCE_IN 0x1
475 #define HFI1_PART_ENFORCE_OUT 0x2
477 /* how often we check for synthetic counter wrap around */
478 #define SYNTH_CNT_TIME 2
481 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
482 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
483 #define CNTR_DISABLED 0x2 /* Disable this counter */
484 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
485 #define CNTR_VL 0x8 /* Per VL counter */
486 #define CNTR_SDMA 0x10
487 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
488 #define CNTR_MODE_W 0x0
489 #define CNTR_MODE_R 0x1
491 /* VLs Supported/Operational */
492 #define HFI1_MIN_VLS_SUPPORTED 1
493 #define HFI1_MAX_VLS_SUPPORTED 8
495 #define HFI1_GUIDS_PER_PORT 5
496 #define HFI1_PORT_GUID_INDEX 0
498 static inline void incr_cntr64(u64 *cntr)
500 if (*cntr < (u64)-1LL)
504 static inline void incr_cntr32(u32 *cntr)
506 if (*cntr < (u32)-1LL)
510 #define MAX_NAME_SIZE 64
511 struct hfi1_msix_entry {
513 struct msix_entry msix;
515 char name[MAX_NAME_SIZE];
517 struct irq_affinity_notify notify;
520 /* per-SL CCA information */
522 struct hrtimer hrtimer;
523 struct hfi1_pportdata *ppd; /* read-only */
524 int sl; /* read-only */
525 u16 ccti; /* read/write - current value of CCTI */
528 struct link_down_reason {
530 * SMA-facing value. Should be set from .latest when
531 * HLS_UP_* -> HLS_DN_* transition actually occurs.
543 struct vl_arb_cache {
544 /* protect vl arb cache */
546 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
550 * The structure below encapsulates data relevant to a physical IB Port.
551 * Current chips support only one such port, but the separation
552 * clarifies things a bit. Note that to conform to IB conventions,
553 * port-numbers are one-based. The first or only port is port1.
555 struct hfi1_pportdata {
556 struct hfi1_ibport ibport_data;
558 struct hfi1_devdata *dd;
559 struct kobject pport_cc_kobj;
560 struct kobject sc2vl_kobj;
561 struct kobject sl2sc_kobj;
562 struct kobject vl2mtu_kobj;
565 struct qsfp_data qsfp_info;
566 /* Values for SI tuning of SerDes */
576 /* GUIDs for this interface, in host order, guids[0] is a port guid */
577 u64 guids[HFI1_GUIDS_PER_PORT];
579 /* GUID for peer interface, in host order */
582 /* up or down physical link state */
586 * this address is mapped read-only into user processes so they can
587 * get status cheaply, whenever they want. One qword of status per port
591 /* SendDMA related entries */
593 struct workqueue_struct *hfi1_wq;
595 /* move out of interrupt context */
596 struct work_struct link_vc_work;
597 struct work_struct link_up_work;
598 struct work_struct link_down_work;
599 struct work_struct sma_message_work;
600 struct work_struct freeze_work;
601 struct work_struct link_downgrade_work;
602 struct work_struct link_bounce_work;
603 struct delayed_work start_link_work;
604 /* host link state variables */
605 struct mutex hls_lock;
608 u32 lstate; /* logical link state */
610 /* these are the "32 bit" regs */
612 u32 ibmtu; /* The MTU programmed for this unit */
614 * Current max size IB packet (in bytes) including IB headers, that
615 * we can send. Changes when ibmtu changes.
618 u32 current_egress_rate; /* units [10^6 bits/sec] */
619 /* LID programmed for this instance */
621 /* list of pkeys programmed; 0 if not set */
622 u16 pkeys[MAX_PKEY_VALUES];
623 u16 link_width_supported;
624 u16 link_width_downgrade_supported;
625 u16 link_speed_supported;
626 u16 link_width_enabled;
627 u16 link_width_downgrade_enabled;
628 u16 link_speed_enabled;
629 u16 link_width_active;
630 u16 link_width_downgrade_tx_active;
631 u16 link_width_downgrade_rx_active;
632 u16 link_speed_active;
635 u8 actual_vls_operational;
636 /* LID mask control */
638 /* Rx Polarity inversion (compensate for ~tx on partner) */
641 u8 hw_pidx; /* physical port index */
642 u8 port; /* IB port number and index into dd->pports - 1 */
643 /* type of neighbor node */
646 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
647 u8 neighbor_port_number;
648 u8 is_sm_config_started;
649 u8 offline_disabled_reason;
650 u8 is_active_optimize_enabled;
651 u8 driver_link_ready; /* driver ready for active link */
652 u8 link_enabled; /* link enabled? */
654 u8 local_tx_rate; /* rate given to 8051 firmware */
655 u8 last_pstate; /* info only */
658 /* placeholders for IB MAD packet settings */
659 u8 overrun_threshold;
660 u8 phy_error_threshold;
662 /* Used to override LED behavior for things like maintenance beaconing*/
664 * Alternates per phase of blink
665 * [0] holds LED off duration, [1] holds LED on duration
667 unsigned long led_override_vals[2];
668 u8 led_override_phase; /* LSB picks from vals[] */
669 atomic_t led_override_timer_active;
670 /* Used to flash LEDs in override mode */
671 struct timer_list led_override_timer;
677 * cca_timer_lock protects access to the per-SL cca_timer
678 * structures (specifically the ccti member).
680 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
681 struct cca_timer cca_timer[OPA_MAX_SLS];
683 /* List of congestion control table entries */
684 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
686 /* congestion entries, each entry corresponding to a SL */
687 struct opa_congestion_setting_entry_shadow
688 congestion_entries[OPA_MAX_SLS];
691 * cc_state_lock protects (write) access to the per-port
694 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
696 struct cc_state __rcu *cc_state;
698 /* Total number of congestion control table entries */
701 /* Bit map identifying service level */
702 u32 cc_sl_control_map;
704 /* CA's max number of 64 entry units in the congestion control table */
705 u8 cc_max_table_entries;
708 * begin congestion log related entries
709 * cc_log_lock protects all congestion log related data
711 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
712 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
713 u16 threshold_event_counter;
714 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
715 int cc_log_idx; /* index for logging events */
716 int cc_mad_idx; /* index for reporting events */
717 /* end congestion log related entries */
719 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
721 /* port relative counter buffer */
723 /* port relative synthetic counter buffer */
725 /* port_xmit_discards are synthesized from different egress errors */
726 u64 port_xmit_discards;
727 u64 port_xmit_discards_vl[C_VL_COUNT];
728 u64 port_xmit_constraint_errors;
729 u64 port_rcv_constraint_errors;
730 /* count of 'link_err' interrupts from DC */
732 /* number of times link retrained successfully */
734 /* number of times a link unknown frame was reported */
735 u64 unknown_frame_count;
736 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
737 u16 port_ltp_crc_mode;
738 /* port_crc_mode_enabled is the crc we support */
739 u8 port_crc_mode_enabled;
740 /* mgmt_allowed is also returned in 'portinfo' MADs */
742 u8 part_enforce; /* partition enforcement flags */
743 struct link_down_reason local_link_down_reason;
744 struct link_down_reason neigh_link_down_reason;
745 /* Value to be sent to link peer on LinkDown .*/
746 u8 remote_link_down_reason;
747 /* Error events that will cause a port bounce. */
748 u32 port_error_action;
749 struct work_struct linkstate_active_work;
750 /* Does this port need to prescan for FECNs */
754 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
756 typedef void (*opcode_handler)(struct hfi1_packet *packet);
758 /* return values for the RHF receive functions */
759 #define RHF_RCV_CONTINUE 0 /* keep going */
760 #define RHF_RCV_DONE 1 /* stop, this packet processed */
761 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
763 struct rcv_array_data {
771 struct send_context *sc;
774 /* 16 to directly index */
775 #define PER_VL_SEND_CONTEXTS 16
777 struct err_info_rcvport {
783 struct err_info_constraint {
790 unsigned int curr; /* current temperature */
791 unsigned int lo_lim; /* low temperature limit */
792 unsigned int hi_lim; /* high temperature limit */
793 unsigned int crit_lim; /* critical temperature limit */
794 u8 triggers; /* temperature triggers */
797 struct hfi1_i2c_bus {
798 struct hfi1_devdata *controlling_dd; /* current controlling device */
799 struct i2c_adapter adapter; /* bus details */
800 struct i2c_algo_bit_data algo; /* bus algorithm details */
801 int num; /* bus number, 0 or 1 */
804 /* common data between shared ASIC HFIs */
805 struct hfi1_asic_data {
806 struct hfi1_devdata *dds[2]; /* back pointers */
807 struct mutex asic_resource_mutex;
808 struct hfi1_i2c_bus *i2c_bus0;
809 struct hfi1_i2c_bus *i2c_bus1;
812 /* device data struct now contains only "general per-device" info.
813 * fields related to a physical IB port are in a hfi1_pportdata struct.
818 #define BOARD_VERS_MAX 96 /* how long the version string can be */
819 #define SERIAL_MAX 16 /* length of the serial number */
821 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
822 struct hfi1_devdata {
823 struct hfi1_ibdev verbs_dev; /* must be first */
824 struct list_head list;
825 /* pointers to related structs for this device */
826 /* pci access data structure */
827 struct pci_dev *pcidev;
828 struct cdev user_cdev;
829 struct cdev diag_cdev;
831 struct device *user_device;
832 struct device *diag_device;
833 struct device *ui_device;
835 /* mem-mapped pointer to base of chip regs */
836 u8 __iomem *kregbase;
837 /* end of mem-mapped chip space excluding sendbuf and user regs */
839 /* physical address of chip for io_remap, etc. */
840 resource_size_t physaddr;
841 /* Per VL data. Enough for all VLs but not all elements are set/used. */
842 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
843 /* send context data */
844 struct send_context_info *send_contexts;
845 /* map hardware send contexts to software index */
847 /* spinlock for allocating and releasing send context resources */
849 /* lock for pio_map */
850 spinlock_t pio_map_lock;
851 /* Send Context initialization lock. */
852 spinlock_t sc_init_lock;
853 /* lock for sdma_map */
854 spinlock_t sde_map_lock;
855 /* array of kernel send contexts */
856 struct send_context **kernel_send_context;
857 /* array of vl maps */
858 struct pio_vl_map __rcu *pio_map;
859 /* default flags to last descriptor */
862 /* fields common to all SDMA engines */
864 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
865 dma_addr_t sdma_heads_phys;
866 void *sdma_pad_dma; /* DMA'ed by chip */
867 dma_addr_t sdma_pad_phys;
868 /* for deallocation */
869 size_t sdma_heads_size;
870 /* number from the chip */
871 u32 chip_sdma_engines;
874 /* array of engines sized by num_sdma */
875 struct sdma_engine *per_sdma;
876 /* array of vl maps */
877 struct sdma_vl_map __rcu *sdma_map;
878 /* SPC freeze waitqueue and variable */
879 wait_queue_head_t sdma_unfreeze_wq;
880 atomic_t sdma_unfreeze_count;
882 u32 lcb_access_count; /* count of LCB users */
884 /* common data between shared ASIC HFIs in this OS */
885 struct hfi1_asic_data *asic_data;
887 /* mem-mapped pointer to base of PIO buffers */
888 void __iomem *piobase;
890 * write-combining mem-mapped pointer to base of RcvArray
893 void __iomem *rcvarray_wc;
895 * credit return base - a per-NUMA range of DMA address that
896 * the chip will use to update the per-context free counter
898 struct credit_return_base *cr_base;
900 /* send context numbers and sizes for each type */
901 struct sc_config_sizes sc_sizes[SC_MAX];
903 char *boardname; /* human readable board info */
910 u64 __percpu *send_schedule;
911 /* number of receive contexts in use by the driver */
912 u32 num_rcv_contexts;
913 /* number of pio send contexts in use by the driver */
914 u32 num_send_contexts;
916 * number of ctxts available for PSM open
919 /* total number of available user/PSM contexts */
920 u32 num_user_contexts;
921 /* base receive interrupt timeout, in CSR units */
922 u32 rcv_intr_timeout_csr;
924 u32 freezelen; /* max length of freezemsg */
925 u64 __iomem *egrtidbase;
926 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
927 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
928 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
929 spinlock_t uctxt_lock; /* rcd and user context changes */
930 /* exclusive access to 8051 */
931 spinlock_t dc8051_lock;
932 /* exclusive access to 8051 memory */
933 spinlock_t dc8051_memlock;
934 int dc8051_timed_out; /* remember if the 8051 timed out */
936 * A page that will hold event notification bitmaps for all
937 * contexts. This page will be mapped into all processes.
939 unsigned long *events;
941 * per unit status, see also portdata statusp
942 * mapped read-only into user processes so they can get unit and
943 * IB link status cheaply
945 struct hfi1_status *status;
947 /* revision register shadow */
949 /* Base GUID for device (network order) */
952 /* these are the "32 bit" regs */
954 /* value we put in kr_rcvhdrsize */
956 /* number of receive contexts the chip supports */
957 u32 chip_rcv_contexts;
958 /* number of receive array entries */
959 u32 chip_rcv_array_count;
960 /* number of PIO send contexts the chip supports */
961 u32 chip_send_contexts;
962 /* number of bytes in the PIO memory buffer */
963 u32 chip_pio_mem_size;
964 /* number of bytes in the SDMA memory buffer */
965 u32 chip_sdma_mem_size;
967 /* size of each rcvegrbuffer */
970 u16 rcvegrbufsize_shift;
971 /* both sides of the PCIe link are gen3 capable */
972 u8 link_gen3_capable;
973 /* default link down value (poll/sleep) */
975 /* localbus width (1, 2,4,8,16,32) from config space */
977 /* localbus speed in MHz */
979 int unit; /* unit # of this chip */
980 int node; /* home node of this chip */
982 /* save these PCI fields to restore after a reset */
995 * ASCII serial number, from flash, large enough for original
996 * all digit strings, and longer serial number format
998 u8 serial[SERIAL_MAX];
999 /* human readable board version */
1000 u8 boardversion[BOARD_VERS_MAX];
1001 u8 lbus_info[32]; /* human readable localbus info */
1002 /* chip major rev, from CceRevision */
1004 /* chip minor rev, from CceRevision */
1008 /* implementation code */
1010 /* vAU of this device */
1012 /* vCU of this device */
1014 /* link credits of this device */
1016 /* initial vl15 credits to use */
1019 /* Misc small ints */
1023 u16 irev; /* implementation revision */
1024 u16 dc8051_ver; /* 8051 firmware version */
1026 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1027 struct platform_config platform_config;
1028 struct platform_config_cache pcfg_cache;
1030 struct diag_client *diag_client;
1032 /* MSI-X information */
1033 struct hfi1_msix_entry *msix_entries;
1034 u32 num_msix_entries;
1036 /* INTx information */
1037 u32 requested_intx_irq; /* did we request one? */
1038 char intx_name[MAX_NAME_SIZE]; /* INTx name */
1040 /* general interrupt: mask of handled interrupts */
1041 u64 gi_mask[CCE_NUM_INT_CSRS];
1043 struct rcv_array_data rcv_entries;
1045 /* cycle length of PS* counters in HW (in picoseconds) */
1046 u16 psxmitwait_check_rate;
1049 * 64 bit synthetic counters
1051 struct timer_list synth_stats_timer;
1057 size_t cntrnameslen;
1063 * remembered values for synthetic counters
1072 char *portcntrnames;
1073 size_t portcntrnameslen;
1075 struct err_info_rcvport err_info_rcvport;
1076 struct err_info_constraint err_info_rcv_constraint;
1077 struct err_info_constraint err_info_xmit_constraint;
1079 atomic_t drop_packet;
1081 u8 err_info_uncorrectable;
1082 u8 err_info_fmconfig;
1085 * Software counters for the status bits defined by the
1086 * associated error status registers
1088 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1089 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1090 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1091 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1092 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1093 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1094 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1096 /* Software counter that spans all contexts */
1097 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1098 /* Software counter that spans all DMA engines */
1099 u64 sw_send_dma_eng_err_status_cnt[
1100 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1101 /* Software counter that aggregates all cce_err_status errors */
1102 u64 sw_cce_err_status_aggregate;
1103 /* Software counter that aggregates all bypass packet rcv errors */
1104 u64 sw_rcv_bypass_packet_errors;
1105 /* receive interrupt function */
1106 rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1108 /* Save the enabled LCB error bits */
1112 * Capability to have different send engines simply by changing a
1115 send_routine process_pio_send ____cacheline_aligned_in_smp;
1116 send_routine process_dma_send;
1117 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1118 u64 pbc, const void *from, size_t count);
1119 /* hfi1_pportdata, points to array of (physical) port-specific
1120 * data structs, indexed by pidx (0..n-1)
1122 struct hfi1_pportdata *pport;
1123 /* receive context data */
1124 struct hfi1_ctxtdata **rcd;
1125 u64 __percpu *int_counter;
1126 /* device (not port) flags, basically device capabilities */
1128 /* Number of physical ports available */
1130 /* Lowest context number which can be used by user processes */
1132 /* adding a new field here would make it part of this cacheline */
1134 /* seqlock for sc2vl */
1135 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1137 /* receive interrupt functions */
1138 rhf_rcv_function_ptr *rhf_rcv_function_map;
1139 u64 __percpu *rcv_limit;
1140 u16 rhf_offset; /* offset of RHF within receive header entry */
1141 /* adding a new field here would make it part of this cacheline */
1143 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1149 /* Timer and counter used to detect RcvBufOvflCnt changes */
1150 struct timer_list rcverr_timer;
1152 wait_queue_head_t event_queue;
1154 /* receive context tail dummy address */
1155 __le64 *rcvhdrtail_dummy_kvaddr;
1156 dma_addr_t rcvhdrtail_dummy_dma;
1159 /* Serialize ASPM enable/disable between multiple verbs contexts */
1160 spinlock_t aspm_lock;
1161 /* Number of verbs contexts which have disabled ASPM */
1162 atomic_t aspm_disabled_cnt;
1163 /* Keeps track of user space clients */
1164 atomic_t user_refcount;
1165 /* Used to wait for outstanding user space clients before dev removal */
1166 struct completion user_comp;
1168 bool eprom_available; /* true if EPROM is available for this device */
1169 bool aspm_supported; /* Does HW support ASPM */
1170 bool aspm_enabled; /* ASPM state: enabled/disabled */
1171 struct rhashtable sdma_rht;
1173 struct kobject kobj;
1176 /* 8051 firmware version helper */
1177 #define dc8051_ver(a, b) ((a) << 8 | (b))
1178 #define dc8051_ver_maj(a) ((a & 0xff00) >> 8)
1179 #define dc8051_ver_min(a) (a & 0x00ff)
1181 /* f_put_tid types */
1182 #define PT_EXPECTED 0
1184 #define PT_INVALID 2
1188 struct mmu_rb_handler;
1190 /* Private data for file operations */
1191 struct hfi1_filedata {
1192 struct hfi1_ctxtdata *uctxt;
1194 struct hfi1_user_sdma_comp_q *cq;
1195 struct hfi1_user_sdma_pkt_q *pq;
1196 /* for cpu affinity; -1 if none */
1199 struct mmu_rb_handler *handler;
1200 struct tid_rb_node **entry_to_rb;
1201 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1205 u32 invalid_tid_idx;
1206 /* protect invalid_tids array and invalid_tid_idx */
1207 spinlock_t invalid_lock;
1208 struct mm_struct *mm;
1211 extern struct list_head hfi1_dev_list;
1212 extern spinlock_t hfi1_devs_lock;
1213 struct hfi1_devdata *hfi1_lookup(int unit);
1214 extern u32 hfi1_cpulist_count;
1215 extern unsigned long *hfi1_cpulist;
1217 int hfi1_init(struct hfi1_devdata *, int);
1218 int hfi1_count_units(int *npresentp, int *nupp);
1219 int hfi1_count_active_units(void);
1221 int hfi1_diag_add(struct hfi1_devdata *);
1222 void hfi1_diag_remove(struct hfi1_devdata *);
1223 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1225 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1227 int hfi1_create_rcvhdrq(struct hfi1_devdata *, struct hfi1_ctxtdata *);
1228 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *);
1229 int hfi1_create_ctxts(struct hfi1_devdata *dd);
1230 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *, u32, int);
1231 void hfi1_init_pportdata(struct pci_dev *, struct hfi1_pportdata *,
1232 struct hfi1_devdata *, u8, u8);
1233 void hfi1_free_ctxtdata(struct hfi1_devdata *, struct hfi1_ctxtdata *);
1235 int handle_receive_interrupt(struct hfi1_ctxtdata *, int);
1236 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *, int);
1237 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *, int);
1238 void set_all_slowpath(struct hfi1_devdata *dd);
1240 extern const struct pci_device_id hfi1_pci_tbl[];
1242 /* receive packet handler dispositions */
1243 #define RCV_PKT_OK 0x0 /* keep going */
1244 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1245 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1247 /* calculate the current RHF address */
1248 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1250 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset;
1253 int hfi1_reset_device(int);
1255 /* return the driver's idea of the logical OPA port state */
1256 static inline u32 driver_lstate(struct hfi1_pportdata *ppd)
1258 return ppd->lstate; /* use the cached value */
1261 void receive_interrupt_work(struct work_struct *work);
1263 /* extract service channel from header and rhf */
1264 static inline int hdr2sc(struct ib_header *hdr, u64 rhf)
1266 return ((be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf) |
1267 ((!!(rhf_dc_info(rhf))) << 4);
1270 #define HFI1_JKEY_WIDTH 16
1271 #define HFI1_JKEY_MASK (BIT(16) - 1)
1272 #define HFI1_ADMIN_JKEY_RANGE 32
1275 * J_KEYs are split and allocated in the following groups:
1276 * 0 - 31 - users with administrator privileges
1277 * 32 - 63 - kernel protocols using KDETH packets
1278 * 64 - 65535 - all other users using KDETH packets
1280 static inline u16 generate_jkey(kuid_t uid)
1282 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1284 if (capable(CAP_SYS_ADMIN))
1285 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1287 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1293 * active_egress_rate
1295 * returns the active egress rate in units of [10^6 bits/sec]
1297 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1299 u16 link_speed = ppd->link_speed_active;
1300 u16 link_width = ppd->link_width_active;
1303 if (link_speed == OPA_LINK_SPEED_25G)
1304 egress_rate = 25000;
1305 else /* assume OPA_LINK_SPEED_12_5G */
1306 egress_rate = 12500;
1308 switch (link_width) {
1309 case OPA_LINK_WIDTH_4X:
1312 case OPA_LINK_WIDTH_3X:
1315 case OPA_LINK_WIDTH_2X:
1319 /* assume IB_WIDTH_1X */
1329 * Returns the number of 'fabric clock cycles' to egress a packet
1330 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1331 * rate is (approximately) 805 MHz, the units of the returned value
1334 static inline u32 egress_cycles(u32 len, u32 rate)
1341 * (length) [bits] / (rate) [bits/sec]
1342 * ---------------------------------------------------
1343 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1346 cycles = len * 8; /* bits */
1353 void set_link_ipg(struct hfi1_pportdata *ppd);
1354 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn,
1355 u32 rqpn, u8 svc_type);
1356 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1357 u32 pkey, u32 slid, u32 dlid, u8 sc5,
1358 const struct ib_grh *old_grh);
1359 #define PKEY_CHECK_INVALID -1
1360 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth,
1361 u8 sc5, int8_t s_pkey_index);
1363 #define PACKET_EGRESS_TIMEOUT 350
1364 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1366 /* Pause at least 1us, to ensure chip returns all credits */
1367 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1369 udelay(usec ? usec : 1);
1373 * sc_to_vlt() reverse lookup sc to vl
1377 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1382 if (sc5 >= OPA_MAX_SCS)
1386 seq = read_seqbegin(&dd->sc2vl_lock);
1387 rval = *(((u8 *)dd->sc2vl) + sc5);
1388 } while (read_seqretry(&dd->sc2vl_lock, seq));
1393 #define PKEY_MEMBER_MASK 0x8000
1394 #define PKEY_LOW_15_MASK 0x7fff
1397 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1398 * being an entry from the ingress partition key table), return 0
1399 * otherwise. Use the matching criteria for ingress partition keys
1400 * specified in the OPAv1 spec., section 9.10.14.
1402 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1404 u16 mkey = pkey & PKEY_LOW_15_MASK;
1405 u16 ment = ent & PKEY_LOW_15_MASK;
1409 * If pkey[15] is clear (limited partition member),
1410 * is bit 15 in the corresponding table element
1411 * clear (limited member)?
1413 if (!(pkey & PKEY_MEMBER_MASK))
1414 return !!(ent & PKEY_MEMBER_MASK);
1421 * ingress_pkey_table_search - search the entire pkey table for
1422 * an entry which matches 'pkey'. return 0 if a match is found,
1425 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1429 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1430 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1437 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1438 * i.e., increment port_rcv_constraint_errors for the port, and record
1439 * the 'error info' for this failure.
1441 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1444 struct hfi1_devdata *dd = ppd->dd;
1446 incr_cntr64(&ppd->port_rcv_constraint_errors);
1447 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1448 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1449 dd->err_info_rcv_constraint.slid = slid;
1450 dd->err_info_rcv_constraint.pkey = pkey;
1455 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1456 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1457 * is a hint as to the best place in the partition key table to begin
1458 * searching. This function should not be called on the data path because
1459 * of performance reasons. On datapath pkey check is expected to be done
1460 * by HW and rcv_pkey_check function should be called instead.
1462 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1463 u8 sc5, u8 idx, u16 slid)
1465 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1468 /* If SC15, pkey[0:14] must be 0x7fff */
1469 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1472 /* Is the pkey = 0x0, or 0x8000? */
1473 if ((pkey & PKEY_LOW_15_MASK) == 0)
1476 /* The most likely matching pkey has index 'idx' */
1477 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1480 /* no match - try the whole table */
1481 if (!ingress_pkey_table_search(ppd, pkey))
1485 ingress_pkey_table_fail(ppd, pkey, slid);
1490 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1491 * otherwise. It only ensures pkey is vlid for QP0. This function
1492 * should be called on the data path instead of ingress_pkey_check
1493 * as on data path, pkey check is done by HW (except for QP0).
1495 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1498 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1501 /* If SC15, pkey[0:14] must be 0x7fff */
1502 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1507 ingress_pkey_table_fail(ppd, pkey, slid);
1513 /* MTU enumeration, 256-4k match IB */
1515 #define OPA_MTU_256 1
1516 #define OPA_MTU_512 2
1517 #define OPA_MTU_1024 3
1518 #define OPA_MTU_2048 4
1519 #define OPA_MTU_4096 5
1521 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1522 int mtu_to_enum(u32 mtu, int default_if_bad);
1523 u16 enum_to_mtu(int);
1524 static inline int valid_ib_mtu(unsigned int mtu)
1526 return mtu == 256 || mtu == 512 ||
1527 mtu == 1024 || mtu == 2048 ||
1531 static inline int valid_opa_max_mtu(unsigned int mtu)
1533 return mtu >= 2048 &&
1534 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1537 int set_mtu(struct hfi1_pportdata *);
1539 int hfi1_set_lid(struct hfi1_pportdata *, u32, u8);
1540 void hfi1_disable_after_error(struct hfi1_devdata *);
1541 int hfi1_set_uevent_bits(struct hfi1_pportdata *, const int);
1542 int hfi1_rcvbuf_validate(u32, u8, u16 *);
1544 int fm_get_table(struct hfi1_pportdata *, int, void *);
1545 int fm_set_table(struct hfi1_pportdata *, int, void *);
1547 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf);
1548 void reset_link_credits(struct hfi1_devdata *dd);
1549 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1551 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1553 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1558 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1560 return container_of(dev, struct hfi1_devdata, verbs_dev);
1563 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1565 return dd_from_dev(to_idev(ibdev));
1568 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1570 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1573 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1575 return container_of(rdi, struct hfi1_ibdev, rdi);
1578 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1580 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1581 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1583 WARN_ON(pidx >= dd->num_pports);
1584 return &dd->pport[pidx].ibport_data;
1587 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1589 return &rcd->ppd->ibport_data;
1592 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1594 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt,
1597 struct ib_other_headers *ohdr = pkt->ohdr;
1600 bth1 = be32_to_cpu(ohdr->bth[1]);
1601 if (unlikely(bth1 & (HFI1_BECN_SMASK | HFI1_FECN_SMASK))) {
1602 hfi1_process_ecn_slowpath(qp, pkt, do_cnp);
1603 return bth1 & HFI1_FECN_SMASK;
1609 * Return the indexed PKEY from the port PKEY table.
1611 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1613 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1616 if (index >= ARRAY_SIZE(ppd->pkeys))
1619 ret = ppd->pkeys[index];
1625 * Return the indexed GUID from the port GUIDs table.
1627 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1629 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1631 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1632 return cpu_to_be64(ppd->guids[index]);
1636 * Called by readers of cc_state only, must call under rcu_read_lock().
1638 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1640 return rcu_dereference(ppd->cc_state);
1644 * Called by writers of cc_state only, must call under cc_state_lock.
1647 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1649 return rcu_dereference_protected(ppd->cc_state,
1650 lockdep_is_held(&ppd->cc_state_lock));
1654 * values for dd->flags (_device_ related flags)
1656 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1657 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1658 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1659 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1660 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1661 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1663 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1664 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1666 /* ctxt_flag bit offsets */
1667 /* context has been setup */
1668 #define HFI1_CTXT_SETUP_DONE 1
1669 /* waiting for a packet to arrive */
1670 #define HFI1_CTXT_WAITING_RCV 2
1671 /* master has not finished initializing */
1672 #define HFI1_CTXT_MASTER_UNINIT 4
1673 /* waiting for an urgent packet to arrive */
1674 #define HFI1_CTXT_WAITING_URG 5
1676 /* free up any allocated data at closes */
1677 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *,
1678 const struct pci_device_id *);
1679 void hfi1_free_devdata(struct hfi1_devdata *);
1680 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1682 /* LED beaconing functions */
1683 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1684 unsigned int timeoff);
1685 void shutdown_led_override(struct hfi1_pportdata *ppd);
1687 #define HFI1_CREDIT_RETURN_RATE (100)
1690 * The number of words for the KDETH protocol field. If this is
1691 * larger then the actual field used, then part of the payload
1692 * will be in the header.
1694 * Optimally, we want this sized so that a typical case will
1695 * use full cache lines. The typical local KDETH header would
1706 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1708 #define DEFAULT_RCVHDRSIZE 9
1711 * Maximal header byte count:
1722 * We also want to maintain a cache line alignment to assist DMA'ing
1723 * of the header bytes. Round up to a good size.
1725 #define DEFAULT_RCVHDR_ENTSIZE 32
1727 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1728 u32 nlocked, u32 npages);
1729 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1730 size_t npages, bool writable, struct page **pages);
1731 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1732 size_t npages, bool dirty);
1734 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1736 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1739 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1742 * volatile because it's a DMA target from the chip, routine is
1743 * inlined, and don't want register caching or reordering.
1745 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1752 extern const char ib_hfi1_version[];
1754 int hfi1_device_create(struct hfi1_devdata *);
1755 void hfi1_device_remove(struct hfi1_devdata *);
1757 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1758 struct kobject *kobj);
1759 int hfi1_verbs_register_sysfs(struct hfi1_devdata *);
1760 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *);
1761 /* Hook for sysfs read of QSFP */
1762 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1764 int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *);
1765 void hfi1_pcie_cleanup(struct pci_dev *);
1766 int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *);
1767 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1768 void hfi1_pcie_flr(struct hfi1_devdata *);
1769 int pcie_speeds(struct hfi1_devdata *);
1770 void request_msix(struct hfi1_devdata *, u32 *, struct hfi1_msix_entry *);
1771 void hfi1_enable_intx(struct pci_dev *);
1772 void restore_pci_variables(struct hfi1_devdata *dd);
1773 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
1774 int parse_platform_config(struct hfi1_devdata *dd);
1775 int get_platform_config_field(struct hfi1_devdata *dd,
1776 enum platform_config_table_type_encoding
1777 table_type, int table_index, int field_index,
1778 u32 *data, u32 len);
1780 const char *get_unit_name(int unit);
1781 const char *get_card_name(struct rvt_dev_info *rdi);
1782 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
1785 * Flush write combining store buffers (if present) and perform a write
1788 static inline void flush_wc(void)
1790 asm volatile("sfence" : : : "memory");
1793 void handle_eflags(struct hfi1_packet *packet);
1794 int process_receive_ib(struct hfi1_packet *packet);
1795 int process_receive_bypass(struct hfi1_packet *packet);
1796 int process_receive_error(struct hfi1_packet *packet);
1797 int kdeth_process_expected(struct hfi1_packet *packet);
1798 int kdeth_process_eager(struct hfi1_packet *packet);
1799 int process_receive_invalid(struct hfi1_packet *packet);
1801 void update_sge(struct rvt_sge_state *ss, u32 length);
1803 /* global module parameter variables */
1804 extern unsigned int hfi1_max_mtu;
1805 extern unsigned int hfi1_cu;
1806 extern unsigned int user_credit_return_threshold;
1807 extern int num_user_contexts;
1808 extern unsigned long n_krcvqs;
1809 extern uint krcvqs[];
1810 extern int krcvqsset;
1811 extern uint kdeth_qp;
1812 extern uint loopback;
1813 extern uint quick_linkup;
1814 extern uint rcv_intr_timeout;
1815 extern uint rcv_intr_count;
1816 extern uint rcv_intr_dynamic;
1817 extern ushort link_crc_mask;
1819 extern struct mutex hfi1_mutex;
1821 /* Number of seconds before our card status check... */
1822 #define STATUS_TIMEOUT 60
1824 #define DRIVER_NAME "hfi1"
1825 #define HFI1_USER_MINOR_BASE 0
1826 #define HFI1_TRACE_MINOR 127
1827 #define HFI1_NMINORS 255
1829 #define PCI_VENDOR_ID_INTEL 0x8086
1830 #define PCI_DEVICE_ID_INTEL0 0x24f0
1831 #define PCI_DEVICE_ID_INTEL1 0x24f1
1833 #define HFI1_PKT_USER_SC_INTEGRITY \
1834 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
1835 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
1836 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
1837 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
1839 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
1840 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
1842 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
1845 u64 base_sc_integrity;
1847 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
1848 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
1852 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1853 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1854 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1855 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1856 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1857 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
1858 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1859 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1860 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1861 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
1862 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1863 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1864 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
1865 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
1866 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
1867 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1869 if (ctxt_type == SC_USER)
1870 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY;
1872 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
1874 /* turn on send-side job key checks if !A0 */
1876 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1878 return base_sc_integrity;
1881 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
1883 u64 base_sdma_integrity;
1885 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
1886 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
1889 base_sdma_integrity =
1890 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1891 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1892 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1893 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1894 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1895 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1896 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1897 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
1898 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1899 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1900 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
1901 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
1902 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
1903 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1905 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
1906 base_sdma_integrity |=
1907 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
1909 /* turn on send-side job key checks if !A0 */
1911 base_sdma_integrity |=
1912 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1914 return base_sdma_integrity;
1918 * hfi1_early_err is used (only!) to print early errors before devdata is
1919 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1920 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
1921 * the same as dd_dev_err, but is used when the message really needs
1922 * the IB port# to be definitive as to what's happening..
1924 #define hfi1_early_err(dev, fmt, ...) \
1925 dev_err(dev, fmt, ##__VA_ARGS__)
1927 #define hfi1_early_info(dev, fmt, ...) \
1928 dev_info(dev, fmt, ##__VA_ARGS__)
1930 #define dd_dev_emerg(dd, fmt, ...) \
1931 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
1932 get_unit_name((dd)->unit), ##__VA_ARGS__)
1933 #define dd_dev_err(dd, fmt, ...) \
1934 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1935 get_unit_name((dd)->unit), ##__VA_ARGS__)
1936 #define dd_dev_warn(dd, fmt, ...) \
1937 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1938 get_unit_name((dd)->unit), ##__VA_ARGS__)
1940 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
1941 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
1942 get_unit_name((dd)->unit), ##__VA_ARGS__)
1944 #define dd_dev_info(dd, fmt, ...) \
1945 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
1946 get_unit_name((dd)->unit), ##__VA_ARGS__)
1948 #define dd_dev_dbg(dd, fmt, ...) \
1949 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
1950 get_unit_name((dd)->unit), ##__VA_ARGS__)
1952 #define hfi1_dev_porterr(dd, port, fmt, ...) \
1953 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
1954 get_unit_name((dd)->unit), (port), ##__VA_ARGS__)
1957 * this is used for formatting hw error messages...
1959 struct hfi1_hwerror_msgs {
1966 void hfi1_format_hwerrors(u64 hwerrs,
1967 const struct hfi1_hwerror_msgs *hwerrmsgs,
1968 size_t nhwerrmsgs, char *msg, size_t lmsg);
1970 #define USER_OPCODE_CHECK_VAL 0xC0
1971 #define USER_OPCODE_CHECK_MASK 0xC0
1972 #define OPCODE_CHECK_VAL_DISABLED 0x0
1973 #define OPCODE_CHECK_MASK_DISABLED 0x0
1975 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
1977 struct hfi1_pportdata *ppd;
1980 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
1981 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
1982 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
1984 ppd = (struct hfi1_pportdata *)(dd + 1);
1985 for (i = 0; i < dd->num_pports; i++, ppd++) {
1986 ppd->ibport_data.rvp.z_rc_acks =
1987 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
1988 ppd->ibport_data.rvp.z_rc_qacks =
1989 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
1993 /* Control LED state */
1994 static inline void setextled(struct hfi1_devdata *dd, u32 on)
1997 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
1999 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2002 /* return the i2c resource given the target */
2003 static inline u32 i2c_target(u32 target)
2005 return target ? CR_I2C2 : CR_I2C1;
2008 /* return the i2c chain chip resource that this HFI uses for QSFP */
2009 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2011 return i2c_target(dd->hfi1_id);
2014 /* Is this device integrated or discrete? */
2015 static inline bool is_integrated(struct hfi1_devdata *dd)
2017 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2020 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2022 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2023 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2025 #define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype }
2026 #define show_packettype(etype) \
2027 __print_symbolic(etype, \
2028 packettype_name(EXPECTED), \
2029 packettype_name(EAGER), \
2030 packettype_name(IB), \
2031 packettype_name(ERROR), \
2032 packettype_name(BYPASS))
2034 #define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode }
2035 #define show_ib_opcode(opcode) \
2036 __print_symbolic(opcode, \
2037 ib_opcode_name(RC_SEND_FIRST), \
2038 ib_opcode_name(RC_SEND_MIDDLE), \
2039 ib_opcode_name(RC_SEND_LAST), \
2040 ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \
2041 ib_opcode_name(RC_SEND_ONLY), \
2042 ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \
2043 ib_opcode_name(RC_RDMA_WRITE_FIRST), \
2044 ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \
2045 ib_opcode_name(RC_RDMA_WRITE_LAST), \
2046 ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2047 ib_opcode_name(RC_RDMA_WRITE_ONLY), \
2048 ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2049 ib_opcode_name(RC_RDMA_READ_REQUEST), \
2050 ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \
2051 ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \
2052 ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \
2053 ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \
2054 ib_opcode_name(RC_ACKNOWLEDGE), \
2055 ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \
2056 ib_opcode_name(RC_COMPARE_SWAP), \
2057 ib_opcode_name(RC_FETCH_ADD), \
2058 ib_opcode_name(UC_SEND_FIRST), \
2059 ib_opcode_name(UC_SEND_MIDDLE), \
2060 ib_opcode_name(UC_SEND_LAST), \
2061 ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \
2062 ib_opcode_name(UC_SEND_ONLY), \
2063 ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \
2064 ib_opcode_name(UC_RDMA_WRITE_FIRST), \
2065 ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \
2066 ib_opcode_name(UC_RDMA_WRITE_LAST), \
2067 ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2068 ib_opcode_name(UC_RDMA_WRITE_ONLY), \
2069 ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2070 ib_opcode_name(UD_SEND_ONLY), \
2071 ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \
2072 ib_opcode_name(CNP))
2073 #endif /* _HFI1_KERNEL_H */