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48 #include <linux/delay.h>
53 #define SC(name) SEND_CTXT_##name
55 * Send Context functions
57 static void sc_wait_for_packet_egress(struct send_context *sc, int pause);
60 * Set the CM reset bit and wait for it to clear. Use the provided
61 * sendctrl register. This routine has no locking.
63 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl)
65 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK);
68 sendctrl = read_csr(dd, SEND_CTRL);
69 if ((sendctrl & SEND_CTRL_CM_RESET_SMASK) == 0)
74 /* global control of PIO send */
75 void pio_send_control(struct hfi1_devdata *dd, int op)
79 int write = 1; /* write sendctrl back */
80 int flush = 0; /* re-read sendctrl to make sure it is flushed */
83 spin_lock_irqsave(&dd->sendctrl_lock, flags);
85 reg = read_csr(dd, SEND_CTRL);
87 case PSC_GLOBAL_ENABLE:
88 reg |= SEND_CTRL_SEND_ENABLE_SMASK;
90 case PSC_DATA_VL_ENABLE:
92 for (i = 0; i < ARRAY_SIZE(dd->vld); i++)
95 /* Disallow sending on VLs not enabled */
96 mask = (mask & SEND_CTRL_UNSUPPORTED_VL_MASK) <<
97 SEND_CTRL_UNSUPPORTED_VL_SHIFT;
98 reg = (reg & ~SEND_CTRL_UNSUPPORTED_VL_SMASK) | mask;
100 case PSC_GLOBAL_DISABLE:
101 reg &= ~SEND_CTRL_SEND_ENABLE_SMASK;
103 case PSC_GLOBAL_VLARB_ENABLE:
104 reg |= SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
106 case PSC_GLOBAL_VLARB_DISABLE:
107 reg &= ~SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
111 write = 0; /* CSR already written (and flushed) */
113 case PSC_DATA_VL_DISABLE:
114 reg |= SEND_CTRL_UNSUPPORTED_VL_SMASK;
118 dd_dev_err(dd, "%s: invalid control %d\n", __func__, op);
123 write_csr(dd, SEND_CTRL, reg);
125 (void)read_csr(dd, SEND_CTRL); /* flush write */
128 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
131 /* number of send context memory pools */
132 #define NUM_SC_POOLS 2
134 /* Send Context Size (SCS) wildcards */
135 #define SCS_POOL_0 -1
136 #define SCS_POOL_1 -2
138 /* Send Context Count (SCC) wildcards */
139 #define SCC_PER_VL -1
140 #define SCC_PER_CPU -2
141 #define SCC_PER_KRCVQ -3
143 /* Send Context Size (SCS) constants */
144 #define SCS_ACK_CREDITS 32
145 #define SCS_VL15_CREDITS 102 /* 3 pkts of 2048B data + 128B header */
147 #define PIO_THRESHOLD_CEILING 4096
149 #define PIO_WAIT_BATCH_SIZE 5
151 /* default send context sizes */
152 static struct sc_config_sizes sc_config_sizes[SC_MAX] = {
153 [SC_KERNEL] = { .size = SCS_POOL_0, /* even divide, pool 0 */
154 .count = SCC_PER_VL }, /* one per NUMA */
155 [SC_ACK] = { .size = SCS_ACK_CREDITS,
156 .count = SCC_PER_KRCVQ },
157 [SC_USER] = { .size = SCS_POOL_0, /* even divide, pool 0 */
158 .count = SCC_PER_CPU }, /* one per CPU */
159 [SC_VL15] = { .size = SCS_VL15_CREDITS,
164 /* send context memory pool configuration */
165 struct mem_pool_config {
166 int centipercent; /* % of memory, in 100ths of 1% */
167 int absolute_blocks; /* absolute block count */
170 /* default memory pool configuration: 100% in pool 0 */
171 static struct mem_pool_config sc_mem_pool_config[NUM_SC_POOLS] = {
172 /* centi%, abs blocks */
173 { 10000, -1 }, /* pool 0 */
174 { 0, -1 }, /* pool 1 */
177 /* memory pool information, used when calculating final sizes */
178 struct mem_pool_info {
180 * 100th of 1% of memory to use, -1 if blocks
183 int count; /* count of contexts in the pool */
184 int blocks; /* block size of the pool */
185 int size; /* context size, in blocks */
189 * Convert a pool wildcard to a valid pool index. The wildcards
190 * start at -1 and increase negatively. Map them as:
195 * Return -1 on non-wildcard input, otherwise convert to a pool number.
197 static int wildcard_to_pool(int wc)
200 return -1; /* non-wildcard */
204 static const char *sc_type_names[SC_MAX] = {
211 static const char *sc_type_name(int index)
213 if (index < 0 || index >= SC_MAX)
215 return sc_type_names[index];
219 * Read the send context memory pool configuration and send context
220 * size configuration. Replace any wildcards and come up with final
221 * counts and sizes for the send context types.
223 int init_sc_pools_and_sizes(struct hfi1_devdata *dd)
225 struct mem_pool_info mem_pool_info[NUM_SC_POOLS] = { { 0 } };
226 int total_blocks = (chip_pio_mem_size(dd) / PIO_BLOCK_SIZE) - 1;
227 int total_contexts = 0;
231 int cp_total; /* centipercent total */
232 int ab_total; /* absolute block total */
237 * When SDMA is enabled, kernel context pio packet size is capped by
238 * "piothreshold". Reduce pio buffer allocation for kernel context by
239 * setting it to a fixed size. The allocation allows 3-deep buffering
240 * of the largest pio packets plus up to 128 bytes header, sufficient
241 * to maintain verbs performance.
243 * When SDMA is disabled, keep the default pooling allocation.
245 if (HFI1_CAP_IS_KSET(SDMA)) {
246 u16 max_pkt_size = (piothreshold < PIO_THRESHOLD_CEILING) ?
247 piothreshold : PIO_THRESHOLD_CEILING;
248 sc_config_sizes[SC_KERNEL].size =
249 3 * (max_pkt_size + 128) / PIO_BLOCK_SIZE;
254 * - copy the centipercents/absolute sizes from the pool config
255 * - sanity check these values
256 * - add up centipercents, then later check for full value
257 * - add up absolute blocks, then later check for over-commit
261 for (i = 0; i < NUM_SC_POOLS; i++) {
262 int cp = sc_mem_pool_config[i].centipercent;
263 int ab = sc_mem_pool_config[i].absolute_blocks;
266 * A negative value is "unused" or "invalid". Both *can*
267 * be valid, but centipercent wins, so check that first
269 if (cp >= 0) { /* centipercent valid */
271 } else if (ab >= 0) { /* absolute blocks valid */
273 } else { /* neither valid */
276 "Send context memory pool %d: both the block count and centipercent are invalid\n",
281 mem_pool_info[i].centipercent = cp;
282 mem_pool_info[i].blocks = ab;
285 /* do not use both % and absolute blocks for different pools */
286 if (cp_total != 0 && ab_total != 0) {
289 "All send context memory pools must be described as either centipercent or blocks, no mixing between pools\n");
293 /* if any percentages are present, they must add up to 100% x 100 */
294 if (cp_total != 0 && cp_total != 10000) {
297 "Send context memory pool centipercent is %d, expecting 10000\n",
302 /* the absolute pool total cannot be more than the mem total */
303 if (ab_total > total_blocks) {
306 "Send context memory pool absolute block count %d is larger than the memory size %d\n",
307 ab_total, total_blocks);
313 * - copy from the context size config
314 * - replace context type wildcard counts with real values
315 * - add up non-memory pool block sizes
316 * - add up memory pool user counts
319 for (i = 0; i < SC_MAX; i++) {
320 int count = sc_config_sizes[i].count;
321 int size = sc_config_sizes[i].size;
325 * Sanity check count: Either a positive value or
326 * one of the expected wildcards is valid. The positive
327 * value is checked later when we compare against total
331 count = dd->n_krcv_queues;
332 } else if (i == SC_KERNEL) {
333 count = INIT_SC_PER_VL * num_vls;
334 } else if (count == SCC_PER_CPU) {
335 count = dd->num_rcv_contexts - dd->n_krcv_queues;
336 } else if (count < 0) {
339 "%s send context invalid count wildcard %d\n",
340 sc_type_name(i), count);
343 if (total_contexts + count > chip_send_contexts(dd))
344 count = chip_send_contexts(dd) - total_contexts;
346 total_contexts += count;
349 * Sanity check pool: The conversion will return a pool
350 * number or -1 if a fixed (non-negative) value. The fixed
351 * value is checked later when we compare against
352 * total memory available.
354 pool = wildcard_to_pool(size);
355 if (pool == -1) { /* non-wildcard */
356 fixed_blocks += size * count;
357 } else if (pool < NUM_SC_POOLS) { /* valid wildcard */
358 mem_pool_info[pool].count += count;
359 } else { /* invalid wildcard */
362 "%s send context invalid pool wildcard %d\n",
363 sc_type_name(i), size);
367 dd->sc_sizes[i].count = count;
368 dd->sc_sizes[i].size = size;
370 if (fixed_blocks > total_blocks) {
373 "Send context fixed block count, %u, larger than total block count %u\n",
374 fixed_blocks, total_blocks);
378 /* step 3: calculate the blocks in the pools, and pool context sizes */
379 pool_blocks = total_blocks - fixed_blocks;
380 if (ab_total > pool_blocks) {
383 "Send context fixed pool sizes, %u, larger than pool block count %u\n",
384 ab_total, pool_blocks);
387 /* subtract off the fixed pool blocks */
388 pool_blocks -= ab_total;
390 for (i = 0; i < NUM_SC_POOLS; i++) {
391 struct mem_pool_info *pi = &mem_pool_info[i];
393 /* % beats absolute blocks */
394 if (pi->centipercent >= 0)
395 pi->blocks = (pool_blocks * pi->centipercent) / 10000;
397 if (pi->blocks == 0 && pi->count != 0) {
400 "Send context memory pool %d has %u contexts, but no blocks\n",
404 if (pi->count == 0) {
405 /* warn about wasted blocks */
409 "Send context memory pool %d has %u blocks, but zero contexts\n",
413 pi->size = pi->blocks / pi->count;
417 /* step 4: fill in the context type sizes from the pool sizes */
419 for (i = 0; i < SC_MAX; i++) {
420 if (dd->sc_sizes[i].size < 0) {
421 unsigned pool = wildcard_to_pool(dd->sc_sizes[i].size);
423 WARN_ON_ONCE(pool >= NUM_SC_POOLS);
424 dd->sc_sizes[i].size = mem_pool_info[pool].size;
426 /* make sure we are not larger than what is allowed by the HW */
427 #define PIO_MAX_BLOCKS 1024
428 if (dd->sc_sizes[i].size > PIO_MAX_BLOCKS)
429 dd->sc_sizes[i].size = PIO_MAX_BLOCKS;
431 /* calculate our total usage */
432 used_blocks += dd->sc_sizes[i].size * dd->sc_sizes[i].count;
434 extra = total_blocks - used_blocks;
436 dd_dev_info(dd, "unused send context blocks: %d\n", extra);
438 return total_contexts;
441 int init_send_contexts(struct hfi1_devdata *dd)
444 int ret, i, j, context;
446 ret = init_credit_return(dd);
450 dd->hw_to_sw = kmalloc_array(TXE_NUM_CONTEXTS, sizeof(u8),
452 dd->send_contexts = kcalloc(dd->num_send_contexts,
453 sizeof(struct send_context_info),
455 if (!dd->send_contexts || !dd->hw_to_sw) {
457 kfree(dd->send_contexts);
458 free_credit_return(dd);
462 /* hardware context map starts with invalid send context indices */
463 for (i = 0; i < TXE_NUM_CONTEXTS; i++)
464 dd->hw_to_sw[i] = INVALID_SCI;
467 * All send contexts have their credit sizes. Allocate credits
468 * for each context one after another from the global space.
472 for (i = 0; i < SC_MAX; i++) {
473 struct sc_config_sizes *scs = &dd->sc_sizes[i];
475 for (j = 0; j < scs->count; j++) {
476 struct send_context_info *sci =
477 &dd->send_contexts[context];
480 sci->credits = scs->size;
491 * Allocate a software index and hardware context of the given type.
493 * Must be called with dd->sc_lock held.
495 static int sc_hw_alloc(struct hfi1_devdata *dd, int type, u32 *sw_index,
498 struct send_context_info *sci;
502 for (index = 0, sci = &dd->send_contexts[0];
503 index < dd->num_send_contexts; index++, sci++) {
504 if (sci->type == type && sci->allocated == 0) {
506 /* use a 1:1 mapping, but make them non-equal */
507 context = chip_send_contexts(dd) - index - 1;
508 dd->hw_to_sw[context] = index;
510 *hw_context = context;
511 return 0; /* success */
514 dd_dev_err(dd, "Unable to locate a free type %d send context\n", type);
519 * Free the send context given by its software index.
521 * Must be called with dd->sc_lock held.
523 static void sc_hw_free(struct hfi1_devdata *dd, u32 sw_index, u32 hw_context)
525 struct send_context_info *sci;
527 sci = &dd->send_contexts[sw_index];
528 if (!sci->allocated) {
529 dd_dev_err(dd, "%s: sw_index %u not allocated? hw_context %u\n",
530 __func__, sw_index, hw_context);
533 dd->hw_to_sw[hw_context] = INVALID_SCI;
536 /* return the base context of a context in a group */
537 static inline u32 group_context(u32 context, u32 group)
539 return (context >> group) << group;
542 /* return the size of a group */
543 static inline u32 group_size(u32 group)
549 * Obtain the credit return addresses, kernel virtual and bus, for the
552 * To understand this routine:
553 * o va and dma are arrays of struct credit_return. One for each physical
554 * send context, per NUMA.
555 * o Each send context always looks in its relative location in a struct
556 * credit_return for its credit return.
557 * o Each send context in a group must have its return address CSR programmed
558 * with the same value. Use the address of the first send context in the
561 static void cr_group_addresses(struct send_context *sc, dma_addr_t *dma)
563 u32 gc = group_context(sc->hw_context, sc->group);
564 u32 index = sc->hw_context & 0x7;
566 sc->hw_free = &sc->dd->cr_base[sc->node].va[gc].cr[index];
567 *dma = (unsigned long)
568 &((struct credit_return *)sc->dd->cr_base[sc->node].dma)[gc];
572 * Work queue function triggered in error interrupt routine for
575 static void sc_halted(struct work_struct *work)
577 struct send_context *sc;
579 sc = container_of(work, struct send_context, halt_work);
584 * Calculate PIO block threshold for this send context using the given MTU.
585 * Trigger a return when one MTU plus optional header of credits remain.
587 * Parameter mtu is in bytes.
588 * Parameter hdrqentsize is in DWORDs.
590 * Return value is what to write into the CSR: trigger return when
591 * unreturned credits pass this count.
593 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize)
598 /* add in the header size, then divide by the PIO block size */
599 mtu += hdrqentsize << 2;
600 release_credits = DIV_ROUND_UP(mtu, PIO_BLOCK_SIZE);
602 /* check against this context's credits */
603 if (sc->credits <= release_credits)
606 threshold = sc->credits - release_credits;
612 * Calculate credit threshold in terms of percent of the allocated credits.
613 * Trigger when unreturned credits equal or exceed the percentage of the whole.
615 * Return value is what to write into the CSR: trigger return when
616 * unreturned credits pass this count.
618 u32 sc_percent_to_threshold(struct send_context *sc, u32 percent)
620 return (sc->credits * percent) / 100;
624 * Set the credit return threshold.
626 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold)
630 int force_return = 0;
632 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
634 old_threshold = (sc->credit_ctrl >>
635 SC(CREDIT_CTRL_THRESHOLD_SHIFT))
636 & SC(CREDIT_CTRL_THRESHOLD_MASK);
638 if (new_threshold != old_threshold) {
641 & ~SC(CREDIT_CTRL_THRESHOLD_SMASK))
643 & SC(CREDIT_CTRL_THRESHOLD_MASK))
644 << SC(CREDIT_CTRL_THRESHOLD_SHIFT));
645 write_kctxt_csr(sc->dd, sc->hw_context,
646 SC(CREDIT_CTRL), sc->credit_ctrl);
648 /* force a credit return on change to avoid a possible stall */
652 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
655 sc_return_credits(sc);
661 * Set the CHECK_ENABLE register for the send context 'sc'.
663 void set_pio_integrity(struct send_context *sc)
665 struct hfi1_devdata *dd = sc->dd;
666 u32 hw_context = sc->hw_context;
669 write_kctxt_csr(dd, hw_context,
671 hfi1_pkt_default_send_ctxt_mask(dd, type));
674 static u32 get_buffers_allocated(struct send_context *sc)
679 for_each_possible_cpu(cpu)
680 ret += *per_cpu_ptr(sc->buffers_allocated, cpu);
684 static void reset_buffers_allocated(struct send_context *sc)
688 for_each_possible_cpu(cpu)
689 (*per_cpu_ptr(sc->buffers_allocated, cpu)) = 0;
693 * Allocate a NUMA relative send context structure of the given type along
696 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
697 uint hdrqentsize, int numa)
699 struct send_context_info *sci;
700 struct send_context *sc = NULL;
710 /* do not allocate while frozen */
711 if (dd->flags & HFI1_FROZEN)
714 sc = kzalloc_node(sizeof(*sc), GFP_KERNEL, numa);
718 sc->buffers_allocated = alloc_percpu(u32);
719 if (!sc->buffers_allocated) {
722 "Cannot allocate buffers_allocated per cpu counters\n"
727 spin_lock_irqsave(&dd->sc_lock, flags);
728 ret = sc_hw_alloc(dd, type, &sw_index, &hw_context);
730 spin_unlock_irqrestore(&dd->sc_lock, flags);
731 free_percpu(sc->buffers_allocated);
736 sci = &dd->send_contexts[sw_index];
742 spin_lock_init(&sc->alloc_lock);
743 spin_lock_init(&sc->release_lock);
744 spin_lock_init(&sc->credit_ctrl_lock);
745 seqlock_init(&sc->waitlock);
746 INIT_LIST_HEAD(&sc->piowait);
747 INIT_WORK(&sc->halt_work, sc_halted);
748 init_waitqueue_head(&sc->halt_wait);
750 /* grouping is always single context for now */
753 sc->sw_index = sw_index;
754 sc->hw_context = hw_context;
755 cr_group_addresses(sc, &dma);
756 sc->credits = sci->credits;
757 sc->size = sc->credits * PIO_BLOCK_SIZE;
759 /* PIO Send Memory Address details */
760 #define PIO_ADDR_CONTEXT_MASK 0xfful
761 #define PIO_ADDR_CONTEXT_SHIFT 16
762 sc->base_addr = dd->piobase + ((hw_context & PIO_ADDR_CONTEXT_MASK)
763 << PIO_ADDR_CONTEXT_SHIFT);
765 /* set base and credits */
766 reg = ((sci->credits & SC(CTRL_CTXT_DEPTH_MASK))
767 << SC(CTRL_CTXT_DEPTH_SHIFT))
768 | ((sci->base & SC(CTRL_CTXT_BASE_MASK))
769 << SC(CTRL_CTXT_BASE_SHIFT));
770 write_kctxt_csr(dd, hw_context, SC(CTRL), reg);
772 set_pio_integrity(sc);
774 /* unmask all errors */
775 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), (u64)-1);
777 /* set the default partition key */
778 write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY),
779 (SC(CHECK_PARTITION_KEY_VALUE_MASK) &
781 SC(CHECK_PARTITION_KEY_VALUE_SHIFT));
783 /* per context type checks */
784 if (type == SC_USER) {
785 opval = USER_OPCODE_CHECK_VAL;
786 opmask = USER_OPCODE_CHECK_MASK;
788 opval = OPCODE_CHECK_VAL_DISABLED;
789 opmask = OPCODE_CHECK_MASK_DISABLED;
792 /* set the send context check opcode mask and value */
793 write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE),
794 ((u64)opmask << SC(CHECK_OPCODE_MASK_SHIFT)) |
795 ((u64)opval << SC(CHECK_OPCODE_VALUE_SHIFT)));
797 /* set up credit return */
798 reg = dma & SC(CREDIT_RETURN_ADDR_ADDRESS_SMASK);
799 write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), reg);
802 * Calculate the initial credit return threshold.
804 * For Ack contexts, set a threshold for half the credits.
805 * For User contexts use the given percentage. This has been
806 * sanitized on driver start-up.
807 * For Kernel contexts, use the default MTU plus a header
808 * or half the credits, whichever is smaller. This should
809 * work for both the 3-deep buffering allocation and the
810 * pooling allocation.
812 if (type == SC_ACK) {
813 thresh = sc_percent_to_threshold(sc, 50);
814 } else if (type == SC_USER) {
815 thresh = sc_percent_to_threshold(sc,
816 user_credit_return_threshold);
817 } else { /* kernel */
818 thresh = min(sc_percent_to_threshold(sc, 50),
819 sc_mtu_to_threshold(sc, hfi1_max_mtu,
822 reg = thresh << SC(CREDIT_CTRL_THRESHOLD_SHIFT);
823 /* add in early return */
824 if (type == SC_USER && HFI1_CAP_IS_USET(EARLY_CREDIT_RETURN))
825 reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
826 else if (HFI1_CAP_IS_KSET(EARLY_CREDIT_RETURN)) /* kernel, ack */
827 reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
829 /* set up write-through credit_ctrl */
830 sc->credit_ctrl = reg;
831 write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), reg);
833 /* User send contexts should not allow sending on VL15 */
834 if (type == SC_USER) {
836 write_kctxt_csr(dd, hw_context, SC(CHECK_VL), reg);
839 spin_unlock_irqrestore(&dd->sc_lock, flags);
842 * Allocate shadow ring to track outstanding PIO buffers _after_
843 * unlocking. We don't know the size until the lock is held and
844 * we can't allocate while the lock is held. No one is using
845 * the context yet, so allocate it now.
847 * User contexts do not get a shadow ring.
849 if (type != SC_USER) {
851 * Size the shadow ring 1 larger than the number of credits
852 * so head == tail can mean empty.
854 sc->sr_size = sci->credits + 1;
855 sc->sr = kcalloc_node(sc->sr_size,
856 sizeof(union pio_shadow_ring),
865 "Send context %u(%u) %s group %u credits %u credit_ctrl 0x%llx threshold %u\n",
877 /* free a per-NUMA send context structure */
878 void sc_free(struct send_context *sc)
880 struct hfi1_devdata *dd;
888 sc->flags |= SCF_IN_FREE; /* ensure no restarts */
890 if (!list_empty(&sc->piowait))
891 dd_dev_err(dd, "piowait list not empty!\n");
892 sw_index = sc->sw_index;
893 hw_context = sc->hw_context;
894 sc_disable(sc); /* make sure the HW is disabled */
895 flush_work(&sc->halt_work);
897 spin_lock_irqsave(&dd->sc_lock, flags);
898 dd->send_contexts[sw_index].sc = NULL;
900 /* clear/disable all registers set in sc_alloc */
901 write_kctxt_csr(dd, hw_context, SC(CTRL), 0);
902 write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), 0);
903 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), 0);
904 write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY), 0);
905 write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE), 0);
906 write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), 0);
907 write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), 0);
909 /* release the index and context for re-use */
910 sc_hw_free(dd, sw_index, hw_context);
911 spin_unlock_irqrestore(&dd->sc_lock, flags);
914 free_percpu(sc->buffers_allocated);
918 /* disable the context */
919 void sc_disable(struct send_context *sc)
922 struct pio_buf *pbuf;
927 /* do all steps, even if already disabled */
928 spin_lock_irq(&sc->alloc_lock);
929 reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL));
930 reg &= ~SC(CTRL_CTXT_ENABLE_SMASK);
931 sc->flags &= ~SCF_ENABLED;
932 sc_wait_for_packet_egress(sc, 1);
933 write_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL), reg);
936 * Flush any waiters. Once the context is disabled,
937 * credit return interrupts are stopped (although there
938 * could be one in-process when the context is disabled).
939 * Wait one microsecond for any lingering interrupts, then
940 * proceed with the flush.
943 spin_lock(&sc->release_lock);
944 if (sc->sr) { /* this context has a shadow ring */
945 while (sc->sr_tail != sc->sr_head) {
946 pbuf = &sc->sr[sc->sr_tail].pbuf;
948 (*pbuf->cb)(pbuf->arg, PRC_SC_DISABLE);
950 if (sc->sr_tail >= sc->sr_size)
954 spin_unlock(&sc->release_lock);
955 spin_unlock_irq(&sc->alloc_lock);
958 /* return SendEgressCtxtStatus.PacketOccupancy */
959 static u64 packet_occupancy(u64 reg)
962 SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK)
963 >> SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT;
966 /* is egress halted on the context? */
967 static bool egress_halted(u64 reg)
969 return !!(reg & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK);
972 /* is the send context halted? */
973 static bool is_sc_halted(struct hfi1_devdata *dd, u32 hw_context)
975 return !!(read_kctxt_csr(dd, hw_context, SC(STATUS)) &
976 SC(STATUS_CTXT_HALTED_SMASK));
980 * sc_wait_for_packet_egress
981 * @sc: valid send context
982 * @pause: wait for credit return
984 * Wait for packet egress, optionally pause for credit return
986 * Egress halt and Context halt are not necessarily the same thing, so
989 * NOTE: The context halt bit may not be set immediately. Because of this,
990 * it is necessary to check the SW SFC_HALTED bit (set in the IRQ) and the HW
991 * context bit to determine if the context is halted.
993 static void sc_wait_for_packet_egress(struct send_context *sc, int pause)
995 struct hfi1_devdata *dd = sc->dd;
1002 reg = read_csr(dd, sc->hw_context * 8 +
1003 SEND_EGRESS_CTXT_STATUS);
1004 /* done if any halt bits, SW or HW are set */
1005 if (sc->flags & SCF_HALTED ||
1006 is_sc_halted(dd, sc->hw_context) || egress_halted(reg))
1008 reg = packet_occupancy(reg);
1011 /* counter is reset if occupancy count changes */
1012 if (reg != reg_prev)
1015 /* timed out - bounce the link */
1017 "%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n",
1018 __func__, sc->sw_index,
1019 sc->hw_context, (u32)reg);
1020 queue_work(dd->pport->link_wq,
1021 &dd->pport->link_bounce_work);
1029 /* Add additional delay to ensure chip returns all credits */
1030 pause_for_credit_return(dd);
1033 void sc_wait(struct hfi1_devdata *dd)
1037 for (i = 0; i < dd->num_send_contexts; i++) {
1038 struct send_context *sc = dd->send_contexts[i].sc;
1042 sc_wait_for_packet_egress(sc, 0);
1047 * Restart a context after it has been halted due to error.
1049 * If the first step fails - wait for the halt to be asserted, return early.
1050 * Otherwise complain about timeouts but keep going.
1052 * It is expected that allocations (enabled flag bit) have been shut off
1053 * already (only applies to kernel contexts).
1055 int sc_restart(struct send_context *sc)
1057 struct hfi1_devdata *dd = sc->dd;
1062 /* bounce off if not halted, or being free'd */
1063 if (!(sc->flags & SCF_HALTED) || (sc->flags & SCF_IN_FREE))
1066 dd_dev_info(dd, "restarting send context %u(%u)\n", sc->sw_index,
1070 * Step 1: Wait for the context to actually halt.
1072 * The error interrupt is asynchronous to actually setting halt
1077 reg = read_kctxt_csr(dd, sc->hw_context, SC(STATUS));
1078 if (reg & SC(STATUS_CTXT_HALTED_SMASK))
1081 dd_dev_err(dd, "%s: context %u(%u) not halting, skipping\n",
1082 __func__, sc->sw_index, sc->hw_context);
1090 * Step 2: Ensure no users are still trying to write to PIO.
1092 * For kernel contexts, we have already turned off buffer allocation.
1093 * Now wait for the buffer count to go to zero.
1095 * For user contexts, the user handling code has cut off write access
1096 * to the context's PIO pages before calling this routine and will
1097 * restore write access after this routine returns.
1099 if (sc->type != SC_USER) {
1100 /* kernel context */
1103 count = get_buffers_allocated(sc);
1108 "%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n",
1109 __func__, sc->sw_index,
1110 sc->hw_context, count);
1118 * Step 3: Wait for all packets to egress.
1119 * This is done while disabling the send context
1121 * Step 4: Disable the context
1123 * This is a superset of the halt. After the disable, the
1124 * errors can be cleared.
1129 * Step 5: Enable the context
1131 * This enable will clear the halted flag and per-send context
1134 return sc_enable(sc);
1138 * PIO freeze processing. To be called after the TXE block is fully frozen.
1139 * Go through all frozen send contexts and disable them. The contexts are
1140 * already stopped by the freeze.
1142 void pio_freeze(struct hfi1_devdata *dd)
1144 struct send_context *sc;
1147 for (i = 0; i < dd->num_send_contexts; i++) {
1148 sc = dd->send_contexts[i].sc;
1150 * Don't disable unallocated, unfrozen, or user send contexts.
1151 * User send contexts will be disabled when the process
1152 * calls into the driver to reset its context.
1154 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
1157 /* only need to disable, the context is already stopped */
1163 * Unfreeze PIO for kernel send contexts. The precondition for calling this
1164 * is that all PIO send contexts have been disabled and the SPC freeze has
1165 * been cleared. Now perform the last step and re-enable each kernel context.
1166 * User (PSM) processing will occur when PSM calls into the kernel to
1167 * acknowledge the freeze.
1169 void pio_kernel_unfreeze(struct hfi1_devdata *dd)
1171 struct send_context *sc;
1174 for (i = 0; i < dd->num_send_contexts; i++) {
1175 sc = dd->send_contexts[i].sc;
1176 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
1178 if (sc->flags & SCF_LINK_DOWN)
1181 sc_enable(sc); /* will clear the sc frozen flag */
1186 * pio_kernel_linkup() - Re-enable send contexts after linkup event
1187 * @dd: valid devive data
1189 * When the link goes down, the freeze path is taken. However, a link down
1190 * event is different from a freeze because if the send context is re-enabled
1191 * whowever is sending data will start sending data again, which will hang
1192 * any QP that is sending data.
1194 * The freeze path now looks at the type of event that occurs and takes this
1195 * path for link down event.
1197 void pio_kernel_linkup(struct hfi1_devdata *dd)
1199 struct send_context *sc;
1202 for (i = 0; i < dd->num_send_contexts; i++) {
1203 sc = dd->send_contexts[i].sc;
1204 if (!sc || !(sc->flags & SCF_LINK_DOWN) || sc->type == SC_USER)
1207 sc_enable(sc); /* will clear the sc link down flag */
1212 * Wait for the SendPioInitCtxt.PioInitInProgress bit to clear.
1214 * -ETIMEDOUT - if we wait too long
1215 * -EIO - if there was an error
1217 static int pio_init_wait_progress(struct hfi1_devdata *dd)
1222 /* max is the longest possible HW init time / delay */
1223 max = (dd->icode == ICODE_FPGA_EMULATION) ? 120 : 5;
1225 reg = read_csr(dd, SEND_PIO_INIT_CTXT);
1226 if (!(reg & SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK))
1234 return reg & SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK ? -EIO : 0;
1238 * Reset all of the send contexts to their power-on state. Used
1239 * only during manual init - no lock against sc_enable needed.
1241 void pio_reset_all(struct hfi1_devdata *dd)
1245 /* make sure the init engine is not busy */
1246 ret = pio_init_wait_progress(dd);
1247 /* ignore any timeout */
1249 /* clear the error */
1250 write_csr(dd, SEND_PIO_ERR_CLEAR,
1251 SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK);
1254 /* reset init all */
1255 write_csr(dd, SEND_PIO_INIT_CTXT,
1256 SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK);
1258 ret = pio_init_wait_progress(dd);
1261 "PIO send context init %s while initializing all PIO blocks\n",
1262 ret == -ETIMEDOUT ? "is stuck" : "had an error");
1266 /* enable the context */
1267 int sc_enable(struct send_context *sc)
1269 u64 sc_ctrl, reg, pio;
1270 struct hfi1_devdata *dd;
1271 unsigned long flags;
1279 * Obtain the allocator lock to guard against any allocation
1280 * attempts (which should not happen prior to context being
1281 * enabled). On the release/disable side we don't need to
1282 * worry about locking since the releaser will not do anything
1283 * if the context accounting values have not changed.
1285 spin_lock_irqsave(&sc->alloc_lock, flags);
1286 sc_ctrl = read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
1287 if ((sc_ctrl & SC(CTRL_CTXT_ENABLE_SMASK)))
1288 goto unlock; /* already enabled */
1290 /* IMPORTANT: only clear free and fill if transitioning 0 -> 1 */
1300 /* the alloc lock insures no fast path allocation */
1301 reset_buffers_allocated(sc);
1304 * Clear all per-context errors. Some of these will be set when
1305 * we are re-enabling after a context halt. Now that the context
1306 * is disabled, the halt will not clear until after the PIO init
1307 * engine runs below.
1309 reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS));
1311 write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR), reg);
1314 * The HW PIO initialization engine can handle only one init
1315 * request at a time. Serialize access to each device's engine.
1317 spin_lock(&dd->sc_init_lock);
1319 * Since access to this code block is serialized and
1320 * each access waits for the initialization to complete
1321 * before releasing the lock, the PIO initialization engine
1322 * should not be in use, so we don't have to wait for the
1323 * InProgress bit to go down.
1325 pio = ((sc->hw_context & SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK) <<
1326 SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT) |
1327 SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK;
1328 write_csr(dd, SEND_PIO_INIT_CTXT, pio);
1330 * Wait until the engine is done. Give the chip the required time
1331 * so, hopefully, we read the register just once.
1334 ret = pio_init_wait_progress(dd);
1335 spin_unlock(&dd->sc_init_lock);
1338 "sctxt%u(%u): Context not enabled due to init failure %d\n",
1339 sc->sw_index, sc->hw_context, ret);
1344 * All is well. Enable the context.
1346 sc_ctrl |= SC(CTRL_CTXT_ENABLE_SMASK);
1347 write_kctxt_csr(dd, sc->hw_context, SC(CTRL), sc_ctrl);
1349 * Read SendCtxtCtrl to force the write out and prevent a timing
1350 * hazard where a PIO write may reach the context before the enable.
1352 read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
1353 sc->flags |= SCF_ENABLED;
1356 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1361 /* force a credit return on the context */
1362 void sc_return_credits(struct send_context *sc)
1367 /* a 0->1 transition schedules a credit return */
1368 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE),
1369 SC(CREDIT_FORCE_FORCE_RETURN_SMASK));
1371 * Ensure that the write is flushed and the credit return is
1372 * scheduled. We care more about the 0 -> 1 transition.
1374 read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE));
1375 /* set back to 0 for next time */
1376 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE), 0);
1379 /* allow all in-flight packets to drain on the context */
1380 void sc_flush(struct send_context *sc)
1385 sc_wait_for_packet_egress(sc, 1);
1388 /* drop all packets on the context, no waiting until they are sent */
1389 void sc_drop(struct send_context *sc)
1394 dd_dev_info(sc->dd, "%s: context %u(%u) - not implemented\n",
1395 __func__, sc->sw_index, sc->hw_context);
1399 * Start the software reaction to a context halt or SPC freeze:
1400 * - mark the context as halted or frozen
1401 * - stop buffer allocations
1403 * Called from the error interrupt. Other work is deferred until
1404 * out of the interrupt.
1406 void sc_stop(struct send_context *sc, int flag)
1408 unsigned long flags;
1410 /* stop buffer allocations */
1411 spin_lock_irqsave(&sc->alloc_lock, flags);
1412 /* mark the context */
1414 sc->flags &= ~SCF_ENABLED;
1415 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1416 wake_up(&sc->halt_wait);
1419 #define BLOCK_DWORDS (PIO_BLOCK_SIZE / sizeof(u32))
1420 #define dwords_to_blocks(x) DIV_ROUND_UP(x, BLOCK_DWORDS)
1423 * The send context buffer "allocator".
1425 * @sc: the PIO send context we are allocating from
1426 * @len: length of whole packet - including PBC - in dwords
1427 * @cb: optional callback to call when the buffer is finished sending
1428 * @arg: argument for cb
1430 * Return a pointer to a PIO buffer if successful, NULL if not enough room.
1432 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
1433 pio_release_cb cb, void *arg)
1435 struct pio_buf *pbuf = NULL;
1436 unsigned long flags;
1437 unsigned long avail;
1438 unsigned long blocks = dwords_to_blocks(dw_len);
1443 spin_lock_irqsave(&sc->alloc_lock, flags);
1444 if (!(sc->flags & SCF_ENABLED)) {
1445 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1450 avail = (unsigned long)sc->credits - (sc->fill - sc->alloc_free);
1451 if (blocks > avail) {
1452 /* not enough room */
1453 if (unlikely(trycount)) { /* already tried to get more room */
1454 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1457 /* copy from receiver cache line and recalculate */
1458 sc->alloc_free = READ_ONCE(sc->free);
1460 (unsigned long)sc->credits -
1461 (sc->fill - sc->alloc_free);
1462 if (blocks > avail) {
1463 /* still no room, actively update */
1464 sc_release_update(sc);
1465 sc->alloc_free = READ_ONCE(sc->free);
1471 /* there is enough room */
1474 this_cpu_inc(*sc->buffers_allocated);
1476 /* read this once */
1479 /* "allocate" the buffer */
1481 fill_wrap = sc->fill_wrap;
1482 sc->fill_wrap += blocks;
1483 if (sc->fill_wrap >= sc->credits)
1484 sc->fill_wrap = sc->fill_wrap - sc->credits;
1487 * Fill the parts that the releaser looks at before moving the head.
1488 * The only necessary piece is the sent_at field. The credits
1489 * we have just allocated cannot have been returned yet, so the
1490 * cb and arg will not be looked at for a "while". Put them
1491 * on this side of the memory barrier anyway.
1493 pbuf = &sc->sr[head].pbuf;
1494 pbuf->sent_at = sc->fill;
1497 pbuf->sc = sc; /* could be filled in at sc->sr init time */
1498 /* make sure this is in memory before updating the head */
1500 /* calculate next head index, do not store */
1502 if (next >= sc->sr_size)
1505 * update the head - must be last! - the releaser can look at fields
1506 * in pbuf once we move the head
1510 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1512 /* finish filling in the buffer outside the lock */
1513 pbuf->start = sc->base_addr + fill_wrap * PIO_BLOCK_SIZE;
1514 pbuf->end = sc->base_addr + sc->size;
1515 pbuf->qw_written = 0;
1516 pbuf->carry_bytes = 0;
1517 pbuf->carry.val64 = 0;
1523 * There are at least two entities that can turn on credit return
1524 * interrupts and they can overlap. Avoid problems by implementing
1525 * a count scheme that is enforced by a lock. The lock is needed because
1526 * the count and CSR write must be paired.
1530 * Start credit return interrupts. This is managed by a count. If already
1531 * on, just increment the count.
1533 void sc_add_credit_return_intr(struct send_context *sc)
1535 unsigned long flags;
1537 /* lock must surround both the count change and the CSR update */
1538 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
1539 if (sc->credit_intr_count == 0) {
1540 sc->credit_ctrl |= SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
1541 write_kctxt_csr(sc->dd, sc->hw_context,
1542 SC(CREDIT_CTRL), sc->credit_ctrl);
1544 sc->credit_intr_count++;
1545 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
1549 * Stop credit return interrupts. This is managed by a count. Decrement the
1550 * count, if the last user, then turn the credit interrupts off.
1552 void sc_del_credit_return_intr(struct send_context *sc)
1554 unsigned long flags;
1556 WARN_ON(sc->credit_intr_count == 0);
1558 /* lock must surround both the count change and the CSR update */
1559 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
1560 sc->credit_intr_count--;
1561 if (sc->credit_intr_count == 0) {
1562 sc->credit_ctrl &= ~SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
1563 write_kctxt_csr(sc->dd, sc->hw_context,
1564 SC(CREDIT_CTRL), sc->credit_ctrl);
1566 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
1570 * The caller must be careful when calling this. All needint calls
1571 * must be paired with !needint.
1573 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint)
1576 sc_add_credit_return_intr(sc);
1578 sc_del_credit_return_intr(sc);
1579 trace_hfi1_wantpiointr(sc, needint, sc->credit_ctrl);
1581 sc_return_credits(sc);
1586 * sc_piobufavail - callback when a PIO buffer is available
1587 * @sc: the send context
1589 * This is called from the interrupt handler when a PIO buffer is
1590 * available after hfi1_verbs_send() returned an error that no buffers were
1591 * available. Disable the interrupt if there are no more QPs waiting.
1593 static void sc_piobufavail(struct send_context *sc)
1595 struct hfi1_devdata *dd = sc->dd;
1596 struct list_head *list;
1597 struct rvt_qp *qps[PIO_WAIT_BATCH_SIZE];
1599 struct hfi1_qp_priv *priv;
1600 unsigned long flags;
1601 uint i, n = 0, top_idx = 0;
1603 if (dd->send_contexts[sc->sw_index].type != SC_KERNEL &&
1604 dd->send_contexts[sc->sw_index].type != SC_VL15)
1606 list = &sc->piowait;
1608 * Note: checking that the piowait list is empty and clearing
1609 * the buffer available interrupt needs to be atomic or we
1610 * could end up with QPs on the wait list with the interrupt
1613 write_seqlock_irqsave(&sc->waitlock, flags);
1614 while (!list_empty(list)) {
1615 struct iowait *wait;
1617 if (n == ARRAY_SIZE(qps))
1619 wait = list_first_entry(list, struct iowait, list);
1620 iowait_get_priority(wait);
1621 qp = iowait_to_qp(wait);
1623 list_del_init(&priv->s_iowait.list);
1624 priv->s_iowait.lock = NULL;
1626 priv = qps[top_idx]->priv;
1627 top_idx = iowait_priority_update_top(wait,
1632 /* refcount held until actual wake up */
1636 * If there had been waiters and there are more
1637 * insure that we redo the force to avoid a potential hang.
1640 hfi1_sc_wantpiobuf_intr(sc, 0);
1641 if (!list_empty(list))
1642 hfi1_sc_wantpiobuf_intr(sc, 1);
1644 write_sequnlock_irqrestore(&sc->waitlock, flags);
1646 /* Wake up the top-priority one first */
1648 hfi1_qp_wakeup(qps[top_idx],
1649 RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
1650 for (i = 0; i < n; i++)
1652 hfi1_qp_wakeup(qps[i],
1653 RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
1656 /* translate a send credit update to a bit code of reasons */
1657 static inline int fill_code(u64 hw_free)
1661 if (hw_free & CR_STATUS_SMASK)
1662 code |= PRC_STATUS_ERR;
1663 if (hw_free & CR_CREDIT_RETURN_DUE_TO_PBC_SMASK)
1665 if (hw_free & CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK)
1666 code |= PRC_THRESHOLD;
1667 if (hw_free & CR_CREDIT_RETURN_DUE_TO_ERR_SMASK)
1668 code |= PRC_FILL_ERR;
1669 if (hw_free & CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK)
1670 code |= PRC_SC_DISABLE;
1674 /* use the jiffies compare to get the wrap right */
1675 #define sent_before(a, b) time_before(a, b) /* a < b */
1678 * The send context buffer "releaser".
1680 void sc_release_update(struct send_context *sc)
1682 struct pio_buf *pbuf;
1685 unsigned long old_free;
1687 unsigned long extra;
1688 unsigned long flags;
1694 spin_lock_irqsave(&sc->release_lock, flags);
1696 hw_free = le64_to_cpu(*sc->hw_free); /* volatile read */
1697 old_free = sc->free;
1698 extra = (((hw_free & CR_COUNTER_SMASK) >> CR_COUNTER_SHIFT)
1699 - (old_free & CR_COUNTER_MASK))
1701 free = old_free + extra;
1702 trace_hfi1_piofree(sc, extra);
1704 /* call sent buffer callbacks */
1705 code = -1; /* code not yet set */
1706 head = READ_ONCE(sc->sr_head); /* snapshot the head */
1708 while (head != tail) {
1709 pbuf = &sc->sr[tail].pbuf;
1711 if (sent_before(free, pbuf->sent_at)) {
1716 if (code < 0) /* fill in code on first user */
1717 code = fill_code(hw_free);
1718 (*pbuf->cb)(pbuf->arg, code);
1722 if (tail >= sc->sr_size)
1726 /* make sure tail is updated before free */
1729 spin_unlock_irqrestore(&sc->release_lock, flags);
1734 * Send context group releaser. Argument is the send context that caused
1735 * the interrupt. Called from the send context interrupt handler.
1737 * Call release on all contexts in the group.
1739 * This routine takes the sc_lock without an irqsave because it is only
1740 * called from an interrupt handler. Adjust if that changes.
1742 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context)
1744 struct send_context *sc;
1748 spin_lock(&dd->sc_lock);
1749 sw_index = dd->hw_to_sw[hw_context];
1750 if (unlikely(sw_index >= dd->num_send_contexts)) {
1751 dd_dev_err(dd, "%s: invalid hw (%u) to sw (%u) mapping\n",
1752 __func__, hw_context, sw_index);
1755 sc = dd->send_contexts[sw_index].sc;
1759 gc = group_context(hw_context, sc->group);
1760 gc_end = gc + group_size(sc->group);
1761 for (; gc < gc_end; gc++) {
1762 sw_index = dd->hw_to_sw[gc];
1763 if (unlikely(sw_index >= dd->num_send_contexts)) {
1765 "%s: invalid hw (%u) to sw (%u) mapping\n",
1766 __func__, hw_context, sw_index);
1769 sc_release_update(dd->send_contexts[sw_index].sc);
1772 spin_unlock(&dd->sc_lock);
1776 * pio_select_send_context_vl() - select send context
1778 * @selector: a spreading factor
1781 * This function returns a send context based on the selector and a vl.
1782 * The mapping fields are protected by RCU
1784 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
1785 u32 selector, u8 vl)
1787 struct pio_vl_map *m;
1788 struct pio_map_elem *e;
1789 struct send_context *rval;
1792 * NOTE This should only happen if SC->VL changed after the initial
1793 * checks on the QP/AH
1794 * Default will return VL0's send context below
1796 if (unlikely(vl >= num_vls)) {
1802 m = rcu_dereference(dd->pio_map);
1805 return dd->vld[0].sc;
1807 e = m->map[vl & m->mask];
1808 rval = e->ksc[selector & e->mask];
1812 rval = !rval ? dd->vld[0].sc : rval;
1817 * pio_select_send_context_sc() - select send context
1819 * @selector: a spreading factor
1820 * @sc5: the 5 bit sc
1822 * This function returns an send context based on the selector and an sc
1824 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
1825 u32 selector, u8 sc5)
1827 u8 vl = sc_to_vlt(dd, sc5);
1829 return pio_select_send_context_vl(dd, selector, vl);
1833 * Free the indicated map struct
1835 static void pio_map_free(struct pio_vl_map *m)
1839 for (i = 0; m && i < m->actual_vls; i++)
1845 * Handle RCU callback
1847 static void pio_map_rcu_callback(struct rcu_head *list)
1849 struct pio_vl_map *m = container_of(list, struct pio_vl_map, list);
1855 * Set credit return threshold for the kernel send context
1857 static void set_threshold(struct hfi1_devdata *dd, int scontext, int i)
1861 thres = min(sc_percent_to_threshold(dd->kernel_send_context[scontext],
1863 sc_mtu_to_threshold(dd->kernel_send_context[scontext],
1865 dd->rcd[0]->rcvhdrqentsize));
1866 sc_set_cr_threshold(dd->kernel_send_context[scontext], thres);
1870 * pio_map_init - called when #vls change
1872 * @port: port number
1873 * @num_vls: number of vls
1874 * @vl_scontexts: per vl send context mapping (optional)
1876 * This routine changes the mapping based on the number of vls.
1878 * vl_scontexts is used to specify a non-uniform vl/send context
1879 * loading. NULL implies auto computing the loading and giving each
1880 * VL an uniform distribution of send contexts per VL.
1882 * The auto algorithm computers the sc_per_vl and the number of extra
1883 * send contexts. Any extra send contexts are added from the last VL
1886 * rcu locking is used here to control access to the mapping fields.
1888 * If either the num_vls or num_send_contexts are non-power of 2, the
1889 * array sizes in the struct pio_vl_map and the struct pio_map_elem are
1890 * rounded up to the next highest power of 2 and the first entry is
1891 * reused in a round robin fashion.
1893 * If an error occurs the map change is not done and the mapping is not
1897 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_scontexts)
1900 int extra, sc_per_vl;
1902 int num_kernel_send_contexts = 0;
1903 u8 lvl_scontexts[OPA_MAX_VLS];
1904 struct pio_vl_map *oldmap, *newmap;
1906 if (!vl_scontexts) {
1907 for (i = 0; i < dd->num_send_contexts; i++)
1908 if (dd->send_contexts[i].type == SC_KERNEL)
1909 num_kernel_send_contexts++;
1910 /* truncate divide */
1911 sc_per_vl = num_kernel_send_contexts / num_vls;
1913 extra = num_kernel_send_contexts % num_vls;
1914 vl_scontexts = lvl_scontexts;
1915 /* add extras from last vl down */
1916 for (i = num_vls - 1; i >= 0; i--, extra--)
1917 vl_scontexts[i] = sc_per_vl + (extra > 0 ? 1 : 0);
1920 newmap = kzalloc(sizeof(*newmap) +
1921 roundup_pow_of_two(num_vls) *
1922 sizeof(struct pio_map_elem *),
1926 newmap->actual_vls = num_vls;
1927 newmap->vls = roundup_pow_of_two(num_vls);
1928 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
1929 for (i = 0; i < newmap->vls; i++) {
1930 /* save for wrap around */
1931 int first_scontext = scontext;
1933 if (i < newmap->actual_vls) {
1934 int sz = roundup_pow_of_two(vl_scontexts[i]);
1936 /* only allocate once */
1937 newmap->map[i] = kzalloc(sizeof(*newmap->map[i]) +
1941 if (!newmap->map[i])
1943 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
1945 * assign send contexts and
1946 * adjust credit return threshold
1948 for (j = 0; j < sz; j++) {
1949 if (dd->kernel_send_context[scontext]) {
1950 newmap->map[i]->ksc[j] =
1951 dd->kernel_send_context[scontext];
1952 set_threshold(dd, scontext, i);
1954 if (++scontext >= first_scontext +
1956 /* wrap back to first send context */
1957 scontext = first_scontext;
1960 /* just re-use entry without allocating */
1961 newmap->map[i] = newmap->map[i % num_vls];
1963 scontext = first_scontext + vl_scontexts[i];
1965 /* newmap in hand, save old map */
1966 spin_lock_irq(&dd->pio_map_lock);
1967 oldmap = rcu_dereference_protected(dd->pio_map,
1968 lockdep_is_held(&dd->pio_map_lock));
1970 /* publish newmap */
1971 rcu_assign_pointer(dd->pio_map, newmap);
1973 spin_unlock_irq(&dd->pio_map_lock);
1974 /* success, free any old map after grace period */
1976 call_rcu(&oldmap->list, pio_map_rcu_callback);
1979 /* free any partial allocation */
1980 pio_map_free(newmap);
1984 void free_pio_map(struct hfi1_devdata *dd)
1986 /* Free PIO map if allocated */
1987 if (rcu_access_pointer(dd->pio_map)) {
1988 spin_lock_irq(&dd->pio_map_lock);
1989 pio_map_free(rcu_access_pointer(dd->pio_map));
1990 RCU_INIT_POINTER(dd->pio_map, NULL);
1991 spin_unlock_irq(&dd->pio_map_lock);
1994 kfree(dd->kernel_send_context);
1995 dd->kernel_send_context = NULL;
1998 int init_pervl_scs(struct hfi1_devdata *dd)
2001 u64 mask, all_vl_mask = (u64)0x80ff; /* VLs 0-7, 15 */
2002 u64 data_vls_mask = (u64)0x00ff; /* VLs 0-7 */
2004 struct hfi1_pportdata *ppd = dd->pport;
2006 dd->vld[15].sc = sc_alloc(dd, SC_VL15,
2007 dd->rcd[0]->rcvhdrqentsize, dd->node);
2008 if (!dd->vld[15].sc)
2011 hfi1_init_ctxt(dd->vld[15].sc);
2012 dd->vld[15].mtu = enum_to_mtu(OPA_MTU_2048);
2014 dd->kernel_send_context = kcalloc_node(dd->num_send_contexts,
2015 sizeof(struct send_context *),
2016 GFP_KERNEL, dd->node);
2017 if (!dd->kernel_send_context)
2020 dd->kernel_send_context[0] = dd->vld[15].sc;
2022 for (i = 0; i < num_vls; i++) {
2024 * Since this function does not deal with a specific
2025 * receive context but we need the RcvHdrQ entry size,
2026 * use the size from rcd[0]. It is guaranteed to be
2027 * valid at this point and will remain the same for all
2030 dd->vld[i].sc = sc_alloc(dd, SC_KERNEL,
2031 dd->rcd[0]->rcvhdrqentsize, dd->node);
2034 dd->kernel_send_context[i + 1] = dd->vld[i].sc;
2035 hfi1_init_ctxt(dd->vld[i].sc);
2036 /* non VL15 start with the max MTU */
2037 dd->vld[i].mtu = hfi1_max_mtu;
2039 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++) {
2040 dd->kernel_send_context[i + 1] =
2041 sc_alloc(dd, SC_KERNEL, dd->rcd[0]->rcvhdrqentsize, dd->node);
2042 if (!dd->kernel_send_context[i + 1])
2044 hfi1_init_ctxt(dd->kernel_send_context[i + 1]);
2047 sc_enable(dd->vld[15].sc);
2048 ctxt = dd->vld[15].sc->hw_context;
2049 mask = all_vl_mask & ~(1LL << 15);
2050 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2052 "Using send context %u(%u) for VL15\n",
2053 dd->vld[15].sc->sw_index, ctxt);
2055 for (i = 0; i < num_vls; i++) {
2056 sc_enable(dd->vld[i].sc);
2057 ctxt = dd->vld[i].sc->hw_context;
2058 mask = all_vl_mask & ~(data_vls_mask);
2059 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2061 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++) {
2062 sc_enable(dd->kernel_send_context[i + 1]);
2063 ctxt = dd->kernel_send_context[i + 1]->hw_context;
2064 mask = all_vl_mask & ~(data_vls_mask);
2065 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2068 if (pio_map_init(dd, ppd->port - 1, num_vls, NULL))
2073 for (i = 0; i < num_vls; i++) {
2074 sc_free(dd->vld[i].sc);
2075 dd->vld[i].sc = NULL;
2078 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++)
2079 sc_free(dd->kernel_send_context[i + 1]);
2081 kfree(dd->kernel_send_context);
2082 dd->kernel_send_context = NULL;
2085 sc_free(dd->vld[15].sc);
2089 int init_credit_return(struct hfi1_devdata *dd)
2094 dd->cr_base = kcalloc(
2095 node_affinity.num_possible_nodes,
2096 sizeof(struct credit_return_base),
2102 for_each_node_with_cpus(i) {
2103 int bytes = TXE_NUM_CONTEXTS * sizeof(struct credit_return);
2105 set_dev_node(&dd->pcidev->dev, i);
2106 dd->cr_base[i].va = dma_alloc_coherent(&dd->pcidev->dev,
2108 &dd->cr_base[i].dma,
2110 if (!dd->cr_base[i].va) {
2111 set_dev_node(&dd->pcidev->dev, dd->node);
2113 "Unable to allocate credit return DMA range for NUMA %d\n",
2119 set_dev_node(&dd->pcidev->dev, dd->node);
2126 void free_credit_return(struct hfi1_devdata *dd)
2132 for (i = 0; i < node_affinity.num_possible_nodes; i++) {
2133 if (dd->cr_base[i].va) {
2134 dma_free_coherent(&dd->pcidev->dev,
2136 sizeof(struct credit_return),
2138 dd->cr_base[i].dma);
2145 void seqfile_dump_sci(struct seq_file *s, u32 i,
2146 struct send_context_info *sci)
2148 struct send_context *sc = sci->sc;
2151 seq_printf(s, "SCI %u: type %u base %u credits %u\n",
2152 i, sci->type, sci->base, sci->credits);
2153 seq_printf(s, " flags 0x%x sw_inx %u hw_ctxt %u grp %u\n",
2154 sc->flags, sc->sw_index, sc->hw_context, sc->group);
2155 seq_printf(s, " sr_size %u credits %u sr_head %u sr_tail %u\n",
2156 sc->sr_size, sc->credits, sc->sr_head, sc->sr_tail);
2157 seq_printf(s, " fill %lu free %lu fill_wrap %u alloc_free %lu\n",
2158 sc->fill, sc->free, sc->fill_wrap, sc->alloc_free);
2159 seq_printf(s, " credit_intr_count %u credit_ctrl 0x%llx\n",
2160 sc->credit_intr_count, sc->credit_ctrl);
2161 reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_STATUS));
2162 seq_printf(s, " *hw_free %llu CurrentFree %llu LastReturned %llu\n",
2163 (le64_to_cpu(*sc->hw_free) & CR_COUNTER_SMASK) >>
2165 (reg >> SC(CREDIT_STATUS_CURRENT_FREE_COUNTER_SHIFT)) &
2166 SC(CREDIT_STATUS_CURRENT_FREE_COUNTER_MASK),
2167 reg & SC(CREDIT_STATUS_LAST_RETURNED_COUNTER_SMASK));