2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
36 #include <rdma/ib_verbs.h>
38 #define DRV_NAME "hns_roce"
40 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
42 #define MAC_ADDR_OCTET_NUM 6
43 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
45 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b))
47 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
49 #define HNS_ROCE_BA_SIZE (32 * 4096)
51 /* Hardware specification only for v1 engine */
52 #define HNS_ROCE_MIN_CQE_NUM 0x40
53 #define HNS_ROCE_MIN_WQE_NUM 0x20
55 /* Hardware specification only for v1 engine */
56 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
57 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
59 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
60 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
61 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
62 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
63 #define HNS_ROCE_MIN_CQE_CNT 16
65 #define HNS_ROCE_MAX_IRQ_NUM 34
67 #define HNS_ROCE_COMP_VEC_NUM 32
69 #define HNS_ROCE_AEQE_VEC_NUM 1
70 #define HNS_ROCE_AEQE_OF_VEC_NUM 1
73 #define HNS_ROCE_SL_SHIFT 28
74 #define HNS_ROCE_TCLASS_SHIFT 20
75 #define HNS_ROCE_FLOW_LABLE_MASK 0xfffff
77 #define HNS_ROCE_MAX_PORTS 6
78 #define HNS_ROCE_MAX_GID_NUM 16
79 #define HNS_ROCE_GID_SIZE 16
81 #define HNS_ROCE_HOP_NUM_0 0xff
83 #define BITMAP_NO_RR 0
86 #define MR_TYPE_MR 0x00
87 #define MR_TYPE_DMA 0x03
89 #define PKEY_ID 0xffff
91 #define NODE_DESC_SIZE 64
92 #define DB_REG_OFFSET 0x1000
94 #define SERV_TYPE_RC 0
95 #define SERV_TYPE_RD 1
96 #define SERV_TYPE_UC 2
97 #define SERV_TYPE_UD 3
99 #define PAGES_SHIFT_8 8
100 #define PAGES_SHIFT_16 16
101 #define PAGES_SHIFT_24 24
102 #define PAGES_SHIFT_32 32
104 enum hns_roce_qp_state {
105 HNS_ROCE_QP_STATE_RST,
106 HNS_ROCE_QP_STATE_INIT,
107 HNS_ROCE_QP_STATE_RTR,
108 HNS_ROCE_QP_STATE_RTS,
109 HNS_ROCE_QP_STATE_SQD,
110 HNS_ROCE_QP_STATE_ERR,
111 HNS_ROCE_QP_NUM_STATE,
114 enum hns_roce_event {
115 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
116 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
117 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
118 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
119 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
120 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
121 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
122 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
123 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
124 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
125 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
126 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
127 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
128 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
129 /* 0x10 and 0x11 is unused in currently application case */
130 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
131 HNS_ROCE_EVENT_TYPE_MB = 0x13,
132 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14,
135 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
137 HNS_ROCE_LWQCE_QPC_ERROR = 1,
138 HNS_ROCE_LWQCE_MTU_ERROR = 2,
139 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3,
140 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4,
141 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5,
142 HNS_ROCE_LWQCE_SL_ERROR = 6,
143 HNS_ROCE_LWQCE_PORT_ERROR = 7,
146 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
148 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1,
149 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2,
150 HNS_ROCE_LAVWQE_VA_ERROR = 3,
151 HNS_ROCE_LAVWQE_PD_ERROR = 4,
152 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5,
153 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6,
154 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7,
157 /* DOORBELL overflow subtype */
159 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1,
160 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2,
161 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3,
162 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4,
163 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5,
164 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6,
168 /* RQ&SRQ related operations */
169 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06,
170 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07,
174 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
175 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
178 enum hns_roce_mtt_type {
183 #define HNS_ROCE_CMD_SUCCESS 1
185 #define HNS_ROCE_PORT_DOWN 0
186 #define HNS_ROCE_PORT_UP 1
188 #define HNS_ROCE_MTT_ENTRY_PER_SEG 8
190 #define PAGE_ADDR_SHIFT 12
192 struct hns_roce_uar {
197 struct hns_roce_ucontext {
198 struct ib_ucontext ibucontext;
199 struct hns_roce_uar uar;
207 struct hns_roce_bitmap {
208 /* Bitmap Traversal last a bit which is 1 */
212 unsigned long reserved_top;
215 unsigned long *table;
218 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */
219 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
220 /* Every bit repesent to a partner free/used status in bitmap */
222 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
223 * Bit = 1 represent to idle and available; bit = 0: not available
225 struct hns_roce_buddy {
226 /* Members point to every order level bitmap */
227 unsigned long **bits;
228 /* Represent to avail bits of the order level bitmap */
234 /* For Hardware Entry Memory */
235 struct hns_roce_hem_table {
236 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
238 /* HEM array elment num */
239 unsigned long num_hem;
240 /* HEM entry record obj total num */
241 unsigned long num_obj;
243 unsigned long obj_size;
244 unsigned long table_chunk_size;
247 struct hns_roce_hem **hem;
249 dma_addr_t *bt_l1_dma_addr;
251 dma_addr_t *bt_l0_dma_addr;
254 struct hns_roce_mtt {
255 unsigned long first_seg;
258 enum hns_roce_mtt_type mtt_type;
261 /* Only support 4K page size for mr register */
266 struct ib_umem *umem;
267 u64 iova; /* MR's virtual orignal addr */
268 u64 size; /* Address range of MR */
269 u32 key; /* Key of MR */
270 u32 pd; /* PD num of MR */
271 u32 access;/* Access permission of MR */
272 int enabled; /* MR's active status */
273 int type; /* MR's register type */
274 u64 *pbl_buf;/* MR's PBL space */
275 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */
276 u32 pbl_size;/* PA number in the PBL */
277 u64 pbl_ba;/* page table address */
278 u32 l0_chunk_last_num;/* L0 last number */
279 u32 l1_chunk_last_num;/* L1 last number */
280 u64 **pbl_bt_l2;/* PBL BT L2 */
281 u64 **pbl_bt_l1;/* PBL BT L1 */
282 u64 *pbl_bt_l0;/* PBL BT L0 */
283 dma_addr_t *pbl_l2_dma_addr;/* PBL BT L2 dma addr */
284 dma_addr_t *pbl_l1_dma_addr;/* PBL BT L1 dma addr */
285 dma_addr_t pbl_l0_dma_addr;/* PBL BT L0 dma addr */
286 u32 pbl_ba_pg_sz;/* BT chunk page size */
287 u32 pbl_buf_pg_sz;/* buf chunk page size */
288 u32 pbl_hop_num;/* multi-hop number */
291 struct hns_roce_mr_table {
292 struct hns_roce_bitmap mtpt_bitmap;
293 struct hns_roce_buddy mtt_buddy;
294 struct hns_roce_hem_table mtt_table;
295 struct hns_roce_hem_table mtpt_table;
296 struct hns_roce_buddy mtt_cqe_buddy;
297 struct hns_roce_hem_table mtt_cqe_table;
301 u64 *wrid; /* Work request ID */
303 int wqe_cnt; /* WQE num */
307 int wqe_shift;/* WQE size */
310 void __iomem *db_reg_l;
313 struct hns_roce_sge {
314 int sge_cnt; /* SGE num */
316 int sge_shift;/* SGE size */
319 struct hns_roce_buf_list {
324 struct hns_roce_buf {
325 struct hns_roce_buf_list direct;
326 struct hns_roce_buf_list *page_list;
332 struct hns_roce_cq_buf {
333 struct hns_roce_buf hr_buf;
334 struct hns_roce_mtt hr_mtt;
339 struct hns_roce_cq_buf hr_buf;
341 struct ib_umem *umem;
342 void (*comp)(struct hns_roce_cq *);
343 void (*event)(struct hns_roce_cq *, enum hns_roce_event);
345 struct hns_roce_uar *uar;
348 void __iomem *cq_db_l;
354 struct completion free;
357 struct hns_roce_srq {
362 struct hns_roce_uar_table {
363 struct hns_roce_bitmap bitmap;
366 struct hns_roce_qp_table {
367 struct hns_roce_bitmap bitmap;
369 struct hns_roce_hem_table qp_table;
370 struct hns_roce_hem_table irrl_table;
371 struct hns_roce_hem_table trrl_table;
374 struct hns_roce_cq_table {
375 struct hns_roce_bitmap bitmap;
377 struct radix_tree_root tree;
378 struct hns_roce_hem_table table;
381 struct hns_roce_raq_table {
382 struct hns_roce_buf_list *e_raq_buf;
390 __le32 sl_tclass_flowlabel;
391 u8 dgid[HNS_ROCE_GID_SIZE];
398 struct hns_roce_av av;
401 struct hns_roce_cmd_context {
402 struct completion done;
409 struct hns_roce_cmdq {
410 struct dma_pool *pool;
411 struct mutex hcr_mutex;
412 struct semaphore poll_sem;
414 * Event mode: cmd register mutex protection,
415 * ensure to not exceed max_cmds and user use limit region
417 struct semaphore event_sem;
419 spinlock_t context_lock;
421 struct hns_roce_cmd_context *context;
423 * Result of get integer part
424 * which max_comds compute according a power of 2
428 * Process whether use event mode, init default non-zero
429 * After the event queue of cmd event ready,
430 * can switch into event mode
431 * close device, switch into poll mode(non event mode)
437 struct hns_roce_cmd_mailbox {
446 struct hns_roce_buf hr_buf;
447 struct hns_roce_wq rq;
449 __le32 sq_signal_bits;
451 int sq_max_wqes_per_wr;
453 struct hns_roce_wq sq;
455 struct ib_umem *umem;
456 struct hns_roce_mtt mtt;
466 void (*event)(struct hns_roce_qp *,
467 enum hns_roce_event);
471 struct completion free;
473 struct hns_roce_sge sge;
477 struct hns_roce_sqp {
478 struct hns_roce_qp hr_qp;
481 struct hns_roce_ib_iboe {
483 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
484 struct notifier_block nb;
485 u8 phy_port[HNS_ROCE_MAX_PORTS];
489 struct hns_roce_dev *hr_dev;
490 void __iomem *doorbell;
492 int type_flag;/* Aeq:1 ceq:0 */
500 struct hns_roce_buf_list *buf_list;
503 struct hns_roce_eq_table {
504 struct hns_roce_eq *eq;
505 void __iomem **eqc_base;
508 struct hns_roce_caps {
510 int gid_table_len[HNS_ROCE_MAX_PORTS];
511 int pkey_table_len[HNS_ROCE_MAX_PORTS];
512 int local_ca_ack_delay;
515 u32 max_sq_sg; /* 2 */
516 u32 max_sq_inline; /* 32 */
517 u32 max_rq_sg; /* 2 */
518 int num_qps; /* 256k */
519 u32 max_wqes; /* 16k */
520 u32 max_sq_desc_sz; /* 64 */
521 u32 max_rq_desc_sz; /* 64 */
523 int max_qp_init_rdma;
524 int max_qp_dest_rdma;
530 int num_aeq_vectors; /* 1 */
531 int num_comp_vectors; /* 32 ceq */
532 int num_other_vectors;
553 int ceqe_depth[HNS_ROCE_COMP_VEC_NUM];
577 u32 chunk_sz; /* chunk size in non multihop mode*/
582 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
583 int (*cmq_init)(struct hns_roce_dev *hr_dev);
584 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
585 int (*hw_profile)(struct hns_roce_dev *hr_dev);
586 int (*hw_init)(struct hns_roce_dev *hr_dev);
587 void (*hw_exit)(struct hns_roce_dev *hr_dev);
588 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
589 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
590 u16 token, int event);
591 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
592 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
593 union ib_gid *gid, const struct ib_gid_attr *attr);
594 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
595 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
597 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
598 unsigned long mtpt_idx);
599 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
600 struct hns_roce_mr *mr, int flags, u32 pdn,
601 int mr_access_flags, u64 iova, u64 size,
603 void (*write_cqc)(struct hns_roce_dev *hr_dev,
604 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
605 dma_addr_t dma_handle, int nent, u32 vector);
606 int (*set_hem)(struct hns_roce_dev *hr_dev,
607 struct hns_roce_hem_table *table, int obj, int step_idx);
608 int (*clear_hem)(struct hns_roce_dev *hr_dev,
609 struct hns_roce_hem_table *table, int obj,
611 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
612 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
613 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
614 int attr_mask, enum ib_qp_state cur_state,
615 enum ib_qp_state new_state);
616 int (*destroy_qp)(struct ib_qp *ibqp);
617 int (*post_send)(struct ib_qp *ibqp, struct ib_send_wr *wr,
618 struct ib_send_wr **bad_wr);
619 int (*post_recv)(struct ib_qp *qp, struct ib_recv_wr *recv_wr,
620 struct ib_recv_wr **bad_recv_wr);
621 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
622 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
623 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr);
624 int (*destroy_cq)(struct ib_cq *ibcq);
625 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
628 struct hns_roce_dev {
629 struct ib_device ib_dev;
630 struct platform_device *pdev;
631 struct pci_dev *pci_dev;
633 struct hns_roce_uar priv_uar;
634 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
636 spinlock_t bt_cmd_lock;
637 struct hns_roce_ib_iboe iboe;
639 int irq[HNS_ROCE_MAX_IRQ_NUM];
640 u8 __iomem *reg_base;
641 struct hns_roce_caps caps;
642 struct radix_tree_root qp_table_tree;
644 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM];
649 void __iomem *priv_addr;
651 struct hns_roce_cmdq cmd;
652 struct hns_roce_bitmap pd_bitmap;
653 struct hns_roce_uar_table uar_table;
654 struct hns_roce_mr_table mr_table;
655 struct hns_roce_cq_table cq_table;
656 struct hns_roce_qp_table qp_table;
657 struct hns_roce_eq_table eq_table;
663 dma_addr_t tptr_dma_addr; /*only for hw v1*/
664 u32 tptr_size; /*only for hw v1*/
665 const struct hns_roce_hw *hw;
669 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
671 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
674 static inline struct hns_roce_ucontext
675 *to_hr_ucontext(struct ib_ucontext *ibucontext)
677 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
680 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
682 return container_of(ibpd, struct hns_roce_pd, ibpd);
685 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
687 return container_of(ibah, struct hns_roce_ah, ibah);
690 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
692 return container_of(ibmr, struct hns_roce_mr, ibmr);
695 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
697 return container_of(ibqp, struct hns_roce_qp, ibqp);
700 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
702 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
705 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
707 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
710 static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp)
712 return container_of(hr_qp, struct hns_roce_sqp, hr_qp);
715 static inline void hns_roce_write64_k(__be32 val[2], void __iomem *dest)
717 __raw_writeq(*(u64 *) val, dest);
720 static inline struct hns_roce_qp
721 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
723 return radix_tree_lookup(&hr_dev->qp_table_tree,
724 qpn & (hr_dev->caps.num_qps - 1));
727 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
729 u32 bits_per_long_val = BITS_PER_LONG;
730 u32 page_size = 1 << buf->page_shift;
732 if ((bits_per_long_val == 64 && buf->page_shift == PAGE_SHIFT) ||
734 return (char *)(buf->direct.buf) + offset;
736 return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
737 (offset & (page_size - 1));
740 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
741 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
742 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
743 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
745 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
746 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
747 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
749 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
750 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
752 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
753 struct hns_roce_mtt *mtt);
754 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev,
755 struct hns_roce_mtt *mtt);
756 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
757 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf);
759 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
760 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
761 int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev);
762 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
763 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
765 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
766 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
767 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
768 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
769 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
771 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
772 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
774 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
775 u32 reserved_bot, u32 resetrved_top);
776 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
777 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
778 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
779 int align, unsigned long *obj);
780 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
781 unsigned long obj, int cnt,
784 struct ib_ah *hns_roce_create_ah(struct ib_pd *pd,
785 struct rdma_ah_attr *ah_attr,
786 struct ib_udata *udata);
787 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
788 int hns_roce_destroy_ah(struct ib_ah *ah);
790 struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
791 struct ib_ucontext *context,
792 struct ib_udata *udata);
793 int hns_roce_dealloc_pd(struct ib_pd *pd);
795 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
796 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
797 u64 virt_addr, int access_flags,
798 struct ib_udata *udata);
799 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
800 u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
801 struct ib_udata *udata);
802 int hns_roce_dereg_mr(struct ib_mr *ibmr);
803 int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
804 struct hns_roce_cmd_mailbox *mailbox,
805 unsigned long mpt_index);
806 unsigned long key_to_hw_index(u32 key);
808 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
809 struct hns_roce_buf *buf);
810 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
811 struct hns_roce_buf *buf, u32 page_shift);
813 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
814 struct hns_roce_mtt *mtt, struct ib_umem *umem);
816 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
817 struct ib_qp_init_attr *init_attr,
818 struct ib_udata *udata);
819 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
820 int attr_mask, struct ib_udata *udata);
821 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
822 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
823 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n);
824 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
825 struct ib_cq *ib_cq);
826 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
827 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
828 struct hns_roce_cq *recv_cq);
829 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
830 struct hns_roce_cq *recv_cq);
831 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
832 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
833 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
835 __be32 send_ieth(struct ib_send_wr *wr);
836 int to_hr_qp_type(int qp_type);
838 struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
839 const struct ib_cq_init_attr *attr,
840 struct ib_ucontext *context,
841 struct ib_udata *udata);
843 int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq);
844 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
846 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
847 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
848 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
849 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
850 int hns_roce_init(struct hns_roce_dev *hr_dev);
851 void hns_roce_exit(struct hns_roce_dev *hr_dev);
853 #endif /* _HNS_ROCE_DEVICE_H */