drivers/infiniband/hw/hns/hns_roce_hw_v1.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/platform_device.h>
  34 #include <linux/acpi.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <rdma/ib_umem.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include "hns_roce_cmd.h"
  43 #include "hns_roce_hem.h"
  44 #include "hns_roce_hw_v1.h"
  45
  46 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
  47 {
  48         dseg->lkey = cpu_to_le32(sg->lkey);
  49         dseg->addr = cpu_to_le64(sg->addr);
  50         dseg->len  = cpu_to_le32(sg->length);
  51 }
  52
  53 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
  54                           u32 rkey)
  55 {
  56         rseg->raddr = cpu_to_le64(remote_addr);
  57         rseg->rkey  = cpu_to_le32(rkey);
  58         rseg->len   = 0;
  59 }
  60
  61 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
  62                                  const struct ib_send_wr *wr,
  63                                  const struct ib_send_wr **bad_wr)
  64 {
  65         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  66         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
  67         struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
  68         struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
  69         struct hns_roce_wqe_data_seg *dseg = NULL;
  70         struct hns_roce_qp *qp = to_hr_qp(ibqp);
  71         struct device *dev = &hr_dev->pdev->dev;
  72         struct hns_roce_sq_db sq_db;
  73         int ps_opcode = 0, i = 0;
  74         unsigned long flags = 0;
  75         void *wqe = NULL;
  76         u32 doorbell[2];
  77         int nreq = 0;
  78         u32 ind = 0;
  79         int ret = 0;
  80         u8 *smac;
  81         int loopback;
  82
  83         if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
  84                 ibqp->qp_type != IB_QPT_RC)) {
  85                 dev_err(dev, "un-supported QP type\n");
  86                 *bad_wr = NULL;
  87                 return -EOPNOTSUPP;
  88         }
  89
  90         spin_lock_irqsave(&qp->sq.lock, flags);
  91         ind = qp->sq_next_wqe;
  92         for (nreq = 0; wr; ++nreq, wr = wr->next) {
  93                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
  94                         ret = -ENOMEM;
  95                         *bad_wr = wr;
  96                         goto out;
  97                 }
  98
  99                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 100                         dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
 101                                 wr->num_sge, qp->sq.max_gs);
 102                         ret = -EINVAL;
 103                         *bad_wr = wr;
 104                         goto out;
 105                 }
 106
 107                 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 108                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
 109                                                                       wr->wr_id;
 110
 111                 /* Corresponding to the RC and RD type wqe process separately */
 112                 if (ibqp->qp_type == IB_QPT_GSI) {
 113                         ud_sq_wqe = wqe;
 114                         roce_set_field(ud_sq_wqe->dmac_h,
 115                                        UD_SEND_WQE_U32_4_DMAC_0_M,
 116                                        UD_SEND_WQE_U32_4_DMAC_0_S,
 117                                        ah->av.mac[0]);
 118                         roce_set_field(ud_sq_wqe->dmac_h,
 119                                        UD_SEND_WQE_U32_4_DMAC_1_M,
 120                                        UD_SEND_WQE_U32_4_DMAC_1_S,
 121                                        ah->av.mac[1]);
 122                         roce_set_field(ud_sq_wqe->dmac_h,
 123                                        UD_SEND_WQE_U32_4_DMAC_2_M,
 124                                        UD_SEND_WQE_U32_4_DMAC_2_S,
 125                                        ah->av.mac[2]);
 126                         roce_set_field(ud_sq_wqe->dmac_h,
 127                                        UD_SEND_WQE_U32_4_DMAC_3_M,
 128                                        UD_SEND_WQE_U32_4_DMAC_3_S,
 129                                        ah->av.mac[3]);
 130
 131                         roce_set_field(ud_sq_wqe->u32_8,
 132                                        UD_SEND_WQE_U32_8_DMAC_4_M,
 133                                        UD_SEND_WQE_U32_8_DMAC_4_S,
 134                                        ah->av.mac[4]);
 135                         roce_set_field(ud_sq_wqe->u32_8,
 136                                        UD_SEND_WQE_U32_8_DMAC_5_M,
 137                                        UD_SEND_WQE_U32_8_DMAC_5_S,
 138                                        ah->av.mac[5]);
 139
 140                         smac = (u8 *)hr_dev->dev_addr[qp->port];
 141                         loopback = ether_addr_equal_unaligned(ah->av.mac,
 142                                                               smac) ? 1 : 0;
 143                         roce_set_bit(ud_sq_wqe->u32_8,
 144                                      UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
 145                                      loopback);
 146
 147                         roce_set_field(ud_sq_wqe->u32_8,
 148                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
 149                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
 150                                        HNS_ROCE_WQE_OPCODE_SEND);
 151                         roce_set_field(ud_sq_wqe->u32_8,
 152                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
 153                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
 154                                        2);
 155                         roce_set_bit(ud_sq_wqe->u32_8,
 156                                 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
 157                                 1);
 158
 159                         ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
 160                                 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 161                                 (wr->send_flags & IB_SEND_SOLICITED ?
 162                                 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 163                                 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
 164                                 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
 165
 166                         roce_set_field(ud_sq_wqe->u32_16,
 167                                        UD_SEND_WQE_U32_16_DEST_QP_M,
 168                                        UD_SEND_WQE_U32_16_DEST_QP_S,
 169                                        ud_wr(wr)->remote_qpn);
 170                         roce_set_field(ud_sq_wqe->u32_16,
 171                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
 172                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
 173                                        ah->av.stat_rate);
 174
 175                         roce_set_field(ud_sq_wqe->u32_36,
 176                                        UD_SEND_WQE_U32_36_FLOW_LABEL_M,
 177                                        UD_SEND_WQE_U32_36_FLOW_LABEL_S,
 178                                        ah->av.sl_tclass_flowlabel &
 179                                        HNS_ROCE_FLOW_LABEL_MASK);
 180                         roce_set_field(ud_sq_wqe->u32_36,
 181                                       UD_SEND_WQE_U32_36_PRIORITY_M,
 182                                       UD_SEND_WQE_U32_36_PRIORITY_S,
 183                                       le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
 184                                       HNS_ROCE_SL_SHIFT);
 185                         roce_set_field(ud_sq_wqe->u32_36,
 186                                        UD_SEND_WQE_U32_36_SGID_INDEX_M,
 187                                        UD_SEND_WQE_U32_36_SGID_INDEX_S,
 188                                        hns_get_gid_index(hr_dev, qp->phy_port,
 189                                                          ah->av.gid_index));
 190
 191                         roce_set_field(ud_sq_wqe->u32_40,
 192                                        UD_SEND_WQE_U32_40_HOP_LIMIT_M,
 193                                        UD_SEND_WQE_U32_40_HOP_LIMIT_S,
 194                                        ah->av.hop_limit);
 195                         roce_set_field(ud_sq_wqe->u32_40,
 196                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
 197                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
 198                                        ah->av.sl_tclass_flowlabel >>
 199                                        HNS_ROCE_TCLASS_SHIFT);
 200
 201                         memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
 202
 203                         ud_sq_wqe->va0_l =
 204                                        cpu_to_le32((u32)wr->sg_list[0].addr);
 205                         ud_sq_wqe->va0_h =
 206                                        cpu_to_le32((wr->sg_list[0].addr) >> 32);
 207                         ud_sq_wqe->l_key0 =
 208                                        cpu_to_le32(wr->sg_list[0].lkey);
 209
 210                         ud_sq_wqe->va1_l =
 211                                        cpu_to_le32((u32)wr->sg_list[1].addr);
 212                         ud_sq_wqe->va1_h =
 213                                        cpu_to_le32((wr->sg_list[1].addr) >> 32);
 214                         ud_sq_wqe->l_key1 =
 215                                        cpu_to_le32(wr->sg_list[1].lkey);
 216                         ind++;
 217                 } else if (ibqp->qp_type == IB_QPT_RC) {
 218                         u32 tmp_len = 0;
 219
 220                         ctrl = wqe;
 221                         memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
 222                         for (i = 0; i < wr->num_sge; i++)
 223                                 tmp_len += wr->sg_list[i].length;
 224
 225                         ctrl->msg_length =
 226                           cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
 227
 228                         ctrl->sgl_pa_h = 0;
 229                         ctrl->flag = 0;
 230
 231                         switch (wr->opcode) {
 232                         case IB_WR_SEND_WITH_IMM:
 233                         case IB_WR_RDMA_WRITE_WITH_IMM:
 234                                 ctrl->imm_data = wr->ex.imm_data;
 235                                 break;
 236                         case IB_WR_SEND_WITH_INV:
 237                                 ctrl->inv_key =
 238                                         cpu_to_le32(wr->ex.invalidate_rkey);
 239                                 break;
 240                         default:
 241                                 ctrl->imm_data = 0;
 242                                 break;
 243                         }
 244
 245                         /*Ctrl field, ctrl set type: sig, solic, imm, fence */
 246                         /* SO wait for conforming application scenarios */
 247                         ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
 248                                       cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 249                                       (wr->send_flags & IB_SEND_SOLICITED ?
 250                                       cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 251                                       ((wr->opcode == IB_WR_SEND_WITH_IMM ||
 252                                       wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
 253                                       cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
 254                                       (wr->send_flags & IB_SEND_FENCE ?
 255                                       (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
 256
 257                         wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
 258
 259                         switch (wr->opcode) {
 260                         case IB_WR_RDMA_READ:
 261                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
 262                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 263                                                rdma_wr(wr)->rkey);
 264                                 break;
 265                         case IB_WR_RDMA_WRITE:
 266                         case IB_WR_RDMA_WRITE_WITH_IMM:
 267                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
 268                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 269                                               rdma_wr(wr)->rkey);
 270                                 break;
 271                         case IB_WR_SEND:
 272                         case IB_WR_SEND_WITH_INV:
 273                         case IB_WR_SEND_WITH_IMM:
 274                                 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
 275                                 break;
 276                         case IB_WR_LOCAL_INV:
 277                                 break;
 278                         case IB_WR_ATOMIC_CMP_AND_SWP:
 279                         case IB_WR_ATOMIC_FETCH_AND_ADD:
 280                         case IB_WR_LSO:
 281                         default:
 282                                 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
 283                                 break;
 284                         }
 285                         ctrl->flag |= cpu_to_le32(ps_opcode);
 286                         wqe += sizeof(struct hns_roce_wqe_raddr_seg);
 287
 288                         dseg = wqe;
 289                         if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
 290                                 if (le32_to_cpu(ctrl->msg_length) >
 291                                     hr_dev->caps.max_sq_inline) {
 292                                         ret = -EINVAL;
 293                                         *bad_wr = wr;
 294                                         dev_err(dev, "inline len(1-%d)=%d, illegal",
 295                                                 ctrl->msg_length,
 296                                                 hr_dev->caps.max_sq_inline);
 297                                         goto out;
 298                                 }
 299                                 for (i = 0; i < wr->num_sge; i++) {
 300                                         memcpy(wqe, ((void *) (uintptr_t)
 301                                                wr->sg_list[i].addr),
 302                                                wr->sg_list[i].length);
 303                                         wqe += wr->sg_list[i].length;
 304                                 }
 305                                 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
 306                         } else {
 307                                 /*sqe num is two */
 308                                 for (i = 0; i < wr->num_sge; i++)
 309                                         set_data_seg(dseg + i, wr->sg_list + i);
 310
 311                                 ctrl->flag |= cpu_to_le32(wr->num_sge <<
 312                                               HNS_ROCE_WQE_SGE_NUM_BIT);
 313                         }
 314                         ind++;
 315                 }
 316         }
 317
 318 out:
 319         /* Set DB return */
 320         if (likely(nreq)) {
 321                 qp->sq.head += nreq;
 322                 /* Memory barrier */
 323                 wmb();
 324
 325                 sq_db.u32_4 = 0;
 326                 sq_db.u32_8 = 0;
 327                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
 328                                SQ_DOORBELL_U32_4_SQ_HEAD_S,
 329                               (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
 330                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
 331                                SQ_DOORBELL_U32_4_SL_S, qp->sl);
 332                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
 333                                SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
 334                 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
 335                                SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
 336                 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
 337
 338                 doorbell[0] = le32_to_cpu(sq_db.u32_4);
 339                 doorbell[1] = le32_to_cpu(sq_db.u32_8);
 340
 341                 hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l);
 342                 qp->sq_next_wqe = ind;
 343         }
 344
 345         spin_unlock_irqrestore(&qp->sq.lock, flags);
 346
 347         return ret;
 348 }
 349
 350 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
 351                                  const struct ib_recv_wr *wr,
 352                                  const struct ib_recv_wr **bad_wr)
 353 {
 354         int ret = 0;
 355         int nreq = 0;
 356         int ind = 0;
 357         int i = 0;
 358         u32 reg_val;
 359         unsigned long flags = 0;
 360         struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
 361         struct hns_roce_wqe_data_seg *scat = NULL;
 362         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 363         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 364         struct device *dev = &hr_dev->pdev->dev;
 365         struct hns_roce_rq_db rq_db;
 366         uint32_t doorbell[2] = {0};
 367
 368         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 369         ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
 370
 371         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 372                 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
 373                         hr_qp->ibqp.recv_cq)) {
 374                         ret = -ENOMEM;
 375                         *bad_wr = wr;
 376                         goto out;
 377                 }
 378
 379                 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
 380                         dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
 381                                 wr->num_sge, hr_qp->rq.max_gs);
 382                         ret = -EINVAL;
 383                         *bad_wr = wr;
 384                         goto out;
 385                 }
 386
 387                 ctrl = get_recv_wqe(hr_qp, ind);
 388
 389                 roce_set_field(ctrl->rwqe_byte_12,
 390                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
 391                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
 392                                wr->num_sge);
 393
 394                 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
 395
 396                 for (i = 0; i < wr->num_sge; i++)
 397                         set_data_seg(scat + i, wr->sg_list + i);
 398
 399                 hr_qp->rq.wrid[ind] = wr->wr_id;
 400
 401                 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
 402         }
 403
 404 out:
 405         if (likely(nreq)) {
 406                 hr_qp->rq.head += nreq;
 407                 /* Memory barrier */
 408                 wmb();
 409
 410                 if (ibqp->qp_type == IB_QPT_GSI) {
 411                         __le32 tmp;
 412
 413                         /* SW update GSI rq header */
 414                         reg_val = roce_read(to_hr_dev(ibqp->device),
 415                                             ROCEE_QP1C_CFG3_0_REG +
 416                                             QP1C_CFGN_OFFSET * hr_qp->phy_port);
 417                         tmp = cpu_to_le32(reg_val);
 418                         roce_set_field(tmp,
 419                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
 420                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
 421                                        hr_qp->rq.head);
 422                         reg_val = le32_to_cpu(tmp);
 423                         roce_write(to_hr_dev(ibqp->device),
 424                                    ROCEE_QP1C_CFG3_0_REG +
 425                                    QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
 426                 } else {
 427                         rq_db.u32_4 = 0;
 428                         rq_db.u32_8 = 0;
 429
 430                         roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
 431                                        RQ_DOORBELL_U32_4_RQ_HEAD_S,
 432                                        hr_qp->rq.head);
 433                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
 434                                        RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
 435                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
 436                                        RQ_DOORBELL_U32_8_CMD_S, 1);
 437                         roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
 438                                      1);
 439
 440                         doorbell[0] = le32_to_cpu(rq_db.u32_4);
 441                         doorbell[1] = le32_to_cpu(rq_db.u32_8);
 442
 443                         hns_roce_write64_k((__le32 *)doorbell,
 444                                            hr_qp->rq.db_reg_l);
 445                 }
 446         }
 447         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 448
 449         return ret;
 450 }
 451
 452 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
 453                                        int sdb_mode, int odb_mode)
 454 {
 455         __le32 tmp;
 456         u32 val;
 457
 458         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 459         tmp = cpu_to_le32(val);
 460         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
 461         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
 462         val = le32_to_cpu(tmp);
 463         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 464 }
 465
 466 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
 467                                      u32 odb_mode)
 468 {
 469         __le32 tmp;
 470         u32 val;
 471
 472         /* Configure SDB/ODB extend mode */
 473         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 474         tmp = cpu_to_le32(val);
 475         roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
 476         roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
 477         val = le32_to_cpu(tmp);
 478         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 479 }
 480
 481 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
 482                              u32 sdb_alful)
 483 {
 484         __le32 tmp;
 485         u32 val;
 486
 487         /* Configure SDB */
 488         val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
 489         tmp = cpu_to_le32(val);
 490         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
 491                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
 492         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
 493                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
 494         val = le32_to_cpu(tmp);
 495         roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
 496 }
 497
 498 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
 499                              u32 odb_alful)
 500 {
 501         __le32 tmp;
 502         u32 val;
 503
 504         /* Configure ODB */
 505         val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
 506         tmp = cpu_to_le32(val);
 507         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
 508                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
 509         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
 510                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
 511         val = le32_to_cpu(tmp);
 512         roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
 513 }
 514
 515 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
 516                                  u32 ext_sdb_alful)
 517 {
 518         struct device *dev = &hr_dev->pdev->dev;
 519         struct hns_roce_v1_priv *priv;
 520         struct hns_roce_db_table *db;
 521         dma_addr_t sdb_dma_addr;
 522         __le32 tmp;
 523         u32 val;
 524
 525         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 526         db = &priv->db_table;
 527
 528         /* Configure extend SDB threshold */
 529         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
 530         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
 531
 532         /* Configure extend SDB base addr */
 533         sdb_dma_addr = db->ext_db->sdb_buf_list->map;
 534         roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
 535
 536         /* Configure extend SDB depth */
 537         val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
 538         tmp = cpu_to_le32(val);
 539         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
 540                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
 541                        db->ext_db->esdb_dep);
 542         /*
 543          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
 544          * using 4K page, and shift more 32 because of
 545          * caculating the high 32 bit value evaluated to hardware.
 546          */
 547         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
 548                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
 549         val = le32_to_cpu(tmp);
 550         roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
 551
 552         dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
 553         dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
 554                 ext_sdb_alept, ext_sdb_alful);
 555 }
 556
 557 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
 558                                  u32 ext_odb_alful)
 559 {
 560         struct device *dev = &hr_dev->pdev->dev;
 561         struct hns_roce_v1_priv *priv;
 562         struct hns_roce_db_table *db;
 563         dma_addr_t odb_dma_addr;
 564         __le32 tmp;
 565         u32 val;
 566
 567         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 568         db = &priv->db_table;
 569
 570         /* Configure extend ODB threshold */
 571         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
 572         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
 573
 574         /* Configure extend ODB base addr */
 575         odb_dma_addr = db->ext_db->odb_buf_list->map;
 576         roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
 577
 578         /* Configure extend ODB depth */
 579         val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
 580         tmp = cpu_to_le32(val);
 581         roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
 582                        ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
 583                        db->ext_db->eodb_dep);
 584         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
 585                        ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
 586                        db->ext_db->eodb_dep);
 587         val = le32_to_cpu(tmp);
 588         roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
 589
 590         dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
 591         dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
 592                 ext_odb_alept, ext_odb_alful);
 593 }
 594
 595 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
 596                                 u32 odb_ext_mod)
 597 {
 598         struct device *dev = &hr_dev->pdev->dev;
 599         struct hns_roce_v1_priv *priv;
 600         struct hns_roce_db_table *db;
 601         dma_addr_t sdb_dma_addr;
 602         dma_addr_t odb_dma_addr;
 603         int ret = 0;
 604
 605         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 606         db = &priv->db_table;
 607
 608         db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
 609         if (!db->ext_db)
 610                 return -ENOMEM;
 611
 612         if (sdb_ext_mod) {
 613                 db->ext_db->sdb_buf_list = kmalloc(
 614                                 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
 615                 if (!db->ext_db->sdb_buf_list) {
 616                         ret = -ENOMEM;
 617                         goto ext_sdb_buf_fail_out;
 618                 }
 619
 620                 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
 621                                                      HNS_ROCE_V1_EXT_SDB_SIZE,
 622                                                      &sdb_dma_addr, GFP_KERNEL);
 623                 if (!db->ext_db->sdb_buf_list->buf) {
 624                         ret = -ENOMEM;
 625                         goto alloc_sq_db_buf_fail;
 626                 }
 627                 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
 628
 629                 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
 630                 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
 631                                      HNS_ROCE_V1_EXT_SDB_ALFUL);
 632         } else
 633                 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
 634                                  HNS_ROCE_V1_SDB_ALFUL);
 635
 636         if (odb_ext_mod) {
 637                 db->ext_db->odb_buf_list = kmalloc(
 638                                 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
 639                 if (!db->ext_db->odb_buf_list) {
 640                         ret = -ENOMEM;
 641                         goto ext_odb_buf_fail_out;
 642                 }
 643
 644                 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
 645                                                      HNS_ROCE_V1_EXT_ODB_SIZE,
 646                                                      &odb_dma_addr, GFP_KERNEL);
 647                 if (!db->ext_db->odb_buf_list->buf) {
 648                         ret = -ENOMEM;
 649                         goto alloc_otr_db_buf_fail;
 650                 }
 651                 db->ext_db->odb_buf_list->map = odb_dma_addr;
 652
 653                 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
 654                 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
 655                                      HNS_ROCE_V1_EXT_ODB_ALFUL);
 656         } else
 657                 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
 658                                  HNS_ROCE_V1_ODB_ALFUL);
 659
 660         hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
 661
 662         return 0;
 663
 664 alloc_otr_db_buf_fail:
 665         kfree(db->ext_db->odb_buf_list);
 666
 667 ext_odb_buf_fail_out:
 668         if (sdb_ext_mod) {
 669                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
 670                                   db->ext_db->sdb_buf_list->buf,
 671                                   db->ext_db->sdb_buf_list->map);
 672         }
 673
 674 alloc_sq_db_buf_fail:
 675         if (sdb_ext_mod)
 676                 kfree(db->ext_db->sdb_buf_list);
 677
 678 ext_sdb_buf_fail_out:
 679         kfree(db->ext_db);
 680         return ret;
 681 }
 682
 683 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
 684                                                     struct ib_pd *pd)
 685 {
 686         struct device *dev = &hr_dev->pdev->dev;
 687         struct ib_qp_init_attr init_attr;
 688         struct ib_qp *qp;
 689
 690         memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
 691         init_attr.qp_type               = IB_QPT_RC;
 692         init_attr.sq_sig_type           = IB_SIGNAL_ALL_WR;
 693         init_attr.cap.max_recv_wr       = HNS_ROCE_MIN_WQE_NUM;
 694         init_attr.cap.max_send_wr       = HNS_ROCE_MIN_WQE_NUM;
 695
 696         qp = hns_roce_create_qp(pd, &init_attr, NULL);
 697         if (IS_ERR(qp)) {
 698                 dev_err(dev, "Create loop qp for mr free failed!");
 699                 return NULL;
 700         }
 701
 702         return to_hr_qp(qp);
 703 }
 704
 705 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 706 {
 707         struct hns_roce_caps *caps = &hr_dev->caps;
 708         struct device *dev = &hr_dev->pdev->dev;
 709         struct ib_cq_init_attr cq_init_attr;
 710         struct hns_roce_free_mr *free_mr;
 711         struct ib_qp_attr attr = { 0 };
 712         struct hns_roce_v1_priv *priv;
 713         struct hns_roce_qp *hr_qp;
 714         struct ib_device *ibdev;
 715         struct ib_cq *cq;
 716         struct ib_pd *pd;
 717         union ib_gid dgid;
 718         u64 subnet_prefix;
 719         int attr_mask = 0;
 720         int ret = -ENOMEM;
 721         int i, j;
 722         u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
 723         u8 phy_port;
 724         u8 port = 0;
 725         u8 sl;
 726
 727         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 728         free_mr = &priv->free_mr;
 729
 730         /* Reserved cq for loop qp */
 731         cq_init_attr.cqe                = HNS_ROCE_MIN_WQE_NUM * 2;
 732         cq_init_attr.comp_vector        = 0;
 733         cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
 734         if (IS_ERR(cq)) {
 735                 dev_err(dev, "Create cq for reserved loop qp failed!");
 736                 return -ENOMEM;
 737         }
 738         free_mr->mr_free_cq = to_hr_cq(cq);
 739         free_mr->mr_free_cq->ib_cq.device               = &hr_dev->ib_dev;
 740         free_mr->mr_free_cq->ib_cq.uobject              = NULL;
 741         free_mr->mr_free_cq->ib_cq.comp_handler         = NULL;
 742         free_mr->mr_free_cq->ib_cq.event_handler        = NULL;
 743         free_mr->mr_free_cq->ib_cq.cq_context           = NULL;
 744         atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
 745
 746         ibdev = &hr_dev->ib_dev;
 747         pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
 748         if (!pd)
 749                 goto alloc_mem_failed;
 750
 751         pd->device  = ibdev;
 752         ret = hns_roce_alloc_pd(pd, NULL, NULL);
 753         if (ret)
 754                 goto alloc_pd_failed;
 755
 756         free_mr->mr_free_pd = to_hr_pd(pd);
 757         free_mr->mr_free_pd->ibpd.device  = &hr_dev->ib_dev;
 758         free_mr->mr_free_pd->ibpd.uobject = NULL;
 759         free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
 760         atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
 761
 762         attr.qp_access_flags    = IB_ACCESS_REMOTE_WRITE;
 763         attr.pkey_index         = 0;
 764         attr.min_rnr_timer      = 0;
 765         /* Disable read ability */
 766         attr.max_dest_rd_atomic = 0;
 767         attr.max_rd_atomic      = 0;
 768         /* Use arbitrary values as rq_psn and sq_psn */
 769         attr.rq_psn             = 0x0808;
 770         attr.sq_psn             = 0x0808;
 771         attr.retry_cnt          = 7;
 772         attr.rnr_retry          = 7;
 773         attr.timeout            = 0x12;
 774         attr.path_mtu           = IB_MTU_256;
 775         attr.ah_attr.type       = RDMA_AH_ATTR_TYPE_ROCE;
 776         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
 777         rdma_ah_set_static_rate(&attr.ah_attr, 3);
 778
 779         subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 780         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 781                 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
 782                                 (i % HNS_ROCE_MAX_PORTS);
 783                 sl = i / HNS_ROCE_MAX_PORTS;
 784
 785                 for (j = 0; j < caps->num_ports; j++) {
 786                         if (hr_dev->iboe.phy_port[j] == phy_port) {
 787                                 queue_en[i] = 1;
 788                                 port = j;
 789                                 break;
 790                         }
 791                 }
 792
 793                 if (!queue_en[i])
 794                         continue;
 795
 796                 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
 797                 if (!free_mr->mr_free_qp[i]) {
 798                         dev_err(dev, "Create loop qp failed!\n");
 799                         ret = -ENOMEM;
 800                         goto create_lp_qp_failed;
 801                 }
 802                 hr_qp = free_mr->mr_free_qp[i];
 803
 804                 hr_qp->port             = port;
 805                 hr_qp->phy_port         = phy_port;
 806                 hr_qp->ibqp.qp_type     = IB_QPT_RC;
 807                 hr_qp->ibqp.device      = &hr_dev->ib_dev;
 808                 hr_qp->ibqp.uobject     = NULL;
 809                 atomic_set(&hr_qp->ibqp.usecnt, 0);
 810                 hr_qp->ibqp.pd          = pd;
 811                 hr_qp->ibqp.recv_cq     = cq;
 812                 hr_qp->ibqp.send_cq     = cq;
 813
 814                 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
 815                 rdma_ah_set_sl(&attr.ah_attr, sl);
 816                 attr.port_num           = port + 1;
 817
 818                 attr.dest_qp_num        = hr_qp->qpn;
 819                 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
 820                        hr_dev->dev_addr[port],
 821                        MAC_ADDR_OCTET_NUM);
 822
 823                 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
 824                 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
 825                 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
 826                 dgid.raw[11] = 0xff;
 827                 dgid.raw[12] = 0xfe;
 828                 dgid.raw[8] ^= 2;
 829                 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
 830
 831                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 832                                             IB_QPS_RESET, IB_QPS_INIT);
 833                 if (ret) {
 834                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 835                         goto create_lp_qp_failed;
 836                 }
 837
 838                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
 839                                             IB_QPS_INIT, IB_QPS_RTR);
 840                 if (ret) {
 841                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 842                         goto create_lp_qp_failed;
 843                 }
 844
 845                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 846                                             IB_QPS_RTR, IB_QPS_RTS);
 847                 if (ret) {
 848                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 849                         goto create_lp_qp_failed;
 850                 }
 851         }
 852
 853         return 0;
 854
 855 create_lp_qp_failed:
 856         for (i -= 1; i >= 0; i--) {
 857                 hr_qp = free_mr->mr_free_qp[i];
 858                 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
 859                         dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
 860         }
 861
 862         hns_roce_dealloc_pd(pd);
 863
 864 alloc_pd_failed:
 865         kfree(pd);
 866
 867 alloc_mem_failed:
 868         if (hns_roce_ib_destroy_cq(cq))
 869                 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
 870
 871         return ret;
 872 }
 873
 874 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
 875 {
 876         struct device *dev = &hr_dev->pdev->dev;
 877         struct hns_roce_free_mr *free_mr;
 878         struct hns_roce_v1_priv *priv;
 879         struct hns_roce_qp *hr_qp;
 880         int ret;
 881         int i;
 882
 883         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 884         free_mr = &priv->free_mr;
 885
 886         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 887                 hr_qp = free_mr->mr_free_qp[i];
 888                 if (!hr_qp)
 889                         continue;
 890
 891                 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
 892                 if (ret)
 893                         dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
 894                                 i, ret);
 895         }
 896
 897         ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
 898         if (ret)
 899                 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
 900
 901         hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
 902 }
 903
 904 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
 905 {
 906         struct device *dev = &hr_dev->pdev->dev;
 907         struct hns_roce_v1_priv *priv;
 908         struct hns_roce_db_table *db;
 909         u32 sdb_ext_mod;
 910         u32 odb_ext_mod;
 911         u32 sdb_evt_mod;
 912         u32 odb_evt_mod;
 913         int ret = 0;
 914
 915         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 916         db = &priv->db_table;
 917
 918         memset(db, 0, sizeof(*db));
 919
 920         /* Default DB mode */
 921         sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
 922         odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
 923         sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
 924         odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
 925
 926         db->sdb_ext_mod = sdb_ext_mod;
 927         db->odb_ext_mod = odb_ext_mod;
 928
 929         /* Init extend DB */
 930         ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
 931         if (ret) {
 932                 dev_err(dev, "Failed in extend DB configuration.\n");
 933                 return ret;
 934         }
 935
 936         hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
 937
 938         return 0;
 939 }
 940
 941 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
 942 {
 943         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 944         struct hns_roce_dev *hr_dev;
 945
 946         lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
 947                                   work);
 948         hr_dev = to_hr_dev(lp_qp_work->ib_dev);
 949
 950         hns_roce_v1_release_lp_qp(hr_dev);
 951
 952         if (hns_roce_v1_rsv_lp_qp(hr_dev))
 953                 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
 954
 955         if (lp_qp_work->comp_flag)
 956                 complete(lp_qp_work->comp);
 957
 958         kfree(lp_qp_work);
 959 }
 960
 961 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
 962 {
 963         struct device *dev = &hr_dev->pdev->dev;
 964         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 965         struct hns_roce_free_mr *free_mr;
 966         struct hns_roce_v1_priv *priv;
 967         struct completion comp;
 968         unsigned long end =
 969           msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
 970
 971         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 972         free_mr = &priv->free_mr;
 973
 974         lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
 975                              GFP_KERNEL);
 976         if (!lp_qp_work)
 977                 return -ENOMEM;
 978
 979         INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
 980
 981         lp_qp_work->ib_dev = &(hr_dev->ib_dev);
 982         lp_qp_work->comp = &comp;
 983         lp_qp_work->comp_flag = 1;
 984
 985         init_completion(lp_qp_work->comp);
 986
 987         queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
 988
 989         while (time_before_eq(jiffies, end)) {
 990                 if (try_wait_for_completion(&comp))
 991                         return 0;
 992                 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
 993         }
 994
 995         lp_qp_work->comp_flag = 0;
 996         if (try_wait_for_completion(&comp))
 997                 return 0;
 998
 999         dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
1000         return -ETIMEDOUT;
1001 }
1002
1003 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
1004 {
1005         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1006         struct device *dev = &hr_dev->pdev->dev;
1007         struct ib_send_wr send_wr;
1008         const struct ib_send_wr *bad_wr;
1009         int ret;
1010
1011         memset(&send_wr, 0, sizeof(send_wr));
1012         send_wr.next    = NULL;
1013         send_wr.num_sge = 0;
1014         send_wr.send_flags = 0;
1015         send_wr.sg_list = NULL;
1016         send_wr.wr_id   = (unsigned long long)&send_wr;
1017         send_wr.opcode  = IB_WR_RDMA_WRITE;
1018
1019         ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1020         if (ret) {
1021                 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1022                 return ret;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1029 {
1030         struct hns_roce_mr_free_work *mr_work;
1031         struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1032         struct hns_roce_free_mr *free_mr;
1033         struct hns_roce_cq *mr_free_cq;
1034         struct hns_roce_v1_priv *priv;
1035         struct hns_roce_dev *hr_dev;
1036         struct hns_roce_mr *hr_mr;
1037         struct hns_roce_qp *hr_qp;
1038         struct device *dev;
1039         unsigned long end =
1040                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1041         int i;
1042         int ret;
1043         int ne = 0;
1044
1045         mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1046         hr_mr = (struct hns_roce_mr *)mr_work->mr;
1047         hr_dev = to_hr_dev(mr_work->ib_dev);
1048         dev = &hr_dev->pdev->dev;
1049
1050         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1051         free_mr = &priv->free_mr;
1052         mr_free_cq = free_mr->mr_free_cq;
1053
1054         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1055                 hr_qp = free_mr->mr_free_qp[i];
1056                 if (!hr_qp)
1057                         continue;
1058                 ne++;
1059
1060                 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1061                 if (ret) {
1062                         dev_err(dev,
1063                              "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1064                              hr_qp->qpn, ret);
1065                         goto free_work;
1066                 }
1067         }
1068
1069         if (!ne) {
1070                 dev_err(dev, "Reserved loop qp is absent!\n");
1071                 goto free_work;
1072         }
1073
1074         do {
1075                 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1076                 if (ret < 0 && hr_qp) {
1077                         dev_err(dev,
1078                            "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1079                            hr_qp->qpn, ret, hr_mr->key, ne);
1080                         goto free_work;
1081                 }
1082                 ne -= ret;
1083                 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1084                              (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1085         } while (ne && time_before_eq(jiffies, end));
1086
1087         if (ne != 0)
1088                 dev_err(dev,
1089                         "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1090                         hr_mr->key, ne);
1091
1092 free_work:
1093         if (mr_work->comp_flag)
1094                 complete(mr_work->comp);
1095         kfree(mr_work);
1096 }
1097
1098 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1099                                 struct hns_roce_mr *mr)
1100 {
1101         struct device *dev = &hr_dev->pdev->dev;
1102         struct hns_roce_mr_free_work *mr_work;
1103         struct hns_roce_free_mr *free_mr;
1104         struct hns_roce_v1_priv *priv;
1105         struct completion comp;
1106         unsigned long end =
1107                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1108         unsigned long start = jiffies;
1109         int npages;
1110         int ret = 0;
1111
1112         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1113         free_mr = &priv->free_mr;
1114
1115         if (mr->enabled) {
1116                 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1117                                        & (hr_dev->caps.num_mtpts - 1)))
1118                         dev_warn(dev, "HW2SW_MPT failed!\n");
1119         }
1120
1121         mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1122         if (!mr_work) {
1123                 ret = -ENOMEM;
1124                 goto free_mr;
1125         }
1126
1127         INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1128
1129         mr_work->ib_dev = &(hr_dev->ib_dev);
1130         mr_work->comp = &comp;
1131         mr_work->comp_flag = 1;
1132         mr_work->mr = (void *)mr;
1133         init_completion(mr_work->comp);
1134
1135         queue_work(free_mr->free_mr_wq, &(mr_work->work));
1136
1137         while (time_before_eq(jiffies, end)) {
1138                 if (try_wait_for_completion(&comp))
1139                         goto free_mr;
1140                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1141         }
1142
1143         mr_work->comp_flag = 0;
1144         if (try_wait_for_completion(&comp))
1145                 goto free_mr;
1146
1147         dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1148         ret = -ETIMEDOUT;
1149
1150 free_mr:
1151         dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1152                 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1153
1154         if (mr->size != ~0ULL) {
1155                 npages = ib_umem_page_count(mr->umem);
1156                 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1157                                   mr->pbl_dma_addr);
1158         }
1159
1160         hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1161                              key_to_hw_index(mr->key), 0);
1162
1163         if (mr->umem)
1164                 ib_umem_release(mr->umem);
1165
1166         kfree(mr);
1167
1168         return ret;
1169 }
1170
1171 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1172 {
1173         struct device *dev = &hr_dev->pdev->dev;
1174         struct hns_roce_v1_priv *priv;
1175         struct hns_roce_db_table *db;
1176
1177         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1178         db = &priv->db_table;
1179
1180         if (db->sdb_ext_mod) {
1181                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1182                                   db->ext_db->sdb_buf_list->buf,
1183                                   db->ext_db->sdb_buf_list->map);
1184                 kfree(db->ext_db->sdb_buf_list);
1185         }
1186
1187         if (db->odb_ext_mod) {
1188                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1189                                   db->ext_db->odb_buf_list->buf,
1190                                   db->ext_db->odb_buf_list->map);
1191                 kfree(db->ext_db->odb_buf_list);
1192         }
1193
1194         kfree(db->ext_db);
1195 }
1196
1197 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1198 {
1199         int ret;
1200         u32 val;
1201         __le32 tmp;
1202         int raq_shift = 0;
1203         dma_addr_t addr;
1204         struct hns_roce_v1_priv *priv;
1205         struct hns_roce_raq_table *raq;
1206         struct device *dev = &hr_dev->pdev->dev;
1207
1208         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1209         raq = &priv->raq_table;
1210
1211         raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1212         if (!raq->e_raq_buf)
1213                 return -ENOMEM;
1214
1215         raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1216                                                  &addr, GFP_KERNEL);
1217         if (!raq->e_raq_buf->buf) {
1218                 ret = -ENOMEM;
1219                 goto err_dma_alloc_raq;
1220         }
1221         raq->e_raq_buf->map = addr;
1222
1223         /* Configure raq extended address. 48bit 4K align*/
1224         roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1225
1226         /* Configure raq_shift */
1227         raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1228         val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1229         tmp = cpu_to_le32(val);
1230         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1231                        ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1232         /*
1233          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1234          * using 4K page, and shift more 32 because of
1235          * caculating the high 32 bit value evaluated to hardware.
1236          */
1237         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1238                        ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1239                        raq->e_raq_buf->map >> 44);
1240         val = le32_to_cpu(tmp);
1241         roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1242         dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1243
1244         /* Configure raq threshold */
1245         val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1246         tmp = cpu_to_le32(val);
1247         roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1248                        ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1249                        HNS_ROCE_V1_EXT_RAQ_WF);
1250         val = le32_to_cpu(tmp);
1251         roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1252         dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1253
1254         /* Enable extend raq */
1255         val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1256         tmp = cpu_to_le32(val);
1257         roce_set_field(tmp,
1258                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1259                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1260                        POL_TIME_INTERVAL_VAL);
1261         roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1262         roce_set_field(tmp,
1263                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1264                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1265                        2);
1266         roce_set_bit(tmp,
1267                      ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1268         val = le32_to_cpu(tmp);
1269         roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1270         dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1271
1272         /* Enable raq drop */
1273         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1274         tmp = cpu_to_le32(val);
1275         roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1276         val = le32_to_cpu(tmp);
1277         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1278         dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1279
1280         return 0;
1281
1282 err_dma_alloc_raq:
1283         kfree(raq->e_raq_buf);
1284         return ret;
1285 }
1286
1287 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1288 {
1289         struct device *dev = &hr_dev->pdev->dev;
1290         struct hns_roce_v1_priv *priv;
1291         struct hns_roce_raq_table *raq;
1292
1293         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1294         raq = &priv->raq_table;
1295
1296         dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1297                           raq->e_raq_buf->map);
1298         kfree(raq->e_raq_buf);
1299 }
1300
1301 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1302 {
1303         __le32 tmp;
1304         u32 val;
1305
1306         if (enable_flag) {
1307                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1308                  /* Open all ports */
1309                 tmp = cpu_to_le32(val);
1310                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1311                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1312                                ALL_PORT_VAL_OPEN);
1313                 val = le32_to_cpu(tmp);
1314                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1315         } else {
1316                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1317                 /* Close all ports */
1318                 tmp = cpu_to_le32(val);
1319                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1320                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1321                 val = le32_to_cpu(tmp);
1322                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1323         }
1324 }
1325
1326 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1327 {
1328         struct device *dev = &hr_dev->pdev->dev;
1329         struct hns_roce_v1_priv *priv;
1330         int ret;
1331
1332         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1333
1334         priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1335                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1336                 GFP_KERNEL);
1337         if (!priv->bt_table.qpc_buf.buf)
1338                 return -ENOMEM;
1339
1340         priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1341                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1342                 GFP_KERNEL);
1343         if (!priv->bt_table.mtpt_buf.buf) {
1344                 ret = -ENOMEM;
1345                 goto err_failed_alloc_mtpt_buf;
1346         }
1347
1348         priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1349                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1350                 GFP_KERNEL);
1351         if (!priv->bt_table.cqc_buf.buf) {
1352                 ret = -ENOMEM;
1353                 goto err_failed_alloc_cqc_buf;
1354         }
1355
1356         return 0;
1357
1358 err_failed_alloc_cqc_buf:
1359         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1360                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1361
1362 err_failed_alloc_mtpt_buf:
1363         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1364                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1365
1366         return ret;
1367 }
1368
1369 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1370 {
1371         struct device *dev = &hr_dev->pdev->dev;
1372         struct hns_roce_v1_priv *priv;
1373
1374         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1375
1376         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1377                 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1378
1379         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1380                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1381
1382         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1383                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1384 }
1385
1386 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1387 {
1388         struct device *dev = &hr_dev->pdev->dev;
1389         struct hns_roce_buf_list *tptr_buf;
1390         struct hns_roce_v1_priv *priv;
1391
1392         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1393         tptr_buf = &priv->tptr_table.tptr_buf;
1394
1395         /*
1396          * This buffer will be used for CQ's tptr(tail pointer), also
1397          * named ci(customer index). Every CQ will use 2 bytes to save
1398          * cqe ci in hip06. Hardware will read this area to get new ci
1399          * when the queue is almost full.
1400          */
1401         tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1402                                            &tptr_buf->map, GFP_KERNEL);
1403         if (!tptr_buf->buf)
1404                 return -ENOMEM;
1405
1406         hr_dev->tptr_dma_addr = tptr_buf->map;
1407         hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1408
1409         return 0;
1410 }
1411
1412 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1413 {
1414         struct device *dev = &hr_dev->pdev->dev;
1415         struct hns_roce_buf_list *tptr_buf;
1416         struct hns_roce_v1_priv *priv;
1417
1418         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1419         tptr_buf = &priv->tptr_table.tptr_buf;
1420
1421         dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1422                           tptr_buf->buf, tptr_buf->map);
1423 }
1424
1425 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1426 {
1427         struct device *dev = &hr_dev->pdev->dev;
1428         struct hns_roce_free_mr *free_mr;
1429         struct hns_roce_v1_priv *priv;
1430         int ret = 0;
1431
1432         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1433         free_mr = &priv->free_mr;
1434
1435         free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1436         if (!free_mr->free_mr_wq) {
1437                 dev_err(dev, "Create free mr workqueue failed!\n");
1438                 return -ENOMEM;
1439         }
1440
1441         ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1442         if (ret) {
1443                 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1444                 flush_workqueue(free_mr->free_mr_wq);
1445                 destroy_workqueue(free_mr->free_mr_wq);
1446         }
1447
1448         return ret;
1449 }
1450
1451 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1452 {
1453         struct hns_roce_free_mr *free_mr;
1454         struct hns_roce_v1_priv *priv;
1455
1456         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1457         free_mr = &priv->free_mr;
1458
1459         flush_workqueue(free_mr->free_mr_wq);
1460         destroy_workqueue(free_mr->free_mr_wq);
1461
1462         hns_roce_v1_release_lp_qp(hr_dev);
1463 }
1464
1465 /**
1466  * hns_roce_v1_reset - reset RoCE
1467  * @hr_dev: RoCE device struct pointer
1468  * @enable: true -- drop reset, false -- reset
1469  * return 0 - success , negative --fail
1470  */
1471 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1472 {
1473         struct device_node *dsaf_node;
1474         struct device *dev = &hr_dev->pdev->dev;
1475         struct device_node *np = dev->of_node;
1476         struct fwnode_handle *fwnode;
1477         int ret;
1478
1479         /* check if this is DT/ACPI case */
1480         if (dev_of_node(dev)) {
1481                 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1482                 if (!dsaf_node) {
1483                         dev_err(dev, "could not find dsaf-handle\n");
1484                         return -EINVAL;
1485                 }
1486                 fwnode = &dsaf_node->fwnode;
1487         } else if (is_acpi_device_node(dev->fwnode)) {
1488                 struct fwnode_reference_args args;
1489
1490                 ret = acpi_node_get_property_reference(dev->fwnode,
1491                                                        "dsaf-handle", 0, &args);
1492                 if (ret) {
1493                         dev_err(dev, "could not find dsaf-handle\n");
1494                         return ret;
1495                 }
1496                 fwnode = args.fwnode;
1497         } else {
1498                 dev_err(dev, "cannot read data from DT or ACPI\n");
1499                 return -ENXIO;
1500         }
1501
1502         ret = hns_dsaf_roce_reset(fwnode, false);
1503         if (ret)
1504                 return ret;
1505
1506         if (dereset) {
1507                 msleep(SLEEP_TIME_INTERVAL);
1508                 ret = hns_dsaf_roce_reset(fwnode, true);
1509         }
1510
1511         return ret;
1512 }
1513
1514 static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1515 {
1516         struct device *dev = &hr_dev->pdev->dev;
1517         struct hns_roce_v1_priv *priv;
1518         struct hns_roce_des_qp *des_qp;
1519
1520         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1521         des_qp = &priv->des_qp;
1522
1523         des_qp->requeue_flag = 1;
1524         des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1525         if (!des_qp->qp_wq) {
1526                 dev_err(dev, "Create destroy qp workqueue failed!\n");
1527                 return -ENOMEM;
1528         }
1529
1530         return 0;
1531 }
1532
1533 static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1534 {
1535         struct hns_roce_v1_priv *priv;
1536         struct hns_roce_des_qp *des_qp;
1537
1538         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1539         des_qp = &priv->des_qp;
1540
1541         des_qp->requeue_flag = 0;
1542         flush_workqueue(des_qp->qp_wq);
1543         destroy_workqueue(des_qp->qp_wq);
1544 }
1545
1546 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1547 {
1548         int i = 0;
1549         struct hns_roce_caps *caps = &hr_dev->caps;
1550
1551         hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1552         hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1553         hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1554                                 ((u64)roce_read(hr_dev,
1555                                             ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1556         hr_dev->hw_rev          = HNS_ROCE_HW_VER1;
1557
1558         caps->num_qps           = HNS_ROCE_V1_MAX_QP_NUM;
1559         caps->max_wqes          = HNS_ROCE_V1_MAX_WQE_NUM;
1560         caps->min_wqes          = HNS_ROCE_MIN_WQE_NUM;
1561         caps->num_cqs           = HNS_ROCE_V1_MAX_CQ_NUM;
1562         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1563         caps->max_cqes          = HNS_ROCE_V1_MAX_CQE_NUM;
1564         caps->max_sq_sg         = HNS_ROCE_V1_SG_NUM;
1565         caps->max_rq_sg         = HNS_ROCE_V1_SG_NUM;
1566         caps->max_sq_inline     = HNS_ROCE_V1_INLINE_SIZE;
1567         caps->num_uars          = HNS_ROCE_V1_UAR_NUM;
1568         caps->phy_num_uars      = HNS_ROCE_V1_PHY_UAR_NUM;
1569         caps->num_aeq_vectors   = HNS_ROCE_V1_AEQE_VEC_NUM;
1570         caps->num_comp_vectors  = HNS_ROCE_V1_COMP_VEC_NUM;
1571         caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1572         caps->num_mtpts         = HNS_ROCE_V1_MAX_MTPT_NUM;
1573         caps->num_mtt_segs      = HNS_ROCE_V1_MAX_MTT_SEGS;
1574         caps->num_pds           = HNS_ROCE_V1_MAX_PD_NUM;
1575         caps->max_qp_init_rdma  = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1576         caps->max_qp_dest_rdma  = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1577         caps->max_sq_desc_sz    = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1578         caps->max_rq_desc_sz    = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1579         caps->qpc_entry_sz      = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1580         caps->irrl_entry_sz     = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1581         caps->cqc_entry_sz      = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1582         caps->mtpt_entry_sz     = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1583         caps->mtt_entry_sz      = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1584         caps->cq_entry_sz       = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1585         caps->page_size_cap     = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1586         caps->reserved_lkey     = 0;
1587         caps->reserved_pds      = 0;
1588         caps->reserved_mrws     = 1;
1589         caps->reserved_uars     = 0;
1590         caps->reserved_cqs      = 0;
1591         caps->chunk_sz          = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1592
1593         for (i = 0; i < caps->num_ports; i++)
1594                 caps->pkey_table_len[i] = 1;
1595
1596         for (i = 0; i < caps->num_ports; i++) {
1597                 /* Six ports shared 16 GID in v1 engine */
1598                 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1599                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1600                                                  caps->num_ports;
1601                 else
1602                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1603                                                  caps->num_ports + 1;
1604         }
1605
1606         caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1607         caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1608         caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1609         caps->max_mtu = IB_MTU_2048;
1610
1611         return 0;
1612 }
1613
1614 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1615 {
1616         int ret;
1617         u32 val;
1618         __le32 tmp;
1619         struct device *dev = &hr_dev->pdev->dev;
1620
1621         /* DMAE user config */
1622         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1623         tmp = cpu_to_le32(val);
1624         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1625                        ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1626         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1627                        ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1628                        1 << PAGES_SHIFT_16);
1629         val = le32_to_cpu(tmp);
1630         roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1631
1632         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1633         tmp = cpu_to_le32(val);
1634         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1635                        ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1636         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1637                        ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1638                        1 << PAGES_SHIFT_16);
1639
1640         ret = hns_roce_db_init(hr_dev);
1641         if (ret) {
1642                 dev_err(dev, "doorbell init failed!\n");
1643                 return ret;
1644         }
1645
1646         ret = hns_roce_raq_init(hr_dev);
1647         if (ret) {
1648                 dev_err(dev, "raq init failed!\n");
1649                 goto error_failed_raq_init;
1650         }
1651
1652         ret = hns_roce_bt_init(hr_dev);
1653         if (ret) {
1654                 dev_err(dev, "bt init failed!\n");
1655                 goto error_failed_bt_init;
1656         }
1657
1658         ret = hns_roce_tptr_init(hr_dev);
1659         if (ret) {
1660                 dev_err(dev, "tptr init failed!\n");
1661                 goto error_failed_tptr_init;
1662         }
1663
1664         ret = hns_roce_des_qp_init(hr_dev);
1665         if (ret) {
1666                 dev_err(dev, "des qp init failed!\n");
1667                 goto error_failed_des_qp_init;
1668         }
1669
1670         ret = hns_roce_free_mr_init(hr_dev);
1671         if (ret) {
1672                 dev_err(dev, "free mr init failed!\n");
1673                 goto error_failed_free_mr_init;
1674         }
1675
1676         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1677
1678         return 0;
1679
1680 error_failed_free_mr_init:
1681         hns_roce_des_qp_free(hr_dev);
1682
1683 error_failed_des_qp_init:
1684         hns_roce_tptr_free(hr_dev);
1685
1686 error_failed_tptr_init:
1687         hns_roce_bt_free(hr_dev);
1688
1689 error_failed_bt_init:
1690         hns_roce_raq_free(hr_dev);
1691
1692 error_failed_raq_init:
1693         hns_roce_db_free(hr_dev);
1694         return ret;
1695 }
1696
1697 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1698 {
1699         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1700         hns_roce_free_mr_free(hr_dev);
1701         hns_roce_des_qp_free(hr_dev);
1702         hns_roce_tptr_free(hr_dev);
1703         hns_roce_bt_free(hr_dev);
1704         hns_roce_raq_free(hr_dev);
1705         hns_roce_db_free(hr_dev);
1706 }
1707
1708 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1709 {
1710         u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1711
1712         return (!!(status & (1 << HCR_GO_BIT)));
1713 }
1714
1715 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1716                                  u64 out_param, u32 in_modifier, u8 op_modifier,
1717                                  u16 op, u16 token, int event)
1718 {
1719         u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1720         unsigned long end;
1721         u32 val = 0;
1722         __le32 tmp;
1723
1724         end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1725         while (hns_roce_v1_cmd_pending(hr_dev)) {
1726                 if (time_after(jiffies, end)) {
1727                         dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1728                                 (int)jiffies, (int)end);
1729                         return -EAGAIN;
1730                 }
1731                 cond_resched();
1732         }
1733
1734         tmp = cpu_to_le32(val);
1735         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1736                        op);
1737         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1738                        ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1739         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1740         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1741         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1742                        ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1743
1744         val = le32_to_cpu(tmp);
1745         writeq(in_param, hcr + 0);
1746         writeq(out_param, hcr + 2);
1747         writel(in_modifier, hcr + 4);
1748         /* Memory barrier */
1749         wmb();
1750
1751         writel(val, hcr + 5);
1752
1753         return 0;
1754 }
1755
1756 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1757                                 unsigned long timeout)
1758 {
1759         u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1760         unsigned long end = 0;
1761         u32 status = 0;
1762
1763         end = msecs_to_jiffies(timeout) + jiffies;
1764         while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1765                 cond_resched();
1766
1767         if (hns_roce_v1_cmd_pending(hr_dev)) {
1768                 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1769                 return -ETIMEDOUT;
1770         }
1771
1772         status = le32_to_cpu((__force __le32)
1773                               __raw_readl(hcr + HCR_STATUS_OFFSET));
1774         if ((status & STATUS_MASK) != 0x1) {
1775                 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1776                 return -EBUSY;
1777         }
1778
1779         return 0;
1780 }
1781
1782 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1783                                int gid_index, const union ib_gid *gid,
1784                                const struct ib_gid_attr *attr)
1785 {
1786         u32 *p = NULL;
1787         u8 gid_idx = 0;
1788
1789         gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1790
1791         p = (u32 *)&gid->raw[0];
1792         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1793                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1794
1795         p = (u32 *)&gid->raw[4];
1796         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1797                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1798
1799         p = (u32 *)&gid->raw[8];
1800         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1801                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1802
1803         p = (u32 *)&gid->raw[0xc];
1804         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1805                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1806
1807         return 0;
1808 }
1809
1810 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1811                                u8 *addr)
1812 {
1813         u32 reg_smac_l;
1814         u16 reg_smac_h;
1815         __le32 tmp;
1816         u16 *p_h;
1817         u32 *p;
1818         u32 val;
1819
1820         /*
1821          * When mac changed, loopback may fail
1822          * because of smac not equal to dmac.
1823          * We Need to release and create reserved qp again.
1824          */
1825         if (hr_dev->hw->dereg_mr) {
1826                 int ret;
1827
1828                 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1829                 if (ret && ret != -ETIMEDOUT)
1830                         return ret;
1831         }
1832
1833         p = (u32 *)(&addr[0]);
1834         reg_smac_l = *p;
1835         roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1836                        PHY_PORT_OFFSET * phy_port);
1837
1838         val = roce_read(hr_dev,
1839                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1840         tmp = cpu_to_le32(val);
1841         p_h = (u16 *)(&addr[4]);
1842         reg_smac_h  = *p_h;
1843         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1844                        ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1845         val = le32_to_cpu(tmp);
1846         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1847                    val);
1848
1849         return 0;
1850 }
1851
1852 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1853                                 enum ib_mtu mtu)
1854 {
1855         __le32 tmp;
1856         u32 val;
1857
1858         val = roce_read(hr_dev,
1859                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1860         tmp = cpu_to_le32(val);
1861         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1862                        ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1863         val = le32_to_cpu(tmp);
1864         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1865                    val);
1866 }
1867
1868 static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1869                                   unsigned long mtpt_idx)
1870 {
1871         struct hns_roce_v1_mpt_entry *mpt_entry;
1872         struct sg_dma_page_iter sg_iter;
1873         u64 *pages;
1874         int i;
1875
1876         /* MPT filled into mailbox buf */
1877         mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1878         memset(mpt_entry, 0, sizeof(*mpt_entry));
1879
1880         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1881                        MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1882         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1883                        MPT_BYTE_4_KEY_S, mr->key);
1884         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1885                        MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1886         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1887         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1888                      (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1889         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1890         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1891                        MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1892         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1893         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1894                      (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1895         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1896                      (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1897         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1898                      (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1899         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1900                      0);
1901         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1902
1903         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1904                        MPT_BYTE_12_PBL_ADDR_H_S, 0);
1905         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1906                        MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1907
1908         mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1909         mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1910         mpt_entry->length = cpu_to_le32((u32)mr->size);
1911
1912         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1913                        MPT_BYTE_28_PD_S, mr->pd);
1914         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1915                        MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1916         roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1917                        MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1918
1919         /* DMA memory register */
1920         if (mr->type == MR_TYPE_DMA)
1921                 return 0;
1922
1923         pages = (u64 *) __get_free_page(GFP_KERNEL);
1924         if (!pages)
1925                 return -ENOMEM;
1926
1927         i = 0;
1928         for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
1929                 pages[i] = ((u64)sg_page_iter_dma_address(&sg_iter)) >> 12;
1930
1931                 /* Directly record to MTPT table firstly 7 entry */
1932                 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1933                         break;
1934                 i++;
1935         }
1936
1937         /* Register user mr */
1938         for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1939                 switch (i) {
1940                 case 0:
1941                         mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1942                         roce_set_field(mpt_entry->mpt_byte_36,
1943                                 MPT_BYTE_36_PA0_H_M,
1944                                 MPT_BYTE_36_PA0_H_S,
1945                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1946                         break;
1947                 case 1:
1948                         roce_set_field(mpt_entry->mpt_byte_36,
1949                                        MPT_BYTE_36_PA1_L_M,
1950                                        MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1951                         roce_set_field(mpt_entry->mpt_byte_40,
1952                                 MPT_BYTE_40_PA1_H_M,
1953                                 MPT_BYTE_40_PA1_H_S,
1954                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1955                         break;
1956                 case 2:
1957                         roce_set_field(mpt_entry->mpt_byte_40,
1958                                        MPT_BYTE_40_PA2_L_M,
1959                                        MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1960                         roce_set_field(mpt_entry->mpt_byte_44,
1961                                 MPT_BYTE_44_PA2_H_M,
1962                                 MPT_BYTE_44_PA2_H_S,
1963                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1964                         break;
1965                 case 3:
1966                         roce_set_field(mpt_entry->mpt_byte_44,
1967                                        MPT_BYTE_44_PA3_L_M,
1968                                        MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1969                         roce_set_field(mpt_entry->mpt_byte_48,
1970                                 MPT_BYTE_48_PA3_H_M,
1971                                 MPT_BYTE_48_PA3_H_S,
1972                                 (u32)(pages[i] >> PAGES_SHIFT_8));
1973                         break;
1974                 case 4:
1975                         mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1976                         roce_set_field(mpt_entry->mpt_byte_56,
1977                                 MPT_BYTE_56_PA4_H_M,
1978                                 MPT_BYTE_56_PA4_H_S,
1979                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1980                         break;
1981                 case 5:
1982                         roce_set_field(mpt_entry->mpt_byte_56,
1983                                        MPT_BYTE_56_PA5_L_M,
1984                                        MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1985                         roce_set_field(mpt_entry->mpt_byte_60,
1986                                 MPT_BYTE_60_PA5_H_M,
1987                                 MPT_BYTE_60_PA5_H_S,
1988                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1989                         break;
1990                 case 6:
1991                         roce_set_field(mpt_entry->mpt_byte_60,
1992                                        MPT_BYTE_60_PA6_L_M,
1993                                        MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1994                         roce_set_field(mpt_entry->mpt_byte_64,
1995                                 MPT_BYTE_64_PA6_H_M,
1996                                 MPT_BYTE_64_PA6_H_S,
1997                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1998                         break;
1999                 default:
2000                         break;
2001                 }
2002         }
2003
2004         free_page((unsigned long) pages);
2005
2006         mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
2007
2008         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
2009                        MPT_BYTE_12_PBL_ADDR_H_S,
2010                        ((u32)(mr->pbl_dma_addr >> 32)));
2011
2012         return 0;
2013 }
2014
2015 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
2016 {
2017         return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2018                                    n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
2019 }
2020
2021 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
2022 {
2023         struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
2024
2025         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2026         return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
2027                 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
2028 }
2029
2030 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
2031 {
2032         return get_sw_cqe(hr_cq, hr_cq->cons_index);
2033 }
2034
2035 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2036 {
2037         __le32 doorbell[2];
2038
2039         doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
2040         doorbell[1] = 0;
2041         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2042         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2043                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2044         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2045                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2046         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2047                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2048
2049         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2050 }
2051
2052 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2053                                    struct hns_roce_srq *srq)
2054 {
2055         struct hns_roce_cqe *cqe, *dest;
2056         u32 prod_index;
2057         int nfreed = 0;
2058         u8 owner_bit;
2059
2060         for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2061              ++prod_index) {
2062                 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2063                         break;
2064         }
2065
2066         /*
2067          * Now backwards through the CQ, removing CQ entries
2068          * that match our QP by overwriting them with next entries.
2069          */
2070         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2071                 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2072                 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2073                                      CQE_BYTE_16_LOCAL_QPN_S) &
2074                                      HNS_ROCE_CQE_QPN_MASK) == qpn) {
2075                         /* In v1 engine, not support SRQ */
2076                         ++nfreed;
2077                 } else if (nfreed) {
2078                         dest = get_cqe(hr_cq, (prod_index + nfreed) &
2079                                        hr_cq->ib_cq.cqe);
2080                         owner_bit = roce_get_bit(dest->cqe_byte_4,
2081                                                  CQE_BYTE_4_OWNER_S);
2082                         memcpy(dest, cqe, sizeof(*cqe));
2083                         roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2084                                      owner_bit);
2085                 }
2086         }
2087
2088         if (nfreed) {
2089                 hr_cq->cons_index += nfreed;
2090                 /*
2091                  * Make sure update of buffer contents is done before
2092                  * updating consumer index.
2093                  */
2094                 wmb();
2095
2096                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2097         }
2098 }
2099
2100 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2101                                  struct hns_roce_srq *srq)
2102 {
2103         spin_lock_irq(&hr_cq->lock);
2104         __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2105         spin_unlock_irq(&hr_cq->lock);
2106 }
2107
2108 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2109                                   struct hns_roce_cq *hr_cq, void *mb_buf,
2110                                   u64 *mtts, dma_addr_t dma_handle, int nent,
2111                                   u32 vector)
2112 {
2113         struct hns_roce_cq_context *cq_context = NULL;
2114         struct hns_roce_buf_list *tptr_buf;
2115         struct hns_roce_v1_priv *priv;
2116         dma_addr_t tptr_dma_addr;
2117         int offset;
2118
2119         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2120         tptr_buf = &priv->tptr_table.tptr_buf;
2121
2122         cq_context = mb_buf;
2123         memset(cq_context, 0, sizeof(*cq_context));
2124
2125         /* Get the tptr for this CQ. */
2126         offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2127         tptr_dma_addr = tptr_buf->map + offset;
2128         hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2129
2130         /* Register cq_context members */
2131         roce_set_field(cq_context->cqc_byte_4,
2132                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2133                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2134         roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2135                        CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2136
2137         cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2138
2139         roce_set_field(cq_context->cqc_byte_12,
2140                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2141                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2142                        ((u64)dma_handle >> 32));
2143         roce_set_field(cq_context->cqc_byte_12,
2144                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2145                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2146                        ilog2((unsigned int)nent));
2147         roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2148                        CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
2149
2150         cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2151
2152         roce_set_field(cq_context->cqc_byte_20,
2153                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2154                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2155         /* Dedicated hardware, directly set 0 */
2156         roce_set_field(cq_context->cqc_byte_20,
2157                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2158                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2159         /**
2160          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2161          * using 4K page, and shift more 32 because of
2162          * caculating the high 32 bit value evaluated to hardware.
2163          */
2164         roce_set_field(cq_context->cqc_byte_20,
2165                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2166                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2167                        tptr_dma_addr >> 44);
2168
2169         cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2170
2171         roce_set_field(cq_context->cqc_byte_32,
2172                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2173                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2174         roce_set_bit(cq_context->cqc_byte_32,
2175                      CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2176         roce_set_bit(cq_context->cqc_byte_32,
2177                      CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2178         roce_set_bit(cq_context->cqc_byte_32,
2179                      CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2180         roce_set_bit(cq_context->cqc_byte_32,
2181                      CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2182                      0);
2183         /* The initial value of cq's ci is 0 */
2184         roce_set_field(cq_context->cqc_byte_32,
2185                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2186                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2187 }
2188
2189 static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2190 {
2191         return -EOPNOTSUPP;
2192 }
2193
2194 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2195                                      enum ib_cq_notify_flags flags)
2196 {
2197         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2198         u32 notification_flag;
2199         __le32 doorbell[2];
2200
2201         notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2202                             IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2203         /*
2204          * flags = 0; Notification Flag = 1, next
2205          * flags = 1; Notification Flag = 0, solocited
2206          */
2207         doorbell[0] =
2208                 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2209         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2210         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2211                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2212         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2213                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2214         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2215                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2216                        hr_cq->cqn | notification_flag);
2217
2218         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2219
2220         return 0;
2221 }
2222
2223 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2224                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2225 {
2226         int qpn;
2227         int is_send;
2228         u16 wqe_ctr;
2229         u32 status;
2230         u32 opcode;
2231         struct hns_roce_cqe *cqe;
2232         struct hns_roce_qp *hr_qp;
2233         struct hns_roce_wq *wq;
2234         struct hns_roce_wqe_ctrl_seg *sq_wqe;
2235         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2236         struct device *dev = &hr_dev->pdev->dev;
2237
2238         /* Find cqe according consumer index */
2239         cqe = next_cqe_sw(hr_cq);
2240         if (!cqe)
2241                 return -EAGAIN;
2242
2243         ++hr_cq->cons_index;
2244         /* Memory barrier */
2245         rmb();
2246         /* 0->SQ, 1->RQ */
2247         is_send  = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2248
2249         /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2250         if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2251                            CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2252                 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2253                                      CQE_BYTE_20_PORT_NUM_S) +
2254                       roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2255                                      CQE_BYTE_16_LOCAL_QPN_S) *
2256                                      HNS_ROCE_MAX_PORTS;
2257         } else {
2258                 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2259                                      CQE_BYTE_16_LOCAL_QPN_S);
2260         }
2261
2262         if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2263                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2264                 if (unlikely(!hr_qp)) {
2265                         dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2266                                 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2267                         return -EINVAL;
2268                 }
2269
2270                 *cur_qp = hr_qp;
2271         }
2272
2273         wc->qp = &(*cur_qp)->ibqp;
2274         wc->vendor_err = 0;
2275
2276         status = roce_get_field(cqe->cqe_byte_4,
2277                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2278                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2279                                 HNS_ROCE_CQE_STATUS_MASK;
2280         switch (status) {
2281         case HNS_ROCE_CQE_SUCCESS:
2282                 wc->status = IB_WC_SUCCESS;
2283                 break;
2284         case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2285                 wc->status = IB_WC_LOC_LEN_ERR;
2286                 break;
2287         case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2288                 wc->status = IB_WC_LOC_QP_OP_ERR;
2289                 break;
2290         case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2291                 wc->status = IB_WC_LOC_PROT_ERR;
2292                 break;
2293         case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2294                 wc->status = IB_WC_WR_FLUSH_ERR;
2295                 break;
2296         case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2297                 wc->status = IB_WC_MW_BIND_ERR;
2298                 break;
2299         case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2300                 wc->status = IB_WC_BAD_RESP_ERR;
2301                 break;
2302         case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2303                 wc->status = IB_WC_LOC_ACCESS_ERR;
2304                 break;
2305         case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2306                 wc->status = IB_WC_REM_INV_REQ_ERR;
2307                 break;
2308         case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2309                 wc->status = IB_WC_REM_ACCESS_ERR;
2310                 break;
2311         case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2312                 wc->status = IB_WC_REM_OP_ERR;
2313                 break;
2314         case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2315                 wc->status = IB_WC_RETRY_EXC_ERR;
2316                 break;
2317         case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2318                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2319                 break;
2320         default:
2321                 wc->status = IB_WC_GENERAL_ERR;
2322                 break;
2323         }
2324
2325         /* CQE status error, directly return */
2326         if (wc->status != IB_WC_SUCCESS)
2327                 return 0;
2328
2329         if (is_send) {
2330                 /* SQ conrespond to CQE */
2331                 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2332                                                 CQE_BYTE_4_WQE_INDEX_M,
2333                                                 CQE_BYTE_4_WQE_INDEX_S)&
2334                                                 ((*cur_qp)->sq.wqe_cnt-1));
2335                 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2336                 case HNS_ROCE_WQE_OPCODE_SEND:
2337                         wc->opcode = IB_WC_SEND;
2338                         break;
2339                 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2340                         wc->opcode = IB_WC_RDMA_READ;
2341                         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2342                         break;
2343                 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2344                         wc->opcode = IB_WC_RDMA_WRITE;
2345                         break;
2346                 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2347                         wc->opcode = IB_WC_LOCAL_INV;
2348                         break;
2349                 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2350                         wc->opcode = IB_WC_SEND;
2351                         break;
2352                 default:
2353                         wc->status = IB_WC_GENERAL_ERR;
2354                         break;
2355                 }
2356                 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2357                                 IB_WC_WITH_IMM : 0);
2358
2359                 wq = &(*cur_qp)->sq;
2360                 if ((*cur_qp)->sq_signal_bits) {
2361                         /*
2362                          * If sg_signal_bit is 1,
2363                          * firstly tail pointer updated to wqe
2364                          * which current cqe correspond to
2365                          */
2366                         wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2367                                                       CQE_BYTE_4_WQE_INDEX_M,
2368                                                       CQE_BYTE_4_WQE_INDEX_S);
2369                         wq->tail += (wqe_ctr - (u16)wq->tail) &
2370                                     (wq->wqe_cnt - 1);
2371                 }
2372                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2373                 ++wq->tail;
2374         } else {
2375                 /* RQ conrespond to CQE */
2376                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2377                 opcode = roce_get_field(cqe->cqe_byte_4,
2378                                         CQE_BYTE_4_OPERATION_TYPE_M,
2379                                         CQE_BYTE_4_OPERATION_TYPE_S) &
2380                                         HNS_ROCE_CQE_OPCODE_MASK;
2381                 switch (opcode) {
2382                 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2383                         wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2384                         wc->wc_flags = IB_WC_WITH_IMM;
2385                         wc->ex.imm_data =
2386                                 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2387                         break;
2388                 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2389                         if (roce_get_bit(cqe->cqe_byte_4,
2390                                          CQE_BYTE_4_IMM_INDICATOR_S)) {
2391                                 wc->opcode = IB_WC_RECV;
2392                                 wc->wc_flags = IB_WC_WITH_IMM;
2393                                 wc->ex.imm_data = cpu_to_be32(
2394                                         le32_to_cpu(cqe->immediate_data));
2395                         } else {
2396                                 wc->opcode = IB_WC_RECV;
2397                                 wc->wc_flags = 0;
2398                         }
2399                         break;
2400                 default:
2401                         wc->status = IB_WC_GENERAL_ERR;
2402                         break;
2403                 }
2404
2405                 /* Update tail pointer, record wr_id */
2406                 wq = &(*cur_qp)->rq;
2407                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2408                 ++wq->tail;
2409                 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2410                                             CQE_BYTE_20_SL_S);
2411                 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2412                                                 CQE_BYTE_20_REMOTE_QPN_M,
2413                                                 CQE_BYTE_20_REMOTE_QPN_S);
2414                 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2415                                               CQE_BYTE_20_GRH_PRESENT_S) ?
2416                                               IB_WC_GRH : 0);
2417                 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2418                                                      CQE_BYTE_28_P_KEY_IDX_M,
2419                                                      CQE_BYTE_28_P_KEY_IDX_S);
2420         }
2421
2422         return 0;
2423 }
2424
2425 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2426 {
2427         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2428         struct hns_roce_qp *cur_qp = NULL;
2429         unsigned long flags;
2430         int npolled;
2431         int ret = 0;
2432
2433         spin_lock_irqsave(&hr_cq->lock, flags);
2434
2435         for (npolled = 0; npolled < num_entries; ++npolled) {
2436                 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2437                 if (ret)
2438                         break;
2439         }
2440
2441         if (npolled) {
2442                 *hr_cq->tptr_addr = hr_cq->cons_index &
2443                         ((hr_cq->cq_depth << 1) - 1);
2444
2445                 /* Memroy barrier */
2446                 wmb();
2447                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2448         }
2449
2450         spin_unlock_irqrestore(&hr_cq->lock, flags);
2451
2452         if (ret == 0 || ret == -EAGAIN)
2453                 return npolled;
2454         else
2455                 return ret;
2456 }
2457
2458 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2459                                  struct hns_roce_hem_table *table, int obj,
2460                                  int step_idx)
2461 {
2462         struct device *dev = &hr_dev->pdev->dev;
2463         struct hns_roce_v1_priv *priv;
2464         unsigned long end = 0, flags = 0;
2465         __le32 bt_cmd_val[2] = {0};
2466         void __iomem *bt_cmd;
2467         u64 bt_ba = 0;
2468
2469         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2470
2471         switch (table->type) {
2472         case HEM_TYPE_QPC:
2473                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2474                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2475                 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2476                 break;
2477         case HEM_TYPE_MTPT:
2478                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2479                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2480                 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2481                 break;
2482         case HEM_TYPE_CQC:
2483                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2484                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2485                 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2486                 break;
2487         case HEM_TYPE_SRQC:
2488                 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2489                 return -EINVAL;
2490         default:
2491                 return 0;
2492         }
2493         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2494                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2495         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2496         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2497
2498         spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2499
2500         bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2501
2502         end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2503         while (1) {
2504                 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2505                         if (!(time_before(jiffies, end))) {
2506                                 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2507                                 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2508                                         flags);
2509                                 return -EBUSY;
2510                         }
2511                 } else {
2512                         break;
2513                 }
2514                 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2515         }
2516
2517         bt_cmd_val[0] = (__le32)bt_ba;
2518         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2519                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2520         hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2521
2522         spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2523
2524         return 0;
2525 }
2526
2527 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2528                                  struct hns_roce_mtt *mtt,
2529                                  enum hns_roce_qp_state cur_state,
2530                                  enum hns_roce_qp_state new_state,
2531                                  struct hns_roce_qp_context *context,
2532                                  struct hns_roce_qp *hr_qp)
2533 {
2534         static const u16
2535         op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2536                 [HNS_ROCE_QP_STATE_RST] = {
2537                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2538                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2539                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2540                 },
2541                 [HNS_ROCE_QP_STATE_INIT] = {
2542                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2543                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2544                 /* Note: In v1 engine, HW doesn't support RST2INIT.
2545                  * We use RST2INIT cmd instead of INIT2INIT.
2546                  */
2547                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2548                 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2549                 },
2550                 [HNS_ROCE_QP_STATE_RTR] = {
2551                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2552                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2553                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2554                 },
2555                 [HNS_ROCE_QP_STATE_RTS] = {
2556                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2557                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2558                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2559                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2560                 },
2561                 [HNS_ROCE_QP_STATE_SQD] = {
2562                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2563                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2564                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2565                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2566                 },
2567                 [HNS_ROCE_QP_STATE_ERR] = {
2568                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2569                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2570                 }
2571         };
2572
2573         struct hns_roce_cmd_mailbox *mailbox;
2574         struct device *dev = &hr_dev->pdev->dev;
2575         int ret = 0;
2576
2577         if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2578             new_state >= HNS_ROCE_QP_NUM_STATE ||
2579             !op[cur_state][new_state]) {
2580                 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2581                         cur_state, new_state);
2582                 return -EINVAL;
2583         }
2584
2585         if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2586                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2587                                          HNS_ROCE_CMD_2RST_QP,
2588                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2589
2590         if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2591                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2592                                          HNS_ROCE_CMD_2ERR_QP,
2593                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2594
2595         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2596         if (IS_ERR(mailbox))
2597                 return PTR_ERR(mailbox);
2598
2599         memcpy(mailbox->buf, context, sizeof(*context));
2600
2601         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2602                                 op[cur_state][new_state],
2603                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
2604
2605         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2606         return ret;
2607 }
2608
2609 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2610                              int attr_mask, enum ib_qp_state cur_state,
2611                              enum ib_qp_state new_state)
2612 {
2613         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2614         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2615         struct hns_roce_sqp_context *context;
2616         struct device *dev = &hr_dev->pdev->dev;
2617         dma_addr_t dma_handle = 0;
2618         u32 __iomem *addr;
2619         int rq_pa_start;
2620         __le32 tmp;
2621         u32 reg_val;
2622         u64 *mtts;
2623
2624         context = kzalloc(sizeof(*context), GFP_KERNEL);
2625         if (!context)
2626                 return -ENOMEM;
2627
2628         /* Search QP buf's MTTs */
2629         mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2630                                    hr_qp->mtt.first_seg, &dma_handle);
2631         if (!mtts) {
2632                 dev_err(dev, "qp buf pa find failed\n");
2633                 goto out;
2634         }
2635
2636         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2637                 roce_set_field(context->qp1c_bytes_4,
2638                                QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2639                                QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2640                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2641                 roce_set_field(context->qp1c_bytes_4,
2642                                QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2643                                QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2644                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2645                 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2646                                QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2647
2648                 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2649                 roce_set_field(context->qp1c_bytes_12,
2650                                QP1C_BYTES_12_SQ_RQ_BT_H_M,
2651                                QP1C_BYTES_12_SQ_RQ_BT_H_S,
2652                                ((u32)(dma_handle >> 32)));
2653
2654                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2655                                QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2656                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2657                                QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2658                 roce_set_bit(context->qp1c_bytes_16,
2659                              QP1C_BYTES_16_SIGNALING_TYPE_S,
2660                              le32_to_cpu(hr_qp->sq_signal_bits));
2661                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2662                              1);
2663                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2664                              1);
2665                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2666                              0);
2667
2668                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2669                                QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2670                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2671                                QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2672
2673                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2674                 context->cur_rq_wqe_ba_l =
2675                                 cpu_to_le32((u32)(mtts[rq_pa_start]));
2676
2677                 roce_set_field(context->qp1c_bytes_28,
2678                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2679                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2680                                (mtts[rq_pa_start]) >> 32);
2681                 roce_set_field(context->qp1c_bytes_28,
2682                                QP1C_BYTES_28_RQ_CUR_IDX_M,
2683                                QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2684
2685                 roce_set_field(context->qp1c_bytes_32,
2686                                QP1C_BYTES_32_RX_CQ_NUM_M,
2687                                QP1C_BYTES_32_RX_CQ_NUM_S,
2688                                to_hr_cq(ibqp->recv_cq)->cqn);
2689                 roce_set_field(context->qp1c_bytes_32,
2690                                QP1C_BYTES_32_TX_CQ_NUM_M,
2691                                QP1C_BYTES_32_TX_CQ_NUM_S,
2692                                to_hr_cq(ibqp->send_cq)->cqn);
2693
2694                 context->cur_sq_wqe_ba_l  = cpu_to_le32((u32)mtts[0]);
2695
2696                 roce_set_field(context->qp1c_bytes_40,
2697                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2698                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2699                                (mtts[0]) >> 32);
2700                 roce_set_field(context->qp1c_bytes_40,
2701                                QP1C_BYTES_40_SQ_CUR_IDX_M,
2702                                QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2703
2704                 /* Copy context to QP1C register */
2705                 addr = (u32 __iomem *)(hr_dev->reg_base +
2706                                        ROCEE_QP1C_CFG0_0_REG +
2707                                        hr_qp->phy_port * sizeof(*context));
2708
2709                 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2710                 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2711                 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2712                 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2713                 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2714                 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2715                 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2716                 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2717                 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2718                 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2719         }
2720
2721         /* Modify QP1C status */
2722         reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2723                             hr_qp->phy_port * sizeof(*context));
2724         tmp = cpu_to_le32(reg_val);
2725         roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2726                        ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2727         reg_val = le32_to_cpu(tmp);
2728         roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2729                     hr_qp->phy_port * sizeof(*context), reg_val);
2730
2731         hr_qp->state = new_state;
2732         if (new_state == IB_QPS_RESET) {
2733                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2734                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2735                 if (ibqp->send_cq != ibqp->recv_cq)
2736                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2737                                              hr_qp->qpn, NULL);
2738
2739                 hr_qp->rq.head = 0;
2740                 hr_qp->rq.tail = 0;
2741                 hr_qp->sq.head = 0;
2742                 hr_qp->sq.tail = 0;
2743                 hr_qp->sq_next_wqe = 0;
2744         }
2745
2746         kfree(context);
2747         return 0;
2748
2749 out:
2750         kfree(context);
2751         return -EINVAL;
2752 }
2753
2754 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2755                             int attr_mask, enum ib_qp_state cur_state,
2756                             enum ib_qp_state new_state)
2757 {
2758         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2759         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2760         struct device *dev = &hr_dev->pdev->dev;
2761         struct hns_roce_qp_context *context;
2762         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2763         dma_addr_t dma_handle_2 = 0;
2764         dma_addr_t dma_handle = 0;
2765         __le32 doorbell[2] = {0};
2766         int rq_pa_start = 0;
2767         u64 *mtts_2 = NULL;
2768         int ret = -EINVAL;
2769         u64 *mtts = NULL;
2770         int port;
2771         u8 port_num;
2772         u8 *dmac;
2773         u8 *smac;
2774
2775         context = kzalloc(sizeof(*context), GFP_KERNEL);
2776         if (!context)
2777                 return -ENOMEM;
2778
2779         /* Search qp buf's mtts */
2780         mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2781                                    hr_qp->mtt.first_seg, &dma_handle);
2782         if (mtts == NULL) {
2783                 dev_err(dev, "qp buf pa find failed\n");
2784                 goto out;
2785         }
2786
2787         /* Search IRRL's mtts */
2788         mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2789                                      hr_qp->qpn, &dma_handle_2);
2790         if (mtts_2 == NULL) {
2791                 dev_err(dev, "qp irrl_table find failed\n");
2792                 goto out;
2793         }
2794
2795         /*
2796          * Reset to init
2797          *      Mandatory param:
2798          *      IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2799          *      Optional param: NA
2800          */
2801         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2802                 roce_set_field(context->qpc_bytes_4,
2803                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2804                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2805                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2806
2807                 roce_set_bit(context->qpc_bytes_4,
2808                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2809                 roce_set_bit(context->qpc_bytes_4,
2810                              QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2811                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2812                 roce_set_bit(context->qpc_bytes_4,
2813                              QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2814                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2815                              );
2816                 roce_set_bit(context->qpc_bytes_4,
2817                              QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2818                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2819                              );
2820                 roce_set_bit(context->qpc_bytes_4,
2821                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2822                 roce_set_field(context->qpc_bytes_4,
2823                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2824                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2825                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2826                 roce_set_field(context->qpc_bytes_4,
2827                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2828                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2829                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2830                 roce_set_field(context->qpc_bytes_4,
2831                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2832                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2833                                to_hr_pd(ibqp->pd)->pdn);
2834                 hr_qp->access_flags = attr->qp_access_flags;
2835                 roce_set_field(context->qpc_bytes_8,
2836                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2837                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2838                                to_hr_cq(ibqp->send_cq)->cqn);
2839                 roce_set_field(context->qpc_bytes_8,
2840                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2841                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2842                                to_hr_cq(ibqp->recv_cq)->cqn);
2843
2844                 if (ibqp->srq)
2845                         roce_set_field(context->qpc_bytes_12,
2846                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2847                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2848                                        to_hr_srq(ibqp->srq)->srqn);
2849
2850                 roce_set_field(context->qpc_bytes_12,
2851                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2852                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2853                                attr->pkey_index);
2854                 hr_qp->pkey_index = attr->pkey_index;
2855                 roce_set_field(context->qpc_bytes_16,
2856                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2857                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2858
2859         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2860                 roce_set_field(context->qpc_bytes_4,
2861                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2862                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2863                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2864                 roce_set_bit(context->qpc_bytes_4,
2865                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2866                 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2867                         roce_set_bit(context->qpc_bytes_4,
2868                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2869                                      !!(attr->qp_access_flags &
2870                                      IB_ACCESS_REMOTE_READ));
2871                         roce_set_bit(context->qpc_bytes_4,
2872                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2873                                      !!(attr->qp_access_flags &
2874                                      IB_ACCESS_REMOTE_WRITE));
2875                 } else {
2876                         roce_set_bit(context->qpc_bytes_4,
2877                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2878                                      !!(hr_qp->access_flags &
2879                                      IB_ACCESS_REMOTE_READ));
2880                         roce_set_bit(context->qpc_bytes_4,
2881                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2882                                      !!(hr_qp->access_flags &
2883                                      IB_ACCESS_REMOTE_WRITE));
2884                 }
2885
2886                 roce_set_bit(context->qpc_bytes_4,
2887                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2888                 roce_set_field(context->qpc_bytes_4,
2889                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2890                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2891                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2892                 roce_set_field(context->qpc_bytes_4,
2893                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2894                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2895                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2896                 roce_set_field(context->qpc_bytes_4,
2897                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2898                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2899                                to_hr_pd(ibqp->pd)->pdn);
2900
2901                 roce_set_field(context->qpc_bytes_8,
2902                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2903                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2904                                to_hr_cq(ibqp->send_cq)->cqn);
2905                 roce_set_field(context->qpc_bytes_8,
2906                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2907                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2908                                to_hr_cq(ibqp->recv_cq)->cqn);
2909
2910                 if (ibqp->srq)
2911                         roce_set_field(context->qpc_bytes_12,
2912                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2913                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2914                                        to_hr_srq(ibqp->srq)->srqn);
2915                 if (attr_mask & IB_QP_PKEY_INDEX)
2916                         roce_set_field(context->qpc_bytes_12,
2917                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2918                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2919                                        attr->pkey_index);
2920                 else
2921                         roce_set_field(context->qpc_bytes_12,
2922                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2923                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2924                                        hr_qp->pkey_index);
2925
2926                 roce_set_field(context->qpc_bytes_16,
2927                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2928                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2929         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2930                 if ((attr_mask & IB_QP_ALT_PATH) ||
2931                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2932                     (attr_mask & IB_QP_PKEY_INDEX) ||
2933                     (attr_mask & IB_QP_QKEY)) {
2934                         dev_err(dev, "INIT2RTR attr_mask error\n");
2935                         goto out;
2936                 }
2937
2938                 dmac = (u8 *)attr->ah_attr.roce.dmac;
2939
2940                 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2941                 roce_set_field(context->qpc_bytes_24,
2942                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2943                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2944                                ((u32)(dma_handle >> 32)));
2945                 roce_set_bit(context->qpc_bytes_24,
2946                              QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2947                              1);
2948                 roce_set_field(context->qpc_bytes_24,
2949                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2950                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2951                                attr->min_rnr_timer);
2952                 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2953                 roce_set_field(context->qpc_bytes_32,
2954                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2955                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2956                                ((u32)(dma_handle_2 >> 32)) &
2957                                 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2958                 roce_set_field(context->qpc_bytes_32,
2959                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2960                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2961                 roce_set_bit(context->qpc_bytes_32,
2962                              QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2963                              1);
2964                 roce_set_bit(context->qpc_bytes_32,
2965                              QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2966                              le32_to_cpu(hr_qp->sq_signal_bits));
2967
2968                 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2969                         hr_qp->port;
2970                 smac = (u8 *)hr_dev->dev_addr[port];
2971                 /* when dmac equals smac or loop_idc is 1, it should loopback */
2972                 if (ether_addr_equal_unaligned(dmac, smac) ||
2973                     hr_dev->loop_idc == 0x1)
2974                         roce_set_bit(context->qpc_bytes_32,
2975                               QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2976
2977                 roce_set_bit(context->qpc_bytes_32,
2978                              QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2979                              rdma_ah_get_ah_flags(&attr->ah_attr));
2980                 roce_set_field(context->qpc_bytes_32,
2981                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2982                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2983                                ilog2((unsigned int)attr->max_dest_rd_atomic));
2984
2985                 if (attr_mask & IB_QP_DEST_QPN)
2986                         roce_set_field(context->qpc_bytes_36,
2987                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2988                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2989                                        attr->dest_qp_num);
2990
2991                 /* Configure GID index */
2992                 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2993                 roce_set_field(context->qpc_bytes_36,
2994                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2995                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2996                                 hns_get_gid_index(hr_dev,
2997                                                   port_num - 1,
2998                                                   grh->sgid_index));
2999
3000                 memcpy(&(context->dmac_l), dmac, 4);
3001
3002                 roce_set_field(context->qpc_bytes_44,
3003                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3004                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
3005                                *((u16 *)(&dmac[4])));
3006                 roce_set_field(context->qpc_bytes_44,
3007                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
3008                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
3009                                rdma_ah_get_static_rate(&attr->ah_attr));
3010                 roce_set_field(context->qpc_bytes_44,
3011                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3012                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
3013                                grh->hop_limit);
3014
3015                 roce_set_field(context->qpc_bytes_48,
3016                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3017                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
3018                                grh->flow_label);
3019                 roce_set_field(context->qpc_bytes_48,
3020                                QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3021                                QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
3022                                grh->traffic_class);
3023                 roce_set_field(context->qpc_bytes_48,
3024                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3025                                QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
3026
3027                 memcpy(context->dgid, grh->dgid.raw,
3028                        sizeof(grh->dgid.raw));
3029
3030                 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
3031                         roce_get_field(context->qpc_bytes_44,
3032                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3033                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
3034
3035                 roce_set_field(context->qpc_bytes_68,
3036                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
3037                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
3038                                hr_qp->rq.head);
3039                 roce_set_field(context->qpc_bytes_68,
3040                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3041                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3042
3043                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
3044                 context->cur_rq_wqe_ba_l =
3045                                 cpu_to_le32((u32)(mtts[rq_pa_start]));
3046
3047                 roce_set_field(context->qpc_bytes_76,
3048                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3049                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3050                         mtts[rq_pa_start] >> 32);
3051                 roce_set_field(context->qpc_bytes_76,
3052                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3053                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3054
3055                 context->rx_rnr_time = 0;
3056
3057                 roce_set_field(context->qpc_bytes_84,
3058                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3059                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3060                                attr->rq_psn - 1);
3061                 roce_set_field(context->qpc_bytes_84,
3062                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3063                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3064
3065                 roce_set_field(context->qpc_bytes_88,
3066                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3067                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3068                                attr->rq_psn);
3069                 roce_set_bit(context->qpc_bytes_88,
3070                              QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3071                 roce_set_bit(context->qpc_bytes_88,
3072                              QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3073                 roce_set_field(context->qpc_bytes_88,
3074                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3075                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3076                         0);
3077                 roce_set_field(context->qpc_bytes_88,
3078                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3079                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3080                                0);
3081
3082                 context->dma_length = 0;
3083                 context->r_key = 0;
3084                 context->va_l = 0;
3085                 context->va_h = 0;
3086
3087                 roce_set_field(context->qpc_bytes_108,
3088                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3089                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3090                 roce_set_bit(context->qpc_bytes_108,
3091                              QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3092                 roce_set_bit(context->qpc_bytes_108,
3093                              QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3094
3095                 roce_set_field(context->qpc_bytes_112,
3096                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3097                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3098                 roce_set_field(context->qpc_bytes_112,
3099                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3100                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3101
3102                 /* For chip resp ack */
3103                 roce_set_field(context->qpc_bytes_156,
3104                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3105                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3106                                hr_qp->phy_port);
3107                 roce_set_field(context->qpc_bytes_156,
3108                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3109                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3110                                rdma_ah_get_sl(&attr->ah_attr));
3111                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3112         } else if (cur_state == IB_QPS_RTR &&
3113                 new_state == IB_QPS_RTS) {
3114                 /* If exist optional param, return error */
3115                 if ((attr_mask & IB_QP_ALT_PATH) ||
3116                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
3117                     (attr_mask & IB_QP_QKEY) ||
3118                     (attr_mask & IB_QP_PATH_MIG_STATE) ||
3119                     (attr_mask & IB_QP_CUR_STATE) ||
3120                     (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3121                         dev_err(dev, "RTR2RTS attr_mask error\n");
3122                         goto out;
3123                 }
3124
3125                 context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3126
3127                 roce_set_field(context->qpc_bytes_120,
3128                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3129                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3130                                (mtts[0]) >> 32);
3131
3132                 roce_set_field(context->qpc_bytes_124,
3133                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3134                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3135                 roce_set_field(context->qpc_bytes_124,
3136                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3137                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3138
3139                 roce_set_field(context->qpc_bytes_128,
3140                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3141                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3142                                attr->sq_psn);
3143                 roce_set_bit(context->qpc_bytes_128,
3144                              QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3145                 roce_set_field(context->qpc_bytes_128,
3146                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3147                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3148                              0);
3149                 roce_set_bit(context->qpc_bytes_128,
3150                              QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3151
3152                 roce_set_field(context->qpc_bytes_132,
3153                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3154                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3155                 roce_set_field(context->qpc_bytes_132,
3156                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3157                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3158
3159                 roce_set_field(context->qpc_bytes_136,
3160                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3161                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3162                                attr->sq_psn);
3163                 roce_set_field(context->qpc_bytes_136,
3164                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3165                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3166                                attr->sq_psn);
3167
3168                 roce_set_field(context->qpc_bytes_140,
3169                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3170                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3171                                (attr->sq_psn >> SQ_PSN_SHIFT));
3172                 roce_set_field(context->qpc_bytes_140,
3173                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3174                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3175                 roce_set_bit(context->qpc_bytes_140,
3176                              QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3177
3178                 roce_set_field(context->qpc_bytes_148,
3179                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3180                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3181                 roce_set_field(context->qpc_bytes_148,
3182                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3183                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3184                                attr->retry_cnt);
3185                 roce_set_field(context->qpc_bytes_148,
3186                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3187                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3188                                attr->rnr_retry);
3189                 roce_set_field(context->qpc_bytes_148,
3190                                QP_CONTEXT_QPC_BYTES_148_LSN_M,
3191                                QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3192
3193                 context->rnr_retry = 0;
3194
3195                 roce_set_field(context->qpc_bytes_156,
3196                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3197                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3198                                attr->retry_cnt);
3199                 if (attr->timeout < 0x12) {
3200                         dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3201                                  attr->timeout);
3202                         roce_set_field(context->qpc_bytes_156,
3203                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3204                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3205                                        0x12);
3206                 } else {
3207                         roce_set_field(context->qpc_bytes_156,
3208                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3209                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3210                                        attr->timeout);
3211                 }
3212                 roce_set_field(context->qpc_bytes_156,
3213                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3214                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3215                                attr->rnr_retry);
3216                 roce_set_field(context->qpc_bytes_156,
3217                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3218                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3219                                hr_qp->phy_port);
3220                 roce_set_field(context->qpc_bytes_156,
3221                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3222                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3223                                rdma_ah_get_sl(&attr->ah_attr));
3224                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3225                 roce_set_field(context->qpc_bytes_156,
3226                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3227                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3228                                ilog2((unsigned int)attr->max_rd_atomic));
3229                 roce_set_field(context->qpc_bytes_156,
3230                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3231                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3232                 context->pkt_use_len = 0;
3233
3234                 roce_set_field(context->qpc_bytes_164,
3235                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3236                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3237                 roce_set_field(context->qpc_bytes_164,
3238                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3239                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3240
3241                 roce_set_field(context->qpc_bytes_168,
3242                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3243                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3244                                attr->sq_psn);
3245                 roce_set_field(context->qpc_bytes_168,
3246                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3247                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3248                 roce_set_field(context->qpc_bytes_168,
3249                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3250                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3251                 roce_set_bit(context->qpc_bytes_168,
3252                              QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3253                 roce_set_bit(context->qpc_bytes_168,
3254                              QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3255                 roce_set_bit(context->qpc_bytes_168,
3256                              QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3257                 context->sge_use_len = 0;
3258
3259                 roce_set_field(context->qpc_bytes_176,
3260                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3261                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3262                 roce_set_field(context->qpc_bytes_176,
3263                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3264                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3265                                0);
3266                 roce_set_field(context->qpc_bytes_180,
3267                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3268                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3269                 roce_set_field(context->qpc_bytes_180,
3270                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3271                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3272
3273                 context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3274
3275                 roce_set_field(context->qpc_bytes_188,
3276                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3277                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3278                                (mtts[0]) >> 32);
3279                 roce_set_bit(context->qpc_bytes_188,
3280                              QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3281                 roce_set_field(context->qpc_bytes_188,
3282                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3283                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3284                                0);
3285         } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3286                    (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3287                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3288                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3289                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3290                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3291                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3292                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3293                 dev_err(dev, "not support this status migration\n");
3294                 goto out;
3295         }
3296
3297         /* Every status migrate must change state */
3298         roce_set_field(context->qpc_bytes_144,
3299                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3300                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3301
3302         /* SW pass context to HW */
3303         ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3304                                     to_hns_roce_state(cur_state),
3305                                     to_hns_roce_state(new_state), context,
3306                                     hr_qp);
3307         if (ret) {
3308                 dev_err(dev, "hns_roce_qp_modify failed\n");
3309                 goto out;
3310         }
3311
3312         /*
3313          * Use rst2init to instead of init2init with drv,
3314          * need to hw to flash RQ HEAD by DB again
3315          */
3316         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3317                 /* Memory barrier */
3318                 wmb();
3319
3320                 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3321                                RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3322                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3323                                RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3324                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3325                                RQ_DOORBELL_U32_8_CMD_S, 1);
3326                 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3327
3328                 if (ibqp->uobject) {
3329                         hr_qp->rq.db_reg_l = hr_dev->reg_base +
3330                                      hr_dev->odb_offset +
3331                                      DB_REG_OFFSET * hr_dev->priv_uar.index;
3332                 }
3333
3334                 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3335         }
3336
3337         hr_qp->state = new_state;
3338
3339         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3340                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3341         if (attr_mask & IB_QP_PORT) {
3342                 hr_qp->port = attr->port_num - 1;
3343                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3344         }
3345
3346         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3347                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3348                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3349                 if (ibqp->send_cq != ibqp->recv_cq)
3350                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3351                                              hr_qp->qpn, NULL);
3352
3353                 hr_qp->rq.head = 0;
3354                 hr_qp->rq.tail = 0;
3355                 hr_qp->sq.head = 0;
3356                 hr_qp->sq.tail = 0;
3357                 hr_qp->sq_next_wqe = 0;
3358         }
3359 out:
3360         kfree(context);
3361         return ret;
3362 }
3363
3364 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3365                                  const struct ib_qp_attr *attr, int attr_mask,
3366                                  enum ib_qp_state cur_state,
3367                                  enum ib_qp_state new_state)
3368 {
3369
3370         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3371                 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3372                                          new_state);
3373         else
3374                 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3375                                         new_state);
3376 }
3377
3378 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3379 {
3380         switch (state) {
3381         case HNS_ROCE_QP_STATE_RST:
3382                 return IB_QPS_RESET;
3383         case HNS_ROCE_QP_STATE_INIT:
3384                 return IB_QPS_INIT;
3385         case HNS_ROCE_QP_STATE_RTR:
3386                 return IB_QPS_RTR;
3387         case HNS_ROCE_QP_STATE_RTS:
3388                 return IB_QPS_RTS;
3389         case HNS_ROCE_QP_STATE_SQD:
3390                 return IB_QPS_SQD;
3391         case HNS_ROCE_QP_STATE_ERR:
3392                 return IB_QPS_ERR;
3393         default:
3394                 return IB_QPS_ERR;
3395         }
3396 }
3397
3398 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3399                                  struct hns_roce_qp *hr_qp,
3400                                  struct hns_roce_qp_context *hr_context)
3401 {
3402         struct hns_roce_cmd_mailbox *mailbox;
3403         int ret;
3404
3405         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3406         if (IS_ERR(mailbox))
3407                 return PTR_ERR(mailbox);
3408
3409         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3410                                 HNS_ROCE_CMD_QUERY_QP,
3411                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
3412         if (!ret)
3413                 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3414         else
3415                 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3416
3417         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3418
3419         return ret;
3420 }
3421
3422 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3423                              int qp_attr_mask,
3424                              struct ib_qp_init_attr *qp_init_attr)
3425 {
3426         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3427         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3428         struct hns_roce_sqp_context context;
3429         u32 addr;
3430
3431         mutex_lock(&hr_qp->mutex);
3432
3433         if (hr_qp->state == IB_QPS_RESET) {
3434                 qp_attr->qp_state = IB_QPS_RESET;
3435                 goto done;
3436         }
3437
3438         addr = ROCEE_QP1C_CFG0_0_REG +
3439                 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3440         context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3441         context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3442         context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3443         context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3444         context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3445         context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3446         context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3447         context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3448         context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3449         context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3450
3451         hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3452                                       QP1C_BYTES_4_QP_STATE_M,
3453                                       QP1C_BYTES_4_QP_STATE_S);
3454         qp_attr->qp_state       = hr_qp->state;
3455         qp_attr->path_mtu       = IB_MTU_256;
3456         qp_attr->path_mig_state = IB_MIG_ARMED;
3457         qp_attr->qkey           = QKEY_VAL;
3458         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3459         qp_attr->rq_psn         = 0;
3460         qp_attr->sq_psn         = 0;
3461         qp_attr->dest_qp_num    = 1;
3462         qp_attr->qp_access_flags = 6;
3463
3464         qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3465                                              QP1C_BYTES_20_PKEY_IDX_M,
3466                                              QP1C_BYTES_20_PKEY_IDX_S);
3467         qp_attr->port_num = hr_qp->port + 1;
3468         qp_attr->sq_draining = 0;
3469         qp_attr->max_rd_atomic = 0;
3470         qp_attr->max_dest_rd_atomic = 0;
3471         qp_attr->min_rnr_timer = 0;
3472         qp_attr->timeout = 0;
3473         qp_attr->retry_cnt = 0;
3474         qp_attr->rnr_retry = 0;
3475         qp_attr->alt_timeout = 0;
3476
3477 done:
3478         qp_attr->cur_qp_state = qp_attr->qp_state;
3479         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3480         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3481         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3482         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3483         qp_attr->cap.max_inline_data = 0;
3484         qp_init_attr->cap = qp_attr->cap;
3485         qp_init_attr->create_flags = 0;
3486
3487         mutex_unlock(&hr_qp->mutex);
3488
3489         return 0;
3490 }
3491
3492 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3493                             int qp_attr_mask,
3494                             struct ib_qp_init_attr *qp_init_attr)
3495 {
3496         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3497         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3498         struct device *dev = &hr_dev->pdev->dev;
3499         struct hns_roce_qp_context *context;
3500         int tmp_qp_state = 0;
3501         int ret = 0;
3502         int state;
3503
3504         context = kzalloc(sizeof(*context), GFP_KERNEL);
3505         if (!context)
3506                 return -ENOMEM;
3507
3508         memset(qp_attr, 0, sizeof(*qp_attr));
3509         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3510
3511         mutex_lock(&hr_qp->mutex);
3512
3513         if (hr_qp->state == IB_QPS_RESET) {
3514                 qp_attr->qp_state = IB_QPS_RESET;
3515                 goto done;
3516         }
3517
3518         ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3519         if (ret) {
3520                 dev_err(dev, "query qpc error\n");
3521                 ret = -EINVAL;
3522                 goto out;
3523         }
3524
3525         state = roce_get_field(context->qpc_bytes_144,
3526                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3527                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3528         tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3529         if (tmp_qp_state == -1) {
3530                 dev_err(dev, "to_ib_qp_state error\n");
3531                 ret = -EINVAL;
3532                 goto out;
3533         }
3534         hr_qp->state = (u8)tmp_qp_state;
3535         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3536         qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3537                                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3538                                                QP_CONTEXT_QPC_BYTES_48_MTU_S);
3539         qp_attr->path_mig_state = IB_MIG_ARMED;
3540         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3541         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3542                 qp_attr->qkey = QKEY_VAL;
3543
3544         qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3545                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3546                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3547         qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3548                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3549                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3550         qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3551                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3552                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3553         qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3554                         QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3555                                    ((roce_get_bit(context->qpc_bytes_4,
3556                         QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3557                                    ((roce_get_bit(context->qpc_bytes_4,
3558                         QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3559
3560         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3561             hr_qp->ibqp.qp_type == IB_QPT_UC) {
3562                 struct ib_global_route *grh =
3563                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3564
3565                 rdma_ah_set_sl(&qp_attr->ah_attr,
3566                                roce_get_field(context->qpc_bytes_156,
3567                                               QP_CONTEXT_QPC_BYTES_156_SL_M,
3568                                               QP_CONTEXT_QPC_BYTES_156_SL_S));
3569                 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3570                 grh->flow_label =
3571                         roce_get_field(context->qpc_bytes_48,
3572                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3573                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3574                 grh->sgid_index =
3575                         roce_get_field(context->qpc_bytes_36,
3576                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3577                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3578                 grh->hop_limit =
3579                         roce_get_field(context->qpc_bytes_44,
3580                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3581                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3582                 grh->traffic_class =
3583                         roce_get_field(context->qpc_bytes_48,
3584                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3585                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3586
3587                 memcpy(grh->dgid.raw, context->dgid,
3588                        sizeof(grh->dgid.raw));
3589         }
3590
3591         qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3592                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3593                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3594         qp_attr->port_num = hr_qp->port + 1;
3595         qp_attr->sq_draining = 0;
3596         qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3597                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3598                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3599         qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3600                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3601                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3602         qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3603                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3604                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3605         qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3606                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3607                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3608         qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3609                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3610                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3611         qp_attr->rnr_retry = (u8)context->rnr_retry;
3612
3613 done:
3614         qp_attr->cur_qp_state = qp_attr->qp_state;
3615         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3616         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3617
3618         if (!ibqp->uobject) {
3619                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3620                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3621         } else {
3622                 qp_attr->cap.max_send_wr = 0;
3623                 qp_attr->cap.max_send_sge = 0;
3624         }
3625
3626         qp_init_attr->cap = qp_attr->cap;
3627
3628 out:
3629         mutex_unlock(&hr_qp->mutex);
3630         kfree(context);
3631         return ret;
3632 }
3633
3634 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3635                                 int qp_attr_mask,
3636                                 struct ib_qp_init_attr *qp_init_attr)
3637 {
3638         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3639
3640         return hr_qp->doorbell_qpn <= 1 ?
3641                 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3642                 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3643 }
3644
3645 static void hns_roce_check_sdb_status(struct hns_roce_dev *hr_dev,
3646                                       u32 *old_send, u32 *old_retry,
3647                                       u32 *tsp_st, u32 *success_flags)
3648 {
3649         __le32 *old_send_tmp, *old_retry_tmp;
3650         u32 sdb_retry_cnt;
3651         u32 sdb_send_ptr;
3652         u32 cur_cnt, old_cnt;
3653         __le32 tmp, tmp1;
3654         u32 send_ptr;
3655
3656         sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3657         sdb_retry_cnt = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3658         tmp = cpu_to_le32(sdb_send_ptr);
3659         tmp1 = cpu_to_le32(sdb_retry_cnt);
3660         cur_cnt = roce_get_field(tmp, ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3661                                  ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3662                   roce_get_field(tmp1, ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3663                                  ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3664
3665         old_send_tmp = (__le32 *)old_send;
3666         old_retry_tmp = (__le32 *)old_retry;
3667         if (!roce_get_bit(*tsp_st, ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3668                 old_cnt = roce_get_field(*old_send_tmp,
3669                                          ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3670                                          ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3671                           roce_get_field(*old_retry_tmp,
3672                                          ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3673                                          ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3674                 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3675                         *success_flags = 1;
3676         } else {
3677                 old_cnt = roce_get_field(*old_send_tmp,
3678                                          ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3679                                          ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3680                 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL) {
3681                         *success_flags = 1;
3682                 } else {
3683                         send_ptr = roce_get_field(*old_send_tmp,
3684                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3685                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3686                                    roce_get_field(tmp1,
3687                                             ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3688                                             ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3689                         roce_set_field(*old_send_tmp,
3690                                        ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3691                                        ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3692                                        send_ptr);
3693                 }
3694         }
3695 }
3696
3697 static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3698                                       struct hns_roce_qp *hr_qp,
3699                                       u32 sdb_issue_ptr,
3700                                       u32 *sdb_inv_cnt,
3701                                       u32 *wait_stage)
3702 {
3703         struct device *dev = &hr_dev->pdev->dev;
3704         u32 sdb_send_ptr, old_send;
3705         __le32 sdb_issue_ptr_tmp;
3706         __le32 sdb_send_ptr_tmp;
3707         u32 success_flags = 0;
3708         unsigned long end;
3709         u32 old_retry;
3710         u32 inv_cnt;
3711         u32 tsp_st;
3712         __le32 tmp;
3713
3714         if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3715             *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3716                 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3717                         hr_qp->qpn, *wait_stage);
3718                 return -EINVAL;
3719         }
3720
3721         /* Calculate the total timeout for the entire verification process */
3722         end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3723
3724         if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3725                 /* Query db process status, until hw process completely */
3726                 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3727                 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3728                                             ROCEE_SDB_PTR_CMP_BITS)) {
3729                         if (!time_before(jiffies, end)) {
3730                                 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3731                                         hr_qp->qpn, sdb_issue_ptr,
3732                                         sdb_send_ptr);
3733                                 return 0;
3734                         }
3735
3736                         msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3737                         sdb_send_ptr = roce_read(hr_dev,
3738                                                  ROCEE_SDB_SEND_PTR_REG);
3739                 }
3740
3741                 sdb_send_ptr_tmp = cpu_to_le32(sdb_send_ptr);
3742                 sdb_issue_ptr_tmp = cpu_to_le32(sdb_issue_ptr);
3743                 if (roce_get_field(sdb_issue_ptr_tmp,
3744                                    ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3745                                    ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3746                     roce_get_field(sdb_send_ptr_tmp,
3747                                    ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3748                                    ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3749                         old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3750                         old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3751
3752                         do {
3753                                 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3754                                 tmp = cpu_to_le32(tsp_st);
3755                                 if (roce_get_bit(tmp,
3756                                         ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3757                                         *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3758                                         return 0;
3759                                 }
3760
3761                                 if (!time_before(jiffies, end)) {
3762                                         dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3763                                                      "issue 0x%x send 0x%x.\n",
3764                                                 hr_qp->qpn,
3765                                                 le32_to_cpu(sdb_issue_ptr_tmp),
3766                                                 le32_to_cpu(sdb_send_ptr_tmp));
3767                                         return 0;
3768                                 }
3769
3770                                 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3771
3772                                 hns_roce_check_sdb_status(hr_dev, &old_send,
3773                                                           &old_retry, &tsp_st,
3774                                                           &success_flags);
3775                         } while (!success_flags);
3776                 }
3777
3778                 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3779
3780                 /* Get list pointer */
3781                 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3782                 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3783                         hr_qp->qpn, *sdb_inv_cnt);
3784         }
3785
3786         if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3787                 /* Query db's list status, until hw reversal */
3788                 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3789                 while (roce_hw_index_cmp_lt(inv_cnt,
3790                                             *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3791                                             ROCEE_SDB_CNT_CMP_BITS)) {
3792                         if (!time_before(jiffies, end)) {
3793                                 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3794                                         hr_qp->qpn, inv_cnt);
3795                                 return 0;
3796                         }
3797
3798                         msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3799                         inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3800                 }
3801
3802                 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3803         }
3804
3805         return 0;
3806 }
3807
3808 static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3809                                 struct hns_roce_qp *hr_qp,
3810                                 struct hns_roce_qp_work *qp_work_entry,
3811                                 int *is_timeout)
3812 {
3813         struct device *dev = &hr_dev->pdev->dev;
3814         u32 sdb_issue_ptr;
3815         int ret;
3816
3817         if (hr_qp->state != IB_QPS_RESET) {
3818                 /* Set qp to ERR, waiting for hw complete processing all dbs */
3819                 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3820                                             IB_QPS_ERR);
3821                 if (ret) {
3822                         dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3823                                 hr_qp->qpn);
3824                         return ret;
3825                 }
3826
3827                 /* Record issued doorbell */
3828                 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3829                 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3830                 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3831
3832                 /* Query db process status, until hw process completely */
3833                 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3834                                                  &qp_work_entry->sdb_inv_cnt,
3835                                                  &qp_work_entry->db_wait_stage);
3836                 if (ret) {
3837                         dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3838                                 hr_qp->qpn);
3839                         return ret;
3840                 }
3841
3842                 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3843                         qp_work_entry->sche_cnt = 0;
3844                         *is_timeout = 1;
3845                         return 0;
3846                 }
3847
3848                 /* Modify qp to reset before destroying qp */
3849                 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3850                                             IB_QPS_RESET);
3851                 if (ret) {
3852                         dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3853                                 hr_qp->qpn);
3854                         return ret;
3855                 }
3856         }
3857
3858         return 0;
3859 }
3860
3861 static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3862 {
3863         struct hns_roce_qp_work *qp_work_entry;
3864         struct hns_roce_v1_priv *priv;
3865         struct hns_roce_dev *hr_dev;
3866         struct hns_roce_qp *hr_qp;
3867         struct device *dev;
3868         unsigned long qpn;
3869         int ret;
3870
3871         qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3872         hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3873         dev = &hr_dev->pdev->dev;
3874         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3875         hr_qp = qp_work_entry->qp;
3876         qpn = hr_qp->qpn;
3877
3878         dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
3879
3880         qp_work_entry->sche_cnt++;
3881
3882         /* Query db process status, until hw process completely */
3883         ret = check_qp_db_process_status(hr_dev, hr_qp,
3884                                          qp_work_entry->sdb_issue_ptr,
3885                                          &qp_work_entry->sdb_inv_cnt,
3886                                          &qp_work_entry->db_wait_stage);
3887         if (ret) {
3888                 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3889                         qpn);
3890                 return;
3891         }
3892
3893         if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3894             priv->des_qp.requeue_flag) {
3895                 queue_work(priv->des_qp.qp_wq, work);
3896                 return;
3897         }
3898
3899         /* Modify qp to reset before destroying qp */
3900         ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3901                                     IB_QPS_RESET);
3902         if (ret) {
3903                 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
3904                 return;
3905         }
3906
3907         hns_roce_qp_remove(hr_dev, hr_qp);
3908         hns_roce_qp_free(hr_dev, hr_qp);
3909
3910         if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3911                 /* RC QP, release QPN */
3912                 hns_roce_release_range_qp(hr_dev, qpn, 1);
3913                 kfree(hr_qp);
3914         } else
3915                 kfree(hr_to_hr_sqp(hr_qp));
3916
3917         kfree(qp_work_entry);
3918
3919         dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
3920 }
3921
3922 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3923 {
3924         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3925         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3926         struct device *dev = &hr_dev->pdev->dev;
3927         struct hns_roce_qp_work qp_work_entry;
3928         struct hns_roce_qp_work *qp_work;
3929         struct hns_roce_v1_priv *priv;
3930         struct hns_roce_cq *send_cq, *recv_cq;
3931         bool is_user = ibqp->uobject;
3932         int is_timeout = 0;
3933         int ret;
3934
3935         ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3936         if (ret) {
3937                 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3938                 return ret;
3939         }
3940
3941         send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3942         recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3943
3944         hns_roce_lock_cqs(send_cq, recv_cq);
3945         if (!is_user) {
3946                 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3947                                        to_hr_srq(hr_qp->ibqp.srq) : NULL);
3948                 if (send_cq != recv_cq)
3949                         __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3950         }
3951         hns_roce_unlock_cqs(send_cq, recv_cq);
3952
3953         if (!is_timeout) {
3954                 hns_roce_qp_remove(hr_dev, hr_qp);
3955                 hns_roce_qp_free(hr_dev, hr_qp);
3956
3957                 /* RC QP, release QPN */
3958                 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3959                         hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3960         }
3961
3962         hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3963
3964         if (is_user)
3965                 ib_umem_release(hr_qp->umem);
3966         else {
3967                 kfree(hr_qp->sq.wrid);
3968                 kfree(hr_qp->rq.wrid);
3969
3970                 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3971         }
3972
3973         if (!is_timeout) {
3974                 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3975                         kfree(hr_qp);
3976                 else
3977                         kfree(hr_to_hr_sqp(hr_qp));
3978         } else {
3979                 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3980                 if (!qp_work)
3981                         return -ENOMEM;
3982
3983                 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3984                 qp_work->ib_dev = &hr_dev->ib_dev;
3985                 qp_work->qp             = hr_qp;
3986                 qp_work->db_wait_stage  = qp_work_entry.db_wait_stage;
3987                 qp_work->sdb_issue_ptr  = qp_work_entry.sdb_issue_ptr;
3988                 qp_work->sdb_inv_cnt    = qp_work_entry.sdb_inv_cnt;
3989                 qp_work->sche_cnt       = qp_work_entry.sche_cnt;
3990
3991                 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3992                 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3993                 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3994         }
3995
3996         return 0;
3997 }
3998
3999 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
4000 {
4001         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
4002         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4003         struct device *dev = &hr_dev->pdev->dev;
4004         u32 cqe_cnt_ori;
4005         u32 cqe_cnt_cur;
4006         u32 cq_buf_size;
4007         int wait_time = 0;
4008         int ret = 0;
4009
4010         hns_roce_free_cq(hr_dev, hr_cq);
4011
4012         /*
4013          * Before freeing cq buffer, we need to ensure that the outstanding CQE
4014          * have been written by checking the CQE counter.
4015          */
4016         cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
4017         while (1) {
4018                 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
4019                     HNS_ROCE_CQE_WCMD_EMPTY_BIT)
4020                         break;
4021
4022                 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
4023                 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
4024                         break;
4025
4026                 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
4027                 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
4028                         dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
4029                                 hr_cq->cqn);
4030                         ret = -ETIMEDOUT;
4031                         break;
4032                 }
4033                 wait_time++;
4034         }
4035
4036         hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
4037
4038         if (ibcq->uobject)
4039                 ib_umem_release(hr_cq->umem);
4040         else {
4041                 /* Free the buff of stored cq */
4042                 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
4043                 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
4044         }
4045
4046         kfree(hr_cq);
4047
4048         return ret;
4049 }
4050
4051 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
4052 {
4053         roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
4054                       (req_not << eq->log_entries), eq->doorbell);
4055 }
4056
4057 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
4058                                             struct hns_roce_aeqe *aeqe, int qpn)
4059 {
4060         struct device *dev = &hr_dev->pdev->dev;
4061
4062         dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
4063         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4064                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4065         case HNS_ROCE_LWQCE_QPC_ERROR:
4066                 dev_warn(dev, "QP %d, QPC error.\n", qpn);
4067                 break;
4068         case HNS_ROCE_LWQCE_MTU_ERROR:
4069                 dev_warn(dev, "QP %d, MTU error.\n", qpn);
4070                 break;
4071         case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4072                 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
4073                 break;
4074         case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4075                 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
4076                 break;
4077         case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4078                 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
4079                 break;
4080         case HNS_ROCE_LWQCE_SL_ERROR:
4081                 dev_warn(dev, "QP %d, SL error.\n", qpn);
4082                 break;
4083         case HNS_ROCE_LWQCE_PORT_ERROR:
4084                 dev_warn(dev, "QP %d, port error.\n", qpn);
4085                 break;
4086         default:
4087                 break;
4088         }
4089 }
4090
4091 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
4092                                                    struct hns_roce_aeqe *aeqe,
4093                                                    int qpn)
4094 {
4095         struct device *dev = &hr_dev->pdev->dev;
4096
4097         dev_warn(dev, "Local Access Violation Work Queue Error.\n");
4098         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4099                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4100         case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4101                 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
4102                 break;
4103         case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4104                 dev_warn(dev, "QP %d, length error.\n", qpn);
4105                 break;
4106         case HNS_ROCE_LAVWQE_VA_ERROR:
4107                 dev_warn(dev, "QP %d, VA error.\n", qpn);
4108                 break;
4109         case HNS_ROCE_LAVWQE_PD_ERROR:
4110                 dev_err(dev, "QP %d, PD error.\n", qpn);
4111                 break;
4112         case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4113                 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
4114                 break;
4115         case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4116                 dev_warn(dev, "QP %d, key state error.\n", qpn);
4117                 break;
4118         case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4119                 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
4120                 break;
4121         default:
4122                 break;
4123         }
4124 }
4125
4126 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
4127                                       struct hns_roce_aeqe *aeqe,
4128                                       int event_type)
4129 {
4130         struct device *dev = &hr_dev->pdev->dev;
4131         int phy_port;
4132         int qpn;
4133
4134         qpn = roce_get_field(aeqe->event.qp_event.qp,
4135                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
4136                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
4137         phy_port = roce_get_field(aeqe->event.qp_event.qp,
4138                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
4139                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
4140         if (qpn <= 1)
4141                 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
4142
4143         switch (event_type) {
4144         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4145                 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
4146                          "QP %d, phy_port %d.\n", qpn, phy_port);
4147                 break;
4148         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4149                 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
4150                 break;
4151         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4152                 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
4153                 break;
4154         default:
4155                 break;
4156         }
4157
4158         hns_roce_qp_event(hr_dev, qpn, event_type);
4159 }
4160
4161 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
4162                                       struct hns_roce_aeqe *aeqe,
4163                                       int event_type)
4164 {
4165         struct device *dev = &hr_dev->pdev->dev;
4166         u32 cqn;
4167
4168         cqn = roce_get_field(aeqe->event.cq_event.cq,
4169                           HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
4170                           HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
4171
4172         switch (event_type) {
4173         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4174                 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
4175                 break;
4176         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4177                 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4178                 break;
4179         case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
4180                 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
4181                 break;
4182         default:
4183                 break;
4184         }
4185
4186         hns_roce_cq_event(hr_dev, cqn, event_type);
4187 }
4188
4189 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
4190                                            struct hns_roce_aeqe *aeqe)
4191 {
4192         struct device *dev = &hr_dev->pdev->dev;
4193
4194         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4195                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4196         case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
4197                 dev_warn(dev, "SDB overflow.\n");
4198                 break;
4199         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
4200                 dev_warn(dev, "SDB almost overflow.\n");
4201                 break;
4202         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
4203                 dev_warn(dev, "SDB almost empty.\n");
4204                 break;
4205         case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
4206                 dev_warn(dev, "ODB overflow.\n");
4207                 break;
4208         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
4209                 dev_warn(dev, "ODB almost overflow.\n");
4210                 break;
4211         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
4212                 dev_warn(dev, "SDB almost empty.\n");
4213                 break;
4214         default:
4215                 break;
4216         }
4217 }
4218
4219 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
4220 {
4221         unsigned long off = (entry & (eq->entries - 1)) *
4222                              HNS_ROCE_AEQ_ENTRY_SIZE;
4223
4224         return (struct hns_roce_aeqe *)((u8 *)
4225                 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
4226                 off % HNS_ROCE_BA_SIZE);
4227 }
4228
4229 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
4230 {
4231         struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
4232
4233         return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
4234                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4235 }
4236
4237 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
4238                                struct hns_roce_eq *eq)
4239 {
4240         struct device *dev = &hr_dev->pdev->dev;
4241         struct hns_roce_aeqe *aeqe;
4242         int aeqes_found = 0;
4243         int event_type;
4244
4245         while ((aeqe = next_aeqe_sw_v1(eq))) {
4246
4247                 /* Make sure we read the AEQ entry after we have checked the
4248                  * ownership bit
4249                  */
4250                 dma_rmb();
4251
4252                 dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
4253                         roce_get_field(aeqe->asyn,
4254                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4255                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
4256                 event_type = roce_get_field(aeqe->asyn,
4257                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4258                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
4259                 switch (event_type) {
4260                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4261                         dev_warn(dev, "PATH MIG not supported\n");
4262                         break;
4263                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4264                         dev_warn(dev, "COMMUNICATION established\n");
4265                         break;
4266                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4267                         dev_warn(dev, "SQ DRAINED not supported\n");
4268                         break;
4269                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4270                         dev_warn(dev, "PATH MIG failed\n");
4271                         break;
4272                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4273                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4274                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4275                         hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
4276                         break;
4277                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4278                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4279                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4280                         dev_warn(dev, "SRQ not support!\n");
4281                         break;
4282                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4283                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4284                 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
4285                         hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
4286                         break;
4287                 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
4288                         dev_warn(dev, "port change.\n");
4289                         break;
4290                 case HNS_ROCE_EVENT_TYPE_MB:
4291                         hns_roce_cmd_event(hr_dev,
4292                                            le16_to_cpu(aeqe->event.cmd.token),
4293                                            aeqe->event.cmd.status,
4294                                            le64_to_cpu(aeqe->event.cmd.out_param
4295                                            ));
4296                         break;
4297                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4298                         hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
4299                         break;
4300                 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
4301                         dev_warn(dev, "CEQ 0x%lx overflow.\n",
4302                         roce_get_field(aeqe->event.ce_event.ceqe,
4303                                      HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M,
4304                                      HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S));
4305                         break;
4306                 default:
4307                         dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4308                                  event_type, eq->eqn, eq->cons_index);
4309                         break;
4310                 }
4311
4312                 eq->cons_index++;
4313                 aeqes_found = 1;
4314
4315                 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
4316                         dev_warn(dev, "cons_index overflow, set back to 0.\n");
4317                         eq->cons_index = 0;
4318                 }
4319         }
4320
4321         set_eq_cons_index_v1(eq, 0);
4322
4323         return aeqes_found;
4324 }
4325
4326 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
4327 {
4328         unsigned long off = (entry & (eq->entries - 1)) *
4329                              HNS_ROCE_CEQ_ENTRY_SIZE;
4330
4331         return (struct hns_roce_ceqe *)((u8 *)
4332                         (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
4333                         off % HNS_ROCE_BA_SIZE);
4334 }
4335
4336 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
4337 {
4338         struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
4339
4340         return (!!(roce_get_bit(ceqe->comp,
4341                 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
4342                 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4343 }
4344
4345 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
4346                                struct hns_roce_eq *eq)
4347 {
4348         struct hns_roce_ceqe *ceqe;
4349         int ceqes_found = 0;
4350         u32 cqn;
4351
4352         while ((ceqe = next_ceqe_sw_v1(eq))) {
4353
4354                 /* Make sure we read CEQ entry after we have checked the
4355                  * ownership bit
4356                  */
4357                 dma_rmb();
4358
4359                 cqn = roce_get_field(ceqe->comp,
4360                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
4361                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
4362                 hns_roce_cq_completion(hr_dev, cqn);
4363
4364                 ++eq->cons_index;
4365                 ceqes_found = 1;
4366
4367                 if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
4368                         dev_warn(&eq->hr_dev->pdev->dev,
4369                                 "cons_index overflow, set back to 0.\n");
4370                         eq->cons_index = 0;
4371                 }
4372         }
4373
4374         set_eq_cons_index_v1(eq, 0);
4375
4376         return ceqes_found;
4377 }
4378
4379 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
4380 {
4381         struct hns_roce_eq  *eq  = eq_ptr;
4382         struct hns_roce_dev *hr_dev = eq->hr_dev;
4383         int int_work = 0;
4384
4385         if (eq->type_flag == HNS_ROCE_CEQ)
4386                 /* CEQ irq routine, CEQ is pulse irq, not clear */
4387                 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4388         else
4389                 /* AEQ irq routine, AEQ is pulse irq, not clear */
4390                 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4391
4392         return IRQ_RETVAL(int_work);
4393 }
4394
4395 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4396 {
4397         struct hns_roce_dev *hr_dev = dev_id;
4398         struct device *dev = &hr_dev->pdev->dev;
4399         int int_work = 0;
4400         u32 caepaemask_val;
4401         u32 cealmovf_val;
4402         u32 caepaest_val;
4403         u32 aeshift_val;
4404         u32 ceshift_val;
4405         u32 cemask_val;
4406         __le32 tmp;
4407         int i;
4408
4409         /*
4410          * Abnormal interrupt:
4411          * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4412          * interrupt, mask irq, clear irq, cancel mask operation
4413          */
4414         aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4415         tmp = cpu_to_le32(aeshift_val);
4416
4417         /* AEQE overflow */
4418         if (roce_get_bit(tmp,
4419                 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4420                 dev_warn(dev, "AEQ overflow!\n");
4421
4422                 /* Set mask */
4423                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4424                 tmp = cpu_to_le32(caepaemask_val);
4425                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4426                              HNS_ROCE_INT_MASK_ENABLE);
4427                 caepaemask_val = le32_to_cpu(tmp);
4428                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4429
4430                 /* Clear int state(INT_WC : write 1 clear) */
4431                 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4432                 tmp = cpu_to_le32(caepaest_val);
4433                 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4434                 caepaest_val = le32_to_cpu(tmp);
4435                 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4436
4437                 /* Clear mask */
4438                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4439                 tmp = cpu_to_le32(caepaemask_val);
4440                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4441                              HNS_ROCE_INT_MASK_DISABLE);
4442                 caepaemask_val = le32_to_cpu(tmp);
4443                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4444         }
4445
4446         /* CEQ almost overflow */
4447         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4448                 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4449                                         i * CEQ_REG_OFFSET);
4450                 tmp = cpu_to_le32(ceshift_val);
4451
4452                 if (roce_get_bit(tmp,
4453                         ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4454                         dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4455                         int_work++;
4456
4457                         /* Set mask */
4458                         cemask_val = roce_read(hr_dev,
4459                                                ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4460                                                i * CEQ_REG_OFFSET);
4461                         tmp = cpu_to_le32(cemask_val);
4462                         roce_set_bit(tmp,
4463                                 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4464                                 HNS_ROCE_INT_MASK_ENABLE);
4465                         cemask_val = le32_to_cpu(tmp);
4466                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4467                                    i * CEQ_REG_OFFSET, cemask_val);
4468
4469                         /* Clear int state(INT_WC : write 1 clear) */
4470                         cealmovf_val = roce_read(hr_dev,
4471                                        ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4472                                        i * CEQ_REG_OFFSET);
4473                         tmp = cpu_to_le32(cealmovf_val);
4474                         roce_set_bit(tmp,
4475                                      ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4476                                      1);
4477                         cealmovf_val = le32_to_cpu(tmp);
4478                         roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4479                                    i * CEQ_REG_OFFSET, cealmovf_val);
4480
4481                         /* Clear mask */
4482                         cemask_val = roce_read(hr_dev,
4483                                      ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4484                                      i * CEQ_REG_OFFSET);
4485                         tmp = cpu_to_le32(cemask_val);
4486                         roce_set_bit(tmp,
4487                                ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4488                                HNS_ROCE_INT_MASK_DISABLE);
4489                         cemask_val = le32_to_cpu(tmp);
4490                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4491                                    i * CEQ_REG_OFFSET, cemask_val);
4492                 }
4493         }
4494
4495         /* ECC multi-bit error alarm */
4496         dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4497                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4498                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4499                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4500
4501         dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4502                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4503                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4504                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4505
4506         return IRQ_RETVAL(int_work);
4507 }
4508
4509 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4510 {
4511         u32 aemask_val;
4512         int masken = 0;
4513         __le32 tmp;
4514         int i;
4515
4516         /* AEQ INT */
4517         aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4518         tmp = cpu_to_le32(aemask_val);
4519         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4520                      masken);
4521         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4522         aemask_val = le32_to_cpu(tmp);
4523         roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4524
4525         /* CEQ INT */
4526         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4527                 /* IRQ mask */
4528                 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4529                            i * CEQ_REG_OFFSET, masken);
4530         }
4531 }
4532
4533 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4534                                 struct hns_roce_eq *eq)
4535 {
4536         int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4537                       HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4538         int i;
4539
4540         if (!eq->buf_list)
4541                 return;
4542
4543         for (i = 0; i < npages; ++i)
4544                 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4545                                   eq->buf_list[i].buf, eq->buf_list[i].map);
4546
4547         kfree(eq->buf_list);
4548 }
4549
4550 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4551                                   int enable_flag)
4552 {
4553         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4554         __le32 tmp;
4555         u32 val;
4556
4557         val = readl(eqc);
4558         tmp = cpu_to_le32(val);
4559
4560         if (enable_flag)
4561                 roce_set_field(tmp,
4562                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4563                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4564                                HNS_ROCE_EQ_STAT_VALID);
4565         else
4566                 roce_set_field(tmp,
4567                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4568                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4569                                HNS_ROCE_EQ_STAT_INVALID);
4570
4571         val = le32_to_cpu(tmp);
4572         writel(val, eqc);
4573 }
4574
4575 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4576                                  struct hns_roce_eq *eq)
4577 {
4578         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4579         struct device *dev = &hr_dev->pdev->dev;
4580         dma_addr_t tmp_dma_addr;
4581         u32 eqconsindx_val = 0;
4582         u32 eqcuridx_val = 0;
4583         u32 eqshift_val = 0;
4584         __le32 tmp2 = 0;
4585         __le32 tmp1 = 0;
4586         __le32 tmp = 0;
4587         int num_bas;
4588         int ret;
4589         int i;
4590
4591         num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4592                    HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4593
4594         if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4595                 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4596                         (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4597                         num_bas);
4598                 return -EINVAL;
4599         }
4600
4601         eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4602         if (!eq->buf_list)
4603                 return -ENOMEM;
4604
4605         for (i = 0; i < num_bas; ++i) {
4606                 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4607                                                          &tmp_dma_addr,
4608                                                          GFP_KERNEL);
4609                 if (!eq->buf_list[i].buf) {
4610                         ret = -ENOMEM;
4611                         goto err_out_free_pages;
4612                 }
4613
4614                 eq->buf_list[i].map = tmp_dma_addr;
4615                 memset(eq->buf_list[i].buf, 0, HNS_ROCE_BA_SIZE);
4616         }
4617         eq->cons_index = 0;
4618         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4619                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4620                        HNS_ROCE_EQ_STAT_INVALID);
4621         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4622                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4623                        eq->log_entries);
4624         eqshift_val = le32_to_cpu(tmp);
4625         writel(eqshift_val, eqc);
4626
4627         /* Configure eq extended address 12~44bit */
4628         writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4629
4630         /*
4631          * Configure eq extended address 45~49 bit.
4632          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4633          * using 4K page, and shift more 32 because of
4634          * caculating the high 32 bit value evaluated to hardware.
4635          */
4636         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4637                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4638                        eq->buf_list[0].map >> 44);
4639         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4640                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4641         eqcuridx_val = le32_to_cpu(tmp1);
4642         writel(eqcuridx_val, eqc + 8);
4643
4644         /* Configure eq consumer index */
4645         roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4646                        ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4647         eqconsindx_val = le32_to_cpu(tmp2);
4648         writel(eqconsindx_val, eqc + 0xc);
4649
4650         return 0;
4651
4652 err_out_free_pages:
4653         for (i -= 1; i >= 0; i--)
4654                 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4655                                   eq->buf_list[i].map);
4656
4657         kfree(eq->buf_list);
4658         return ret;
4659 }
4660
4661 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4662 {
4663         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4664         struct device *dev = &hr_dev->pdev->dev;
4665         struct hns_roce_eq *eq;
4666         int irq_num;
4667         int eq_num;
4668         int ret;
4669         int i, j;
4670
4671         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4672         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4673
4674         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4675         if (!eq_table->eq)
4676                 return -ENOMEM;
4677
4678         eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4679                                      GFP_KERNEL);
4680         if (!eq_table->eqc_base) {
4681                 ret = -ENOMEM;
4682                 goto err_eqc_base_alloc_fail;
4683         }
4684
4685         for (i = 0; i < eq_num; i++) {
4686                 eq = &eq_table->eq[i];
4687                 eq->hr_dev = hr_dev;
4688                 eq->eqn = i;
4689                 eq->irq = hr_dev->irq[i];
4690                 eq->log_page_size = PAGE_SHIFT;
4691
4692                 if (i < hr_dev->caps.num_comp_vectors) {
4693                         /* CEQ */
4694                         eq_table->eqc_base[i] = hr_dev->reg_base +
4695                                                 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4696                                                 CEQ_REG_OFFSET * i;
4697                         eq->type_flag = HNS_ROCE_CEQ;
4698                         eq->doorbell = hr_dev->reg_base +
4699                                        ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4700                                        CEQ_REG_OFFSET * i;
4701                         eq->entries = hr_dev->caps.ceqe_depth;
4702                         eq->log_entries = ilog2(eq->entries);
4703                         eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
4704                 } else {
4705                         /* AEQ */
4706                         eq_table->eqc_base[i] = hr_dev->reg_base +
4707                                                 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4708                         eq->type_flag = HNS_ROCE_AEQ;
4709                         eq->doorbell = hr_dev->reg_base +
4710                                        ROCEE_CAEP_AEQE_CONS_IDX_REG;
4711                         eq->entries = hr_dev->caps.aeqe_depth;
4712                         eq->log_entries = ilog2(eq->entries);
4713                         eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
4714                 }
4715         }
4716
4717         /* Disable irq */
4718         hns_roce_v1_int_mask_enable(hr_dev);
4719
4720         /* Configure ce int interval */
4721         roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4722                    HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4723
4724         /* Configure ce int burst num */
4725         roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4726                    HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4727
4728         for (i = 0; i < eq_num; i++) {
4729                 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4730                 if (ret) {
4731                         dev_err(dev, "eq create failed\n");
4732                         goto err_create_eq_fail;
4733                 }
4734         }
4735
4736         for (j = 0; j < irq_num; j++) {
4737                 if (j < eq_num)
4738                         ret = request_irq(hr_dev->irq[j],
4739                                           hns_roce_v1_msix_interrupt_eq, 0,
4740                                           hr_dev->irq_names[j],
4741                                           &eq_table->eq[j]);
4742                 else
4743                         ret = request_irq(hr_dev->irq[j],
4744                                           hns_roce_v1_msix_interrupt_abn, 0,
4745                                           hr_dev->irq_names[j], hr_dev);
4746
4747                 if (ret) {
4748                         dev_err(dev, "request irq error!\n");
4749                         goto err_request_irq_fail;
4750                 }
4751         }
4752
4753         for (i = 0; i < eq_num; i++)
4754                 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4755
4756         return 0;
4757
4758 err_request_irq_fail:
4759         for (j -= 1; j >= 0; j--)
4760                 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4761
4762 err_create_eq_fail:
4763         for (i -= 1; i >= 0; i--)
4764                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4765
4766         kfree(eq_table->eqc_base);
4767
4768 err_eqc_base_alloc_fail:
4769         kfree(eq_table->eq);
4770
4771         return ret;
4772 }
4773
4774 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4775 {
4776         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4777         int irq_num;
4778         int eq_num;
4779         int i;
4780
4781         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4782         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4783         for (i = 0; i < eq_num; i++) {
4784                 /* Disable EQ */
4785                 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4786
4787                 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4788
4789                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4790         }
4791         for (i = eq_num; i < irq_num; i++)
4792                 free_irq(hr_dev->irq[i], hr_dev);
4793
4794         kfree(eq_table->eqc_base);
4795         kfree(eq_table->eq);
4796 }
4797
4798 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4799         .destroy_qp = hns_roce_v1_destroy_qp,
4800         .modify_cq = hns_roce_v1_modify_cq,
4801         .poll_cq = hns_roce_v1_poll_cq,
4802         .post_recv = hns_roce_v1_post_recv,
4803         .post_send = hns_roce_v1_post_send,
4804         .query_qp = hns_roce_v1_query_qp,
4805         .req_notify_cq = hns_roce_v1_req_notify_cq,
4806 };
4807
4808 static const struct hns_roce_hw hns_roce_hw_v1 = {
4809         .reset = hns_roce_v1_reset,
4810         .hw_profile = hns_roce_v1_profile,
4811         .hw_init = hns_roce_v1_init,
4812         .hw_exit = hns_roce_v1_exit,
4813         .post_mbox = hns_roce_v1_post_mbox,
4814         .chk_mbox = hns_roce_v1_chk_mbox,
4815         .set_gid = hns_roce_v1_set_gid,
4816         .set_mac = hns_roce_v1_set_mac,
4817         .set_mtu = hns_roce_v1_set_mtu,
4818         .write_mtpt = hns_roce_v1_write_mtpt,
4819         .write_cqc = hns_roce_v1_write_cqc,
4820         .modify_cq = hns_roce_v1_modify_cq,
4821         .clear_hem = hns_roce_v1_clear_hem,
4822         .modify_qp = hns_roce_v1_modify_qp,
4823         .query_qp = hns_roce_v1_query_qp,
4824         .destroy_qp = hns_roce_v1_destroy_qp,
4825         .post_send = hns_roce_v1_post_send,
4826         .post_recv = hns_roce_v1_post_recv,
4827         .req_notify_cq = hns_roce_v1_req_notify_cq,
4828         .poll_cq = hns_roce_v1_poll_cq,
4829         .dereg_mr = hns_roce_v1_dereg_mr,
4830         .destroy_cq = hns_roce_v1_destroy_cq,
4831         .init_eq = hns_roce_v1_init_eq_table,
4832         .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4833         .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4834 };
4835
4836 static const struct of_device_id hns_roce_of_match[] = {
4837         { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4838         {},
4839 };
4840 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4841
4842 static const struct acpi_device_id hns_roce_acpi_match[] = {
4843         { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4844         {},
4845 };
4846 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4847
4848 static int hns_roce_node_match(struct device *dev, void *fwnode)
4849 {
4850         return dev->fwnode == fwnode;
4851 }
4852
4853 static struct
4854 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4855 {
4856         struct device *dev;
4857
4858         /* get the 'device' corresponding to the matching 'fwnode' */
4859         dev = bus_find_device(&platform_bus_type, NULL,
4860                               fwnode, hns_roce_node_match);
4861         /* get the platform device */
4862         return dev ? to_platform_device(dev) : NULL;
4863 }
4864
4865 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4866 {
4867         struct device *dev = &hr_dev->pdev->dev;
4868         struct platform_device *pdev = NULL;
4869         struct net_device *netdev = NULL;
4870         struct device_node *net_node;
4871         struct resource *res;
4872         int port_cnt = 0;
4873         u8 phy_port;
4874         int ret;
4875         int i;
4876
4877         /* check if we are compatible with the underlying SoC */
4878         if (dev_of_node(dev)) {
4879                 const struct of_device_id *of_id;
4880
4881                 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4882                 if (!of_id) {
4883                         dev_err(dev, "device is not compatible!\n");
4884                         return -ENXIO;
4885                 }
4886                 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4887                 if (!hr_dev->hw) {
4888                         dev_err(dev, "couldn't get H/W specific DT data!\n");
4889                         return -ENXIO;
4890                 }
4891         } else if (is_acpi_device_node(dev->fwnode)) {
4892                 const struct acpi_device_id *acpi_id;
4893
4894                 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4895                 if (!acpi_id) {
4896                         dev_err(dev, "device is not compatible!\n");
4897                         return -ENXIO;
4898                 }
4899                 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4900                 if (!hr_dev->hw) {
4901                         dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4902                         return -ENXIO;
4903                 }
4904         } else {
4905                 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4906                 return -ENXIO;
4907         }
4908
4909         /* get the mapped register base address */
4910         res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4911         hr_dev->reg_base = devm_ioremap_resource(dev, res);
4912         if (IS_ERR(hr_dev->reg_base))
4913                 return PTR_ERR(hr_dev->reg_base);
4914
4915         /* read the node_guid of IB device from the DT or ACPI */
4916         ret = device_property_read_u8_array(dev, "node-guid",
4917                                             (u8 *)&hr_dev->ib_dev.node_guid,
4918                                             GUID_LEN);
4919         if (ret) {
4920                 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4921                 return ret;
4922         }
4923
4924         /* get the RoCE associated ethernet ports or netdevices */
4925         for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4926                 if (dev_of_node(dev)) {
4927                         net_node = of_parse_phandle(dev->of_node, "eth-handle",
4928                                                     i);
4929                         if (!net_node)
4930                                 continue;
4931                         pdev = of_find_device_by_node(net_node);
4932                 } else if (is_acpi_device_node(dev->fwnode)) {
4933                         struct fwnode_reference_args args;
4934
4935                         ret = acpi_node_get_property_reference(dev->fwnode,
4936                                                                "eth-handle",
4937                                                                i, &args);
4938                         if (ret)
4939                                 continue;
4940                         pdev = hns_roce_find_pdev(args.fwnode);
4941                 } else {
4942                         dev_err(dev, "cannot read data from DT or ACPI\n");
4943                         return -ENXIO;
4944                 }
4945
4946                 if (pdev) {
4947                         netdev = platform_get_drvdata(pdev);
4948                         phy_port = (u8)i;
4949                         if (netdev) {
4950                                 hr_dev->iboe.netdevs[port_cnt] = netdev;
4951                                 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4952                         } else {
4953                                 dev_err(dev, "no netdev found with pdev %s\n",
4954                                         pdev->name);
4955                                 return -ENODEV;
4956                         }
4957                         port_cnt++;
4958                 }
4959         }
4960
4961         if (port_cnt == 0) {
4962                 dev_err(dev, "unable to get eth-handle for available ports!\n");
4963                 return -EINVAL;
4964         }
4965
4966         hr_dev->caps.num_ports = port_cnt;
4967
4968         /* cmd issue mode: 0 is poll, 1 is event */
4969         hr_dev->cmd_mod = 1;
4970         hr_dev->loop_idc = 0;
4971         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4972         hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4973
4974         /* read the interrupt names from the DT or ACPI */
4975         ret = device_property_read_string_array(dev, "interrupt-names",
4976                                                 hr_dev->irq_names,
4977                                                 HNS_ROCE_V1_MAX_IRQ_NUM);
4978         if (ret < 0) {
4979                 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4980                 return ret;
4981         }
4982
4983         /* fetch the interrupt numbers */
4984         for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4985                 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4986                 if (hr_dev->irq[i] <= 0) {
4987                         dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4988                         return -EINVAL;
4989                 }
4990         }
4991
4992         return 0;
4993 }
4994
4995 /**
4996  * hns_roce_probe - RoCE driver entrance
4997  * @pdev: pointer to platform device
4998  * Return : int
4999  *
5000  */
5001 static int hns_roce_probe(struct platform_device *pdev)
5002 {
5003         int ret;
5004         struct hns_roce_dev *hr_dev;
5005         struct device *dev = &pdev->dev;
5006
5007         hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
5008         if (!hr_dev)
5009                 return -ENOMEM;
5010
5011         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
5012         if (!hr_dev->priv) {
5013                 ret = -ENOMEM;
5014                 goto error_failed_kzalloc;
5015         }
5016
5017         hr_dev->pdev = pdev;
5018         hr_dev->dev = dev;
5019         platform_set_drvdata(pdev, hr_dev);
5020
5021         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
5022             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
5023                 dev_err(dev, "Not usable DMA addressing mode\n");
5024                 ret = -EIO;
5025                 goto error_failed_get_cfg;
5026         }
5027
5028         ret = hns_roce_get_cfg(hr_dev);
5029         if (ret) {
5030                 dev_err(dev, "Get Configuration failed!\n");
5031                 goto error_failed_get_cfg;
5032         }
5033
5034         ret = hns_roce_init(hr_dev);
5035         if (ret) {
5036                 dev_err(dev, "RoCE engine init failed!\n");
5037                 goto error_failed_get_cfg;
5038         }
5039
5040         return 0;
5041
5042 error_failed_get_cfg:
5043         kfree(hr_dev->priv);
5044
5045 error_failed_kzalloc:
5046         ib_dealloc_device(&hr_dev->ib_dev);
5047
5048         return ret;
5049 }
5050
5051 /**
5052  * hns_roce_remove - remove RoCE device
5053  * @pdev: pointer to platform device
5054  */
5055 static int hns_roce_remove(struct platform_device *pdev)
5056 {
5057         struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
5058
5059         hns_roce_exit(hr_dev);
5060         kfree(hr_dev->priv);
5061         ib_dealloc_device(&hr_dev->ib_dev);
5062
5063         return 0;
5064 }
5065
5066 static struct platform_driver hns_roce_driver = {
5067         .probe = hns_roce_probe,
5068         .remove = hns_roce_remove,
5069         .driver = {
5070                 .name = DRV_NAME,
5071                 .of_match_table = hns_roce_of_match,
5072                 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
5073         },
5074 };
5075
5076 module_platform_driver(hns_roce_driver);
5077
5078 MODULE_LICENSE("Dual BSD/GPL");
5079 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5080 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
5081 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5082 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");