2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
58 #define DRIVER_NAME "mlx5_ib"
59 #define DRIVER_VERSION "2.2-1"
60 #define DRIVER_RELDATE "Feb 2014"
62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_VERSION(DRIVER_VERSION);
67 static int deprecated_prof_sel = 2;
68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
71 static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
79 static enum rdma_link_layer
80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
82 switch (port_type_cap) {
83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
88 return IB_LINK_LAYER_UNSPECIFIED;
92 static enum rdma_link_layer
93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
101 static int mlx5_netdev_event(struct notifier_block *this,
102 unsigned long event, void *ptr)
104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
109 case NETDEV_REGISTER:
110 case NETDEV_UNREGISTER:
111 write_lock(&ibdev->roce.netdev_lock);
112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
115 write_unlock(&ibdev->roce.netdev_lock);
120 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
121 struct net_device *upper = NULL;
124 upper = netdev_master_upper_dev_get(lag_ndev);
128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
129 && ibdev->ib_active) {
130 struct ib_event ibev = {0};
132 ibev.device = &ibdev->ib_dev;
133 ibev.event = (event == NETDEV_UP) ?
134 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
135 ibev.element.port_num = 1;
136 ib_dispatch_event(&ibev);
148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
151 struct mlx5_ib_dev *ibdev = to_mdev(device);
152 struct net_device *ndev;
154 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
158 /* Ensure ndev does not disappear before we invoke dev_hold()
160 read_lock(&ibdev->roce.netdev_lock);
161 ndev = ibdev->roce.netdev;
164 read_unlock(&ibdev->roce.netdev_lock);
169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
170 struct ib_port_attr *props)
172 struct mlx5_ib_dev *dev = to_mdev(device);
173 struct net_device *ndev, *upper;
174 enum ib_mtu ndev_ib_mtu;
177 memset(props, 0, sizeof(*props));
179 props->port_cap_flags |= IB_PORT_CM_SUP;
180 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
182 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
183 roce_address_table_size);
184 props->max_mtu = IB_MTU_4096;
185 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
186 props->pkey_tbl_len = 1;
187 props->state = IB_PORT_DOWN;
188 props->phys_state = 3;
190 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
191 props->qkey_viol_cntr = qkey_viol_cntr;
193 ndev = mlx5_ib_get_netdev(device, port_num);
197 if (mlx5_lag_is_active(dev->mdev)) {
199 upper = netdev_master_upper_dev_get_rcu(ndev);
208 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
209 props->state = IB_PORT_ACTIVE;
210 props->phys_state = 5;
213 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
217 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
219 props->active_width = IB_WIDTH_4X; /* TODO */
220 props->active_speed = IB_SPEED_QDR; /* TODO */
225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
226 const struct ib_gid_attr *attr,
229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
230 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
232 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
238 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
240 if (is_vlan_dev(attr->ndev)) {
241 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
242 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
245 switch (attr->gid_type) {
247 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
249 case IB_GID_TYPE_ROCE_UDP_ENCAP:
250 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
257 if (attr->gid_type != IB_GID_TYPE_IB) {
258 if (ipv6_addr_v4mapped((void *)gid))
259 MLX5_SET_RA(mlx5_addr, roce_l3_type,
260 MLX5_ROCE_L3_TYPE_IPV4);
262 MLX5_SET_RA(mlx5_addr, roce_l3_type,
263 MLX5_ROCE_L3_TYPE_IPV6);
266 if ((attr->gid_type == IB_GID_TYPE_IB) ||
267 !ipv6_addr_v4mapped((void *)gid))
268 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
270 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
273 static int set_roce_addr(struct ib_device *device, u8 port_num,
275 const union ib_gid *gid,
276 const struct ib_gid_attr *attr)
278 struct mlx5_ib_dev *dev = to_mdev(device);
279 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
280 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
281 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
282 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
284 if (ll != IB_LINK_LAYER_ETHERNET)
287 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
289 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
290 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
291 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
295 unsigned int index, const union ib_gid *gid,
296 const struct ib_gid_attr *attr,
297 __always_unused void **context)
299 return set_roce_addr(device, port_num, index, gid, attr);
302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
303 unsigned int index, __always_unused void **context)
305 return set_roce_addr(device, port_num, index, NULL, NULL);
308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
311 struct ib_gid_attr attr;
314 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
322 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
325 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
328 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
330 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
331 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
336 MLX5_VPORT_ACCESS_METHOD_MAD,
337 MLX5_VPORT_ACCESS_METHOD_HCA,
338 MLX5_VPORT_ACCESS_METHOD_NIC,
341 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
343 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
344 return MLX5_VPORT_ACCESS_METHOD_MAD;
346 if (mlx5_ib_port_link_layer(ibdev, 1) ==
347 IB_LINK_LAYER_ETHERNET)
348 return MLX5_VPORT_ACCESS_METHOD_NIC;
350 return MLX5_VPORT_ACCESS_METHOD_HCA;
353 static void get_atomic_caps(struct mlx5_ib_dev *dev,
354 struct ib_device_attr *props)
357 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
358 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
359 u8 atomic_req_8B_endianness_mode =
360 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
362 /* Check if HW supports 8 bytes standard atomic operations and capable
363 * of host endianness respond
365 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
366 if (((atomic_operations & tmp) == tmp) &&
367 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
368 (atomic_req_8B_endianness_mode)) {
369 props->atomic_cap = IB_ATOMIC_HCA;
371 props->atomic_cap = IB_ATOMIC_NONE;
375 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
376 __be64 *sys_image_guid)
378 struct mlx5_ib_dev *dev = to_mdev(ibdev);
379 struct mlx5_core_dev *mdev = dev->mdev;
383 switch (mlx5_get_vport_access_method(ibdev)) {
384 case MLX5_VPORT_ACCESS_METHOD_MAD:
385 return mlx5_query_mad_ifc_system_image_guid(ibdev,
388 case MLX5_VPORT_ACCESS_METHOD_HCA:
389 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
392 case MLX5_VPORT_ACCESS_METHOD_NIC:
393 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
401 *sys_image_guid = cpu_to_be64(tmp);
407 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
410 struct mlx5_ib_dev *dev = to_mdev(ibdev);
411 struct mlx5_core_dev *mdev = dev->mdev;
413 switch (mlx5_get_vport_access_method(ibdev)) {
414 case MLX5_VPORT_ACCESS_METHOD_MAD:
415 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
417 case MLX5_VPORT_ACCESS_METHOD_HCA:
418 case MLX5_VPORT_ACCESS_METHOD_NIC:
419 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
428 static int mlx5_query_vendor_id(struct ib_device *ibdev,
431 struct mlx5_ib_dev *dev = to_mdev(ibdev);
433 switch (mlx5_get_vport_access_method(ibdev)) {
434 case MLX5_VPORT_ACCESS_METHOD_MAD:
435 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
437 case MLX5_VPORT_ACCESS_METHOD_HCA:
438 case MLX5_VPORT_ACCESS_METHOD_NIC:
439 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
446 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
452 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
453 case MLX5_VPORT_ACCESS_METHOD_MAD:
454 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
456 case MLX5_VPORT_ACCESS_METHOD_HCA:
457 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
460 case MLX5_VPORT_ACCESS_METHOD_NIC:
461 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
469 *node_guid = cpu_to_be64(tmp);
474 struct mlx5_reg_node_desc {
475 u8 desc[IB_DEVICE_NODE_DESC_MAX];
478 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
480 struct mlx5_reg_node_desc in;
482 if (mlx5_use_mad_ifc(dev))
483 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
485 memset(&in, 0, sizeof(in));
487 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
488 sizeof(struct mlx5_reg_node_desc),
489 MLX5_REG_NODE_DESC, 0, 0);
492 static int mlx5_ib_query_device(struct ib_device *ibdev,
493 struct ib_device_attr *props,
494 struct ib_udata *uhw)
496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
497 struct mlx5_core_dev *mdev = dev->mdev;
501 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
502 struct mlx5_ib_query_device_resp resp = {};
506 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
507 if (uhw->outlen && uhw->outlen < resp_len)
510 resp.response_length = resp_len;
512 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
515 memset(props, 0, sizeof(*props));
516 err = mlx5_query_system_image_guid(ibdev,
517 &props->sys_image_guid);
521 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
525 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
529 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
530 (fw_rev_min(dev->mdev) << 16) |
531 fw_rev_sub(dev->mdev);
532 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
533 IB_DEVICE_PORT_ACTIVE_EVENT |
534 IB_DEVICE_SYS_IMAGE_GUID |
535 IB_DEVICE_RC_RNR_NAK_GEN;
537 if (MLX5_CAP_GEN(mdev, pkv))
538 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
539 if (MLX5_CAP_GEN(mdev, qkv))
540 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
541 if (MLX5_CAP_GEN(mdev, apm))
542 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
543 if (MLX5_CAP_GEN(mdev, xrc))
544 props->device_cap_flags |= IB_DEVICE_XRC;
545 if (MLX5_CAP_GEN(mdev, imaicl)) {
546 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
547 IB_DEVICE_MEM_WINDOW_TYPE_2B;
548 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
549 /* We support 'Gappy' memory registration too */
550 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
552 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
553 if (MLX5_CAP_GEN(mdev, sho)) {
554 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
555 /* At this stage no support for signature handover */
556 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
557 IB_PROT_T10DIF_TYPE_2 |
558 IB_PROT_T10DIF_TYPE_3;
559 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
560 IB_GUARD_T10DIF_CSUM;
562 if (MLX5_CAP_GEN(mdev, block_lb_mc))
563 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
565 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
566 if (MLX5_CAP_ETH(mdev, csum_cap))
567 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
569 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
570 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
572 resp.tso_caps.max_tso = 1 << max_tso;
573 resp.tso_caps.supported_qpts |=
574 1 << IB_QPT_RAW_PACKET;
575 resp.response_length += sizeof(resp.tso_caps);
579 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
580 resp.rss_caps.rx_hash_function =
581 MLX5_RX_HASH_FUNC_TOEPLITZ;
582 resp.rss_caps.rx_hash_fields_mask =
583 MLX5_RX_HASH_SRC_IPV4 |
584 MLX5_RX_HASH_DST_IPV4 |
585 MLX5_RX_HASH_SRC_IPV6 |
586 MLX5_RX_HASH_DST_IPV6 |
587 MLX5_RX_HASH_SRC_PORT_TCP |
588 MLX5_RX_HASH_DST_PORT_TCP |
589 MLX5_RX_HASH_SRC_PORT_UDP |
590 MLX5_RX_HASH_DST_PORT_UDP;
591 resp.response_length += sizeof(resp.rss_caps);
594 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
595 resp.response_length += sizeof(resp.tso_caps);
596 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
597 resp.response_length += sizeof(resp.rss_caps);
600 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
601 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
602 props->device_cap_flags |= IB_DEVICE_UD_TSO;
605 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
606 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
607 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
609 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
610 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
612 props->vendor_part_id = mdev->pdev->device;
613 props->hw_ver = mdev->pdev->revision;
615 props->max_mr_size = ~0ull;
616 props->page_size_cap = ~(min_page_size - 1);
617 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
618 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
619 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
620 sizeof(struct mlx5_wqe_data_seg);
621 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
622 sizeof(struct mlx5_wqe_ctrl_seg)) /
623 sizeof(struct mlx5_wqe_data_seg);
624 props->max_sge = min(max_rq_sg, max_sq_sg);
625 props->max_sge_rd = MLX5_MAX_SGE_RD;
626 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
627 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
628 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
629 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
630 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
631 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
632 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
633 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
634 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
635 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
636 props->max_srq_sge = max_rq_sg - 1;
637 props->max_fast_reg_page_list_len =
638 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
639 get_atomic_caps(dev, props);
640 props->masked_atomic_cap = IB_ATOMIC_NONE;
641 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
642 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
643 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
644 props->max_mcast_grp;
645 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
646 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
647 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
649 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
650 if (MLX5_CAP_GEN(mdev, pg))
651 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
652 props->odp_caps = dev->odp_caps;
655 if (MLX5_CAP_GEN(mdev, cd))
656 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
658 if (!mlx5_core_is_pf(mdev))
659 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
661 if (mlx5_ib_port_link_layer(ibdev, 1) ==
662 IB_LINK_LAYER_ETHERNET) {
663 props->rss_caps.max_rwq_indirection_tables =
664 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
665 props->rss_caps.max_rwq_indirection_table_size =
666 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
667 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
668 props->max_wq_type_rq =
669 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
673 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
683 MLX5_IB_WIDTH_1X = 1 << 0,
684 MLX5_IB_WIDTH_2X = 1 << 1,
685 MLX5_IB_WIDTH_4X = 1 << 2,
686 MLX5_IB_WIDTH_8X = 1 << 3,
687 MLX5_IB_WIDTH_12X = 1 << 4
690 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
693 struct mlx5_ib_dev *dev = to_mdev(ibdev);
696 if (active_width & MLX5_IB_WIDTH_1X) {
697 *ib_width = IB_WIDTH_1X;
698 } else if (active_width & MLX5_IB_WIDTH_2X) {
699 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
702 } else if (active_width & MLX5_IB_WIDTH_4X) {
703 *ib_width = IB_WIDTH_4X;
704 } else if (active_width & MLX5_IB_WIDTH_8X) {
705 *ib_width = IB_WIDTH_8X;
706 } else if (active_width & MLX5_IB_WIDTH_12X) {
707 *ib_width = IB_WIDTH_12X;
709 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
717 static int mlx5_mtu_to_ib_mtu(int mtu)
726 pr_warn("invalid mtu\n");
736 __IB_MAX_VL_0_14 = 5,
739 enum mlx5_vl_hw_cap {
751 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
756 *max_vl_num = __IB_MAX_VL_0;
759 *max_vl_num = __IB_MAX_VL_0_1;
762 *max_vl_num = __IB_MAX_VL_0_3;
765 *max_vl_num = __IB_MAX_VL_0_7;
767 case MLX5_VL_HW_0_14:
768 *max_vl_num = __IB_MAX_VL_0_14;
778 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
779 struct ib_port_attr *props)
781 struct mlx5_ib_dev *dev = to_mdev(ibdev);
782 struct mlx5_core_dev *mdev = dev->mdev;
783 struct mlx5_hca_vport_context *rep;
787 u8 ib_link_width_oper;
790 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
796 memset(props, 0, sizeof(*props));
798 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
802 props->lid = rep->lid;
803 props->lmc = rep->lmc;
804 props->sm_lid = rep->sm_lid;
805 props->sm_sl = rep->sm_sl;
806 props->state = rep->vport_state;
807 props->phys_state = rep->port_physical_state;
808 props->port_cap_flags = rep->cap_mask1;
809 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
810 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
811 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
812 props->bad_pkey_cntr = rep->pkey_violation_counter;
813 props->qkey_viol_cntr = rep->qkey_violation_counter;
814 props->subnet_timeout = rep->subnet_timeout;
815 props->init_type_reply = rep->init_type_reply;
816 props->grh_required = rep->grh_required;
818 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
822 err = translate_active_width(ibdev, ib_link_width_oper,
823 &props->active_width);
826 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
830 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
832 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
834 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
836 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
838 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
842 err = translate_max_vl_num(ibdev, vl_hw_cap,
849 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
850 struct ib_port_attr *props)
852 switch (mlx5_get_vport_access_method(ibdev)) {
853 case MLX5_VPORT_ACCESS_METHOD_MAD:
854 return mlx5_query_mad_ifc_port(ibdev, port, props);
856 case MLX5_VPORT_ACCESS_METHOD_HCA:
857 return mlx5_query_hca_port(ibdev, port, props);
859 case MLX5_VPORT_ACCESS_METHOD_NIC:
860 return mlx5_query_port_roce(ibdev, port, props);
867 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
870 struct mlx5_ib_dev *dev = to_mdev(ibdev);
871 struct mlx5_core_dev *mdev = dev->mdev;
873 switch (mlx5_get_vport_access_method(ibdev)) {
874 case MLX5_VPORT_ACCESS_METHOD_MAD:
875 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
877 case MLX5_VPORT_ACCESS_METHOD_HCA:
878 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
886 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
889 struct mlx5_ib_dev *dev = to_mdev(ibdev);
890 struct mlx5_core_dev *mdev = dev->mdev;
892 switch (mlx5_get_vport_access_method(ibdev)) {
893 case MLX5_VPORT_ACCESS_METHOD_MAD:
894 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
896 case MLX5_VPORT_ACCESS_METHOD_HCA:
897 case MLX5_VPORT_ACCESS_METHOD_NIC:
898 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
905 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
906 struct ib_device_modify *props)
908 struct mlx5_ib_dev *dev = to_mdev(ibdev);
909 struct mlx5_reg_node_desc in;
910 struct mlx5_reg_node_desc out;
913 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
916 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
920 * If possible, pass node desc to FW, so it can generate
921 * a 144 trap. If cmd fails, just ignore.
923 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
924 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
925 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
929 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
934 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
935 struct ib_port_modify *props)
937 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938 struct ib_port_attr attr;
942 mutex_lock(&dev->cap_mask_mutex);
944 err = mlx5_ib_query_port(ibdev, port, &attr);
948 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
949 ~props->clr_port_cap_mask;
951 err = mlx5_set_port_caps(dev->mdev, port, tmp);
954 mutex_unlock(&dev->cap_mask_mutex);
958 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
959 struct ib_udata *udata)
961 struct mlx5_ib_dev *dev = to_mdev(ibdev);
962 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
963 struct mlx5_ib_alloc_ucontext_resp resp = {};
964 struct mlx5_ib_ucontext *context;
965 struct mlx5_uuar_info *uuari;
966 struct mlx5_uar *uars;
974 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
978 return ERR_PTR(-EAGAIN);
980 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
981 return ERR_PTR(-EINVAL);
983 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
984 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
986 else if (reqlen >= min_req_v2)
989 return ERR_PTR(-EINVAL);
991 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
996 return ERR_PTR(-EINVAL);
998 if (req.total_num_uuars > MLX5_MAX_UUARS)
999 return ERR_PTR(-ENOMEM);
1001 if (req.total_num_uuars == 0)
1002 return ERR_PTR(-EINVAL);
1004 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1005 return ERR_PTR(-EOPNOTSUPP);
1007 if (reqlen > sizeof(req) &&
1008 !ib_is_udata_cleared(udata, sizeof(req),
1009 reqlen - sizeof(req)))
1010 return ERR_PTR(-EOPNOTSUPP);
1012 req.total_num_uuars = ALIGN(req.total_num_uuars,
1013 MLX5_NON_FP_BF_REGS_PER_PAGE);
1014 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1015 return ERR_PTR(-EINVAL);
1017 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1018 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1019 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1020 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1021 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1022 resp.cache_line_size = L1_CACHE_BYTES;
1023 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1024 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1025 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1026 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1027 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1028 resp.cqe_version = min_t(__u8,
1029 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1030 req.max_cqe_version);
1031 resp.response_length = min(offsetof(typeof(resp), response_length) +
1032 sizeof(resp.response_length), udata->outlen);
1034 context = kzalloc(sizeof(*context), GFP_KERNEL);
1036 return ERR_PTR(-ENOMEM);
1038 uuari = &context->uuari;
1039 mutex_init(&uuari->lock);
1040 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1046 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1047 sizeof(*uuari->bitmap),
1049 if (!uuari->bitmap) {
1054 * clear all fast path uuars
1056 for (i = 0; i < gross_uuars; i++) {
1058 if (uuarn == 2 || uuarn == 3)
1059 set_bit(i, uuari->bitmap);
1062 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1063 if (!uuari->count) {
1068 for (i = 0; i < num_uars; i++) {
1069 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1074 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1075 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1078 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1079 err = mlx5_core_alloc_transport_domain(dev->mdev,
1085 INIT_LIST_HEAD(&context->vma_private_list);
1086 INIT_LIST_HEAD(&context->db_page_list);
1087 mutex_init(&context->db_page_mutex);
1089 resp.tot_uuars = req.total_num_uuars;
1090 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1092 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1093 resp.response_length += sizeof(resp.cqe_version);
1095 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1096 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1097 resp.response_length += sizeof(resp.cmds_supp_uhw);
1101 * We don't want to expose information from the PCI bar that is located
1102 * after 4096 bytes, so if the arch only supports larger pages, let's
1103 * pretend we don't support reading the HCA's core clock. This is also
1104 * forced by mmap function.
1106 if (PAGE_SIZE <= 4096 &&
1107 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1109 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1110 resp.hca_core_clock_offset =
1111 offsetof(struct mlx5_init_seg, internal_timer_h) %
1113 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1114 sizeof(resp.reserved2);
1117 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1122 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1124 uuari->num_uars = num_uars;
1125 context->cqe_version = resp.cqe_version;
1127 return &context->ibucontext;
1130 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1131 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1134 for (i--; i >= 0; i--)
1135 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1137 kfree(uuari->count);
1140 kfree(uuari->bitmap);
1147 return ERR_PTR(err);
1150 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1152 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1153 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1154 struct mlx5_uuar_info *uuari = &context->uuari;
1157 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1158 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1160 for (i = 0; i < uuari->num_uars; i++) {
1161 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1162 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1165 kfree(uuari->count);
1166 kfree(uuari->bitmap);
1173 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1175 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1178 static int get_command(unsigned long offset)
1180 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1183 static int get_arg(unsigned long offset)
1185 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1188 static int get_index(unsigned long offset)
1190 return get_arg(offset);
1193 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1195 /* vma_open is called when a new VMA is created on top of our VMA. This
1196 * is done through either mremap flow or split_vma (usually due to
1197 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1198 * as this VMA is strongly hardware related. Therefore we set the
1199 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1200 * calling us again and trying to do incorrect actions. We assume that
1201 * the original VMA size is exactly a single page, and therefore all
1202 * "splitting" operation will not happen to it.
1204 area->vm_ops = NULL;
1207 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1209 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1211 /* It's guaranteed that all VMAs opened on a FD are closed before the
1212 * file itself is closed, therefore no sync is needed with the regular
1213 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1214 * However need a sync with accessing the vma as part of
1215 * mlx5_ib_disassociate_ucontext.
1216 * The close operation is usually called under mm->mmap_sem except when
1217 * process is exiting.
1218 * The exiting case is handled explicitly as part of
1219 * mlx5_ib_disassociate_ucontext.
1221 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1223 /* setting the vma context pointer to null in the mlx5_ib driver's
1224 * private data, to protect a race condition in
1225 * mlx5_ib_disassociate_ucontext().
1227 mlx5_ib_vma_priv_data->vma = NULL;
1228 list_del(&mlx5_ib_vma_priv_data->list);
1229 kfree(mlx5_ib_vma_priv_data);
1232 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1233 .open = mlx5_ib_vma_open,
1234 .close = mlx5_ib_vma_close
1237 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1238 struct mlx5_ib_ucontext *ctx)
1240 struct mlx5_ib_vma_private_data *vma_prv;
1241 struct list_head *vma_head = &ctx->vma_private_list;
1243 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1248 vma->vm_private_data = vma_prv;
1249 vma->vm_ops = &mlx5_ib_vm_ops;
1251 list_add(&vma_prv->list, vma_head);
1256 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1259 struct vm_area_struct *vma;
1260 struct mlx5_ib_vma_private_data *vma_private, *n;
1261 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1262 struct task_struct *owning_process = NULL;
1263 struct mm_struct *owning_mm = NULL;
1265 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1266 if (!owning_process)
1269 owning_mm = get_task_mm(owning_process);
1271 pr_info("no mm, disassociate ucontext is pending task termination\n");
1273 put_task_struct(owning_process);
1274 usleep_range(1000, 2000);
1275 owning_process = get_pid_task(ibcontext->tgid,
1277 if (!owning_process ||
1278 owning_process->state == TASK_DEAD) {
1279 pr_info("disassociate ucontext done, task was terminated\n");
1280 /* in case task was dead need to release the
1284 put_task_struct(owning_process);
1290 /* need to protect from a race on closing the vma as part of
1291 * mlx5_ib_vma_close.
1293 down_read(&owning_mm->mmap_sem);
1294 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1296 vma = vma_private->vma;
1297 ret = zap_vma_ptes(vma, vma->vm_start,
1299 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1300 /* context going to be destroyed, should
1301 * not access ops any more.
1304 list_del(&vma_private->list);
1307 up_read(&owning_mm->mmap_sem);
1309 put_task_struct(owning_process);
1312 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1315 case MLX5_IB_MMAP_WC_PAGE:
1317 case MLX5_IB_MMAP_REGULAR_PAGE:
1318 return "best effort WC";
1319 case MLX5_IB_MMAP_NC_PAGE:
1326 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1327 struct vm_area_struct *vma,
1328 struct mlx5_ib_ucontext *context)
1330 struct mlx5_uuar_info *uuari = &context->uuari;
1333 phys_addr_t pfn, pa;
1337 case MLX5_IB_MMAP_WC_PAGE:
1338 /* Some architectures don't support WC memory */
1339 #if defined(CONFIG_X86)
1342 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1346 case MLX5_IB_MMAP_REGULAR_PAGE:
1347 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1348 prot = pgprot_writecombine(vma->vm_page_prot);
1350 case MLX5_IB_MMAP_NC_PAGE:
1351 prot = pgprot_noncached(vma->vm_page_prot);
1357 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1360 idx = get_index(vma->vm_pgoff);
1361 if (idx >= uuari->num_uars)
1364 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1365 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1367 vma->vm_page_prot = prot;
1368 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1369 PAGE_SIZE, vma->vm_page_prot);
1371 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1372 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1376 pa = pfn << PAGE_SHIFT;
1377 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1378 vma->vm_start, &pa);
1380 return mlx5_ib_set_vma_data(vma, context);
1383 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1385 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1386 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1387 unsigned long command;
1390 command = get_command(vma->vm_pgoff);
1392 case MLX5_IB_MMAP_WC_PAGE:
1393 case MLX5_IB_MMAP_NC_PAGE:
1394 case MLX5_IB_MMAP_REGULAR_PAGE:
1395 return uar_mmap(dev, command, vma, context);
1397 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1400 case MLX5_IB_MMAP_CORE_CLOCK:
1401 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1404 if (vma->vm_flags & VM_WRITE)
1407 /* Don't expose to user-space information it shouldn't have */
1408 if (PAGE_SIZE > 4096)
1411 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1412 pfn = (dev->mdev->iseg_base +
1413 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1415 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1416 PAGE_SIZE, vma->vm_page_prot))
1419 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1421 (unsigned long long)pfn << PAGE_SHIFT);
1431 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1432 struct ib_ucontext *context,
1433 struct ib_udata *udata)
1435 struct mlx5_ib_alloc_pd_resp resp;
1436 struct mlx5_ib_pd *pd;
1439 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1441 return ERR_PTR(-ENOMEM);
1443 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1446 return ERR_PTR(err);
1451 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1452 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1454 return ERR_PTR(-EFAULT);
1461 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1463 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1464 struct mlx5_ib_pd *mpd = to_mpd(pd);
1466 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1473 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1474 MATCH_CRITERIA_ENABLE_MISC_BIT,
1475 MATCH_CRITERIA_ENABLE_INNER_BIT
1478 #define HEADER_IS_ZERO(match_criteria, headers) \
1479 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1480 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1482 static u8 get_match_criteria_enable(u32 *match_criteria)
1484 u8 match_criteria_enable;
1486 match_criteria_enable =
1487 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1488 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1489 match_criteria_enable |=
1490 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1491 MATCH_CRITERIA_ENABLE_MISC_BIT;
1492 match_criteria_enable |=
1493 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1494 MATCH_CRITERIA_ENABLE_INNER_BIT;
1496 return match_criteria_enable;
1499 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1501 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1502 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1505 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1507 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1508 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1509 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1510 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1513 #define LAST_ETH_FIELD vlan_tag
1514 #define LAST_IB_FIELD sl
1515 #define LAST_IPV4_FIELD tos
1516 #define LAST_IPV6_FIELD traffic_class
1517 #define LAST_TCP_UDP_FIELD src_port
1519 /* Field is the last supported field */
1520 #define FIELDS_NOT_SUPPORTED(filter, field)\
1521 memchr_inv((void *)&filter.field +\
1522 sizeof(filter.field), 0,\
1524 offsetof(typeof(filter), field) -\
1525 sizeof(filter.field))
1527 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1528 const union ib_flow_spec *ib_spec)
1530 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1532 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1534 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1536 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1539 switch (ib_spec->type) {
1540 case IB_FLOW_SPEC_ETH:
1541 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1544 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1546 ib_spec->eth.mask.dst_mac);
1547 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1549 ib_spec->eth.val.dst_mac);
1551 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1553 ib_spec->eth.mask.src_mac);
1554 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1556 ib_spec->eth.val.src_mac);
1558 if (ib_spec->eth.mask.vlan_tag) {
1559 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1561 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1564 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1565 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1566 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1567 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1569 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1571 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1572 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1574 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1576 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1578 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1579 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1581 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1583 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1584 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1585 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1586 ethertype, ntohs(ib_spec->eth.val.ether_type));
1588 case IB_FLOW_SPEC_IPV4:
1589 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1592 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1594 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1595 ethertype, ETH_P_IP);
1597 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1598 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1599 &ib_spec->ipv4.mask.src_ip,
1600 sizeof(ib_spec->ipv4.mask.src_ip));
1601 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1602 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1603 &ib_spec->ipv4.val.src_ip,
1604 sizeof(ib_spec->ipv4.val.src_ip));
1605 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1606 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1607 &ib_spec->ipv4.mask.dst_ip,
1608 sizeof(ib_spec->ipv4.mask.dst_ip));
1609 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1610 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1611 &ib_spec->ipv4.val.dst_ip,
1612 sizeof(ib_spec->ipv4.val.dst_ip));
1614 set_tos(outer_headers_c, outer_headers_v,
1615 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1617 set_proto(outer_headers_c, outer_headers_v,
1618 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1620 case IB_FLOW_SPEC_IPV6:
1621 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1624 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1626 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1627 ethertype, ETH_P_IPV6);
1629 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1630 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1631 &ib_spec->ipv6.mask.src_ip,
1632 sizeof(ib_spec->ipv6.mask.src_ip));
1633 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1634 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1635 &ib_spec->ipv6.val.src_ip,
1636 sizeof(ib_spec->ipv6.val.src_ip));
1637 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1638 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1639 &ib_spec->ipv6.mask.dst_ip,
1640 sizeof(ib_spec->ipv6.mask.dst_ip));
1641 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1642 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1643 &ib_spec->ipv6.val.dst_ip,
1644 sizeof(ib_spec->ipv6.val.dst_ip));
1646 set_tos(outer_headers_c, outer_headers_v,
1647 ib_spec->ipv6.mask.traffic_class,
1648 ib_spec->ipv6.val.traffic_class);
1650 set_proto(outer_headers_c, outer_headers_v,
1651 ib_spec->ipv6.mask.next_hdr,
1652 ib_spec->ipv6.val.next_hdr);
1654 MLX5_SET(fte_match_set_misc, misc_params_c,
1655 outer_ipv6_flow_label,
1656 ntohl(ib_spec->ipv6.mask.flow_label));
1657 MLX5_SET(fte_match_set_misc, misc_params_v,
1658 outer_ipv6_flow_label,
1659 ntohl(ib_spec->ipv6.val.flow_label));
1661 case IB_FLOW_SPEC_TCP:
1662 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1663 LAST_TCP_UDP_FIELD))
1666 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1668 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1671 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1672 ntohs(ib_spec->tcp_udp.mask.src_port));
1673 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1674 ntohs(ib_spec->tcp_udp.val.src_port));
1676 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1677 ntohs(ib_spec->tcp_udp.mask.dst_port));
1678 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1679 ntohs(ib_spec->tcp_udp.val.dst_port));
1681 case IB_FLOW_SPEC_UDP:
1682 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1683 LAST_TCP_UDP_FIELD))
1686 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1688 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1691 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1692 ntohs(ib_spec->tcp_udp.mask.src_port));
1693 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1694 ntohs(ib_spec->tcp_udp.val.src_port));
1696 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1697 ntohs(ib_spec->tcp_udp.mask.dst_port));
1698 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1699 ntohs(ib_spec->tcp_udp.val.dst_port));
1708 /* If a flow could catch both multicast and unicast packets,
1709 * it won't fall into the multicast flow steering table and this rule
1710 * could steal other multicast packets.
1712 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1714 struct ib_flow_spec_eth *eth_spec;
1716 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1717 ib_attr->size < sizeof(struct ib_flow_attr) +
1718 sizeof(struct ib_flow_spec_eth) ||
1719 ib_attr->num_of_specs < 1)
1722 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1723 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1724 eth_spec->size != sizeof(*eth_spec))
1727 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1728 is_multicast_ether_addr(eth_spec->val.dst_mac);
1731 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1733 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1734 bool has_ipv4_spec = false;
1735 bool eth_type_ipv4 = true;
1736 unsigned int spec_index;
1738 /* Validate that ethertype is correct */
1739 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1740 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1741 ib_spec->eth.mask.ether_type) {
1742 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1743 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1744 eth_type_ipv4 = false;
1745 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1746 has_ipv4_spec = true;
1748 ib_spec = (void *)ib_spec + ib_spec->size;
1750 return !has_ipv4_spec || eth_type_ipv4;
1753 static void put_flow_table(struct mlx5_ib_dev *dev,
1754 struct mlx5_ib_flow_prio *prio, bool ft_added)
1756 prio->refcount -= !!ft_added;
1757 if (!prio->refcount) {
1758 mlx5_destroy_flow_table(prio->flow_table);
1759 prio->flow_table = NULL;
1763 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1765 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1766 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1767 struct mlx5_ib_flow_handler,
1769 struct mlx5_ib_flow_handler *iter, *tmp;
1771 mutex_lock(&dev->flow_db.lock);
1773 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1774 mlx5_del_flow_rule(iter->rule);
1775 put_flow_table(dev, iter->prio, true);
1776 list_del(&iter->list);
1780 mlx5_del_flow_rule(handler->rule);
1781 put_flow_table(dev, handler->prio, true);
1782 mutex_unlock(&dev->flow_db.lock);
1789 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1797 enum flow_table_type {
1802 #define MLX5_FS_MAX_TYPES 10
1803 #define MLX5_FS_MAX_ENTRIES 32000UL
1804 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1805 struct ib_flow_attr *flow_attr,
1806 enum flow_table_type ft_type)
1808 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1809 struct mlx5_flow_namespace *ns = NULL;
1810 struct mlx5_ib_flow_prio *prio;
1811 struct mlx5_flow_table *ft;
1817 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1818 if (flow_is_multicast_only(flow_attr) &&
1820 priority = MLX5_IB_FLOW_MCAST_PRIO;
1822 priority = ib_prio_to_core_prio(flow_attr->priority,
1824 ns = mlx5_get_flow_namespace(dev->mdev,
1825 MLX5_FLOW_NAMESPACE_BYPASS);
1826 num_entries = MLX5_FS_MAX_ENTRIES;
1827 num_groups = MLX5_FS_MAX_TYPES;
1828 prio = &dev->flow_db.prios[priority];
1829 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1830 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1831 ns = mlx5_get_flow_namespace(dev->mdev,
1832 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1833 build_leftovers_ft_param(&priority,
1836 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1837 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1838 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1839 allow_sniffer_and_nic_rx_shared_tir))
1840 return ERR_PTR(-ENOTSUPP);
1842 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1843 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1844 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1846 prio = &dev->flow_db.sniffer[ft_type];
1853 return ERR_PTR(-ENOTSUPP);
1855 ft = prio->flow_table;
1857 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1864 prio->flow_table = ft;
1870 return err ? ERR_PTR(err) : prio;
1873 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1874 struct mlx5_ib_flow_prio *ft_prio,
1875 const struct ib_flow_attr *flow_attr,
1876 struct mlx5_flow_destination *dst)
1878 struct mlx5_flow_table *ft = ft_prio->flow_table;
1879 struct mlx5_ib_flow_handler *handler;
1880 struct mlx5_flow_spec *spec;
1881 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1882 unsigned int spec_index;
1886 if (!is_valid_attr(flow_attr))
1887 return ERR_PTR(-EINVAL);
1889 spec = mlx5_vzalloc(sizeof(*spec));
1890 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1891 if (!handler || !spec) {
1896 INIT_LIST_HEAD(&handler->list);
1898 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1899 err = parse_flow_attr(spec->match_criteria,
1900 spec->match_value, ib_flow);
1904 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1907 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1908 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1909 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1910 handler->rule = mlx5_add_flow_rule(ft, spec,
1912 MLX5_FS_DEFAULT_FLOW_TAG,
1915 if (IS_ERR(handler->rule)) {
1916 err = PTR_ERR(handler->rule);
1920 ft_prio->refcount++;
1921 handler->prio = ft_prio;
1923 ft_prio->flow_table = ft;
1928 return err ? ERR_PTR(err) : handler;
1931 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1932 struct mlx5_ib_flow_prio *ft_prio,
1933 struct ib_flow_attr *flow_attr,
1934 struct mlx5_flow_destination *dst)
1936 struct mlx5_ib_flow_handler *handler_dst = NULL;
1937 struct mlx5_ib_flow_handler *handler = NULL;
1939 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1940 if (!IS_ERR(handler)) {
1941 handler_dst = create_flow_rule(dev, ft_prio,
1943 if (IS_ERR(handler_dst)) {
1944 mlx5_del_flow_rule(handler->rule);
1945 ft_prio->refcount--;
1947 handler = handler_dst;
1949 list_add(&handler_dst->list, &handler->list);
1960 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1961 struct mlx5_ib_flow_prio *ft_prio,
1962 struct ib_flow_attr *flow_attr,
1963 struct mlx5_flow_destination *dst)
1965 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1966 struct mlx5_ib_flow_handler *handler = NULL;
1969 struct ib_flow_attr flow_attr;
1970 struct ib_flow_spec_eth eth_flow;
1971 } leftovers_specs[] = {
1975 .size = sizeof(leftovers_specs[0])
1978 .type = IB_FLOW_SPEC_ETH,
1979 .size = sizeof(struct ib_flow_spec_eth),
1980 .mask = {.dst_mac = {0x1} },
1981 .val = {.dst_mac = {0x1} }
1987 .size = sizeof(leftovers_specs[0])
1990 .type = IB_FLOW_SPEC_ETH,
1991 .size = sizeof(struct ib_flow_spec_eth),
1992 .mask = {.dst_mac = {0x1} },
1993 .val = {.dst_mac = {} }
1998 handler = create_flow_rule(dev, ft_prio,
1999 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2001 if (!IS_ERR(handler) &&
2002 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2003 handler_ucast = create_flow_rule(dev, ft_prio,
2004 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2006 if (IS_ERR(handler_ucast)) {
2007 mlx5_del_flow_rule(handler->rule);
2008 ft_prio->refcount--;
2010 handler = handler_ucast;
2012 list_add(&handler_ucast->list, &handler->list);
2019 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2020 struct mlx5_ib_flow_prio *ft_rx,
2021 struct mlx5_ib_flow_prio *ft_tx,
2022 struct mlx5_flow_destination *dst)
2024 struct mlx5_ib_flow_handler *handler_rx;
2025 struct mlx5_ib_flow_handler *handler_tx;
2027 static const struct ib_flow_attr flow_attr = {
2029 .size = sizeof(flow_attr)
2032 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2033 if (IS_ERR(handler_rx)) {
2034 err = PTR_ERR(handler_rx);
2038 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2039 if (IS_ERR(handler_tx)) {
2040 err = PTR_ERR(handler_tx);
2044 list_add(&handler_tx->list, &handler_rx->list);
2049 mlx5_del_flow_rule(handler_rx->rule);
2053 return ERR_PTR(err);
2056 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2057 struct ib_flow_attr *flow_attr,
2060 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2061 struct mlx5_ib_qp *mqp = to_mqp(qp);
2062 struct mlx5_ib_flow_handler *handler = NULL;
2063 struct mlx5_flow_destination *dst = NULL;
2064 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2065 struct mlx5_ib_flow_prio *ft_prio;
2068 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2069 return ERR_PTR(-ENOSPC);
2071 if (domain != IB_FLOW_DOMAIN_USER ||
2072 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2073 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2074 return ERR_PTR(-EINVAL);
2076 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2078 return ERR_PTR(-ENOMEM);
2080 mutex_lock(&dev->flow_db.lock);
2082 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2083 if (IS_ERR(ft_prio)) {
2084 err = PTR_ERR(ft_prio);
2087 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2088 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2089 if (IS_ERR(ft_prio_tx)) {
2090 err = PTR_ERR(ft_prio_tx);
2096 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2097 if (mqp->flags & MLX5_IB_QP_RSS)
2098 dst->tir_num = mqp->rss_qp.tirn;
2100 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2102 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2103 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2104 handler = create_dont_trap_rule(dev, ft_prio,
2107 handler = create_flow_rule(dev, ft_prio, flow_attr,
2110 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2111 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2112 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2114 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2115 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2121 if (IS_ERR(handler)) {
2122 err = PTR_ERR(handler);
2127 mutex_unlock(&dev->flow_db.lock);
2130 return &handler->ibflow;
2133 put_flow_table(dev, ft_prio, false);
2135 put_flow_table(dev, ft_prio_tx, false);
2137 mutex_unlock(&dev->flow_db.lock);
2140 return ERR_PTR(err);
2143 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2145 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2148 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2150 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2151 ibqp->qp_num, gid->raw);
2156 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2158 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2161 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2163 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2164 ibqp->qp_num, gid->raw);
2169 static int init_node_data(struct mlx5_ib_dev *dev)
2173 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2177 dev->mdev->rev_id = dev->mdev->pdev->revision;
2179 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2182 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2185 struct mlx5_ib_dev *dev =
2186 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2188 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2191 static ssize_t show_reg_pages(struct device *device,
2192 struct device_attribute *attr, char *buf)
2194 struct mlx5_ib_dev *dev =
2195 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2197 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2200 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2203 struct mlx5_ib_dev *dev =
2204 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2205 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2208 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2211 struct mlx5_ib_dev *dev =
2212 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2213 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2216 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2219 struct mlx5_ib_dev *dev =
2220 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2221 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2222 dev->mdev->board_id);
2225 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2226 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2227 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2228 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2229 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2231 static struct device_attribute *mlx5_class_attributes[] = {
2236 &dev_attr_reg_pages,
2239 static void pkey_change_handler(struct work_struct *work)
2241 struct mlx5_ib_port_resources *ports =
2242 container_of(work, struct mlx5_ib_port_resources,
2245 mutex_lock(&ports->devr->mutex);
2246 mlx5_ib_gsi_pkey_change(ports->gsi);
2247 mutex_unlock(&ports->devr->mutex);
2250 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2252 struct mlx5_ib_qp *mqp;
2253 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2254 struct mlx5_core_cq *mcq;
2255 struct list_head cq_armed_list;
2256 unsigned long flags_qp;
2257 unsigned long flags_cq;
2258 unsigned long flags;
2260 INIT_LIST_HEAD(&cq_armed_list);
2262 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2263 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2264 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2265 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2266 if (mqp->sq.tail != mqp->sq.head) {
2267 send_mcq = to_mcq(mqp->ibqp.send_cq);
2268 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2269 if (send_mcq->mcq.comp &&
2270 mqp->ibqp.send_cq->comp_handler) {
2271 if (!send_mcq->mcq.reset_notify_added) {
2272 send_mcq->mcq.reset_notify_added = 1;
2273 list_add_tail(&send_mcq->mcq.reset_notify,
2277 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2279 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2280 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2281 /* no handling is needed for SRQ */
2282 if (!mqp->ibqp.srq) {
2283 if (mqp->rq.tail != mqp->rq.head) {
2284 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2285 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2286 if (recv_mcq->mcq.comp &&
2287 mqp->ibqp.recv_cq->comp_handler) {
2288 if (!recv_mcq->mcq.reset_notify_added) {
2289 recv_mcq->mcq.reset_notify_added = 1;
2290 list_add_tail(&recv_mcq->mcq.reset_notify,
2294 spin_unlock_irqrestore(&recv_mcq->lock,
2298 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2300 /*At that point all inflight post send were put to be executed as of we
2301 * lock/unlock above locks Now need to arm all involved CQs.
2303 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2306 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2309 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2310 enum mlx5_dev_event event, unsigned long param)
2312 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2313 struct ib_event ibev;
2318 case MLX5_DEV_EVENT_SYS_ERROR:
2319 ibdev->ib_active = false;
2320 ibev.event = IB_EVENT_DEVICE_FATAL;
2321 mlx5_ib_handle_internal_error(ibdev);
2324 case MLX5_DEV_EVENT_PORT_UP:
2325 case MLX5_DEV_EVENT_PORT_DOWN:
2326 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2329 /* In RoCE, port up/down events are handled in
2330 * mlx5_netdev_event().
2332 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2333 IB_LINK_LAYER_ETHERNET)
2336 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2337 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2340 case MLX5_DEV_EVENT_LID_CHANGE:
2341 ibev.event = IB_EVENT_LID_CHANGE;
2345 case MLX5_DEV_EVENT_PKEY_CHANGE:
2346 ibev.event = IB_EVENT_PKEY_CHANGE;
2349 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2352 case MLX5_DEV_EVENT_GUID_CHANGE:
2353 ibev.event = IB_EVENT_GID_CHANGE;
2357 case MLX5_DEV_EVENT_CLIENT_REREG:
2358 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2363 ibev.device = &ibdev->ib_dev;
2364 ibev.element.port_num = port;
2366 if (port < 1 || port > ibdev->num_ports) {
2367 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2371 if (ibdev->ib_active)
2372 ib_dispatch_event(&ibev);
2375 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2379 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2380 mlx5_query_ext_port_caps(dev, port);
2383 static int get_port_caps(struct mlx5_ib_dev *dev)
2385 struct ib_device_attr *dprops = NULL;
2386 struct ib_port_attr *pprops = NULL;
2389 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2391 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2395 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2399 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2401 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2405 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2406 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2408 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2412 dev->mdev->port_caps[port - 1].pkey_table_len =
2414 dev->mdev->port_caps[port - 1].gid_table_len =
2415 pprops->gid_tbl_len;
2416 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2417 dprops->max_pkeys, pprops->gid_tbl_len);
2427 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2431 err = mlx5_mr_cache_cleanup(dev);
2433 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2435 mlx5_ib_destroy_qp(dev->umrc.qp);
2436 ib_free_cq(dev->umrc.cq);
2437 ib_dealloc_pd(dev->umrc.pd);
2444 static int create_umr_res(struct mlx5_ib_dev *dev)
2446 struct ib_qp_init_attr *init_attr = NULL;
2447 struct ib_qp_attr *attr = NULL;
2453 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2454 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2455 if (!attr || !init_attr) {
2460 pd = ib_alloc_pd(&dev->ib_dev, 0);
2462 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2467 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2469 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2474 init_attr->send_cq = cq;
2475 init_attr->recv_cq = cq;
2476 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2477 init_attr->cap.max_send_wr = MAX_UMR_WR;
2478 init_attr->cap.max_send_sge = 1;
2479 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2480 init_attr->port_num = 1;
2481 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2483 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2487 qp->device = &dev->ib_dev;
2490 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2492 attr->qp_state = IB_QPS_INIT;
2494 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2497 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2501 memset(attr, 0, sizeof(*attr));
2502 attr->qp_state = IB_QPS_RTR;
2503 attr->path_mtu = IB_MTU_256;
2505 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2507 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2511 memset(attr, 0, sizeof(*attr));
2512 attr->qp_state = IB_QPS_RTS;
2513 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2515 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2523 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2524 ret = mlx5_mr_cache_init(dev);
2526 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2536 mlx5_ib_destroy_qp(qp);
2550 static int create_dev_resources(struct mlx5_ib_resources *devr)
2552 struct ib_srq_init_attr attr;
2553 struct mlx5_ib_dev *dev;
2554 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2558 dev = container_of(devr, struct mlx5_ib_dev, devr);
2560 mutex_init(&devr->mutex);
2562 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2563 if (IS_ERR(devr->p0)) {
2564 ret = PTR_ERR(devr->p0);
2567 devr->p0->device = &dev->ib_dev;
2568 devr->p0->uobject = NULL;
2569 atomic_set(&devr->p0->usecnt, 0);
2571 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2572 if (IS_ERR(devr->c0)) {
2573 ret = PTR_ERR(devr->c0);
2576 devr->c0->device = &dev->ib_dev;
2577 devr->c0->uobject = NULL;
2578 devr->c0->comp_handler = NULL;
2579 devr->c0->event_handler = NULL;
2580 devr->c0->cq_context = NULL;
2581 atomic_set(&devr->c0->usecnt, 0);
2583 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2584 if (IS_ERR(devr->x0)) {
2585 ret = PTR_ERR(devr->x0);
2588 devr->x0->device = &dev->ib_dev;
2589 devr->x0->inode = NULL;
2590 atomic_set(&devr->x0->usecnt, 0);
2591 mutex_init(&devr->x0->tgt_qp_mutex);
2592 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2594 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2595 if (IS_ERR(devr->x1)) {
2596 ret = PTR_ERR(devr->x1);
2599 devr->x1->device = &dev->ib_dev;
2600 devr->x1->inode = NULL;
2601 atomic_set(&devr->x1->usecnt, 0);
2602 mutex_init(&devr->x1->tgt_qp_mutex);
2603 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2605 memset(&attr, 0, sizeof(attr));
2606 attr.attr.max_sge = 1;
2607 attr.attr.max_wr = 1;
2608 attr.srq_type = IB_SRQT_XRC;
2609 attr.ext.xrc.cq = devr->c0;
2610 attr.ext.xrc.xrcd = devr->x0;
2612 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2613 if (IS_ERR(devr->s0)) {
2614 ret = PTR_ERR(devr->s0);
2617 devr->s0->device = &dev->ib_dev;
2618 devr->s0->pd = devr->p0;
2619 devr->s0->uobject = NULL;
2620 devr->s0->event_handler = NULL;
2621 devr->s0->srq_context = NULL;
2622 devr->s0->srq_type = IB_SRQT_XRC;
2623 devr->s0->ext.xrc.xrcd = devr->x0;
2624 devr->s0->ext.xrc.cq = devr->c0;
2625 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2626 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2627 atomic_inc(&devr->p0->usecnt);
2628 atomic_set(&devr->s0->usecnt, 0);
2630 memset(&attr, 0, sizeof(attr));
2631 attr.attr.max_sge = 1;
2632 attr.attr.max_wr = 1;
2633 attr.srq_type = IB_SRQT_BASIC;
2634 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2635 if (IS_ERR(devr->s1)) {
2636 ret = PTR_ERR(devr->s1);
2639 devr->s1->device = &dev->ib_dev;
2640 devr->s1->pd = devr->p0;
2641 devr->s1->uobject = NULL;
2642 devr->s1->event_handler = NULL;
2643 devr->s1->srq_context = NULL;
2644 devr->s1->srq_type = IB_SRQT_BASIC;
2645 devr->s1->ext.xrc.cq = devr->c0;
2646 atomic_inc(&devr->p0->usecnt);
2647 atomic_set(&devr->s0->usecnt, 0);
2649 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2650 INIT_WORK(&devr->ports[port].pkey_change_work,
2651 pkey_change_handler);
2652 devr->ports[port].devr = devr;
2658 mlx5_ib_destroy_srq(devr->s0);
2660 mlx5_ib_dealloc_xrcd(devr->x1);
2662 mlx5_ib_dealloc_xrcd(devr->x0);
2664 mlx5_ib_destroy_cq(devr->c0);
2666 mlx5_ib_dealloc_pd(devr->p0);
2671 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2673 struct mlx5_ib_dev *dev =
2674 container_of(devr, struct mlx5_ib_dev, devr);
2677 mlx5_ib_destroy_srq(devr->s1);
2678 mlx5_ib_destroy_srq(devr->s0);
2679 mlx5_ib_dealloc_xrcd(devr->x0);
2680 mlx5_ib_dealloc_xrcd(devr->x1);
2681 mlx5_ib_destroy_cq(devr->c0);
2682 mlx5_ib_dealloc_pd(devr->p0);
2684 /* Make sure no change P_Key work items are still executing */
2685 for (port = 0; port < dev->num_ports; ++port)
2686 cancel_work_sync(&devr->ports[port].pkey_change_work);
2689 static u32 get_core_cap_flags(struct ib_device *ibdev)
2691 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2692 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2693 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2694 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2697 if (ll == IB_LINK_LAYER_INFINIBAND)
2698 return RDMA_CORE_PORT_IBA_IB;
2700 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2703 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2706 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2707 ret |= RDMA_CORE_PORT_IBA_ROCE;
2709 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2710 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2715 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2716 struct ib_port_immutable *immutable)
2718 struct ib_port_attr attr;
2721 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2725 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2726 immutable->gid_tbl_len = attr.gid_tbl_len;
2727 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2728 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2733 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2736 struct mlx5_ib_dev *dev =
2737 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2738 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2739 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2742 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2744 struct mlx5_core_dev *mdev = dev->mdev;
2745 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2746 MLX5_FLOW_NAMESPACE_LAG);
2747 struct mlx5_flow_table *ft;
2750 if (!ns || !mlx5_lag_is_active(mdev))
2753 err = mlx5_cmd_create_vport_lag(mdev);
2757 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2760 goto err_destroy_vport_lag;
2763 dev->flow_db.lag_demux_ft = ft;
2766 err_destroy_vport_lag:
2767 mlx5_cmd_destroy_vport_lag(mdev);
2771 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2773 struct mlx5_core_dev *mdev = dev->mdev;
2775 if (dev->flow_db.lag_demux_ft) {
2776 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2777 dev->flow_db.lag_demux_ft = NULL;
2779 mlx5_cmd_destroy_vport_lag(mdev);
2783 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2785 if (dev->roce.nb.notifier_call) {
2786 unregister_netdevice_notifier(&dev->roce.nb);
2787 dev->roce.nb.notifier_call = NULL;
2791 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2795 dev->roce.nb.notifier_call = mlx5_netdev_event;
2796 err = register_netdevice_notifier(&dev->roce.nb);
2798 dev->roce.nb.notifier_call = NULL;
2802 err = mlx5_nic_vport_enable_roce(dev->mdev);
2804 goto err_unregister_netdevice_notifier;
2806 err = mlx5_roce_lag_init(dev);
2808 goto err_disable_roce;
2813 mlx5_nic_vport_disable_roce(dev->mdev);
2815 err_unregister_netdevice_notifier:
2816 mlx5_remove_roce_notifier(dev);
2820 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2822 mlx5_roce_lag_cleanup(dev);
2823 mlx5_nic_vport_disable_roce(dev->mdev);
2826 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2830 for (i = 0; i < dev->num_ports; i++)
2831 mlx5_core_dealloc_q_counter(dev->mdev,
2832 dev->port[i].q_cnt_id);
2835 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2840 for (i = 0; i < dev->num_ports; i++) {
2841 ret = mlx5_core_alloc_q_counter(dev->mdev,
2842 &dev->port[i].q_cnt_id);
2845 "couldn't allocate queue counter for port %d, err %d\n",
2847 goto dealloc_counters;
2855 mlx5_core_dealloc_q_counter(dev->mdev,
2856 dev->port[i].q_cnt_id);
2861 static const char * const names[] = {
2862 "rx_write_requests",
2864 "rx_atomic_requests",
2867 "duplicate_request",
2868 "rnr_nak_retry_err",
2870 "implied_nak_seq_err",
2871 "local_ack_timeout_err",
2874 static const size_t stats_offsets[] = {
2875 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2876 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2877 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2878 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2879 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2880 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2881 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2882 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2883 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2884 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2887 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2890 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2892 /* We support only per port stats */
2896 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2897 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2900 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2901 struct rdma_hw_stats *stats,
2904 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2905 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2911 if (!port || !stats)
2914 out = mlx5_vzalloc(outlen);
2918 ret = mlx5_core_query_q_counter(dev->mdev,
2919 dev->port[port - 1].q_cnt_id, 0,
2924 for (i = 0; i < ARRAY_SIZE(names); i++) {
2925 val = *(__be32 *)(out + stats_offsets[i]);
2926 stats->value[i] = (u64)be32_to_cpu(val);
2930 return ARRAY_SIZE(names);
2933 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2935 struct mlx5_ib_dev *dev;
2936 enum rdma_link_layer ll;
2942 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2943 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2945 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2948 printk_once(KERN_INFO "%s", mlx5_version);
2950 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2956 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2961 rwlock_init(&dev->roce.netdev_lock);
2962 err = get_port_caps(dev);
2966 if (mlx5_use_mad_ifc(dev))
2967 get_ext_port_caps(dev);
2969 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2971 if (!mlx5_lag_is_active(mdev))
2974 name = "mlx5_bond_%d";
2976 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
2977 dev->ib_dev.owner = THIS_MODULE;
2978 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
2979 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
2980 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
2981 dev->ib_dev.phys_port_cnt = dev->num_ports;
2982 dev->ib_dev.num_comp_vectors =
2983 dev->mdev->priv.eq_table.num_comp_vectors;
2984 dev->ib_dev.dma_device = &mdev->pdev->dev;
2986 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2987 dev->ib_dev.uverbs_cmd_mask =
2988 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2989 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2990 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2991 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2992 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2993 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2994 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2995 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2996 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2997 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2998 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2999 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3000 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3001 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3002 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3003 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3004 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3005 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3006 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3007 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3008 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3009 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3010 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3011 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3012 dev->ib_dev.uverbs_ex_cmd_mask =
3013 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3014 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3015 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3017 dev->ib_dev.query_device = mlx5_ib_query_device;
3018 dev->ib_dev.query_port = mlx5_ib_query_port;
3019 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3020 if (ll == IB_LINK_LAYER_ETHERNET)
3021 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3022 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3023 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3024 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3025 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3026 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3027 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3028 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3029 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3030 dev->ib_dev.mmap = mlx5_ib_mmap;
3031 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3032 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3033 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3034 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3035 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3036 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3037 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3038 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3039 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3040 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3041 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3042 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3043 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3044 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3045 dev->ib_dev.post_send = mlx5_ib_post_send;
3046 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3047 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3048 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3049 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3050 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3051 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3052 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3053 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3054 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3055 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3056 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3057 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3058 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3059 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3060 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3061 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3062 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3063 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3064 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3065 if (mlx5_core_is_pf(mdev)) {
3066 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3067 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3068 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3069 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3072 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3074 mlx5_ib_internal_fill_odp_caps(dev);
3076 if (MLX5_CAP_GEN(mdev, imaicl)) {
3077 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3078 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3079 dev->ib_dev.uverbs_cmd_mask |=
3080 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3081 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3084 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3085 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3086 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3087 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3090 if (MLX5_CAP_GEN(mdev, xrc)) {
3091 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3092 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3093 dev->ib_dev.uverbs_cmd_mask |=
3094 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3095 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3098 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3099 IB_LINK_LAYER_ETHERNET) {
3100 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3101 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3102 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3103 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3104 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3105 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3106 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3107 dev->ib_dev.uverbs_ex_cmd_mask |=
3108 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3109 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3110 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3111 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3112 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3113 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3114 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3116 err = init_node_data(dev);
3120 mutex_init(&dev->flow_db.lock);
3121 mutex_init(&dev->cap_mask_mutex);
3122 INIT_LIST_HEAD(&dev->qp_list);
3123 spin_lock_init(&dev->reset_flow_resource_lock);
3125 if (ll == IB_LINK_LAYER_ETHERNET) {
3126 err = mlx5_enable_roce(dev);
3131 err = create_dev_resources(&dev->devr);
3133 goto err_disable_roce;
3135 err = mlx5_ib_odp_init_one(dev);
3139 err = mlx5_ib_alloc_q_counters(dev);
3143 err = ib_register_device(&dev->ib_dev, NULL);
3147 err = create_umr_res(dev);
3151 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3152 err = device_create_file(&dev->ib_dev.dev,
3153 mlx5_class_attributes[i]);
3158 dev->ib_active = true;
3163 destroy_umrc_res(dev);
3166 ib_unregister_device(&dev->ib_dev);
3169 mlx5_ib_dealloc_q_counters(dev);
3172 mlx5_ib_odp_remove_one(dev);
3175 destroy_dev_resources(&dev->devr);
3178 if (ll == IB_LINK_LAYER_ETHERNET) {
3179 mlx5_disable_roce(dev);
3180 mlx5_remove_roce_notifier(dev);
3187 ib_dealloc_device((struct ib_device *)dev);
3192 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3194 struct mlx5_ib_dev *dev = context;
3195 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3197 mlx5_remove_roce_notifier(dev);
3198 ib_unregister_device(&dev->ib_dev);
3199 mlx5_ib_dealloc_q_counters(dev);
3200 destroy_umrc_res(dev);
3201 mlx5_ib_odp_remove_one(dev);
3202 destroy_dev_resources(&dev->devr);
3203 if (ll == IB_LINK_LAYER_ETHERNET)
3204 mlx5_disable_roce(dev);
3206 ib_dealloc_device(&dev->ib_dev);
3209 static struct mlx5_interface mlx5_ib_interface = {
3211 .remove = mlx5_ib_remove,
3212 .event = mlx5_ib_event,
3213 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3216 static int __init mlx5_ib_init(void)
3220 if (deprecated_prof_sel != 2)
3221 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3223 err = mlx5_ib_odp_init();
3227 err = mlx5_register_interface(&mlx5_ib_interface);
3234 mlx5_ib_odp_cleanup();
3238 static void __exit mlx5_ib_cleanup(void)
3240 mlx5_unregister_interface(&mlx5_ib_interface);
3241 mlx5_ib_odp_cleanup();
3244 module_init(mlx5_ib_init);
3245 module_exit(mlx5_ib_cleanup);