2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 #include <linux/mlx5/transobj.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/mlx5-abi.h>
48 #include <rdma/uverbs_ioctl.h>
49 #include <rdma/mlx5_user_ioctl_cmds.h>
51 #define mlx5_ib_dbg(dev, format, arg...) \
52 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
53 __LINE__, current->pid, ##arg)
55 #define mlx5_ib_err(dev, format, arg...) \
56 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
57 __LINE__, current->pid, ##arg)
59 #define mlx5_ib_warn(dev, format, arg...) \
60 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
61 __LINE__, current->pid, ##arg)
63 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
64 sizeof(((type *)0)->fld) <= (sz))
65 #define MLX5_IB_DEFAULT_UIDX 0xffffff
66 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
68 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
71 MLX5_IB_MMAP_CMD_SHIFT = 8,
72 MLX5_IB_MMAP_CMD_MASK = 0xff,
76 MLX5_RES_SCAT_DATA32_CQE = 0x1,
77 MLX5_RES_SCAT_DATA64_CQE = 0x2,
78 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
79 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
82 enum mlx5_ib_mad_ifc_flags {
83 MLX5_MAD_IFC_IGNORE_MKEY = 1,
84 MLX5_MAD_IFC_IGNORE_BKEY = 2,
85 MLX5_MAD_IFC_NET_VIEW = 4,
89 MLX5_CROSS_CHANNEL_BFREG = 0,
98 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
103 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
104 MLX5_IB_INVALID_BFREG = BIT(31),
108 MLX5_MAX_MEMIC_PAGES = 0x100,
109 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
113 MLX5_MEMIC_BASE_ALIGN = 6,
114 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
117 struct mlx5_ib_vma_private_data {
118 struct list_head list;
119 struct vm_area_struct *vma;
120 /* protect vma_private_list add/del */
121 struct mutex *vma_private_list_mutex;
124 struct mlx5_ib_ucontext {
125 struct ib_ucontext ibucontext;
126 struct list_head db_page_list;
128 /* protect doorbell record alloc/free
130 struct mutex db_page_mutex;
131 struct mlx5_bfreg_info bfregi;
133 /* Transport Domain number */
135 struct list_head vma_private_list;
136 /* protect vma_private_list add/del */
137 struct mutex vma_private_list_mutex;
140 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES);
144 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
146 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
154 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
155 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
156 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
157 #error "Invalid number of bypass priorities"
159 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
161 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
162 #define MLX5_IB_NUM_SNIFFER_FTS 2
163 #define MLX5_IB_NUM_EGRESS_FTS 1
164 struct mlx5_ib_flow_prio {
165 struct mlx5_flow_table *flow_table;
166 unsigned int refcount;
169 struct mlx5_ib_flow_handler {
170 struct list_head list;
171 struct ib_flow ibflow;
172 struct mlx5_ib_flow_prio *prio;
173 struct mlx5_flow_handle *rule;
174 struct ib_counters *ibcounters;
177 struct mlx5_ib_flow_matcher {
178 struct mlx5_ib_match_params matcher_mask;
180 enum mlx5_ib_flow_type flow_type;
182 struct mlx5_core_dev *mdev;
184 u8 match_criteria_enable;
187 struct mlx5_ib_flow_db {
188 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
189 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
190 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
191 struct mlx5_flow_table *lag_demux_ft;
192 /* Protect flow steering bypass flow tables
193 * when add/del flow rules.
194 * only single add/removal of flow steering rule could be done
200 /* Use macros here so that don't have to duplicate
201 * enum ib_send_flags and enum ib_qp_type for low-level driver
204 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
205 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
206 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
207 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
208 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
209 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
211 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
213 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
214 * creates the actual hardware QP.
216 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
217 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
218 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
219 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
221 #define MLX5_IB_UMR_OCTOWORD 16
222 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
224 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
225 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
226 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
227 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
228 #define MLX5_IB_UPD_XLT_PD BIT(4)
229 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
230 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
232 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
234 * These flags are intended for internal use by the mlx5_ib driver, and they
235 * rely on the range reserved for that use in the ib_qp_create_flags enum.
238 /* Create a UD QP whose source QP number is 1 */
239 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
241 return IB_QP_CREATE_RESERVED_START;
249 enum mlx5_ib_rq_flags {
250 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
251 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
257 struct wr_list *w_list;
261 /* serialize post to the work queue
276 enum mlx5_ib_wq_flags {
277 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
278 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
281 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
282 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
283 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
284 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
288 struct mlx5_core_qp core_qp;
295 u32 two_byte_shift_en;
296 u32 single_stride_log_num_of_bytes;
297 struct ib_umem *umem;
299 unsigned int page_shift;
306 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
320 struct mlx5_ib_rwq_ind_table {
321 struct ib_rwq_ind_table ib_rwq_ind_tbl;
325 struct mlx5_ib_ubuffer {
326 struct ib_umem *umem;
331 struct mlx5_ib_qp_base {
332 struct mlx5_ib_qp *container_mibqp;
333 struct mlx5_core_qp mqp;
334 struct mlx5_ib_ubuffer ubuffer;
337 struct mlx5_ib_qp_trans {
338 struct mlx5_ib_qp_base base;
345 struct mlx5_ib_rss_qp {
350 struct mlx5_ib_qp_base base;
351 struct mlx5_ib_wq *rq;
352 struct mlx5_ib_ubuffer ubuffer;
353 struct mlx5_db *doorbell;
360 struct mlx5_ib_qp_base base;
361 struct mlx5_ib_wq *sq;
362 struct mlx5_ib_ubuffer ubuffer;
363 struct mlx5_db *doorbell;
364 struct mlx5_flow_handle *flow_rule;
369 struct mlx5_ib_raw_packet_qp {
370 struct mlx5_ib_sq sq;
371 struct mlx5_ib_rq rq;
376 unsigned long offset;
377 struct mlx5_sq_bfreg *bfreg;
381 struct mlx5_core_dct mdct;
388 struct mlx5_ib_qp_trans trans_qp;
389 struct mlx5_ib_raw_packet_qp raw_packet_qp;
390 struct mlx5_ib_rss_qp rss_qp;
391 struct mlx5_ib_dct dct;
393 struct mlx5_frag_buf buf;
396 struct mlx5_ib_wq rq;
400 struct mlx5_ib_wq sq;
402 /* serialize qp state modifications
414 /* only for user space QPs. For kernel
415 * we have it from the bf object
421 /* Store signature errors */
424 struct list_head qps_list;
425 struct list_head cq_recv_list;
426 struct list_head cq_send_list;
427 struct mlx5_rate_limit rl;
429 bool tunnel_offload_en;
430 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */
431 enum ib_qp_type qp_sub_type;
434 struct mlx5_ib_cq_buf {
435 struct mlx5_frag_buf_ctrl fbc;
436 struct ib_umem *umem;
441 enum mlx5_ib_qp_flags {
442 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
443 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
444 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
445 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
446 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
447 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
448 /* QP uses 1 as its source QP number */
449 MLX5_IB_QP_SQPN_QP1 = 1 << 6,
450 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
451 MLX5_IB_QP_RSS = 1 << 8,
452 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9,
453 MLX5_IB_QP_UNDERLAY = 1 << 10,
454 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11,
455 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12,
459 struct ib_send_wr wr;
463 unsigned int page_shift;
464 unsigned int xlt_size;
470 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr)
472 return container_of(wr, struct mlx5_umr_wr, wr);
475 struct mlx5_shared_mr_info {
477 struct ib_umem *umem;
480 enum mlx5_ib_cq_pr_flags {
481 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
486 struct mlx5_core_cq mcq;
487 struct mlx5_ib_cq_buf buf;
490 /* serialize access to the CQ
496 struct mutex resize_mutex;
497 struct mlx5_ib_cq_buf *resize_buf;
498 struct ib_umem *resize_umem;
500 struct list_head list_send_qp;
501 struct list_head list_recv_qp;
503 struct list_head wc_list;
504 enum ib_cq_notify_flags notify_flags;
505 struct work_struct notify_work;
506 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
511 struct list_head list;
516 struct mlx5_core_srq msrq;
517 struct mlx5_frag_buf buf;
520 /* protect SRQ hanlding
526 struct ib_umem *umem;
527 /* serialize arming a SRQ
533 struct mlx5_ib_xrcd {
534 struct ib_xrcd ibxrcd;
538 enum mlx5_ib_mtt_access_flags {
539 MLX5_IB_MTT_READ = (1 << 0),
540 MLX5_IB_MTT_WRITE = (1 << 1),
545 phys_addr_t dev_addr;
548 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
550 #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
551 IB_ACCESS_REMOTE_WRITE |\
552 IB_ACCESS_REMOTE_READ |\
553 IB_ACCESS_REMOTE_ATOMIC |\
564 struct mlx5_core_mkey mmkey;
565 struct ib_umem *umem;
566 struct mlx5_shared_mr_info *smr_info;
567 struct list_head list;
569 bool allocated_from_cache;
571 struct mlx5_ib_dev *dev;
572 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
573 struct mlx5_core_sig_ctx *sig;
576 int access_flags; /* Needed for rereg MR */
578 struct mlx5_ib_mr *parent;
579 atomic_t num_leaf_free;
580 wait_queue_head_t q_leaf_free;
585 struct mlx5_core_mkey mmkey;
589 struct mlx5_ib_umr_context {
591 enum ib_wc_status status;
592 struct completion done;
599 /* control access to UMR QP
601 struct semaphore sem;
610 struct mlx5_cache_ent {
611 struct list_head head;
612 /* sync access to the cahce entry
629 struct dentry *fsize;
631 struct dentry *fmiss;
632 struct dentry *flimit;
634 struct mlx5_ib_dev *dev;
635 struct work_struct work;
636 struct delayed_work dwork;
638 struct completion compl;
641 struct mlx5_mr_cache {
642 struct workqueue_struct *wq;
643 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
646 unsigned long last_add;
649 struct mlx5_ib_gsi_qp;
651 struct mlx5_ib_port_resources {
652 struct mlx5_ib_resources *devr;
653 struct mlx5_ib_gsi_qp *gsi;
654 struct work_struct pkey_change_work;
657 struct mlx5_ib_resources {
664 struct mlx5_ib_port_resources ports[2];
665 /* Protects changes to the port resources */
669 struct mlx5_ib_counters {
673 u32 num_cong_counters;
674 u32 num_ext_ppcnt_counters;
679 struct mlx5_ib_multiport_info;
681 struct mlx5_ib_multiport {
682 struct mlx5_ib_multiport_info *mpi;
683 /* To be held when accessing the multiport info */
687 struct mlx5_ib_port {
688 struct mlx5_ib_counters cnts;
689 struct mlx5_ib_multiport mp;
690 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
694 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
697 rwlock_t netdev_lock;
698 struct net_device *netdev;
699 struct notifier_block nb;
701 enum ib_port_state last_port_state;
702 struct mlx5_ib_dev *dev;
706 struct mlx5_ib_dbg_param {
708 struct mlx5_ib_dev *dev;
709 struct dentry *dentry;
713 enum mlx5_ib_dbg_cc_types {
714 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
715 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
716 MLX5_IB_DBG_CC_RP_TIME_RESET,
717 MLX5_IB_DBG_CC_RP_BYTE_RESET,
718 MLX5_IB_DBG_CC_RP_THRESHOLD,
719 MLX5_IB_DBG_CC_RP_AI_RATE,
720 MLX5_IB_DBG_CC_RP_HAI_RATE,
721 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
722 MLX5_IB_DBG_CC_RP_MIN_RATE,
723 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
724 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
725 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
726 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
727 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
728 MLX5_IB_DBG_CC_RP_GD,
729 MLX5_IB_DBG_CC_NP_CNP_DSCP,
730 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
731 MLX5_IB_DBG_CC_NP_CNP_PRIO,
735 struct mlx5_ib_dbg_cc_params {
737 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
741 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
744 struct mlx5_ib_dbg_delay_drop {
745 struct dentry *dir_debugfs;
746 struct dentry *rqs_cnt_debugfs;
747 struct dentry *events_cnt_debugfs;
748 struct dentry *timeout_debugfs;
751 struct mlx5_ib_delay_drop {
752 struct mlx5_ib_dev *dev;
753 struct work_struct delay_drop_work;
754 /* serialize setting of delay drop */
760 struct mlx5_ib_dbg_delay_drop *dbg;
763 enum mlx5_ib_stages {
765 MLX5_IB_STAGE_FLOW_DB,
767 MLX5_IB_STAGE_NON_DEFAULT_CB,
769 MLX5_IB_STAGE_DEVICE_RESOURCES,
771 MLX5_IB_STAGE_COUNTERS,
772 MLX5_IB_STAGE_CONG_DEBUGFS,
775 MLX5_IB_STAGE_PRE_IB_REG_UMR,
777 MLX5_IB_STAGE_IB_REG,
778 MLX5_IB_STAGE_POST_IB_REG_UMR,
779 MLX5_IB_STAGE_DELAY_DROP,
780 MLX5_IB_STAGE_CLASS_ATTR,
781 MLX5_IB_STAGE_REP_REG,
785 struct mlx5_ib_stage {
786 int (*init)(struct mlx5_ib_dev *dev);
787 void (*cleanup)(struct mlx5_ib_dev *dev);
790 #define STAGE_CREATE(_stage, _init, _cleanup) \
791 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
793 struct mlx5_ib_profile {
794 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
797 struct mlx5_ib_multiport_info {
798 struct list_head list;
799 struct mlx5_ib_dev *ibdev;
800 struct mlx5_core_dev *mdev;
801 struct completion unref_comp;
808 struct mlx5_ib_flow_action {
809 struct ib_flow_action ib_action;
813 struct mlx5_accel_esp_xfrm *ctx;
819 struct mlx5_core_dev *dev;
820 spinlock_t memic_lock;
821 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
824 struct mlx5_read_counters_attr {
825 struct mlx5_fc *hw_cntrs_hndl;
830 enum mlx5_ib_counters_type {
831 MLX5_IB_COUNTERS_FLOW,
834 struct mlx5_ib_mcounters {
835 struct ib_counters ibcntrs;
836 enum mlx5_ib_counters_type type;
837 /* number of counters supported for this counters type */
839 struct mlx5_fc *hw_cntrs_hndl;
840 /* read function for this counters type */
841 int (*read_counters)(struct ib_device *ibdev,
842 struct mlx5_read_counters_attr *read_attr);
843 /* max index set as part of create_flow */
845 /* number of counters data entries (<description,index> pair) */
847 /* counters data array for descriptions and indexes */
848 struct mlx5_ib_flow_counters_desc *counters_data;
849 /* protects access to mcounters internal data */
850 struct mutex mcntrs_mutex;
853 static inline struct mlx5_ib_mcounters *
854 to_mcounters(struct ib_counters *ibcntrs)
856 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
860 struct ib_device ib_dev;
861 struct mlx5_core_dev *mdev;
862 struct mlx5_roce roce[MLX5_MAX_PORTS];
864 /* serialize update of capability mask
866 struct mutex cap_mask_mutex;
868 struct umr_common umrc;
869 /* sync used page count stats
871 struct mlx5_ib_resources devr;
872 struct mlx5_mr_cache cache;
873 struct timer_list delay_timer;
874 /* Prevents soft lock on massive reg MRs */
875 struct mutex slow_path_mutex;
877 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
878 struct ib_odp_caps odp_caps;
881 * Sleepable RCU that prevents destruction of MRs while they are still
882 * being used by a page fault handler.
884 struct srcu_struct mr_srcu;
887 struct mlx5_ib_flow_db *flow_db;
888 /* protect resources needed as part of reset flow */
889 spinlock_t reset_flow_resource_lock;
890 struct list_head qp_list;
891 /* Array with num_ports elements */
892 struct mlx5_ib_port *port;
893 struct mlx5_sq_bfreg bfreg;
894 struct mlx5_sq_bfreg fp_bfreg;
895 struct mlx5_ib_delay_drop delay_drop;
896 const struct mlx5_ib_profile *profile;
897 struct mlx5_eswitch_rep *rep;
899 /* protect the user_td */
900 struct mutex lb_mutex;
903 struct list_head ib_dev_list;
905 struct mlx5_memic memic;
908 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
910 return container_of(mcq, struct mlx5_ib_cq, mcq);
913 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
915 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
918 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
920 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
923 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
925 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
928 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
930 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
933 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
935 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
938 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
940 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
943 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
945 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
948 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
950 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
953 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
955 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
958 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
960 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
963 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
965 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
968 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
970 return container_of(msrq, struct mlx5_ib_srq, msrq);
973 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
975 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
978 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
980 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
983 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
985 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
988 static inline struct mlx5_ib_flow_action *
989 to_mflow_act(struct ib_flow_action *ibact)
991 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
994 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
996 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
997 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
998 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
999 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1000 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
1001 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1002 const void *in_mad, void *response_mad);
1003 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr,
1004 struct ib_udata *udata);
1005 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1006 int mlx5_ib_destroy_ah(struct ib_ah *ah);
1007 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
1008 struct ib_srq_init_attr *init_attr,
1009 struct ib_udata *udata);
1010 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1011 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1012 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1013 int mlx5_ib_destroy_srq(struct ib_srq *srq);
1014 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
1015 struct ib_recv_wr **bad_wr);
1016 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1017 struct ib_qp_init_attr *init_attr,
1018 struct ib_udata *udata);
1019 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1020 int attr_mask, struct ib_udata *udata);
1021 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1022 struct ib_qp_init_attr *qp_init_attr);
1023 int mlx5_ib_destroy_qp(struct ib_qp *qp);
1024 void mlx5_ib_drain_sq(struct ib_qp *qp);
1025 void mlx5_ib_drain_rq(struct ib_qp *qp);
1026 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1027 struct ib_send_wr **bad_wr);
1028 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1029 struct ib_recv_wr **bad_wr);
1030 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
1031 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
1032 void *buffer, u32 length,
1033 struct mlx5_ib_qp_base *base);
1034 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
1035 const struct ib_cq_init_attr *attr,
1036 struct ib_ucontext *context,
1037 struct ib_udata *udata);
1038 int mlx5_ib_destroy_cq(struct ib_cq *cq);
1039 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1040 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1041 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1042 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1043 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1044 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1045 u64 virt_addr, int access_flags,
1046 struct ib_udata *udata);
1047 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1048 struct ib_udata *udata);
1049 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1050 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1051 int page_shift, int flags);
1052 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1054 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1055 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1056 u64 length, u64 virt_addr, int access_flags,
1057 struct ib_pd *pd, struct ib_udata *udata);
1058 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
1059 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
1060 enum ib_mr_type mr_type,
1062 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1063 unsigned int *sg_offset);
1064 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1065 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1066 const struct ib_mad_hdr *in, size_t in_mad_size,
1067 struct ib_mad_hdr *out, size_t *out_mad_size,
1068 u16 *out_mad_pkey_index);
1069 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1070 struct ib_ucontext *context,
1071 struct ib_udata *udata);
1072 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
1073 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1074 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1075 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1076 struct ib_smp *out_mad);
1077 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1078 __be64 *sys_image_guid);
1079 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1081 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1083 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1084 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1085 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1087 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1089 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1090 struct ib_port_attr *props);
1091 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1092 struct ib_port_attr *props);
1093 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
1094 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
1095 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1096 unsigned long max_page_shift,
1097 int *count, int *shift,
1098 int *ncont, int *order);
1099 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1100 int page_shift, size_t offset, size_t num_pages,
1101 __be64 *pas, int access_flags);
1102 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1103 int page_shift, __be64 *pas, int access_flags);
1104 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1105 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
1106 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1107 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1109 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry);
1110 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1111 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1112 struct ib_mr_status *mr_status);
1113 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1114 struct ib_wq_init_attr *init_attr,
1115 struct ib_udata *udata);
1116 int mlx5_ib_destroy_wq(struct ib_wq *wq);
1117 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1118 u32 wq_attr_mask, struct ib_udata *udata);
1119 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1120 struct ib_rwq_ind_table_init_attr *init_attr,
1121 struct ib_udata *udata);
1122 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1123 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev);
1124 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1125 struct ib_ucontext *context,
1126 struct ib_dm_alloc_attr *attr,
1127 struct uverbs_attr_bundle *attrs);
1128 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm);
1129 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1130 struct ib_dm_mr_attr *attr,
1131 struct uverbs_attr_bundle *attrs);
1133 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1134 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1135 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context,
1136 struct mlx5_pagefault *pfault);
1137 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1138 int __init mlx5_ib_odp_init(void);
1139 void mlx5_ib_odp_cleanup(void);
1140 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
1142 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1143 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1144 size_t nentries, struct mlx5_ib_mr *mr, int flags);
1145 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1146 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1151 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1152 static inline int mlx5_ib_odp_init(void) { return 0; }
1153 static inline void mlx5_ib_odp_cleanup(void) {}
1154 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
1155 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1156 size_t nentries, struct mlx5_ib_mr *mr,
1159 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1161 /* Needed for rep profile */
1162 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev);
1163 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev);
1164 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev);
1165 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev);
1166 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev);
1167 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev);
1168 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev);
1169 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev);
1170 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev);
1171 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev);
1172 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev);
1173 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev);
1174 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev);
1175 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev);
1176 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev);
1177 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev);
1178 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev);
1179 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev);
1180 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1181 const struct mlx5_ib_profile *profile,
1183 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1184 const struct mlx5_ib_profile *profile);
1186 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1187 u8 port, struct ifla_vf_info *info);
1188 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1189 u8 port, int state);
1190 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1191 u8 port, struct ifla_vf_stats *stats);
1192 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1193 u64 guid, int type);
1195 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
1196 const struct ib_gid_attr *attr);
1198 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1199 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1201 /* GSI QP helper functions */
1202 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1203 struct ib_qp_init_attr *init_attr);
1204 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1205 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1207 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1209 struct ib_qp_init_attr *qp_init_attr);
1210 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr,
1211 struct ib_send_wr **bad_wr);
1212 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr,
1213 struct ib_recv_wr **bad_wr);
1214 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1216 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1218 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1220 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1221 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1223 u8 *native_port_num);
1224 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1227 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
1228 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1229 struct mlx5_ib_ucontext *context);
1230 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev,
1231 struct mlx5_ib_ucontext *context);
1232 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void);
1233 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1234 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1235 void *cmd_in, int inlen, int dest_id, int dest_type);
1236 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type);
1239 mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1240 struct mlx5_ib_ucontext *context) { return -EOPNOTSUPP; };
1241 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev,
1242 struct mlx5_ib_ucontext *context) {}
1243 static inline const struct uverbs_object_tree_def *
1244 mlx5_ib_get_devx_tree(void) { return NULL; }
1245 static inline struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1246 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1247 void *cmd_in, int inlen, int dest_id, int dest_type)
1249 return ERR_PTR(-EOPNOTSUPP);
1251 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id,
1257 static inline void init_query_mad(struct ib_smp *mad)
1259 mad->base_version = 1;
1260 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1261 mad->class_version = 1;
1262 mad->method = IB_MGMT_METHOD_GET;
1265 static inline u8 convert_access(int acc)
1267 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1268 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1269 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1270 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1271 MLX5_PERM_LOCAL_READ;
1274 static inline int is_qp1(enum ib_qp_type qp_type)
1276 return qp_type == MLX5_IB_QPT_HW_GSI;
1279 #define MLX5_MAX_UMR_SHIFT 16
1280 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1282 static inline u32 check_cq_create_flags(u32 flags)
1285 * It returns non-zero value for unsupported CQ
1286 * create flags, otherwise it returns zero.
1288 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1289 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1292 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1296 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1297 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1299 *user_index = cmd_uidx;
1301 *user_index = MLX5_IB_DEFAULT_UIDX;
1307 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1308 struct mlx5_ib_create_qp *ucmd,
1312 u8 cqe_version = ucontext->cqe_version;
1314 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
1315 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1318 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
1322 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1325 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1326 struct mlx5_ib_create_srq *ucmd,
1330 u8 cqe_version = ucontext->cqe_version;
1332 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
1333 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1336 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
1340 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1343 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1345 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1346 MLX5_UARS_IN_PAGE : 1;
1349 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1350 struct mlx5_bfreg_info *bfregi)
1352 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1355 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1356 void mlx5_ib_put_xlt_emergency_page(void);
1358 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1359 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1361 #endif /* MLX5_IB_H */