2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 #include <linux/mlx5/transobj.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/mlx5-abi.h>
48 #include <rdma/uverbs_ioctl.h>
50 #define mlx5_ib_dbg(dev, format, arg...) \
51 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
52 __LINE__, current->pid, ##arg)
54 #define mlx5_ib_err(dev, format, arg...) \
55 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
56 __LINE__, current->pid, ##arg)
58 #define mlx5_ib_warn(dev, format, arg...) \
59 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
60 __LINE__, current->pid, ##arg)
62 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
63 sizeof(((type *)0)->fld) <= (sz))
64 #define MLX5_IB_DEFAULT_UIDX 0xffffff
65 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
67 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
70 MLX5_IB_MMAP_CMD_SHIFT = 8,
71 MLX5_IB_MMAP_CMD_MASK = 0xff,
75 MLX5_RES_SCAT_DATA32_CQE = 0x1,
76 MLX5_RES_SCAT_DATA64_CQE = 0x2,
77 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
78 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
81 enum mlx5_ib_latency_class {
82 MLX5_IB_LATENCY_CLASS_LOW,
83 MLX5_IB_LATENCY_CLASS_MEDIUM,
84 MLX5_IB_LATENCY_CLASS_HIGH,
87 enum mlx5_ib_mad_ifc_flags {
88 MLX5_MAD_IFC_IGNORE_MKEY = 1,
89 MLX5_MAD_IFC_IGNORE_BKEY = 2,
90 MLX5_MAD_IFC_NET_VIEW = 4,
94 MLX5_CROSS_CHANNEL_BFREG = 0,
103 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
108 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
109 MLX5_IB_INVALID_BFREG = BIT(31),
113 MLX5_MAX_MEMIC_PAGES = 0x100,
114 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
118 MLX5_MEMIC_BASE_ALIGN = 6,
119 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
122 struct mlx5_ib_vma_private_data {
123 struct list_head list;
124 struct vm_area_struct *vma;
125 /* protect vma_private_list add/del */
126 struct mutex *vma_private_list_mutex;
129 struct mlx5_ib_ucontext {
130 struct ib_ucontext ibucontext;
131 struct list_head db_page_list;
133 /* protect doorbell record alloc/free
135 struct mutex db_page_mutex;
136 struct mlx5_bfreg_info bfregi;
138 /* Transport Domain number */
140 struct list_head vma_private_list;
141 /* protect vma_private_list add/del */
142 struct mutex vma_private_list_mutex;
145 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES);
148 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
150 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
158 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
159 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
160 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
161 #error "Invalid number of bypass priorities"
163 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
165 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
166 #define MLX5_IB_NUM_SNIFFER_FTS 2
167 #define MLX5_IB_NUM_EGRESS_FTS 1
168 struct mlx5_ib_flow_prio {
169 struct mlx5_flow_table *flow_table;
170 unsigned int refcount;
173 struct mlx5_ib_flow_handler {
174 struct list_head list;
175 struct ib_flow ibflow;
176 struct mlx5_ib_flow_prio *prio;
177 struct mlx5_flow_handle *rule;
180 struct mlx5_ib_flow_db {
181 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
182 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
183 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
184 struct mlx5_flow_table *lag_demux_ft;
185 /* Protect flow steering bypass flow tables
186 * when add/del flow rules.
187 * only single add/removal of flow steering rule could be done
193 /* Use macros here so that don't have to duplicate
194 * enum ib_send_flags and enum ib_qp_type for low-level driver
197 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
198 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
199 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
200 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
201 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
202 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
204 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
206 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
207 * creates the actual hardware QP.
209 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
210 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
211 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
212 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
214 #define MLX5_IB_UMR_OCTOWORD 16
215 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
217 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
218 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
219 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
220 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
221 #define MLX5_IB_UPD_XLT_PD BIT(4)
222 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
223 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
225 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
227 * These flags are intended for internal use by the mlx5_ib driver, and they
228 * rely on the range reserved for that use in the ib_qp_create_flags enum.
231 /* Create a UD QP whose source QP number is 1 */
232 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
234 return IB_QP_CREATE_RESERVED_START;
242 enum mlx5_ib_rq_flags {
243 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
244 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
250 struct wr_list *w_list;
254 /* serialize post to the work queue
269 enum mlx5_ib_wq_flags {
270 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
271 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
274 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
275 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
276 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
277 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
281 struct mlx5_core_qp core_qp;
288 u32 two_byte_shift_en;
289 u32 single_stride_log_num_of_bytes;
290 struct ib_umem *umem;
292 unsigned int page_shift;
299 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
313 struct mlx5_ib_rwq_ind_table {
314 struct ib_rwq_ind_table ib_rwq_ind_tbl;
318 struct mlx5_ib_ubuffer {
319 struct ib_umem *umem;
324 struct mlx5_ib_qp_base {
325 struct mlx5_ib_qp *container_mibqp;
326 struct mlx5_core_qp mqp;
327 struct mlx5_ib_ubuffer ubuffer;
330 struct mlx5_ib_qp_trans {
331 struct mlx5_ib_qp_base base;
338 struct mlx5_ib_rss_qp {
343 struct mlx5_ib_qp_base base;
344 struct mlx5_ib_wq *rq;
345 struct mlx5_ib_ubuffer ubuffer;
346 struct mlx5_db *doorbell;
353 struct mlx5_ib_qp_base base;
354 struct mlx5_ib_wq *sq;
355 struct mlx5_ib_ubuffer ubuffer;
356 struct mlx5_db *doorbell;
357 struct mlx5_flow_handle *flow_rule;
362 struct mlx5_ib_raw_packet_qp {
363 struct mlx5_ib_sq sq;
364 struct mlx5_ib_rq rq;
369 unsigned long offset;
370 struct mlx5_sq_bfreg *bfreg;
374 struct mlx5_core_dct mdct;
381 struct mlx5_ib_qp_trans trans_qp;
382 struct mlx5_ib_raw_packet_qp raw_packet_qp;
383 struct mlx5_ib_rss_qp rss_qp;
384 struct mlx5_ib_dct dct;
386 struct mlx5_frag_buf buf;
389 struct mlx5_ib_wq rq;
393 struct mlx5_ib_wq sq;
395 /* serialize qp state modifications
407 /* only for user space QPs. For kernel
408 * we have it from the bf object
414 /* Store signature errors */
417 struct list_head qps_list;
418 struct list_head cq_recv_list;
419 struct list_head cq_send_list;
420 struct mlx5_rate_limit rl;
422 bool tunnel_offload_en;
423 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */
424 enum ib_qp_type qp_sub_type;
427 struct mlx5_ib_cq_buf {
428 struct mlx5_frag_buf_ctrl fbc;
429 struct ib_umem *umem;
434 enum mlx5_ib_qp_flags {
435 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
436 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
437 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
438 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
439 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
440 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
441 /* QP uses 1 as its source QP number */
442 MLX5_IB_QP_SQPN_QP1 = 1 << 6,
443 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
444 MLX5_IB_QP_RSS = 1 << 8,
445 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9,
446 MLX5_IB_QP_UNDERLAY = 1 << 10,
447 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11,
448 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12,
452 struct ib_send_wr wr;
456 unsigned int page_shift;
457 unsigned int xlt_size;
463 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr)
465 return container_of(wr, struct mlx5_umr_wr, wr);
468 struct mlx5_shared_mr_info {
470 struct ib_umem *umem;
473 enum mlx5_ib_cq_pr_flags {
474 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
479 struct mlx5_core_cq mcq;
480 struct mlx5_ib_cq_buf buf;
483 /* serialize access to the CQ
489 struct mutex resize_mutex;
490 struct mlx5_ib_cq_buf *resize_buf;
491 struct ib_umem *resize_umem;
493 struct list_head list_send_qp;
494 struct list_head list_recv_qp;
496 struct list_head wc_list;
497 enum ib_cq_notify_flags notify_flags;
498 struct work_struct notify_work;
499 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
504 struct list_head list;
509 struct mlx5_core_srq msrq;
510 struct mlx5_frag_buf buf;
513 /* protect SRQ hanlding
519 struct ib_umem *umem;
520 /* serialize arming a SRQ
526 struct mlx5_ib_xrcd {
527 struct ib_xrcd ibxrcd;
531 enum mlx5_ib_mtt_access_flags {
532 MLX5_IB_MTT_READ = (1 << 0),
533 MLX5_IB_MTT_WRITE = (1 << 1),
538 phys_addr_t dev_addr;
541 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
543 #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
544 IB_ACCESS_REMOTE_WRITE |\
545 IB_ACCESS_REMOTE_READ |\
546 IB_ACCESS_REMOTE_ATOMIC |\
557 struct mlx5_core_mkey mmkey;
558 struct ib_umem *umem;
559 struct mlx5_shared_mr_info *smr_info;
560 struct list_head list;
562 bool allocated_from_cache;
564 struct mlx5_ib_dev *dev;
565 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
566 struct mlx5_core_sig_ctx *sig;
569 int access_flags; /* Needed for rereg MR */
571 struct mlx5_ib_mr *parent;
572 atomic_t num_leaf_free;
573 wait_queue_head_t q_leaf_free;
578 struct mlx5_core_mkey mmkey;
582 struct mlx5_ib_umr_context {
584 enum ib_wc_status status;
585 struct completion done;
592 /* control access to UMR QP
594 struct semaphore sem;
603 struct mlx5_cache_ent {
604 struct list_head head;
605 /* sync access to the cahce entry
622 struct dentry *fsize;
624 struct dentry *fmiss;
625 struct dentry *flimit;
627 struct mlx5_ib_dev *dev;
628 struct work_struct work;
629 struct delayed_work dwork;
631 struct completion compl;
634 struct mlx5_mr_cache {
635 struct workqueue_struct *wq;
636 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
639 unsigned long last_add;
642 struct mlx5_ib_gsi_qp;
644 struct mlx5_ib_port_resources {
645 struct mlx5_ib_resources *devr;
646 struct mlx5_ib_gsi_qp *gsi;
647 struct work_struct pkey_change_work;
650 struct mlx5_ib_resources {
657 struct mlx5_ib_port_resources ports[2];
658 /* Protects changes to the port resources */
662 struct mlx5_ib_counters {
666 u32 num_cong_counters;
671 struct mlx5_ib_multiport_info;
673 struct mlx5_ib_multiport {
674 struct mlx5_ib_multiport_info *mpi;
675 /* To be held when accessing the multiport info */
679 struct mlx5_ib_port {
680 struct mlx5_ib_counters cnts;
681 struct mlx5_ib_multiport mp;
682 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
686 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
689 rwlock_t netdev_lock;
690 struct net_device *netdev;
691 struct notifier_block nb;
693 enum ib_port_state last_port_state;
694 struct mlx5_ib_dev *dev;
698 struct mlx5_ib_dbg_param {
700 struct mlx5_ib_dev *dev;
701 struct dentry *dentry;
705 enum mlx5_ib_dbg_cc_types {
706 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
707 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
708 MLX5_IB_DBG_CC_RP_TIME_RESET,
709 MLX5_IB_DBG_CC_RP_BYTE_RESET,
710 MLX5_IB_DBG_CC_RP_THRESHOLD,
711 MLX5_IB_DBG_CC_RP_AI_RATE,
712 MLX5_IB_DBG_CC_RP_HAI_RATE,
713 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
714 MLX5_IB_DBG_CC_RP_MIN_RATE,
715 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
716 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
717 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
718 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
719 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
720 MLX5_IB_DBG_CC_RP_GD,
721 MLX5_IB_DBG_CC_NP_CNP_DSCP,
722 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
723 MLX5_IB_DBG_CC_NP_CNP_PRIO,
727 struct mlx5_ib_dbg_cc_params {
729 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
733 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
736 struct mlx5_ib_dbg_delay_drop {
737 struct dentry *dir_debugfs;
738 struct dentry *rqs_cnt_debugfs;
739 struct dentry *events_cnt_debugfs;
740 struct dentry *timeout_debugfs;
743 struct mlx5_ib_delay_drop {
744 struct mlx5_ib_dev *dev;
745 struct work_struct delay_drop_work;
746 /* serialize setting of delay drop */
752 struct mlx5_ib_dbg_delay_drop *dbg;
755 enum mlx5_ib_stages {
757 MLX5_IB_STAGE_FLOW_DB,
759 MLX5_IB_STAGE_NON_DEFAULT_CB,
761 MLX5_IB_STAGE_DEVICE_RESOURCES,
763 MLX5_IB_STAGE_COUNTERS,
764 MLX5_IB_STAGE_CONG_DEBUGFS,
767 MLX5_IB_STAGE_PRE_IB_REG_UMR,
769 MLX5_IB_STAGE_IB_REG,
770 MLX5_IB_STAGE_POST_IB_REG_UMR,
771 MLX5_IB_STAGE_DELAY_DROP,
772 MLX5_IB_STAGE_CLASS_ATTR,
773 MLX5_IB_STAGE_REP_REG,
777 struct mlx5_ib_stage {
778 int (*init)(struct mlx5_ib_dev *dev);
779 void (*cleanup)(struct mlx5_ib_dev *dev);
782 #define STAGE_CREATE(_stage, _init, _cleanup) \
783 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
785 struct mlx5_ib_profile {
786 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
789 struct mlx5_ib_multiport_info {
790 struct list_head list;
791 struct mlx5_ib_dev *ibdev;
792 struct mlx5_core_dev *mdev;
793 struct completion unref_comp;
800 struct mlx5_ib_flow_action {
801 struct ib_flow_action ib_action;
805 struct mlx5_accel_esp_xfrm *ctx;
811 struct mlx5_core_dev *dev;
812 spinlock_t memic_lock;
813 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
817 struct ib_device ib_dev;
818 struct mlx5_core_dev *mdev;
819 struct mlx5_roce roce[MLX5_MAX_PORTS];
821 /* serialize update of capability mask
823 struct mutex cap_mask_mutex;
825 struct umr_common umrc;
826 /* sync used page count stats
828 struct mlx5_ib_resources devr;
829 struct mlx5_mr_cache cache;
830 struct timer_list delay_timer;
831 /* Prevents soft lock on massive reg MRs */
832 struct mutex slow_path_mutex;
834 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
835 struct ib_odp_caps odp_caps;
838 * Sleepable RCU that prevents destruction of MRs while they are still
839 * being used by a page fault handler.
841 struct srcu_struct mr_srcu;
844 struct mlx5_ib_flow_db *flow_db;
845 /* protect resources needed as part of reset flow */
846 spinlock_t reset_flow_resource_lock;
847 struct list_head qp_list;
848 /* Array with num_ports elements */
849 struct mlx5_ib_port *port;
850 struct mlx5_sq_bfreg bfreg;
851 struct mlx5_sq_bfreg fp_bfreg;
852 struct mlx5_ib_delay_drop delay_drop;
853 const struct mlx5_ib_profile *profile;
854 struct mlx5_eswitch_rep *rep;
856 /* protect the user_td */
857 struct mutex lb_mutex;
860 struct list_head ib_dev_list;
862 struct mlx5_memic memic;
865 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
867 return container_of(mcq, struct mlx5_ib_cq, mcq);
870 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
872 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
875 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
877 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
880 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
882 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
885 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
887 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
890 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
892 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
895 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
897 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
900 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
902 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
905 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
907 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
910 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
912 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
915 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
917 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
920 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
922 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
925 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
927 return container_of(msrq, struct mlx5_ib_srq, msrq);
930 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
932 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
935 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
937 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
940 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
942 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
945 static inline struct mlx5_ib_flow_action *
946 to_mflow_act(struct ib_flow_action *ibact)
948 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
951 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
953 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
954 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
955 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
956 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
957 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
958 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
959 const void *in_mad, void *response_mad);
960 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr,
961 struct ib_udata *udata);
962 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
963 int mlx5_ib_destroy_ah(struct ib_ah *ah);
964 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
965 struct ib_srq_init_attr *init_attr,
966 struct ib_udata *udata);
967 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
968 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
969 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
970 int mlx5_ib_destroy_srq(struct ib_srq *srq);
971 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
972 struct ib_recv_wr **bad_wr);
973 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
974 struct ib_qp_init_attr *init_attr,
975 struct ib_udata *udata);
976 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
977 int attr_mask, struct ib_udata *udata);
978 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
979 struct ib_qp_init_attr *qp_init_attr);
980 int mlx5_ib_destroy_qp(struct ib_qp *qp);
981 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
982 struct ib_send_wr **bad_wr);
983 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
984 struct ib_recv_wr **bad_wr);
985 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
986 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
987 void *buffer, u32 length,
988 struct mlx5_ib_qp_base *base);
989 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
990 const struct ib_cq_init_attr *attr,
991 struct ib_ucontext *context,
992 struct ib_udata *udata);
993 int mlx5_ib_destroy_cq(struct ib_cq *cq);
994 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
995 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
996 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
997 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
998 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
999 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1000 u64 virt_addr, int access_flags,
1001 struct ib_udata *udata);
1002 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1003 struct ib_udata *udata);
1004 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1005 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1006 int page_shift, int flags);
1007 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1009 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1010 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1011 u64 length, u64 virt_addr, int access_flags,
1012 struct ib_pd *pd, struct ib_udata *udata);
1013 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
1014 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
1015 enum ib_mr_type mr_type,
1017 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1018 unsigned int *sg_offset);
1019 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1020 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1021 const struct ib_mad_hdr *in, size_t in_mad_size,
1022 struct ib_mad_hdr *out, size_t *out_mad_size,
1023 u16 *out_mad_pkey_index);
1024 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1025 struct ib_ucontext *context,
1026 struct ib_udata *udata);
1027 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
1028 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1029 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1030 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1031 struct ib_smp *out_mad);
1032 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1033 __be64 *sys_image_guid);
1034 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1036 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1038 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1039 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1040 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1042 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1044 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1045 struct ib_port_attr *props);
1046 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1047 struct ib_port_attr *props);
1048 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
1049 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
1050 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1051 unsigned long max_page_shift,
1052 int *count, int *shift,
1053 int *ncont, int *order);
1054 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1055 int page_shift, size_t offset, size_t num_pages,
1056 __be64 *pas, int access_flags);
1057 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1058 int page_shift, __be64 *pas, int access_flags);
1059 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1060 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
1061 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1062 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1064 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry);
1065 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1066 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1067 struct ib_mr_status *mr_status);
1068 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1069 struct ib_wq_init_attr *init_attr,
1070 struct ib_udata *udata);
1071 int mlx5_ib_destroy_wq(struct ib_wq *wq);
1072 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1073 u32 wq_attr_mask, struct ib_udata *udata);
1074 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1075 struct ib_rwq_ind_table_init_attr *init_attr,
1076 struct ib_udata *udata);
1077 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1078 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev);
1079 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1080 struct ib_ucontext *context,
1081 struct ib_dm_alloc_attr *attr,
1082 struct uverbs_attr_bundle *attrs);
1083 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm);
1084 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1085 struct ib_dm_mr_attr *attr,
1086 struct uverbs_attr_bundle *attrs);
1088 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1089 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1090 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context,
1091 struct mlx5_pagefault *pfault);
1092 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1093 int __init mlx5_ib_odp_init(void);
1094 void mlx5_ib_odp_cleanup(void);
1095 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
1097 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1098 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1099 size_t nentries, struct mlx5_ib_mr *mr, int flags);
1100 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1101 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1106 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1107 static inline int mlx5_ib_odp_init(void) { return 0; }
1108 static inline void mlx5_ib_odp_cleanup(void) {}
1109 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
1110 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1111 size_t nentries, struct mlx5_ib_mr *mr,
1114 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1116 /* Needed for rep profile */
1117 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev);
1118 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev);
1119 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev);
1120 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev);
1121 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev);
1122 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev);
1123 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev);
1124 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev);
1125 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev);
1126 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev);
1127 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev);
1128 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev);
1129 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev);
1130 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev);
1131 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev);
1132 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev);
1133 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev);
1134 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev);
1135 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1136 const struct mlx5_ib_profile *profile,
1138 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1139 const struct mlx5_ib_profile *profile);
1141 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1142 u8 port, struct ifla_vf_info *info);
1143 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1144 u8 port, int state);
1145 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1146 u8 port, struct ifla_vf_stats *stats);
1147 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1148 u64 guid, int type);
1150 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
1152 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
1153 int index, enum ib_gid_type *gid_type);
1155 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1156 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1158 /* GSI QP helper functions */
1159 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1160 struct ib_qp_init_attr *init_attr);
1161 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1162 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1164 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1166 struct ib_qp_init_attr *qp_init_attr);
1167 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr,
1168 struct ib_send_wr **bad_wr);
1169 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr,
1170 struct ib_recv_wr **bad_wr);
1171 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1173 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1175 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1177 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1178 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1180 u8 *native_port_num);
1181 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1184 static inline void init_query_mad(struct ib_smp *mad)
1186 mad->base_version = 1;
1187 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1188 mad->class_version = 1;
1189 mad->method = IB_MGMT_METHOD_GET;
1192 static inline u8 convert_access(int acc)
1194 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1195 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1196 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1197 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1198 MLX5_PERM_LOCAL_READ;
1201 static inline int is_qp1(enum ib_qp_type qp_type)
1203 return qp_type == MLX5_IB_QPT_HW_GSI;
1206 #define MLX5_MAX_UMR_SHIFT 16
1207 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1209 static inline u32 check_cq_create_flags(u32 flags)
1212 * It returns non-zero value for unsupported CQ
1213 * create flags, otherwise it returns zero.
1215 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1216 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1219 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1223 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1224 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1226 *user_index = cmd_uidx;
1228 *user_index = MLX5_IB_DEFAULT_UIDX;
1234 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1235 struct mlx5_ib_create_qp *ucmd,
1239 u8 cqe_version = ucontext->cqe_version;
1241 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
1242 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1245 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
1249 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1252 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1253 struct mlx5_ib_create_srq *ucmd,
1257 u8 cqe_version = ucontext->cqe_version;
1259 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
1260 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1263 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
1267 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1270 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1272 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1273 MLX5_UARS_IN_PAGE : 1;
1276 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1277 struct mlx5_bfreg_info *bfregi)
1279 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1282 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1283 void mlx5_ib_put_xlt_emergency_page(void);
1285 #endif /* MLX5_IB_H */