2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kref.h>
35 #include <linux/random.h>
36 #include <linux/debugfs.h>
37 #include <linux/export.h>
38 #include <linux/delay.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_umem_odp.h>
41 #include <rdma/ib_verbs.h>
45 MAX_PENDING_REG_MR = 8,
48 #define MLX5_UMR_ALIGN 2048
50 static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
51 static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
52 static int mr_cache_max_order(struct mlx5_ib_dev *dev);
54 static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev)
56 return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled);
59 static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
61 WARN_ON(xa_load(&dev->odp_mkeys, mlx5_base_mkey(mr->mmkey.key)));
63 return mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
66 static int order2idx(struct mlx5_ib_dev *dev, int order)
68 struct mlx5_mr_cache *cache = &dev->cache;
70 if (order < cache->ent[0].order)
73 return order - cache->ent[0].order;
76 static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length)
78 return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >=
79 length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1));
82 static void reg_mr_callback(int status, struct mlx5_async_work *context)
84 struct mlx5_ib_mr *mr =
85 container_of(context, struct mlx5_ib_mr, cb_work);
86 struct mlx5_ib_dev *dev = mr->dev;
87 struct mlx5_mr_cache *cache = &dev->cache;
88 int c = order2idx(dev, mr->order);
89 struct mlx5_cache_ent *ent = &cache->ent[c];
93 spin_lock_irqsave(&ent->lock, flags);
95 spin_unlock_irqrestore(&ent->lock, flags);
97 mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
100 mod_timer(&dev->delay_timer, jiffies + HZ);
104 mr->mmkey.type = MLX5_MKEY_MR;
105 spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags);
106 key = dev->mdev->priv.mkey_key++;
107 spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags);
108 mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key;
110 cache->last_add = jiffies;
112 spin_lock_irqsave(&ent->lock, flags);
113 list_add_tail(&mr->list, &ent->head);
116 spin_unlock_irqrestore(&ent->lock, flags);
118 if (!completion_done(&ent->compl))
119 complete(&ent->compl);
122 static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
124 struct mlx5_mr_cache *cache = &dev->cache;
125 struct mlx5_cache_ent *ent = &cache->ent[c];
126 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
127 struct mlx5_ib_mr *mr;
133 in = kzalloc(inlen, GFP_KERNEL);
137 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
138 for (i = 0; i < num; i++) {
139 if (ent->pending >= MAX_PENDING_REG_MR) {
144 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
149 mr->order = ent->order;
150 mr->allocated_from_cache = true;
153 MLX5_SET(mkc, mkc, free, 1);
154 MLX5_SET(mkc, mkc, umr_en, 1);
155 MLX5_SET(mkc, mkc, access_mode_1_0, ent->access_mode & 0x3);
156 MLX5_SET(mkc, mkc, access_mode_4_2,
157 (ent->access_mode >> 2) & 0x7);
159 MLX5_SET(mkc, mkc, qpn, 0xffffff);
160 MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt);
161 MLX5_SET(mkc, mkc, log_page_size, ent->page);
163 spin_lock_irq(&ent->lock);
165 spin_unlock_irq(&ent->lock);
166 err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey,
167 &dev->async_ctx, in, inlen,
168 mr->out, sizeof(mr->out),
169 reg_mr_callback, &mr->cb_work);
171 spin_lock_irq(&ent->lock);
173 spin_unlock_irq(&ent->lock);
174 mlx5_ib_warn(dev, "create mkey failed %d\n", err);
184 static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
186 struct mlx5_mr_cache *cache = &dev->cache;
187 struct mlx5_cache_ent *ent = &cache->ent[c];
188 struct mlx5_ib_mr *tmp_mr;
189 struct mlx5_ib_mr *mr;
193 for (i = 0; i < num; i++) {
194 spin_lock_irq(&ent->lock);
195 if (list_empty(&ent->head)) {
196 spin_unlock_irq(&ent->lock);
199 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
200 list_move(&mr->list, &del_list);
203 spin_unlock_irq(&ent->lock);
204 mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
207 list_for_each_entry_safe(mr, tmp_mr, &del_list, list) {
213 static ssize_t size_write(struct file *filp, const char __user *buf,
214 size_t count, loff_t *pos)
216 struct mlx5_cache_ent *ent = filp->private_data;
217 struct mlx5_ib_dev *dev = ent->dev;
223 count = min(count, sizeof(lbuf) - 1);
224 if (copy_from_user(lbuf, buf, count))
227 c = order2idx(dev, ent->order);
229 if (sscanf(lbuf, "%u", &var) != 1)
232 if (var < ent->limit)
235 if (var > ent->size) {
237 err = add_keys(dev, c, var - ent->size);
238 if (err && err != -EAGAIN)
241 usleep_range(3000, 5000);
243 } else if (var < ent->size) {
244 remove_keys(dev, c, ent->size - var);
250 static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
253 struct mlx5_cache_ent *ent = filp->private_data;
257 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
261 return simple_read_from_buffer(buf, count, pos, lbuf, err);
264 static const struct file_operations size_fops = {
265 .owner = THIS_MODULE,
271 static ssize_t limit_write(struct file *filp, const char __user *buf,
272 size_t count, loff_t *pos)
274 struct mlx5_cache_ent *ent = filp->private_data;
275 struct mlx5_ib_dev *dev = ent->dev;
281 count = min(count, sizeof(lbuf) - 1);
282 if (copy_from_user(lbuf, buf, count))
285 c = order2idx(dev, ent->order);
287 if (sscanf(lbuf, "%u", &var) != 1)
295 if (ent->cur < ent->limit) {
296 err = add_keys(dev, c, 2 * ent->limit - ent->cur);
304 static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
307 struct mlx5_cache_ent *ent = filp->private_data;
311 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
315 return simple_read_from_buffer(buf, count, pos, lbuf, err);
318 static const struct file_operations limit_fops = {
319 .owner = THIS_MODULE,
321 .write = limit_write,
325 static int someone_adding(struct mlx5_mr_cache *cache)
329 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
330 if (cache->ent[i].cur < cache->ent[i].limit)
337 static void __cache_work_func(struct mlx5_cache_ent *ent)
339 struct mlx5_ib_dev *dev = ent->dev;
340 struct mlx5_mr_cache *cache = &dev->cache;
341 int i = order2idx(dev, ent->order);
347 ent = &dev->cache.ent[i];
348 if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
349 err = add_keys(dev, i, 1);
350 if (ent->cur < 2 * ent->limit) {
351 if (err == -EAGAIN) {
352 mlx5_ib_dbg(dev, "returned eagain, order %d\n",
354 queue_delayed_work(cache->wq, &ent->dwork,
355 msecs_to_jiffies(3));
357 mlx5_ib_warn(dev, "command failed order %d, err %d\n",
359 queue_delayed_work(cache->wq, &ent->dwork,
360 msecs_to_jiffies(1000));
362 queue_work(cache->wq, &ent->work);
365 } else if (ent->cur > 2 * ent->limit) {
367 * The remove_keys() logic is performed as garbage collection
368 * task. Such task is intended to be run when no other active
369 * processes are running.
371 * The need_resched() will return TRUE if there are user tasks
372 * to be activated in near future.
374 * In such case, we don't execute remove_keys() and postpone
375 * the garbage collection work to try to run in next cycle,
376 * in order to free CPU resources to other tasks.
378 if (!need_resched() && !someone_adding(cache) &&
379 time_after(jiffies, cache->last_add + 300 * HZ)) {
380 remove_keys(dev, i, 1);
381 if (ent->cur > ent->limit)
382 queue_work(cache->wq, &ent->work);
384 queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
389 static void delayed_cache_work_func(struct work_struct *work)
391 struct mlx5_cache_ent *ent;
393 ent = container_of(work, struct mlx5_cache_ent, dwork.work);
394 __cache_work_func(ent);
397 static void cache_work_func(struct work_struct *work)
399 struct mlx5_cache_ent *ent;
401 ent = container_of(work, struct mlx5_cache_ent, work);
402 __cache_work_func(ent);
405 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry)
407 struct mlx5_mr_cache *cache = &dev->cache;
408 struct mlx5_cache_ent *ent;
409 struct mlx5_ib_mr *mr;
412 if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) {
413 mlx5_ib_err(dev, "cache entry %d is out of range\n", entry);
414 return ERR_PTR(-EINVAL);
417 ent = &cache->ent[entry];
419 spin_lock_irq(&ent->lock);
420 if (list_empty(&ent->head)) {
421 spin_unlock_irq(&ent->lock);
423 err = add_keys(dev, entry, 1);
424 if (err && err != -EAGAIN)
427 wait_for_completion(&ent->compl);
429 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
433 spin_unlock_irq(&ent->lock);
434 if (ent->cur < ent->limit)
435 queue_work(cache->wq, &ent->work);
441 static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
443 struct mlx5_mr_cache *cache = &dev->cache;
444 struct mlx5_ib_mr *mr = NULL;
445 struct mlx5_cache_ent *ent;
446 int last_umr_cache_entry;
450 c = order2idx(dev, order);
451 last_umr_cache_entry = order2idx(dev, mr_cache_max_order(dev));
452 if (c < 0 || c > last_umr_cache_entry) {
453 mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
457 for (i = c; i <= last_umr_cache_entry; i++) {
458 ent = &cache->ent[i];
460 mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
462 spin_lock_irq(&ent->lock);
463 if (!list_empty(&ent->head)) {
464 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
468 spin_unlock_irq(&ent->lock);
469 if (ent->cur < ent->limit)
470 queue_work(cache->wq, &ent->work);
473 spin_unlock_irq(&ent->lock);
475 queue_work(cache->wq, &ent->work);
479 cache->ent[c].miss++;
484 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
486 struct mlx5_mr_cache *cache = &dev->cache;
487 struct mlx5_cache_ent *ent;
491 if (!mr->allocated_from_cache)
494 c = order2idx(dev, mr->order);
495 WARN_ON(c < 0 || c >= MAX_MR_CACHE_ENTRIES);
497 if (mlx5_mr_cache_invalidate(mr)) {
498 mr->allocated_from_cache = false;
499 destroy_mkey(dev, mr);
500 ent = &cache->ent[c];
501 if (ent->cur < ent->limit)
502 queue_work(cache->wq, &ent->work);
506 ent = &cache->ent[c];
507 spin_lock_irq(&ent->lock);
508 list_add_tail(&mr->list, &ent->head);
510 if (ent->cur > 2 * ent->limit)
512 spin_unlock_irq(&ent->lock);
515 queue_work(cache->wq, &ent->work);
518 static void clean_keys(struct mlx5_ib_dev *dev, int c)
520 struct mlx5_mr_cache *cache = &dev->cache;
521 struct mlx5_cache_ent *ent = &cache->ent[c];
522 struct mlx5_ib_mr *tmp_mr;
523 struct mlx5_ib_mr *mr;
526 cancel_delayed_work(&ent->dwork);
528 spin_lock_irq(&ent->lock);
529 if (list_empty(&ent->head)) {
530 spin_unlock_irq(&ent->lock);
533 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
534 list_move(&mr->list, &del_list);
537 spin_unlock_irq(&ent->lock);
538 mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
541 list_for_each_entry_safe(mr, tmp_mr, &del_list, list) {
547 static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
549 if (!mlx5_debugfs_root || dev->is_rep)
552 debugfs_remove_recursive(dev->cache.root);
553 dev->cache.root = NULL;
556 static void mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
558 struct mlx5_mr_cache *cache = &dev->cache;
559 struct mlx5_cache_ent *ent;
563 if (!mlx5_debugfs_root || dev->is_rep)
566 cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root);
568 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
569 ent = &cache->ent[i];
570 sprintf(ent->name, "%d", ent->order);
571 dir = debugfs_create_dir(ent->name, cache->root);
572 debugfs_create_file("size", 0600, dir, ent, &size_fops);
573 debugfs_create_file("limit", 0600, dir, ent, &limit_fops);
574 debugfs_create_u32("cur", 0400, dir, &ent->cur);
575 debugfs_create_u32("miss", 0600, dir, &ent->miss);
579 static void delay_time_func(struct timer_list *t)
581 struct mlx5_ib_dev *dev = from_timer(dev, t, delay_timer);
586 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
588 struct mlx5_mr_cache *cache = &dev->cache;
589 struct mlx5_cache_ent *ent;
592 mutex_init(&dev->slow_path_mutex);
593 cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM);
595 mlx5_ib_warn(dev, "failed to create work queue\n");
599 mlx5_cmd_init_async_ctx(dev->mdev, &dev->async_ctx);
600 timer_setup(&dev->delay_timer, delay_time_func, 0);
601 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
602 ent = &cache->ent[i];
603 INIT_LIST_HEAD(&ent->head);
604 spin_lock_init(&ent->lock);
609 init_completion(&ent->compl);
610 INIT_WORK(&ent->work, cache_work_func);
611 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
613 if (i > MR_CACHE_LAST_STD_ENTRY) {
614 mlx5_odp_init_mr_cache_entry(ent);
618 if (ent->order > mr_cache_max_order(dev))
621 ent->page = PAGE_SHIFT;
622 ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) /
623 MLX5_IB_UMR_OCTOWORD;
624 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
625 if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) &&
627 mlx5_core_is_pf(dev->mdev))
628 ent->limit = dev->mdev->profile->mr_cache[i].limit;
631 queue_work(cache->wq, &ent->work);
634 mlx5_mr_cache_debugfs_init(dev);
639 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
646 dev->cache.stopped = 1;
647 flush_workqueue(dev->cache.wq);
649 mlx5_mr_cache_debugfs_cleanup(dev);
650 mlx5_cmd_cleanup_async_ctx(&dev->async_ctx);
652 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
655 destroy_workqueue(dev->cache.wq);
656 del_timer_sync(&dev->delay_timer);
661 static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr,
664 struct mlx5_ib_dev *dev = to_mdev(pd->device);
666 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
667 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
668 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ));
669 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
670 MLX5_SET(mkc, mkc, lr, 1);
672 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write))
673 MLX5_SET(mkc, mkc, relaxed_ordering_write,
674 !!(acc & IB_ACCESS_RELAXED_ORDERING));
675 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read))
676 MLX5_SET(mkc, mkc, relaxed_ordering_read,
677 !!(acc & IB_ACCESS_RELAXED_ORDERING));
679 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
680 MLX5_SET(mkc, mkc, qpn, 0xffffff);
681 MLX5_SET64(mkc, mkc, start_addr, start_addr);
684 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
686 struct mlx5_ib_dev *dev = to_mdev(pd->device);
687 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
688 struct mlx5_core_dev *mdev = dev->mdev;
689 struct mlx5_ib_mr *mr;
694 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
696 return ERR_PTR(-ENOMEM);
698 in = kzalloc(inlen, GFP_KERNEL);
704 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
706 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
707 MLX5_SET(mkc, mkc, length64, 1);
708 set_mkc_access_pd_addr_fields(mkc, acc, 0, pd);
710 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen);
715 mr->mmkey.type = MLX5_MKEY_MR;
716 mr->ibmr.lkey = mr->mmkey.key;
717 mr->ibmr.rkey = mr->mmkey.key;
731 static int get_octo_len(u64 addr, u64 len, int page_shift)
733 u64 page_size = 1ULL << page_shift;
737 offset = addr & (page_size - 1);
738 npages = ALIGN(len + offset, page_size) >> page_shift;
739 return (npages + 1) / 2;
742 static int mr_cache_max_order(struct mlx5_ib_dev *dev)
744 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
745 return MR_CACHE_LAST_STD_ENTRY + 2;
746 return MLX5_MAX_UMR_SHIFT;
749 static int mr_umem_get(struct mlx5_ib_dev *dev, u64 start, u64 length,
750 int access_flags, struct ib_umem **umem, int *npages,
751 int *page_shift, int *ncont, int *order)
757 if (access_flags & IB_ACCESS_ON_DEMAND) {
758 struct ib_umem_odp *odp;
760 odp = ib_umem_odp_get(&dev->ib_dev, start, length, access_flags,
763 mlx5_ib_dbg(dev, "umem get failed (%ld)\n",
770 *page_shift = odp->page_shift;
771 *ncont = ib_umem_odp_num_pages(odp);
772 *npages = *ncont << (*page_shift - PAGE_SHIFT);
774 *order = ilog2(roundup_pow_of_two(*ncont));
776 u = ib_umem_get(&dev->ib_dev, start, length, access_flags);
778 mlx5_ib_dbg(dev, "umem get failed (%ld)\n", PTR_ERR(u));
782 mlx5_ib_cont_pages(u, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages,
783 page_shift, ncont, order);
787 mlx5_ib_warn(dev, "avoid zero region\n");
794 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
795 *npages, *ncont, *order, *page_shift);
800 static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc)
802 struct mlx5_ib_umr_context *context =
803 container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe);
805 context->status = wc->status;
806 complete(&context->done);
809 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
811 context->cqe.done = mlx5_ib_umr_done;
812 context->status = -1;
813 init_completion(&context->done);
816 static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev,
817 struct mlx5_umr_wr *umrwr)
819 struct umr_common *umrc = &dev->umrc;
820 const struct ib_send_wr *bad;
822 struct mlx5_ib_umr_context umr_context;
824 mlx5_ib_init_umr_context(&umr_context);
825 umrwr->wr.wr_cqe = &umr_context.cqe;
828 err = ib_post_send(umrc->qp, &umrwr->wr, &bad);
830 mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err);
832 wait_for_completion(&umr_context.done);
833 if (umr_context.status != IB_WC_SUCCESS) {
834 mlx5_ib_warn(dev, "reg umr failed (%u)\n",
843 static struct mlx5_ib_mr *alloc_mr_from_cache(
844 struct ib_pd *pd, struct ib_umem *umem,
845 u64 virt_addr, u64 len, int npages,
846 int page_shift, int order, int access_flags)
848 struct mlx5_ib_dev *dev = to_mdev(pd->device);
849 struct mlx5_ib_mr *mr;
853 for (i = 0; i < 1; i++) {
854 mr = alloc_cached_mr(dev, order);
858 err = add_keys(dev, order2idx(dev, order), 1);
859 if (err && err != -EAGAIN) {
860 mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
866 return ERR_PTR(-EAGAIN);
870 mr->access_flags = access_flags;
871 mr->desc_size = sizeof(struct mlx5_mtt);
872 mr->mmkey.iova = virt_addr;
873 mr->mmkey.size = len;
874 mr->mmkey.pd = to_mpd(pd)->pdn;
879 #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \
880 MLX5_UMR_MTT_ALIGNMENT)
881 #define MLX5_SPARE_UMR_CHUNK 0x10000
883 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
884 int page_shift, int flags)
886 struct mlx5_ib_dev *dev = mr->dev;
887 struct device *ddev = dev->ib_dev.dev.parent;
891 struct mlx5_umr_wr wr;
894 int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT)
895 ? sizeof(struct mlx5_klm)
896 : sizeof(struct mlx5_mtt);
897 const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size;
898 const int page_mask = page_align - 1;
899 size_t pages_mapped = 0;
900 size_t pages_to_map = 0;
901 size_t pages_iter = 0;
902 size_t size_to_map = 0;
904 bool use_emergency_page = false;
906 if ((flags & MLX5_IB_UPD_XLT_INDIRECT) &&
907 !umr_can_use_indirect_mkey(dev))
910 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
911 * so we need to align the offset and length accordingly
913 if (idx & page_mask) {
914 npages += idx & page_mask;
918 gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL;
919 gfp |= __GFP_ZERO | __GFP_NOWARN;
921 pages_to_map = ALIGN(npages, page_align);
922 size = desc_size * pages_to_map;
923 size = min_t(int, size, MLX5_MAX_UMR_CHUNK);
925 xlt = (void *)__get_free_pages(gfp, get_order(size));
926 if (!xlt && size > MLX5_SPARE_UMR_CHUNK) {
927 mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n",
928 size, get_order(size), MLX5_SPARE_UMR_CHUNK);
930 size = MLX5_SPARE_UMR_CHUNK;
931 xlt = (void *)__get_free_pages(gfp, get_order(size));
935 mlx5_ib_warn(dev, "Using XLT emergency buffer\n");
936 xlt = (void *)mlx5_ib_get_xlt_emergency_page();
938 memset(xlt, 0, size);
939 use_emergency_page = true;
941 pages_iter = size / desc_size;
942 dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE);
943 if (dma_mapping_error(ddev, dma)) {
944 mlx5_ib_err(dev, "unable to map DMA during XLT update.\n");
949 if (mr->umem->is_odp) {
950 if (!(flags & MLX5_IB_UPD_XLT_INDIRECT)) {
951 struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
952 size_t max_pages = ib_umem_odp_num_pages(odp) - idx;
954 pages_to_map = min_t(size_t, pages_to_map, max_pages);
959 sg.lkey = dev->umrc.pd->local_dma_lkey;
961 memset(&wr, 0, sizeof(wr));
962 wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT;
963 if (!(flags & MLX5_IB_UPD_XLT_ENABLE))
964 wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE;
967 wr.wr.opcode = MLX5_IB_WR_UMR;
970 wr.mkey = mr->mmkey.key;
971 wr.length = mr->mmkey.size;
972 wr.virt_addr = mr->mmkey.iova;
973 wr.access_flags = mr->access_flags;
974 wr.page_shift = page_shift;
976 for (pages_mapped = 0;
977 pages_mapped < pages_to_map && !err;
978 pages_mapped += pages_iter, idx += pages_iter) {
979 npages = min_t(int, pages_iter, pages_to_map - pages_mapped);
980 size_to_map = npages * desc_size;
981 dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE);
982 if (mr->umem->is_odp) {
983 mlx5_odp_populate_xlt(xlt, idx, npages, mr, flags);
985 __mlx5_ib_populate_pas(dev, mr->umem, page_shift, idx,
987 MLX5_IB_MTT_PRESENT);
988 /* Clear padding after the pages
989 * brought from the umem.
991 memset(xlt + size_to_map, 0, size - size_to_map);
993 dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE);
995 sg.length = ALIGN(size_to_map, MLX5_UMR_MTT_ALIGNMENT);
997 if (pages_mapped + pages_iter >= pages_to_map) {
998 if (flags & MLX5_IB_UPD_XLT_ENABLE)
1000 MLX5_IB_SEND_UMR_ENABLE_MR |
1001 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS |
1002 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
1003 if (flags & MLX5_IB_UPD_XLT_PD ||
1004 flags & MLX5_IB_UPD_XLT_ACCESS)
1006 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1007 if (flags & MLX5_IB_UPD_XLT_ADDR)
1009 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
1012 wr.offset = idx * desc_size;
1013 wr.xlt_size = sg.length;
1015 err = mlx5_ib_post_send_wait(dev, &wr);
1017 dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE);
1020 if (use_emergency_page)
1021 mlx5_ib_put_xlt_emergency_page();
1023 free_pages((unsigned long)xlt, get_order(size));
1029 * If ibmr is NULL it will be allocated by reg_create.
1030 * Else, the given ibmr will be used.
1032 static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd,
1033 u64 virt_addr, u64 length,
1034 struct ib_umem *umem, int npages,
1035 int page_shift, int access_flags,
1038 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1039 struct mlx5_ib_mr *mr;
1045 bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg));
1047 mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL);
1049 return ERR_PTR(-ENOMEM);
1052 mr->access_flags = access_flags;
1054 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1056 inlen += sizeof(*pas) * roundup(npages, 2);
1057 in = kvzalloc(inlen, GFP_KERNEL);
1062 pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
1063 if (populate && !(access_flags & IB_ACCESS_ON_DEMAND))
1064 mlx5_ib_populate_pas(dev, umem, page_shift, pas,
1065 pg_cap ? MLX5_IB_MTT_PRESENT : 0);
1067 /* The pg_access bit allows setting the access flags
1068 * in the page list submitted with the command. */
1069 MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap));
1071 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1072 MLX5_SET(mkc, mkc, free, !populate);
1073 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
1074 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write))
1075 MLX5_SET(mkc, mkc, relaxed_ordering_write,
1076 !!(access_flags & IB_ACCESS_RELAXED_ORDERING));
1077 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read))
1078 MLX5_SET(mkc, mkc, relaxed_ordering_read,
1079 !!(access_flags & IB_ACCESS_RELAXED_ORDERING));
1080 MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
1081 MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
1082 MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
1083 MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
1084 MLX5_SET(mkc, mkc, lr, 1);
1085 MLX5_SET(mkc, mkc, umr_en, 1);
1087 MLX5_SET64(mkc, mkc, start_addr, virt_addr);
1088 MLX5_SET64(mkc, mkc, len, length);
1089 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1090 MLX5_SET(mkc, mkc, bsf_octword_size, 0);
1091 MLX5_SET(mkc, mkc, translations_octword_size,
1092 get_octo_len(virt_addr, length, page_shift));
1093 MLX5_SET(mkc, mkc, log_page_size, page_shift);
1094 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1096 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
1097 get_octo_len(virt_addr, length, page_shift));
1100 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1102 mlx5_ib_warn(dev, "create mkey failed\n");
1105 mr->mmkey.type = MLX5_MKEY_MR;
1106 mr->desc_size = sizeof(struct mlx5_mtt);
1110 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key);
1121 return ERR_PTR(err);
1124 static void set_mr_fields(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
1125 int npages, u64 length, int access_flags)
1127 mr->npages = npages;
1128 atomic_add(npages, &dev->mdev->priv.reg_pages);
1129 mr->ibmr.lkey = mr->mmkey.key;
1130 mr->ibmr.rkey = mr->mmkey.key;
1131 mr->ibmr.length = length;
1132 mr->access_flags = access_flags;
1135 static struct ib_mr *mlx5_ib_get_dm_mr(struct ib_pd *pd, u64 start_addr,
1136 u64 length, int acc, int mode)
1138 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1139 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1140 struct mlx5_core_dev *mdev = dev->mdev;
1141 struct mlx5_ib_mr *mr;
1146 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1148 return ERR_PTR(-ENOMEM);
1150 in = kzalloc(inlen, GFP_KERNEL);
1156 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1158 MLX5_SET(mkc, mkc, access_mode_1_0, mode & 0x3);
1159 MLX5_SET(mkc, mkc, access_mode_4_2, (mode >> 2) & 0x7);
1160 MLX5_SET64(mkc, mkc, len, length);
1161 set_mkc_access_pd_addr_fields(mkc, acc, start_addr, pd);
1163 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen);
1170 set_mr_fields(dev, mr, 0, length, acc);
1180 return ERR_PTR(err);
1183 int mlx5_ib_advise_mr(struct ib_pd *pd,
1184 enum ib_uverbs_advise_mr_advice advice,
1186 struct ib_sge *sg_list,
1188 struct uverbs_attr_bundle *attrs)
1190 if (advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH &&
1191 advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE)
1194 return mlx5_ib_advise_mr_prefetch(pd, advice, flags,
1198 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1199 struct ib_dm_mr_attr *attr,
1200 struct uverbs_attr_bundle *attrs)
1202 struct mlx5_ib_dm *mdm = to_mdm(dm);
1203 struct mlx5_core_dev *dev = to_mdev(dm->device)->mdev;
1204 u64 start_addr = mdm->dev_addr + attr->offset;
1207 switch (mdm->type) {
1208 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
1209 if (attr->access_flags & ~MLX5_IB_DM_MEMIC_ALLOWED_ACCESS)
1210 return ERR_PTR(-EINVAL);
1212 mode = MLX5_MKC_ACCESS_MODE_MEMIC;
1213 start_addr -= pci_resource_start(dev->pdev, 0);
1215 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
1216 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
1217 if (attr->access_flags & ~MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS)
1218 return ERR_PTR(-EINVAL);
1220 mode = MLX5_MKC_ACCESS_MODE_SW_ICM;
1223 return ERR_PTR(-EINVAL);
1226 return mlx5_ib_get_dm_mr(pd, start_addr, attr->length,
1227 attr->access_flags, mode);
1230 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1231 u64 virt_addr, int access_flags,
1232 struct ib_udata *udata)
1234 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1235 struct mlx5_ib_mr *mr = NULL;
1237 struct ib_umem *umem;
1244 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM))
1245 return ERR_PTR(-EOPNOTSUPP);
1247 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1248 start, virt_addr, length, access_flags);
1250 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && !start &&
1251 length == U64_MAX) {
1252 if (virt_addr != start)
1253 return ERR_PTR(-EINVAL);
1254 if (!(access_flags & IB_ACCESS_ON_DEMAND) ||
1255 !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1256 return ERR_PTR(-EINVAL);
1258 mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), udata, access_flags);
1260 return ERR_CAST(mr);
1264 err = mr_umem_get(dev, start, length, access_flags, &umem,
1265 &npages, &page_shift, &ncont, &order);
1268 return ERR_PTR(err);
1270 use_umr = mlx5_ib_can_use_umr(dev, true, access_flags);
1272 if (order <= mr_cache_max_order(dev) && use_umr) {
1273 mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont,
1274 page_shift, order, access_flags);
1275 if (PTR_ERR(mr) == -EAGAIN) {
1276 mlx5_ib_dbg(dev, "cache empty for order %d\n", order);
1279 } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) {
1280 if (access_flags & IB_ACCESS_ON_DEMAND) {
1282 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n");
1289 mutex_lock(&dev->slow_path_mutex);
1290 mr = reg_create(NULL, pd, virt_addr, length, umem, ncont,
1291 page_shift, access_flags, !use_umr);
1292 mutex_unlock(&dev->slow_path_mutex);
1300 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key);
1303 set_mr_fields(dev, mr, npages, length, access_flags);
1306 int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE;
1308 if (access_flags & IB_ACCESS_ON_DEMAND)
1309 update_xlt_flags |= MLX5_IB_UPD_XLT_ZAP;
1311 err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift,
1316 return ERR_PTR(err);
1320 if (is_odp_mr(mr)) {
1321 to_ib_umem_odp(mr->umem)->private = mr;
1322 atomic_set(&mr->num_deferred_work, 0);
1323 err = xa_err(xa_store(&dev->odp_mkeys,
1324 mlx5_base_mkey(mr->mmkey.key), &mr->mmkey,
1328 return ERR_PTR(err);
1334 ib_umem_release(umem);
1335 return ERR_PTR(err);
1339 * mlx5_mr_cache_invalidate - Fence all DMA on the MR
1340 * @mr: The MR to fence
1342 * Upon return the NIC will not be doing any DMA to the pages under the MR,
1343 * and any DMA inprogress will be completed. Failure of this function
1344 * indicates the HW has failed catastrophically.
1346 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr)
1348 struct mlx5_umr_wr umrwr = {};
1350 if (mr->dev->mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
1353 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR |
1354 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1355 umrwr.wr.opcode = MLX5_IB_WR_UMR;
1356 umrwr.pd = mr->dev->umrc.pd;
1357 umrwr.mkey = mr->mmkey.key;
1358 umrwr.ignore_free_state = 1;
1360 return mlx5_ib_post_send_wait(mr->dev, &umrwr);
1363 static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1364 int access_flags, int flags)
1366 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1367 struct mlx5_umr_wr umrwr = {};
1370 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE;
1372 umrwr.wr.opcode = MLX5_IB_WR_UMR;
1373 umrwr.mkey = mr->mmkey.key;
1375 if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) {
1377 umrwr.access_flags = access_flags;
1378 umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1381 err = mlx5_ib_post_send_wait(dev, &umrwr);
1386 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1387 u64 length, u64 virt_addr, int new_access_flags,
1388 struct ib_pd *new_pd, struct ib_udata *udata)
1390 struct mlx5_ib_dev *dev = to_mdev(ib_mr->device);
1391 struct mlx5_ib_mr *mr = to_mmr(ib_mr);
1392 struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd;
1393 int access_flags = flags & IB_MR_REREG_ACCESS ?
1404 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1405 start, virt_addr, length, access_flags);
1407 atomic_sub(mr->npages, &dev->mdev->priv.reg_pages);
1415 if (flags & IB_MR_REREG_TRANS) {
1419 addr = mr->umem->address;
1420 len = mr->umem->length;
1423 if (flags != IB_MR_REREG_PD) {
1425 * Replace umem. This needs to be done whether or not UMR is
1428 flags |= IB_MR_REREG_TRANS;
1429 ib_umem_release(mr->umem);
1431 err = mr_umem_get(dev, addr, len, access_flags, &mr->umem,
1432 &npages, &page_shift, &ncont, &order);
1437 if (!mlx5_ib_can_use_umr(dev, true, access_flags) ||
1438 (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len))) {
1440 * UMR can't be used - MKey needs to be replaced.
1442 if (mr->allocated_from_cache)
1443 err = mlx5_mr_cache_invalidate(mr);
1445 err = destroy_mkey(dev, mr);
1449 mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont,
1450 page_shift, access_flags, true);
1458 mr->allocated_from_cache = false;
1464 mr->access_flags = access_flags;
1465 mr->mmkey.iova = addr;
1466 mr->mmkey.size = len;
1467 mr->mmkey.pd = to_mpd(pd)->pdn;
1469 if (flags & IB_MR_REREG_TRANS) {
1470 upd_flags = MLX5_IB_UPD_XLT_ADDR;
1471 if (flags & IB_MR_REREG_PD)
1472 upd_flags |= MLX5_IB_UPD_XLT_PD;
1473 if (flags & IB_MR_REREG_ACCESS)
1474 upd_flags |= MLX5_IB_UPD_XLT_ACCESS;
1475 err = mlx5_ib_update_xlt(mr, 0, npages, page_shift,
1478 err = rereg_umr(pd, mr, access_flags, flags);
1485 set_mr_fields(dev, mr, npages, len, access_flags);
1490 ib_umem_release(mr->umem);
1498 mlx5_alloc_priv_descs(struct ib_device *device,
1499 struct mlx5_ib_mr *mr,
1503 int size = ndescs * desc_size;
1507 add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0);
1509 mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL);
1510 if (!mr->descs_alloc)
1513 mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN);
1515 mr->desc_map = dma_map_single(device->dev.parent, mr->descs,
1516 size, DMA_TO_DEVICE);
1517 if (dma_mapping_error(device->dev.parent, mr->desc_map)) {
1524 kfree(mr->descs_alloc);
1530 mlx5_free_priv_descs(struct mlx5_ib_mr *mr)
1533 struct ib_device *device = mr->ibmr.device;
1534 int size = mr->max_descs * mr->desc_size;
1536 dma_unmap_single(device->dev.parent, mr->desc_map,
1537 size, DMA_TO_DEVICE);
1538 kfree(mr->descs_alloc);
1543 static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1545 int allocated_from_cache = mr->allocated_from_cache;
1548 if (mlx5_core_destroy_psv(dev->mdev,
1549 mr->sig->psv_memory.psv_idx))
1550 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1551 mr->sig->psv_memory.psv_idx);
1552 if (mlx5_core_destroy_psv(dev->mdev,
1553 mr->sig->psv_wire.psv_idx))
1554 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1555 mr->sig->psv_wire.psv_idx);
1556 xa_erase(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key));
1561 if (!allocated_from_cache) {
1562 destroy_mkey(dev, mr);
1563 mlx5_free_priv_descs(mr);
1567 static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1569 int npages = mr->npages;
1570 struct ib_umem *umem = mr->umem;
1574 mlx5_ib_fence_odp_mr(mr);
1578 if (mr->allocated_from_cache)
1579 mlx5_mr_cache_free(dev, mr);
1583 ib_umem_release(umem);
1584 atomic_sub(npages, &dev->mdev->priv.reg_pages);
1588 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)
1590 struct mlx5_ib_mr *mmr = to_mmr(ibmr);
1592 if (ibmr->type == IB_MR_TYPE_INTEGRITY) {
1593 dereg_mr(to_mdev(mmr->mtt_mr->ibmr.device), mmr->mtt_mr);
1594 dereg_mr(to_mdev(mmr->klm_mr->ibmr.device), mmr->klm_mr);
1597 if (is_odp_mr(mmr) && to_ib_umem_odp(mmr->umem)->is_implicit_odp) {
1598 mlx5_ib_free_implicit_mr(mmr);
1602 dereg_mr(to_mdev(ibmr->device), mmr);
1607 static void mlx5_set_umr_free_mkey(struct ib_pd *pd, u32 *in, int ndescs,
1608 int access_mode, int page_shift)
1612 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1614 MLX5_SET(mkc, mkc, free, 1);
1615 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1616 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1617 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1618 MLX5_SET(mkc, mkc, access_mode_1_0, access_mode & 0x3);
1619 MLX5_SET(mkc, mkc, access_mode_4_2, (access_mode >> 2) & 0x7);
1620 MLX5_SET(mkc, mkc, umr_en, 1);
1621 MLX5_SET(mkc, mkc, log_page_size, page_shift);
1624 static int _mlx5_alloc_mkey_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1625 int ndescs, int desc_size, int page_shift,
1626 int access_mode, u32 *in, int inlen)
1628 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1631 mr->access_mode = access_mode;
1632 mr->desc_size = desc_size;
1633 mr->max_descs = ndescs;
1635 err = mlx5_alloc_priv_descs(pd->device, mr, ndescs, desc_size);
1639 mlx5_set_umr_free_mkey(pd, in, ndescs, access_mode, page_shift);
1641 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1643 goto err_free_descs;
1645 mr->mmkey.type = MLX5_MKEY_MR;
1646 mr->ibmr.lkey = mr->mmkey.key;
1647 mr->ibmr.rkey = mr->mmkey.key;
1652 mlx5_free_priv_descs(mr);
1656 static struct mlx5_ib_mr *mlx5_ib_alloc_pi_mr(struct ib_pd *pd,
1657 u32 max_num_sg, u32 max_num_meta_sg,
1658 int desc_size, int access_mode)
1660 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1661 int ndescs = ALIGN(max_num_sg + max_num_meta_sg, 4);
1663 struct mlx5_ib_mr *mr;
1667 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1669 return ERR_PTR(-ENOMEM);
1672 mr->ibmr.device = pd->device;
1674 in = kzalloc(inlen, GFP_KERNEL);
1680 if (access_mode == MLX5_MKC_ACCESS_MODE_MTT)
1681 page_shift = PAGE_SHIFT;
1683 err = _mlx5_alloc_mkey_descs(pd, mr, ndescs, desc_size, page_shift,
1684 access_mode, in, inlen);
1697 return ERR_PTR(err);
1700 static int mlx5_alloc_mem_reg_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1701 int ndescs, u32 *in, int inlen)
1703 return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_mtt),
1704 PAGE_SHIFT, MLX5_MKC_ACCESS_MODE_MTT, in,
1708 static int mlx5_alloc_sg_gaps_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1709 int ndescs, u32 *in, int inlen)
1711 return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_klm),
1712 0, MLX5_MKC_ACCESS_MODE_KLMS, in, inlen);
1715 static int mlx5_alloc_integrity_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1716 int max_num_sg, int max_num_meta_sg,
1719 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1724 mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL);
1728 /* create mem & wire PSVs */
1729 err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, 2, psv_index);
1733 mr->sig->psv_memory.psv_idx = psv_index[0];
1734 mr->sig->psv_wire.psv_idx = psv_index[1];
1736 mr->sig->sig_status_checked = true;
1737 mr->sig->sig_err_exists = false;
1738 /* Next UMR, Arm SIGERR */
1739 ++mr->sig->sigerr_count;
1740 mr->klm_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg,
1741 sizeof(struct mlx5_klm),
1742 MLX5_MKC_ACCESS_MODE_KLMS);
1743 if (IS_ERR(mr->klm_mr)) {
1744 err = PTR_ERR(mr->klm_mr);
1745 goto err_destroy_psv;
1747 mr->mtt_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg,
1748 sizeof(struct mlx5_mtt),
1749 MLX5_MKC_ACCESS_MODE_MTT);
1750 if (IS_ERR(mr->mtt_mr)) {
1751 err = PTR_ERR(mr->mtt_mr);
1752 goto err_free_klm_mr;
1755 /* Set bsf descriptors for mkey */
1756 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1757 MLX5_SET(mkc, mkc, bsf_en, 1);
1758 MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE);
1760 err = _mlx5_alloc_mkey_descs(pd, mr, 4, sizeof(struct mlx5_klm), 0,
1761 MLX5_MKC_ACCESS_MODE_KLMS, in, inlen);
1763 goto err_free_mtt_mr;
1765 err = xa_err(xa_store(&dev->sig_mrs, mlx5_base_mkey(mr->mmkey.key),
1766 mr->sig, GFP_KERNEL));
1768 goto err_free_descs;
1772 destroy_mkey(dev, mr);
1773 mlx5_free_priv_descs(mr);
1775 dereg_mr(to_mdev(mr->mtt_mr->ibmr.device), mr->mtt_mr);
1778 dereg_mr(to_mdev(mr->klm_mr->ibmr.device), mr->klm_mr);
1781 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_memory.psv_idx))
1782 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1783 mr->sig->psv_memory.psv_idx);
1784 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_wire.psv_idx))
1785 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1786 mr->sig->psv_wire.psv_idx);
1793 static struct ib_mr *__mlx5_ib_alloc_mr(struct ib_pd *pd,
1794 enum ib_mr_type mr_type, u32 max_num_sg,
1795 u32 max_num_meta_sg)
1797 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1798 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1799 int ndescs = ALIGN(max_num_sg, 4);
1800 struct mlx5_ib_mr *mr;
1804 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1806 return ERR_PTR(-ENOMEM);
1808 in = kzalloc(inlen, GFP_KERNEL);
1814 mr->ibmr.device = pd->device;
1818 case IB_MR_TYPE_MEM_REG:
1819 err = mlx5_alloc_mem_reg_descs(pd, mr, ndescs, in, inlen);
1821 case IB_MR_TYPE_SG_GAPS:
1822 err = mlx5_alloc_sg_gaps_descs(pd, mr, ndescs, in, inlen);
1824 case IB_MR_TYPE_INTEGRITY:
1825 err = mlx5_alloc_integrity_descs(pd, mr, max_num_sg,
1826 max_num_meta_sg, in, inlen);
1829 mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type);
1844 return ERR_PTR(err);
1847 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1848 u32 max_num_sg, struct ib_udata *udata)
1850 return __mlx5_ib_alloc_mr(pd, mr_type, max_num_sg, 0);
1853 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1854 u32 max_num_sg, u32 max_num_meta_sg)
1856 return __mlx5_ib_alloc_mr(pd, IB_MR_TYPE_INTEGRITY, max_num_sg,
1860 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1861 struct ib_udata *udata)
1863 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1864 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1865 struct mlx5_ib_mw *mw = NULL;
1870 struct mlx5_ib_alloc_mw req = {};
1873 __u32 response_length;
1876 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1878 return ERR_PTR(err);
1880 if (req.comp_mask || req.reserved1 || req.reserved2)
1881 return ERR_PTR(-EOPNOTSUPP);
1883 if (udata->inlen > sizeof(req) &&
1884 !ib_is_udata_cleared(udata, sizeof(req),
1885 udata->inlen - sizeof(req)))
1886 return ERR_PTR(-EOPNOTSUPP);
1888 ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4);
1890 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
1891 in = kzalloc(inlen, GFP_KERNEL);
1897 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1899 MLX5_SET(mkc, mkc, free, 1);
1900 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1901 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1902 MLX5_SET(mkc, mkc, umr_en, 1);
1903 MLX5_SET(mkc, mkc, lr, 1);
1904 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
1905 MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2)));
1906 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1908 err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen);
1912 mw->mmkey.type = MLX5_MKEY_MW;
1913 mw->ibmw.rkey = mw->mmkey.key;
1914 mw->ndescs = ndescs;
1916 resp.response_length = min(offsetof(typeof(resp), response_length) +
1917 sizeof(resp.response_length), udata->outlen);
1918 if (resp.response_length) {
1919 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1921 mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey);
1926 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1927 err = xa_err(xa_store(&dev->odp_mkeys,
1928 mlx5_base_mkey(mw->mmkey.key), &mw->mmkey,
1938 mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey);
1942 return ERR_PTR(err);
1945 int mlx5_ib_dealloc_mw(struct ib_mw *mw)
1947 struct mlx5_ib_dev *dev = to_mdev(mw->device);
1948 struct mlx5_ib_mw *mmw = to_mmw(mw);
1951 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1952 xa_erase(&dev->odp_mkeys, mlx5_base_mkey(mmw->mmkey.key));
1954 * pagefault_single_data_segment() may be accessing mmw under
1955 * SRCU if the user bound an ODP MR to this MW.
1957 synchronize_srcu(&dev->odp_srcu);
1960 err = mlx5_core_destroy_mkey(dev->mdev, &mmw->mmkey);
1967 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1968 struct ib_mr_status *mr_status)
1970 struct mlx5_ib_mr *mmr = to_mmr(ibmr);
1973 if (check_mask & ~IB_MR_CHECK_SIG_STATUS) {
1974 pr_err("Invalid status check mask\n");
1979 mr_status->fail_status = 0;
1980 if (check_mask & IB_MR_CHECK_SIG_STATUS) {
1983 pr_err("signature status check requested on a non-signature enabled MR\n");
1987 mmr->sig->sig_status_checked = true;
1988 if (!mmr->sig->sig_err_exists)
1991 if (ibmr->lkey == mmr->sig->err_item.key)
1992 memcpy(&mr_status->sig_err, &mmr->sig->err_item,
1993 sizeof(mr_status->sig_err));
1995 mr_status->sig_err.err_type = IB_SIG_BAD_GUARD;
1996 mr_status->sig_err.sig_err_offset = 0;
1997 mr_status->sig_err.key = mmr->sig->err_item.key;
2000 mmr->sig->sig_err_exists = false;
2001 mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS;
2009 mlx5_ib_map_pa_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2010 int data_sg_nents, unsigned int *data_sg_offset,
2011 struct scatterlist *meta_sg, int meta_sg_nents,
2012 unsigned int *meta_sg_offset)
2014 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2015 unsigned int sg_offset = 0;
2018 mr->meta_length = 0;
2019 if (data_sg_nents == 1) {
2023 sg_offset = *data_sg_offset;
2024 mr->data_length = sg_dma_len(data_sg) - sg_offset;
2025 mr->data_iova = sg_dma_address(data_sg) + sg_offset;
2026 if (meta_sg_nents == 1) {
2028 mr->meta_ndescs = 1;
2030 sg_offset = *meta_sg_offset;
2033 mr->meta_length = sg_dma_len(meta_sg) - sg_offset;
2034 mr->pi_iova = sg_dma_address(meta_sg) + sg_offset;
2036 ibmr->length = mr->data_length + mr->meta_length;
2043 mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr,
2044 struct scatterlist *sgl,
2045 unsigned short sg_nents,
2046 unsigned int *sg_offset_p,
2047 struct scatterlist *meta_sgl,
2048 unsigned short meta_sg_nents,
2049 unsigned int *meta_sg_offset_p)
2051 struct scatterlist *sg = sgl;
2052 struct mlx5_klm *klms = mr->descs;
2053 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0;
2054 u32 lkey = mr->ibmr.pd->local_dma_lkey;
2057 mr->ibmr.iova = sg_dma_address(sg) + sg_offset;
2058 mr->ibmr.length = 0;
2060 for_each_sg(sgl, sg, sg_nents, i) {
2061 if (unlikely(i >= mr->max_descs))
2063 klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset);
2064 klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset);
2065 klms[i].key = cpu_to_be32(lkey);
2066 mr->ibmr.length += sg_dma_len(sg) - sg_offset;
2072 *sg_offset_p = sg_offset;
2075 mr->data_length = mr->ibmr.length;
2077 if (meta_sg_nents) {
2079 sg_offset = meta_sg_offset_p ? *meta_sg_offset_p : 0;
2080 for_each_sg(meta_sgl, sg, meta_sg_nents, j) {
2081 if (unlikely(i + j >= mr->max_descs))
2083 klms[i + j].va = cpu_to_be64(sg_dma_address(sg) +
2085 klms[i + j].bcount = cpu_to_be32(sg_dma_len(sg) -
2087 klms[i + j].key = cpu_to_be32(lkey);
2088 mr->ibmr.length += sg_dma_len(sg) - sg_offset;
2092 if (meta_sg_offset_p)
2093 *meta_sg_offset_p = sg_offset;
2095 mr->meta_ndescs = j;
2096 mr->meta_length = mr->ibmr.length - mr->data_length;
2102 static int mlx5_set_page(struct ib_mr *ibmr, u64 addr)
2104 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2107 if (unlikely(mr->ndescs == mr->max_descs))
2111 descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
2116 static int mlx5_set_page_pi(struct ib_mr *ibmr, u64 addr)
2118 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2121 if (unlikely(mr->ndescs + mr->meta_ndescs == mr->max_descs))
2125 descs[mr->ndescs + mr->meta_ndescs++] =
2126 cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
2132 mlx5_ib_map_mtt_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2133 int data_sg_nents, unsigned int *data_sg_offset,
2134 struct scatterlist *meta_sg, int meta_sg_nents,
2135 unsigned int *meta_sg_offset)
2137 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2138 struct mlx5_ib_mr *pi_mr = mr->mtt_mr;
2142 pi_mr->meta_ndescs = 0;
2143 pi_mr->meta_length = 0;
2145 ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map,
2146 pi_mr->desc_size * pi_mr->max_descs,
2149 pi_mr->ibmr.page_size = ibmr->page_size;
2150 n = ib_sg_to_pages(&pi_mr->ibmr, data_sg, data_sg_nents, data_sg_offset,
2152 if (n != data_sg_nents)
2155 pi_mr->data_iova = pi_mr->ibmr.iova;
2156 pi_mr->data_length = pi_mr->ibmr.length;
2157 pi_mr->ibmr.length = pi_mr->data_length;
2158 ibmr->length = pi_mr->data_length;
2160 if (meta_sg_nents) {
2161 u64 page_mask = ~((u64)ibmr->page_size - 1);
2162 u64 iova = pi_mr->data_iova;
2164 n += ib_sg_to_pages(&pi_mr->ibmr, meta_sg, meta_sg_nents,
2165 meta_sg_offset, mlx5_set_page_pi);
2167 pi_mr->meta_length = pi_mr->ibmr.length;
2169 * PI address for the HW is the offset of the metadata address
2170 * relative to the first data page address.
2171 * It equals to first data page address + size of data pages +
2172 * metadata offset at the first metadata page
2174 pi_mr->pi_iova = (iova & page_mask) +
2175 pi_mr->ndescs * ibmr->page_size +
2176 (pi_mr->ibmr.iova & ~page_mask);
2178 * In order to use one MTT MR for data and metadata, we register
2179 * also the gaps between the end of the data and the start of
2180 * the metadata (the sig MR will verify that the HW will access
2181 * to right addresses). This mapping is safe because we use
2182 * internal mkey for the registration.
2184 pi_mr->ibmr.length = pi_mr->pi_iova + pi_mr->meta_length - iova;
2185 pi_mr->ibmr.iova = iova;
2186 ibmr->length += pi_mr->meta_length;
2189 ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map,
2190 pi_mr->desc_size * pi_mr->max_descs,
2197 mlx5_ib_map_klm_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2198 int data_sg_nents, unsigned int *data_sg_offset,
2199 struct scatterlist *meta_sg, int meta_sg_nents,
2200 unsigned int *meta_sg_offset)
2202 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2203 struct mlx5_ib_mr *pi_mr = mr->klm_mr;
2207 pi_mr->meta_ndescs = 0;
2208 pi_mr->meta_length = 0;
2210 ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map,
2211 pi_mr->desc_size * pi_mr->max_descs,
2214 n = mlx5_ib_sg_to_klms(pi_mr, data_sg, data_sg_nents, data_sg_offset,
2215 meta_sg, meta_sg_nents, meta_sg_offset);
2217 ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map,
2218 pi_mr->desc_size * pi_mr->max_descs,
2221 /* This is zero-based memory region */
2222 pi_mr->data_iova = 0;
2223 pi_mr->ibmr.iova = 0;
2224 pi_mr->pi_iova = pi_mr->data_length;
2225 ibmr->length = pi_mr->ibmr.length;
2230 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2231 int data_sg_nents, unsigned int *data_sg_offset,
2232 struct scatterlist *meta_sg, int meta_sg_nents,
2233 unsigned int *meta_sg_offset)
2235 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2236 struct mlx5_ib_mr *pi_mr = NULL;
2239 WARN_ON(ibmr->type != IB_MR_TYPE_INTEGRITY);
2242 mr->data_length = 0;
2244 mr->meta_ndescs = 0;
2247 * As a performance optimization, if possible, there is no need to
2248 * perform UMR operation to register the data/metadata buffers.
2249 * First try to map the sg lists to PA descriptors with local_dma_lkey.
2250 * Fallback to UMR only in case of a failure.
2252 n = mlx5_ib_map_pa_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2253 data_sg_offset, meta_sg, meta_sg_nents,
2255 if (n == data_sg_nents + meta_sg_nents)
2258 * As a performance optimization, if possible, there is no need to map
2259 * the sg lists to KLM descriptors. First try to map the sg lists to MTT
2260 * descriptors and fallback to KLM only in case of a failure.
2261 * It's more efficient for the HW to work with MTT descriptors
2262 * (especially in high load).
2263 * Use KLM (indirect access) only if it's mandatory.
2266 n = mlx5_ib_map_mtt_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2267 data_sg_offset, meta_sg, meta_sg_nents,
2269 if (n == data_sg_nents + meta_sg_nents)
2273 n = mlx5_ib_map_klm_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2274 data_sg_offset, meta_sg, meta_sg_nents,
2276 if (unlikely(n != data_sg_nents + meta_sg_nents))
2280 /* This is zero-based memory region */
2284 ibmr->sig_attrs->meta_length = pi_mr->meta_length;
2286 ibmr->sig_attrs->meta_length = mr->meta_length;
2291 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
2292 unsigned int *sg_offset)
2294 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2299 ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map,
2300 mr->desc_size * mr->max_descs,
2303 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
2304 n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset, NULL, 0,
2307 n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset,
2310 ib_dma_sync_single_for_device(ibmr->device, mr->desc_map,
2311 mr->desc_size * mr->max_descs,