1 /* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/dma-mapping.h>
33 #include <linux/crc32.h>
34 #include <linux/iommu.h>
39 #include <rdma/ib_verbs.h>
40 #include <rdma/ib_user_verbs.h>
41 #include <rdma/iw_cm.h>
42 #include <rdma/ib_umem.h>
43 #include <rdma/ib_addr.h>
44 #include <rdma/ib_cache.h>
47 #include <linux/qed/qed_if.h>
48 #include <linux/qed/qed_roce_if.h>
52 #include <rdma/qedr-abi.h>
56 void qedr_inc_sw_gsi_cons(struct qedr_qp_hwq_info *info)
58 info->gsi_cons = (info->gsi_cons + 1) % info->max_wr;
61 void qedr_store_gsi_qp_cq(struct qedr_dev *dev, struct qedr_qp *qp,
62 struct ib_qp_init_attr *attrs)
64 dev->gsi_qp_created = 1;
65 dev->gsi_sqcq = get_qedr_cq(attrs->send_cq);
66 dev->gsi_rqcq = get_qedr_cq(attrs->recv_cq);
70 void qedr_ll2_tx_cb(void *_qdev, struct qed_roce_ll2_packet *pkt)
72 struct qedr_dev *dev = (struct qedr_dev *)_qdev;
73 struct qedr_cq *cq = dev->gsi_sqcq;
74 struct qedr_qp *qp = dev->gsi_qp;
77 DP_DEBUG(dev, QEDR_MSG_GSI,
78 "LL2 TX CB: gsi_sqcq=%p, gsi_rqcq=%p, gsi_cons=%d, ibcq_comp=%s\n",
79 dev->gsi_sqcq, dev->gsi_rqcq, qp->sq.gsi_cons,
80 cq->ibcq.comp_handler ? "Yes" : "No");
82 dma_free_coherent(&dev->pdev->dev, pkt->header.len, pkt->header.vaddr,
86 spin_lock_irqsave(&qp->q_lock, flags);
87 qedr_inc_sw_gsi_cons(&qp->sq);
88 spin_unlock_irqrestore(&qp->q_lock, flags);
90 if (cq->ibcq.comp_handler)
91 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
94 void qedr_ll2_rx_cb(void *_dev, struct qed_roce_ll2_packet *pkt,
95 struct qed_roce_ll2_rx_params *params)
97 struct qedr_dev *dev = (struct qedr_dev *)_dev;
98 struct qedr_cq *cq = dev->gsi_rqcq;
99 struct qedr_qp *qp = dev->gsi_qp;
102 spin_lock_irqsave(&qp->q_lock, flags);
104 qp->rqe_wr_id[qp->rq.gsi_cons].rc = params->rc;
105 qp->rqe_wr_id[qp->rq.gsi_cons].vlan_id = params->vlan_id;
106 qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length = pkt->payload[0].len;
107 ether_addr_copy(qp->rqe_wr_id[qp->rq.gsi_cons].smac, params->smac);
109 qedr_inc_sw_gsi_cons(&qp->rq);
111 spin_unlock_irqrestore(&qp->q_lock, flags);
113 if (cq->ibcq.comp_handler)
114 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
117 static void qedr_destroy_gsi_cq(struct qedr_dev *dev,
118 struct ib_qp_init_attr *attrs)
120 struct qed_rdma_destroy_cq_in_params iparams;
121 struct qed_rdma_destroy_cq_out_params oparams;
124 cq = get_qedr_cq(attrs->send_cq);
125 iparams.icid = cq->icid;
126 dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
127 dev->ops->common->chain_free(dev->cdev, &cq->pbl);
129 cq = get_qedr_cq(attrs->recv_cq);
130 /* if a dedicated recv_cq was used, delete it too */
131 if (iparams.icid != cq->icid) {
132 iparams.icid = cq->icid;
133 dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
134 dev->ops->common->chain_free(dev->cdev, &cq->pbl);
138 static inline int qedr_check_gsi_qp_attrs(struct qedr_dev *dev,
139 struct ib_qp_init_attr *attrs)
141 if (attrs->cap.max_recv_sge > QEDR_GSI_MAX_RECV_SGE) {
143 " create gsi qp: failed. max_recv_sge is larger the max %d>%d\n",
144 attrs->cap.max_recv_sge, QEDR_GSI_MAX_RECV_SGE);
148 if (attrs->cap.max_recv_wr > QEDR_GSI_MAX_RECV_WR) {
150 " create gsi qp: failed. max_recv_wr is too large %d>%d\n",
151 attrs->cap.max_recv_wr, QEDR_GSI_MAX_RECV_WR);
155 if (attrs->cap.max_send_wr > QEDR_GSI_MAX_SEND_WR) {
157 " create gsi qp: failed. max_send_wr is too large %d>%d\n",
158 attrs->cap.max_send_wr, QEDR_GSI_MAX_SEND_WR);
165 struct ib_qp *qedr_create_gsi_qp(struct qedr_dev *dev,
166 struct ib_qp_init_attr *attrs,
169 struct qed_roce_ll2_params ll2_params;
172 rc = qedr_check_gsi_qp_attrs(dev, attrs);
176 /* configure and start LL2 */
177 memset(&ll2_params, 0, sizeof(ll2_params));
178 ll2_params.max_tx_buffers = attrs->cap.max_send_wr;
179 ll2_params.max_rx_buffers = attrs->cap.max_recv_wr;
180 ll2_params.cbs.tx_cb = qedr_ll2_tx_cb;
181 ll2_params.cbs.rx_cb = qedr_ll2_rx_cb;
182 ll2_params.cb_cookie = (void *)dev;
183 ll2_params.mtu = dev->ndev->mtu;
184 ether_addr_copy(ll2_params.mac_address, dev->ndev->dev_addr);
185 rc = dev->ops->roce_ll2_start(dev->cdev, &ll2_params);
187 DP_ERR(dev, "create gsi qp: failed on ll2 start. rc=%d\n", rc);
193 qp->rq.max_wr = attrs->cap.max_recv_wr;
194 qp->sq.max_wr = attrs->cap.max_send_wr;
196 qp->rqe_wr_id = kcalloc(qp->rq.max_wr, sizeof(*qp->rqe_wr_id),
200 qp->wqe_wr_id = kcalloc(qp->sq.max_wr, sizeof(*qp->wqe_wr_id),
205 qedr_store_gsi_qp_cq(dev, qp, attrs);
206 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
208 /* the GSI CQ is handled by the driver so remove it from the FW */
209 qedr_destroy_gsi_cq(dev, attrs);
210 dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
211 dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
213 DP_DEBUG(dev, QEDR_MSG_GSI, "created GSI QP %p\n", qp);
218 kfree(qp->rqe_wr_id);
220 rc = dev->ops->roce_ll2_stop(dev->cdev);
222 DP_ERR(dev, "create gsi qp: failed destroy on create\n");
224 return ERR_PTR(-ENOMEM);
227 int qedr_destroy_gsi_qp(struct qedr_dev *dev)
231 rc = dev->ops->roce_ll2_stop(dev->cdev);
233 DP_ERR(dev, "destroy gsi qp: failed (rc=%d)\n", rc);
235 DP_DEBUG(dev, QEDR_MSG_GSI, "destroy gsi qp: success\n");
240 #define QEDR_MAX_UD_HEADER_SIZE (100)
241 #define QEDR_GSI_QPN (1)
242 static inline int qedr_gsi_build_header(struct qedr_dev *dev,
244 struct ib_send_wr *swr,
245 struct ib_ud_header *udh,
248 bool has_vlan = false, has_grh_ipv6 = true;
249 struct ib_ah_attr *ah_attr = &get_qedr_ah(ud_wr(swr)->ah)->attr;
250 struct ib_global_route *grh = &ah_attr->grh;
255 struct ib_gid_attr sgid_attr;
259 bool has_udp = false;
263 for (i = 0; i < swr->num_sge; ++i)
264 send_size += swr->sg_list[i].length;
266 rc = ib_get_cached_gid(qp->ibqp.device, ah_attr->port_num,
267 grh->sgid_index, &sgid, &sgid_attr);
270 "gsi post send: failed to get cached GID (port=%d, ix=%d)\n",
271 ah_attr->port_num, grh->sgid_index);
275 vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
276 if (vlan_id < VLAN_CFI_MASK)
279 dev_put(sgid_attr.ndev);
281 if (!memcmp(&sgid, &zgid, sizeof(sgid))) {
282 DP_ERR(dev, "gsi post send: GID not found GID index %d\n",
283 ah_attr->grh.sgid_index);
287 has_udp = (sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
290 ether_type = ETH_P_ROCE;
291 *roce_mode = ROCE_V1;
292 } else if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
295 ether_type = ETH_P_IP;
296 has_grh_ipv6 = false;
297 *roce_mode = ROCE_V2_IPV4;
301 ether_type = ETH_P_IPV6;
302 *roce_mode = ROCE_V2_IPV6;
305 rc = ib_ud_header_init(send_size, false, true, has_vlan,
306 has_grh_ipv6, ip_ver, has_udp, 0, udh);
308 DP_ERR(dev, "gsi post send: failed to init header\n");
312 /* ENET + VLAN headers */
313 ether_addr_copy(udh->eth.dmac_h, ah_attr->dmac);
314 ether_addr_copy(udh->eth.smac_h, dev->ndev->dev_addr);
316 udh->eth.type = htons(ETH_P_8021Q);
317 udh->vlan.tag = htons(vlan_id);
318 udh->vlan.type = htons(ether_type);
320 udh->eth.type = htons(ether_type);
324 udh->bth.solicited_event = !!(swr->send_flags & IB_SEND_SOLICITED);
325 udh->bth.pkey = QEDR_ROCE_PKEY_DEFAULT;
326 udh->bth.destination_qpn = htonl(ud_wr(swr)->remote_qpn);
327 udh->bth.psn = htonl((qp->sq_psn++) & ((1 << 24) - 1));
328 udh->bth.opcode = IB_OPCODE_UD_SEND_ONLY;
331 udh->deth.qkey = htonl(0x80010000);
332 udh->deth.source_qpn = htonl(QEDR_GSI_QPN);
335 /* GRH / IPv6 header */
336 udh->grh.traffic_class = grh->traffic_class;
337 udh->grh.flow_label = grh->flow_label;
338 udh->grh.hop_limit = grh->hop_limit;
339 udh->grh.destination_gid = grh->dgid;
340 memcpy(&udh->grh.source_gid.raw, &sgid.raw,
341 sizeof(udh->grh.source_gid.raw));
346 udh->ip4.protocol = IPPROTO_UDP;
347 udh->ip4.tos = htonl(ah_attr->grh.flow_label);
348 udh->ip4.frag_off = htons(IP_DF);
349 udh->ip4.ttl = ah_attr->grh.hop_limit;
351 ipv4_addr = qedr_get_ipv4_from_gid(sgid.raw);
352 udh->ip4.saddr = ipv4_addr;
353 ipv4_addr = qedr_get_ipv4_from_gid(ah_attr->grh.dgid.raw);
354 udh->ip4.daddr = ipv4_addr;
355 /* note: checksum is calculated by the device */
360 udh->udp.sport = htons(QEDR_ROCE_V2_UDP_SPORT);
361 udh->udp.dport = htons(ROCE_V2_UDP_DPORT);
363 /* UDP length is untouched hence is zero */
368 static inline int qedr_gsi_build_packet(struct qedr_dev *dev,
370 struct ib_send_wr *swr,
371 struct qed_roce_ll2_packet **p_packet)
373 u8 ud_header_buffer[QEDR_MAX_UD_HEADER_SIZE];
374 struct qed_roce_ll2_packet *packet;
375 struct pci_dev *pdev = dev->pdev;
376 int roce_mode, header_size;
377 struct ib_ud_header udh;
382 rc = qedr_gsi_build_header(dev, qp, swr, &udh, &roce_mode);
386 header_size = ib_ud_header_pack(&udh, &ud_header_buffer);
388 packet = kzalloc(sizeof(*packet), GFP_ATOMIC);
392 packet->header.vaddr = dma_alloc_coherent(&pdev->dev, header_size,
393 &packet->header.baddr,
395 if (!packet->header.vaddr) {
400 if (ether_addr_equal(udh.eth.smac_h, udh.eth.dmac_h))
401 packet->tx_dest = QED_ROCE_LL2_TX_DEST_LB;
403 packet->tx_dest = QED_ROCE_LL2_TX_DEST_NW;
405 packet->roce_mode = roce_mode;
406 memcpy(packet->header.vaddr, ud_header_buffer, header_size);
407 packet->header.len = header_size;
408 packet->n_seg = swr->num_sge;
409 for (i = 0; i < packet->n_seg; i++) {
410 packet->payload[i].baddr = swr->sg_list[i].addr;
411 packet->payload[i].len = swr->sg_list[i].length;
419 int qedr_gsi_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
420 struct ib_send_wr **bad_wr)
422 struct qed_roce_ll2_packet *pkt = NULL;
423 struct qedr_qp *qp = get_qedr_qp(ibqp);
424 struct qed_roce_ll2_tx_params params;
425 struct qedr_dev *dev = qp->dev;
429 if (qp->state != QED_ROCE_QP_STATE_RTS) {
432 "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTS\n",
437 if (wr->num_sge > RDMA_MAX_SGE_PER_SQ_WQE) {
438 DP_ERR(dev, "gsi post send: num_sge is too large (%d>%d)\n",
439 wr->num_sge, RDMA_MAX_SGE_PER_SQ_WQE);
444 if (wr->opcode != IB_WR_SEND) {
446 "gsi post send: failed due to unsupported opcode %d\n",
452 memset(¶ms, 0, sizeof(params));
454 spin_lock_irqsave(&qp->q_lock, flags);
456 rc = qedr_gsi_build_packet(dev, qp, wr, &pkt);
458 spin_unlock_irqrestore(&qp->q_lock, flags);
462 rc = dev->ops->roce_ll2_tx(dev->cdev, pkt, ¶ms);
464 qp->wqe_wr_id[qp->sq.prod].wr_id = wr->wr_id;
465 qedr_inc_sw_prod(&qp->sq);
466 DP_DEBUG(qp->dev, QEDR_MSG_GSI,
467 "gsi post send: opcode=%d, in_irq=%ld, irqs_disabled=%d, wr_id=%llx\n",
468 wr->opcode, in_irq(), irqs_disabled(), wr->wr_id);
470 if (rc == QED_ROCE_TX_HEAD_FAILURE) {
471 /* TX failed while posting header - release resources */
472 dma_free_coherent(&dev->pdev->dev, pkt->header.len,
473 pkt->header.vaddr, pkt->header.baddr);
475 } else if (rc == QED_ROCE_TX_FRAG_FAILURE) {
476 /* NTD since TX failed while posting a fragment. We will
477 * release the resources on TX callback
481 DP_ERR(dev, "gsi post send: failed to transmit (rc=%d)\n", rc);
486 spin_unlock_irqrestore(&qp->q_lock, flags);
490 "gsi post send: failed second WR. Only one WR may be passed at a time\n");
502 int qedr_gsi_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
503 struct ib_recv_wr **bad_wr)
505 struct qedr_dev *dev = get_qedr_dev(ibqp->device);
506 struct qedr_qp *qp = get_qedr_qp(ibqp);
507 struct qed_roce_ll2_buffer buf;
512 if ((qp->state != QED_ROCE_QP_STATE_RTR) &&
513 (qp->state != QED_ROCE_QP_STATE_RTS)) {
516 "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTR/S\n",
521 memset(&buf, 0, sizeof(buf));
523 spin_lock_irqsave(&qp->q_lock, flags);
526 if (wr->num_sge > QEDR_GSI_MAX_RECV_SGE) {
528 "gsi post recv: failed to post rx buffer. too many sges %d>%d\n",
529 wr->num_sge, QEDR_GSI_MAX_RECV_SGE);
533 buf.baddr = wr->sg_list[0].addr;
534 buf.len = wr->sg_list[0].length;
536 rc = dev->ops->roce_ll2_post_rx_buffer(dev->cdev, &buf, 0, 1);
539 "gsi post recv: failed to post rx buffer (rc=%d)\n",
544 memset(&qp->rqe_wr_id[qp->rq.prod], 0,
545 sizeof(qp->rqe_wr_id[qp->rq.prod]));
546 qp->rqe_wr_id[qp->rq.prod].sg_list[0] = wr->sg_list[0];
547 qp->rqe_wr_id[qp->rq.prod].wr_id = wr->wr_id;
549 qedr_inc_sw_prod(&qp->rq);
554 spin_unlock_irqrestore(&qp->q_lock, flags);
558 spin_unlock_irqrestore(&qp->q_lock, flags);
563 int qedr_gsi_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
565 struct qedr_dev *dev = get_qedr_dev(ibcq->device);
566 struct qedr_cq *cq = get_qedr_cq(ibcq);
567 struct qedr_qp *qp = dev->gsi_qp;
571 spin_lock_irqsave(&cq->cq_lock, flags);
573 while (i < num_entries && qp->rq.cons != qp->rq.gsi_cons) {
574 memset(&wc[i], 0, sizeof(*wc));
576 wc[i].qp = &qp->ibqp;
577 wc[i].wr_id = qp->rqe_wr_id[qp->rq.cons].wr_id;
578 wc[i].opcode = IB_WC_RECV;
579 wc[i].pkey_index = 0;
580 wc[i].status = (qp->rqe_wr_id[qp->rq.cons].rc) ?
581 IB_WC_GENERAL_ERR : IB_WC_SUCCESS;
582 /* 0 - currently only one recv sg is supported */
583 wc[i].byte_len = qp->rqe_wr_id[qp->rq.cons].sg_list[0].length;
584 wc[i].wc_flags |= IB_WC_GRH | IB_WC_IP_CSUM_OK;
585 ether_addr_copy(wc[i].smac, qp->rqe_wr_id[qp->rq.cons].smac);
586 wc[i].wc_flags |= IB_WC_WITH_SMAC;
587 if (qp->rqe_wr_id[qp->rq.cons].vlan_id) {
588 wc[i].wc_flags |= IB_WC_WITH_VLAN;
589 wc[i].vlan_id = qp->rqe_wr_id[qp->rq.cons].vlan_id;
592 qedr_inc_sw_cons(&qp->rq);
596 while (i < num_entries && qp->sq.cons != qp->sq.gsi_cons) {
597 memset(&wc[i], 0, sizeof(*wc));
599 wc[i].qp = &qp->ibqp;
600 wc[i].wr_id = qp->wqe_wr_id[qp->sq.cons].wr_id;
601 wc[i].opcode = IB_WC_SEND;
602 wc[i].status = IB_WC_SUCCESS;
604 qedr_inc_sw_cons(&qp->sq);
608 spin_unlock_irqrestore(&cq->cq_lock, flags);
610 DP_DEBUG(dev, QEDR_MSG_GSI,
611 "gsi poll_cq: requested entries=%d, actual=%d, qp->rq.cons=%d, qp->rq.gsi_cons=%x, qp->sq.cons=%d, qp->sq.gsi_cons=%d, qp_num=%d\n",
612 num_entries, i, qp->rq.cons, qp->rq.gsi_cons, qp->sq.cons,
613 qp->sq.gsi_cons, qp->ibqp.qp_num);