2 * Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 * This file contains all of the code that is specific to the
37 * QLogic_IB 6120 PCIe chip.
40 #include <linux/interrupt.h>
41 #include <linux/pci.h>
42 #include <linux/delay.h>
43 #include <rdma/ib_verbs.h>
46 #include "qib_6120_regs.h"
48 static void qib_6120_setup_setextled(struct qib_pportdata *, u32);
49 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op);
50 static u8 qib_6120_phys_portstate(u64);
51 static u32 qib_6120_iblink_state(u64);
54 * This file contains all the chip-specific register information and
55 * access functions for the Intel Intel_IB PCI-Express chip.
59 /* KREG_IDX uses machine-generated #defines */
60 #define KREG_IDX(regname) (QIB_6120_##regname##_OFFS / sizeof(u64))
62 /* Use defines to tie machine-generated names to lower-case names */
63 #define kr_extctrl KREG_IDX(EXTCtrl)
64 #define kr_extstatus KREG_IDX(EXTStatus)
65 #define kr_gpio_clear KREG_IDX(GPIOClear)
66 #define kr_gpio_mask KREG_IDX(GPIOMask)
67 #define kr_gpio_out KREG_IDX(GPIOOut)
68 #define kr_gpio_status KREG_IDX(GPIOStatus)
69 #define kr_rcvctrl KREG_IDX(RcvCtrl)
70 #define kr_sendctrl KREG_IDX(SendCtrl)
71 #define kr_partitionkey KREG_IDX(RcvPartitionKey)
72 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
73 #define kr_ibcstatus KREG_IDX(IBCStatus)
74 #define kr_ibcctrl KREG_IDX(IBCCtrl)
75 #define kr_sendbuffererror KREG_IDX(SendBufErr0)
76 #define kr_rcvbthqp KREG_IDX(RcvBTHQP)
77 #define kr_counterregbase KREG_IDX(CntrRegBase)
78 #define kr_palign KREG_IDX(PageAlign)
79 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
80 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
81 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
82 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
83 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
84 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
85 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
86 #define kr_scratch KREG_IDX(Scratch)
87 #define kr_sendctrl KREG_IDX(SendCtrl)
88 #define kr_sendpioavailaddr KREG_IDX(SendPIOAvailAddr)
89 #define kr_sendpiobufbase KREG_IDX(SendPIOBufBase)
90 #define kr_sendpiobufcnt KREG_IDX(SendPIOBufCnt)
91 #define kr_sendpiosize KREG_IDX(SendPIOSize)
92 #define kr_sendregbase KREG_IDX(SendRegBase)
93 #define kr_userregbase KREG_IDX(UserRegBase)
94 #define kr_control KREG_IDX(Control)
95 #define kr_intclear KREG_IDX(IntClear)
96 #define kr_intmask KREG_IDX(IntMask)
97 #define kr_intstatus KREG_IDX(IntStatus)
98 #define kr_errclear KREG_IDX(ErrClear)
99 #define kr_errmask KREG_IDX(ErrMask)
100 #define kr_errstatus KREG_IDX(ErrStatus)
101 #define kr_hwerrclear KREG_IDX(HwErrClear)
102 #define kr_hwerrmask KREG_IDX(HwErrMask)
103 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
104 #define kr_revision KREG_IDX(Revision)
105 #define kr_portcnt KREG_IDX(PortCnt)
106 #define kr_serdes_cfg0 KREG_IDX(SerdesCfg0)
107 #define kr_serdes_cfg1 (kr_serdes_cfg0 + 1)
108 #define kr_serdes_stat KREG_IDX(SerdesStat)
109 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
111 /* These must only be written via qib_write_kreg_ctxt() */
112 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
113 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
115 #define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \
116 QIB_6120_LBIntCnt_OFFS) / sizeof(u64))
118 #define cr_badformat CREG_IDX(RxBadFormatCnt)
119 #define cr_erricrc CREG_IDX(RxICRCErrCnt)
120 #define cr_errlink CREG_IDX(RxLinkProblemCnt)
121 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
122 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
123 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlErrCnt)
124 #define cr_err_rlen CREG_IDX(RxLenErrCnt)
125 #define cr_errslen CREG_IDX(TxLenErrCnt)
126 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
127 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
128 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
129 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
130 #define cr_lbint CREG_IDX(LBIntCnt)
131 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
132 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
133 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
134 #define cr_pktrcv CREG_IDX(RxDataPktCnt)
135 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
136 #define cr_pktsend CREG_IDX(TxDataPktCnt)
137 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
138 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
139 #define cr_rcvebp CREG_IDX(RxEBPCnt)
140 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
141 #define cr_senddropped CREG_IDX(TxDroppedPktCnt)
142 #define cr_sendstall CREG_IDX(TxFlowStallCnt)
143 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
144 #define cr_wordrcv CREG_IDX(RxDwordCnt)
145 #define cr_wordsend CREG_IDX(TxDwordCnt)
146 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
147 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
148 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
149 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
150 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
152 #define SYM_RMASK(regname, fldname) ((u64) \
153 QIB_6120_##regname##_##fldname##_RMASK)
154 #define SYM_MASK(regname, fldname) ((u64) \
155 QIB_6120_##regname##_##fldname##_RMASK << \
156 QIB_6120_##regname##_##fldname##_LSB)
157 #define SYM_LSB(regname, fldname) (QIB_6120_##regname##_##fldname##_LSB)
159 #define SYM_FIELD(value, regname, fldname) ((u64) \
160 (((value) >> SYM_LSB(regname, fldname)) & \
161 SYM_RMASK(regname, fldname)))
162 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
163 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
165 /* link training states, from IBC */
166 #define IB_6120_LT_STATE_DISABLED 0x00
167 #define IB_6120_LT_STATE_LINKUP 0x01
168 #define IB_6120_LT_STATE_POLLACTIVE 0x02
169 #define IB_6120_LT_STATE_POLLQUIET 0x03
170 #define IB_6120_LT_STATE_SLEEPDELAY 0x04
171 #define IB_6120_LT_STATE_SLEEPQUIET 0x05
172 #define IB_6120_LT_STATE_CFGDEBOUNCE 0x08
173 #define IB_6120_LT_STATE_CFGRCVFCFG 0x09
174 #define IB_6120_LT_STATE_CFGWAITRMT 0x0a
175 #define IB_6120_LT_STATE_CFGIDLE 0x0b
176 #define IB_6120_LT_STATE_RECOVERRETRAIN 0x0c
177 #define IB_6120_LT_STATE_RECOVERWAITRMT 0x0e
178 #define IB_6120_LT_STATE_RECOVERIDLE 0x0f
180 /* link state machine states from IBC */
181 #define IB_6120_L_STATE_DOWN 0x0
182 #define IB_6120_L_STATE_INIT 0x1
183 #define IB_6120_L_STATE_ARM 0x2
184 #define IB_6120_L_STATE_ACTIVE 0x3
185 #define IB_6120_L_STATE_ACT_DEFER 0x4
187 static const u8 qib_6120_physportstate[0x20] = {
188 [IB_6120_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
189 [IB_6120_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
190 [IB_6120_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
191 [IB_6120_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
192 [IB_6120_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
193 [IB_6120_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
194 [IB_6120_LT_STATE_CFGDEBOUNCE] =
195 IB_PHYSPORTSTATE_CFG_TRAIN,
196 [IB_6120_LT_STATE_CFGRCVFCFG] =
197 IB_PHYSPORTSTATE_CFG_TRAIN,
198 [IB_6120_LT_STATE_CFGWAITRMT] =
199 IB_PHYSPORTSTATE_CFG_TRAIN,
200 [IB_6120_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
201 [IB_6120_LT_STATE_RECOVERRETRAIN] =
202 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
203 [IB_6120_LT_STATE_RECOVERWAITRMT] =
204 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
205 [IB_6120_LT_STATE_RECOVERIDLE] =
206 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
207 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
208 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
209 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
210 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
211 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
212 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
213 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
214 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
218 struct qib_chip_specific {
219 u64 __iomem *cregbase;
222 void *dummy_hdrq; /* used after ctxt close */
223 dma_addr_t dummy_hdrq_phys;
224 spinlock_t kernel_tid_lock; /* no back to back kernel TID writes */
225 spinlock_t user_tid_lock; /* no back to back user TID writes */
226 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
227 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
230 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
231 u64 gpio_mask; /* shadow the gpio mask register */
232 u64 extctrl; /* shadow the gpio output enable, etc... */
234 * these 5 fields are used to establish deltas for IB symbol
235 * errors and linkrecovery errors. They can be reported on
236 * some chips during link negotiation prior to INIT, and with
237 * DDR when faking DDR negotiations with non-IBTA switches.
238 * The chip counters are adjusted at driver unload if there is
246 u64 ibcctrl; /* shadow for kr_ibcctrl */
247 u32 lastlinkrecov; /* link recovery issue */
252 /* used with gpio interrupts to implement IB counters */
253 u32 rxfc_unsupvl_errs;
254 u32 overrun_thresh_errs;
256 * these count only cases where _successive_ LocalLinkIntegrity
257 * errors were seen in the receive headers of IB standard packets
262 u64 sword; /* total dwords sent (sample result) */
263 u64 rword; /* total dwords received (sample result) */
264 u64 spkts; /* total packets sent (sample result) */
265 u64 rpkts; /* total packets received (sample result) */
266 u64 xmit_wait; /* # of ticks no data sent (sample result) */
267 struct timer_list pma_timer;
268 struct qib_pportdata *ppd;
271 u8 pma_sample_status;
275 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
276 /* cycle through TS1/TS2 till OK */
277 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
278 /* wait for TS1, then go on */
279 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
280 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
282 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
283 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
284 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
285 #define QLOGIC_IB_IBCC_LINKCMD_SHIFT 18
288 * We could have a single register get/put routine, that takes a group type,
289 * but this is somewhat clearer and cleaner. It also gives us some error
290 * checking. 64 bit register reads should always work, but are inefficient
291 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
292 * so we use kreg32 wherever possible. User register and counter register
293 * reads are always 32 bit reads, so only one form of those routines.
297 * qib_read_ureg32 - read 32-bit virtualized per-context register
299 * @regno: register number
300 * @ctxt: context number
302 * Return the contents of a register that is virtualized to be per context.
303 * Returns -1 on errors (not distinguishable from valid contents at
304 * runtime; we may add a separate error variable at some point).
306 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
307 enum qib_ureg regno, int ctxt)
309 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
313 return readl(regno + (u64 __iomem *)
314 ((char __iomem *)dd->userbase +
315 dd->ureg_align * ctxt));
317 return readl(regno + (u64 __iomem *)
319 (char __iomem *)dd->kregbase +
320 dd->ureg_align * ctxt));
324 * qib_write_ureg - write 32-bit virtualized per-context register
326 * @regno: register number
330 * Write the contents of a register that is virtualized to be per context.
332 static inline void qib_write_ureg(const struct qib_devdata *dd,
333 enum qib_ureg regno, u64 value, int ctxt)
338 ubase = (u64 __iomem *)
339 ((char __iomem *) dd->userbase +
340 dd->ureg_align * ctxt);
342 ubase = (u64 __iomem *)
344 (char __iomem *) dd->kregbase +
345 dd->ureg_align * ctxt);
347 if (dd->kregbase && (dd->flags & QIB_PRESENT))
348 writeq(value, &ubase[regno]);
351 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
354 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
356 return readl((u32 __iomem *)&dd->kregbase[regno]);
359 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
362 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
365 return readq(&dd->kregbase[regno]);
368 static inline void qib_write_kreg(const struct qib_devdata *dd,
369 const u16 regno, u64 value)
371 if (dd->kregbase && (dd->flags & QIB_PRESENT))
372 writeq(value, &dd->kregbase[regno]);
376 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
377 * @dd: the qlogic_ib device
378 * @regno: the register number to write
379 * @ctxt: the context containing the register
380 * @value: the value to write
382 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
383 const u16 regno, unsigned ctxt,
386 qib_write_kreg(dd, regno + ctxt, value);
389 static inline void write_6120_creg(const struct qib_devdata *dd,
390 u16 regno, u64 value)
392 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
393 writeq(value, &dd->cspec->cregbase[regno]);
396 static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno)
398 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
400 return readq(&dd->cspec->cregbase[regno]);
403 static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno)
405 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
407 return readl(&dd->cspec->cregbase[regno]);
410 /* kr_control bits */
411 #define QLOGIC_IB_C_RESET 1U
413 /* kr_intstatus, kr_intclear, kr_intmask bits */
414 #define QLOGIC_IB_I_RCVURG_MASK ((1U << 5) - 1)
415 #define QLOGIC_IB_I_RCVURG_SHIFT 0
416 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1U << 5) - 1)
417 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 12
419 #define QLOGIC_IB_C_FREEZEMODE 0x00000002
420 #define QLOGIC_IB_C_LINKENABLE 0x00000004
421 #define QLOGIC_IB_I_ERROR 0x0000000080000000ULL
422 #define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL
423 #define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL
424 #define QLOGIC_IB_I_GPIO 0x0000000010000000ULL
425 #define QLOGIC_IB_I_BITSEXTANT \
426 ((QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
427 (QLOGIC_IB_I_RCVAVAIL_MASK << \
428 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
429 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
430 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO)
432 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
433 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
434 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
435 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
436 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
437 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
438 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
439 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
440 #define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
441 #define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
442 #define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
443 #define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
444 #define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL
447 /* kr_extstatus bits */
448 #define QLOGIC_IB_EXTS_FREQSEL 0x2
449 #define QLOGIC_IB_EXTS_SERDESSEL 0x4
450 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000
451 #define QLOGIC_IB_EXTS_MEMBIST_FOUND 0x0000000000008000
453 /* kr_xgxsconfig bits */
454 #define QLOGIC_IB_XGXS_RESET 0x5ULL
456 #define _QIB_GPIO_SDA_NUM 1
457 #define _QIB_GPIO_SCL_NUM 0
459 /* Bits in GPIO for the added IB link interrupts */
460 #define GPIO_RXUVL_BIT 3
461 #define GPIO_OVRUN_BIT 4
462 #define GPIO_LLI_BIT 5
463 #define GPIO_ERRINTR_MASK 0x38
466 #define QLOGIC_IB_RT_BUFSIZE_MASK 0xe0000000ULL
467 #define QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid) \
468 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
469 #define QLOGIC_IB_RT_BUFSIZE(tid) (1 << QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid))
470 #define QLOGIC_IB_RT_IS_VALID(tid) \
471 (((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) && \
472 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) != QLOGIC_IB_RT_BUFSIZE_MASK)))
473 #define QLOGIC_IB_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
474 #define QLOGIC_IB_RT_ADDR_SHIFT 10
476 #define QLOGIC_IB_R_INTRAVAIL_SHIFT 16
477 #define QLOGIC_IB_R_TAILUPD_SHIFT 31
478 #define IBA6120_R_PKEY_DIS_SHIFT 30
480 #define PBC_6120_VL15_SEND_CTRL (1ULL << 31) /* pbc; VL15; link_buf only */
482 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
483 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
485 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
486 ((1ULL << (SYM_LSB(regname, fldname) + (bit)))))
488 #define TXEMEMPARITYERR_PIOBUF \
489 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
490 #define TXEMEMPARITYERR_PIOPBC \
491 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
492 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \
493 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
495 #define RXEMEMPARITYERR_RCVBUF \
496 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
497 #define RXEMEMPARITYERR_LOOKUPQ \
498 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
499 #define RXEMEMPARITYERR_EXPTID \
500 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
501 #define RXEMEMPARITYERR_EAGERTID \
502 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
503 #define RXEMEMPARITYERR_FLAGBUF \
504 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
505 #define RXEMEMPARITYERR_DATAINFO \
506 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
507 #define RXEMEMPARITYERR_HDRINFO \
508 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
510 /* 6120 specific hardware errors... */
511 static const struct qib_hwerror_msgs qib_6120_hwerror_msgs[] = {
512 /* generic hardware errors */
513 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
514 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
516 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
517 "TXE PIOBUF Memory Parity"),
518 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
519 "TXE PIOPBC Memory Parity"),
520 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
521 "TXE PIOLAUNCHFIFO Memory Parity"),
523 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
524 "RXE RCVBUF Memory Parity"),
525 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
526 "RXE LOOKUPQ Memory Parity"),
527 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
528 "RXE EAGERTID Memory Parity"),
529 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
530 "RXE EXPTID Memory Parity"),
531 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
532 "RXE FLAGBUF Memory Parity"),
533 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
534 "RXE DATAINFO Memory Parity"),
535 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
536 "RXE HDRINFO Memory Parity"),
538 /* chip-specific hardware errors */
539 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
540 "PCIe Poisoned TLP"),
541 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
542 "PCIe completion timeout"),
544 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
545 * parity or memory parity error failures, because most likely we
546 * won't be able to talk to the core of the chip. Nonetheless, we
547 * might see them, if they are in parts of the PCIe core that aren't
550 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
552 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
554 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
555 "PCIe XTLH core parity"),
556 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
557 "PCIe ADM TX core parity"),
558 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
559 "PCIe ADM RX core parity"),
560 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
564 #define TXE_PIO_PARITY (TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC)
565 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \
566 QLOGIC_IB_HWE_COREPLL_RFSLIP)
568 /* variables for sanity checking interrupt and errors */
569 #define IB_HWE_BITSEXTANT \
570 (HWE_MASK(RXEMemParityErr) | \
571 HWE_MASK(TXEMemParityErr) | \
572 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \
573 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
574 QLOGIC_IB_HWE_PCIE1PLLFAILED | \
575 QLOGIC_IB_HWE_PCIE0PLLFAILED | \
576 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
577 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
578 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
579 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
580 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
581 HWE_MASK(PowerOnBISTFailed) | \
582 QLOGIC_IB_HWE_COREPLL_FBSLIP | \
583 QLOGIC_IB_HWE_COREPLL_RFSLIP | \
584 QLOGIC_IB_HWE_SERDESPLLFAILED | \
585 HWE_MASK(IBCBusToSPCParityErr) | \
586 HWE_MASK(IBCBusFromSPCParityErr))
588 #define IB_E_BITSEXTANT \
589 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \
590 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \
591 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \
592 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
593 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \
594 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \
595 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \
596 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \
597 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \
598 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendMaxPktLenErr) | \
599 ERR_MASK(SendUnderRunErr) | ERR_MASK(SendPktLenErr) | \
600 ERR_MASK(SendDroppedSmpPktErr) | \
601 ERR_MASK(SendDroppedDataPktErr) | \
602 ERR_MASK(SendPioArmLaunchErr) | \
603 ERR_MASK(SendUnexpectedPktNumErr) | \
604 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(IBStatusChanged) | \
605 ERR_MASK(InvalidAddrErr) | ERR_MASK(ResetNegated) | \
606 ERR_MASK(HardwareErr))
608 #define QLOGIC_IB_E_PKTERRS ( \
609 ERR_MASK(SendPktLenErr) | \
610 ERR_MASK(SendDroppedDataPktErr) | \
611 ERR_MASK(RcvVCRCErr) | \
612 ERR_MASK(RcvICRCErr) | \
613 ERR_MASK(RcvShortPktLenErr) | \
616 /* These are all rcv-related errors which we want to count for stats */
617 #define E_SUM_PKTERRS \
618 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \
619 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \
620 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \
621 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
622 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \
623 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
625 /* These are all send-related errors which we want to count for stats */
627 (ERR_MASK(SendPioArmLaunchErr) | \
628 ERR_MASK(SendUnexpectedPktNumErr) | \
629 ERR_MASK(SendDroppedDataPktErr) | \
630 ERR_MASK(SendDroppedSmpPktErr) | \
631 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \
632 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
633 ERR_MASK(InvalidAddrErr))
636 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
637 * errors not related to freeze and cancelling buffers. Can't ignore
638 * armlaunch because could get more while still cleaning up, and need
639 * to cancel those as they happen.
641 #define E_SPKT_ERRS_IGNORE \
642 (ERR_MASK(SendDroppedDataPktErr) | \
643 ERR_MASK(SendDroppedSmpPktErr) | \
644 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \
645 ERR_MASK(SendPktLenErr))
648 * these are errors that can occur when the link changes state while
649 * a packet is being sent or received. This doesn't cover things
650 * like EBP or VCRC that can be the result of a sending having the
651 * link change state, so we receive a "known bad" packet.
653 #define E_SUM_LINK_PKTERRS \
654 (ERR_MASK(SendDroppedDataPktErr) | \
655 ERR_MASK(SendDroppedSmpPktErr) | \
656 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
657 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
658 ERR_MASK(RcvUnexpectedCharErr))
660 static void qib_6120_put_tid_2(struct qib_devdata *, u64 __iomem *,
664 * On platforms using this chip, and not having ordered WC stores, we
665 * can get TXE parity errors due to speculative reads to the PIO buffers,
666 * and this, due to a chip issue can result in (many) false parity error
667 * reports. So it's a debug print on those, and an info print on systems
668 * where the speculative reads don't occur.
670 static void qib_6120_txe_recover(struct qib_devdata *dd)
672 if (!qib_unordered_wc())
673 qib_devinfo(dd->pcidev,
674 "Recovering from TXE PIO parity error\n");
677 /* enable/disable chip from delivering interrupts */
678 static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable)
681 if (dd->flags & QIB_BADINTR)
683 qib_write_kreg(dd, kr_intmask, ~0ULL);
684 /* force re-interrupt of any pending interrupts. */
685 qib_write_kreg(dd, kr_intclear, 0ULL);
687 qib_write_kreg(dd, kr_intmask, 0ULL);
691 * Try to cleanup as much as possible for anything that might have gone
692 * wrong while in freeze mode, such as pio buffers being written by user
693 * processes (causing armlaunch), send errors due to going into freeze mode,
694 * etc., and try to avoid causing extra interrupts while doing so.
695 * Forcibly update the in-memory pioavail register copies after cleanup
696 * because the chip won't do it while in freeze mode (the register values
697 * themselves are kept correct).
698 * Make sure that we don't lose any important interrupts by using the chip
699 * feature that says that writing 0 to a bit in *clear that is set in
700 * *status will cause an interrupt to be generated again (if allowed by
702 * This is in chip-specific code because of all of the register accesses,
703 * even though the details are similar on most chips
705 static void qib_6120_clear_freeze(struct qib_devdata *dd)
707 /* disable error interrupts, to avoid confusion */
708 qib_write_kreg(dd, kr_errmask, 0ULL);
710 /* also disable interrupts; errormask is sometimes overwritten */
711 qib_6120_set_intr_state(dd, 0);
713 qib_cancel_sends(dd->pport);
715 /* clear the freeze, and be sure chip saw it */
716 qib_write_kreg(dd, kr_control, dd->control);
717 qib_read_kreg32(dd, kr_scratch);
719 /* force in-memory update now we are out of freeze */
720 qib_force_pio_avail_update(dd);
723 * force new interrupt if any hwerr, error or interrupt bits are
724 * still set, and clear "safe" send packet errors related to freeze
725 * and cancelling sends. Re-enable error interrupts before possible
726 * force of re-interrupt on pending interrupts.
728 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
729 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
730 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
731 qib_6120_set_intr_state(dd, 1);
735 * qib_handle_6120_hwerrors - display hardware errors.
736 * @dd: the qlogic_ib device
737 * @msg: the output buffer
738 * @msgl: the size of the output buffer
740 * Use same msg buffer as regular errors to avoid excessive stack
741 * use. Most hardware errors are catastrophic, but for right now,
742 * we'll print them and continue. Reuse the same message buffer as
743 * handle_6120_errors() to avoid excessive stack usage.
745 static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg,
753 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
756 if (hwerrs == ~0ULL) {
758 "Read of hardware error status failed (all bits set); ignoring\n");
761 qib_stats.sps_hwerrs++;
763 /* Always clear the error status register, except MEMBISTFAIL,
764 * regardless of whether we continue or stop using the chip.
765 * We want that set so we know it failed, even across driver reload.
766 * We'll still ignore it in the hwerrmask. We do this partly for
767 * diagnostics, but also for support */
768 qib_write_kreg(dd, kr_hwerrclear,
769 hwerrs & ~HWE_MASK(PowerOnBISTFailed));
771 hwerrs &= dd->cspec->hwerrmask;
774 * Make sure we get this much out, unless told to be quiet,
775 * or it's occurred within the last 5 seconds.
777 if (hwerrs & ~(TXE_PIO_PARITY | RXEMEMPARITYERR_EAGERTID))
778 qib_devinfo(dd->pcidev,
779 "Hardware error: hwerr=0x%llx (cleared)\n",
780 (unsigned long long) hwerrs);
782 if (hwerrs & ~IB_HWE_BITSEXTANT)
784 "hwerror interrupt with unknown errors %llx set\n",
785 (unsigned long long)(hwerrs & ~IB_HWE_BITSEXTANT));
787 ctrl = qib_read_kreg32(dd, kr_control);
788 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
790 * Parity errors in send memory are recoverable,
791 * just cancel the send (if indicated in * sendbuffererror),
792 * count the occurrence, unfreeze (if no other handled
793 * hardware error bits are set), and continue. They can
794 * occur if a processor speculative read is done to the PIO
795 * buffer while we are sending a packet, for example.
797 if (hwerrs & TXE_PIO_PARITY) {
798 qib_6120_txe_recover(dd);
799 hwerrs &= ~TXE_PIO_PARITY;
803 static u32 freeze_cnt;
806 qib_6120_clear_freeze(dd);
813 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
816 "[Memory BIST test failed, InfiniPath hardware unusable]",
818 /* ignore from now on, so disable until driver reloaded */
819 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
820 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
823 qib_format_hwerrors(hwerrs, qib_6120_hwerror_msgs,
824 ARRAY_SIZE(qib_6120_hwerror_msgs), msg, msgl);
826 bitsmsg = dd->cspec->bitsmsgbuf;
827 if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
828 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
829 bits = (u32) ((hwerrs >>
830 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
831 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
832 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf),
833 "[PCIe Mem Parity Errs %x] ", bits);
834 strlcat(msg, bitsmsg, msgl);
837 if (hwerrs & _QIB_PLL_FAIL) {
839 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf),
840 "[PLL failed (%llx), InfiniPath hardware unusable]",
841 (unsigned long long) hwerrs & _QIB_PLL_FAIL);
842 strlcat(msg, bitsmsg, msgl);
843 /* ignore from now on, so disable until driver reloaded */
844 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
845 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
848 if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
850 * If it occurs, it is left masked since the external
851 * interface is unused
853 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
854 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
859 * if any set that we aren't ignoring; only
860 * make the complaint once, in case it's stuck
861 * or recurring, and we get here multiple
864 qib_dev_err(dd, "%s hardware error\n", msg);
866 *msg = 0; /* recovered from all of them */
868 if (isfatal && !dd->diag_client) {
870 "Fatal Hardware Error, no longer usable, SN %.16s\n",
873 * for /sys status file and user programs to print; if no
874 * trailing brace is copied, we'll know it was truncated.
877 snprintf(dd->freezemsg, dd->freezelen,
879 qib_disable_after_error(dd);
884 * Decode the error status into strings, deciding whether to always
885 * print * it or not depending on "normal packet errors" vs everything
886 * else. Return 1 if "real" errors, otherwise 0 if only packet
887 * errors, so caller can decide what to print with the string.
889 static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen,
895 if (err & QLOGIC_IB_E_PKTERRS) {
896 if (!(err & ~QLOGIC_IB_E_PKTERRS))
898 if ((err & ERR_MASK(RcvICRCErr)) &&
899 !(err&(ERR_MASK(RcvVCRCErr)|ERR_MASK(RcvEBPErr))))
900 strlcat(buf, "CRC ", blen);
904 if (err & ERR_MASK(RcvHdrLenErr))
905 strlcat(buf, "rhdrlen ", blen);
906 if (err & ERR_MASK(RcvBadTidErr))
907 strlcat(buf, "rbadtid ", blen);
908 if (err & ERR_MASK(RcvBadVersionErr))
909 strlcat(buf, "rbadversion ", blen);
910 if (err & ERR_MASK(RcvHdrErr))
911 strlcat(buf, "rhdr ", blen);
912 if (err & ERR_MASK(RcvLongPktLenErr))
913 strlcat(buf, "rlongpktlen ", blen);
914 if (err & ERR_MASK(RcvMaxPktLenErr))
915 strlcat(buf, "rmaxpktlen ", blen);
916 if (err & ERR_MASK(RcvMinPktLenErr))
917 strlcat(buf, "rminpktlen ", blen);
918 if (err & ERR_MASK(SendMinPktLenErr))
919 strlcat(buf, "sminpktlen ", blen);
920 if (err & ERR_MASK(RcvFormatErr))
921 strlcat(buf, "rformaterr ", blen);
922 if (err & ERR_MASK(RcvUnsupportedVLErr))
923 strlcat(buf, "runsupvl ", blen);
924 if (err & ERR_MASK(RcvUnexpectedCharErr))
925 strlcat(buf, "runexpchar ", blen);
926 if (err & ERR_MASK(RcvIBFlowErr))
927 strlcat(buf, "ribflow ", blen);
928 if (err & ERR_MASK(SendUnderRunErr))
929 strlcat(buf, "sunderrun ", blen);
930 if (err & ERR_MASK(SendPioArmLaunchErr))
931 strlcat(buf, "spioarmlaunch ", blen);
932 if (err & ERR_MASK(SendUnexpectedPktNumErr))
933 strlcat(buf, "sunexperrpktnum ", blen);
934 if (err & ERR_MASK(SendDroppedSmpPktErr))
935 strlcat(buf, "sdroppedsmppkt ", blen);
936 if (err & ERR_MASK(SendMaxPktLenErr))
937 strlcat(buf, "smaxpktlen ", blen);
938 if (err & ERR_MASK(SendUnsupportedVLErr))
939 strlcat(buf, "sunsupVL ", blen);
940 if (err & ERR_MASK(InvalidAddrErr))
941 strlcat(buf, "invalidaddr ", blen);
942 if (err & ERR_MASK(RcvEgrFullErr))
943 strlcat(buf, "rcvegrfull ", blen);
944 if (err & ERR_MASK(RcvHdrFullErr))
945 strlcat(buf, "rcvhdrfull ", blen);
946 if (err & ERR_MASK(IBStatusChanged))
947 strlcat(buf, "ibcstatuschg ", blen);
948 if (err & ERR_MASK(RcvIBLostLinkErr))
949 strlcat(buf, "riblostlink ", blen);
950 if (err & ERR_MASK(HardwareErr))
951 strlcat(buf, "hardware ", blen);
952 if (err & ERR_MASK(ResetNegated))
953 strlcat(buf, "reset ", blen);
959 * Called when we might have an error that is specific to a particular
960 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
962 static void qib_disarm_6120_senderrbufs(struct qib_pportdata *ppd)
964 unsigned long sbuf[2];
965 struct qib_devdata *dd = ppd->dd;
968 * It's possible that sendbuffererror could have bits set; might
969 * have already done this as a result of hardware error handling.
971 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
972 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
974 if (sbuf[0] || sbuf[1])
975 qib_disarm_piobufs_set(dd, sbuf,
976 dd->piobcnt2k + dd->piobcnt4k);
979 static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs)
982 u32 ibstate = qib_6120_iblink_state(ibcs);
983 u32 linkrecov = read_6120_creg32(dd, cr_iblinkerrrecov);
985 if (linkrecov != dd->cspec->lastlinkrecov) {
986 /* and no more until active again */
987 dd->cspec->lastlinkrecov = 0;
988 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN);
991 if (ibstate == IB_PORT_ACTIVE)
992 dd->cspec->lastlinkrecov =
993 read_6120_creg32(dd, cr_iblinkerrrecov);
997 static void handle_6120_errors(struct qib_devdata *dd, u64 errs)
1000 u64 ignore_this_time = 0;
1002 struct qib_pportdata *ppd = dd->pport;
1005 /* don't report errors that are masked */
1006 errs &= dd->cspec->errormask;
1007 msg = dd->cspec->emsgbuf;
1009 /* do these first, they are most important */
1010 if (errs & ERR_MASK(HardwareErr))
1011 qib_handle_6120_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1013 if (errs & ~IB_E_BITSEXTANT)
1015 "error interrupt with unknown errors %llx set\n",
1016 (unsigned long long) (errs & ~IB_E_BITSEXTANT));
1018 if (errs & E_SUM_ERRS) {
1019 qib_disarm_6120_senderrbufs(ppd);
1020 if ((errs & E_SUM_LINK_PKTERRS) &&
1021 !(ppd->lflags & QIBL_LINKACTIVE)) {
1023 * This can happen when trying to bring the link
1024 * up, but the IB link changes state at the "wrong"
1025 * time. The IB logic then complains that the packet
1026 * isn't valid. We don't want to confuse people, so
1027 * we just don't print them, except at debug
1029 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1031 } else if ((errs & E_SUM_LINK_PKTERRS) &&
1032 !(ppd->lflags & QIBL_LINKACTIVE)) {
1034 * This can happen when SMA is trying to bring the link
1035 * up, but the IB link changes state at the "wrong" time.
1036 * The IB logic then complains that the packet isn't
1037 * valid. We don't want to confuse people, so we just
1038 * don't print them, except at debug
1040 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1043 qib_write_kreg(dd, kr_errclear, errs);
1045 errs &= ~ignore_this_time;
1050 * The ones we mask off are handled specially below
1053 mask = ERR_MASK(IBStatusChanged) | ERR_MASK(RcvEgrFullErr) |
1054 ERR_MASK(RcvHdrFullErr) | ERR_MASK(HardwareErr);
1055 qib_decode_6120_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask);
1057 if (errs & E_SUM_PKTERRS)
1058 qib_stats.sps_rcverrs++;
1059 if (errs & E_SUM_ERRS)
1060 qib_stats.sps_txerrs++;
1062 iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS);
1064 if (errs & ERR_MASK(IBStatusChanged)) {
1065 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1066 u32 ibstate = qib_6120_iblink_state(ibcs);
1069 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov)
1070 handle = chk_6120_linkrecovery(dd, ibcs);
1072 * Since going into a recovery state causes the link state
1073 * to go down and since recovery is transitory, it is better
1074 * if we "miss" ever seeing the link training state go into
1075 * recovery (i.e., ignore this transition for link state
1076 * special handling purposes) without updating lastibcstat.
1078 if (handle && qib_6120_phys_portstate(ibcs) ==
1079 IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1082 qib_handle_e_ibstatuschanged(ppd, ibcs);
1085 if (errs & ERR_MASK(ResetNegated)) {
1087 "Got reset, requires re-init (unload and reload driver)\n");
1088 dd->flags &= ~QIB_INITTED; /* needs re-init */
1089 /* mark as having had error */
1090 *dd->devstatusp |= QIB_STATUS_HWERROR;
1091 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1095 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1097 if (ppd->state_wanted & ppd->lflags)
1098 wake_up_interruptible(&ppd->state_wait);
1101 * If there were hdrq or egrfull errors, wake up any processes
1102 * waiting in poll. We used to try to check which contexts had
1103 * the overflow, but given the cost of that and the chip reads
1104 * to support it, it's better to just wake everybody up if we
1105 * get an overflow; waiters can poll again if it's not them.
1107 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1108 qib_handle_urcv(dd, ~0U);
1109 if (errs & ERR_MASK(RcvEgrFullErr))
1110 qib_stats.sps_buffull++;
1112 qib_stats.sps_hdrfull++;
1119 * qib_6120_init_hwerrors - enable hardware errors
1120 * @dd: the qlogic_ib device
1122 * now that we have finished initializing everything that might reasonably
1123 * cause a hardware error, and cleared those errors bits as they occur,
1124 * we can enable hardware errors in the mask (potentially enabling
1125 * freeze mode), and enable hardware errors as errors (along with
1126 * everything else) in errormask
1128 static void qib_6120_init_hwerrors(struct qib_devdata *dd)
1133 extsval = qib_read_kreg64(dd, kr_extstatus);
1135 if (!(extsval & QLOGIC_IB_EXTS_MEMBIST_ENDTEST))
1136 qib_dev_err(dd, "MemBIST did not complete!\n");
1138 /* init so all hwerrors interrupt, and enter freeze, ajdust below */
1140 if (dd->minrev < 2) {
1142 * Avoid problem with internal interface bus parity
1143 * checking. Fixed in Rev2.
1145 val &= ~QLOGIC_IB_HWE_PCIEBUSPARITYRADM;
1147 /* avoid some intel cpu's speculative read freeze mode issue */
1148 val &= ~TXEMEMPARITYERR_PIOBUF;
1150 dd->cspec->hwerrmask = val;
1152 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1153 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1156 qib_write_kreg(dd, kr_errclear, ~0ULL);
1157 /* enable errors that are masked, at least this first time. */
1158 qib_write_kreg(dd, kr_errmask, ~0ULL);
1159 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1160 /* clear any interrupts up to this point (ints still not enabled) */
1161 qib_write_kreg(dd, kr_intclear, ~0ULL);
1163 qib_write_kreg(dd, kr_rcvbthqp,
1164 dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) |
1169 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
1170 * on chips that are count-based, rather than trigger-based. There is no
1171 * reference counting, but that's also fine, given the intended use.
1172 * Only chip-specific because it's all register accesses
1174 static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable)
1177 qib_write_kreg(dd, kr_errclear,
1178 ERR_MASK(SendPioArmLaunchErr));
1179 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1181 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1182 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1186 * Formerly took parameter <which> in pre-shifted,
1187 * pre-merged form with LinkCmd and LinkInitCmd
1188 * together, and assuming the zero was NOP.
1190 static void qib_set_ib_6120_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1194 struct qib_devdata *dd = ppd->dd;
1195 unsigned long flags;
1197 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1199 * If we are told to disable, note that so link-recovery
1200 * code does not attempt to bring us back up.
1202 spin_lock_irqsave(&ppd->lflags_lock, flags);
1203 ppd->lflags |= QIBL_IB_LINK_DISABLED;
1204 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1205 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1207 * Any other linkinitcmd will lead to LINKDOWN and then
1208 * to INIT (if all is well), so clear flag to let
1209 * link-recovery code attempt to bring us back up.
1211 spin_lock_irqsave(&ppd->lflags_lock, flags);
1212 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1213 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1216 mod_wd = (linkcmd << QLOGIC_IB_IBCC_LINKCMD_SHIFT) |
1217 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1219 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd);
1220 /* write to chip to prevent back-to-back writes of control reg */
1221 qib_write_kreg(dd, kr_scratch, 0);
1225 * qib_6120_bringup_serdes - bring up the serdes
1226 * @dd: the qlogic_ib device
1228 static int qib_6120_bringup_serdes(struct qib_pportdata *ppd)
1230 struct qib_devdata *dd = ppd->dd;
1231 u64 val, config1, prev_val, hwstat, ibc;
1233 /* Put IBC in reset, sends disabled */
1234 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1235 qib_write_kreg(dd, kr_control, 0ULL);
1237 dd->cspec->ibdeltainprog = 1;
1238 dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr);
1239 dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov);
1241 /* flowcontrolwatermark is in units of KBytes */
1242 ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1244 * How often flowctrl sent. More or less in usecs; balance against
1245 * watermark value, so that in theory senders always get a flow
1246 * control update in time to not let the IB link go idle.
1248 ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1249 /* max error tolerance */
1250 dd->cspec->lli_thresh = 0xf;
1251 ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold);
1252 /* use "real" buffer space for */
1253 ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1254 /* IB credit flow control. */
1255 ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1257 * set initial max size pkt IBC will send, including ICRC; it's the
1258 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1260 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1261 dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1263 /* initially come up waiting for TS1, without sending anything. */
1264 val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1265 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1266 qib_write_kreg(dd, kr_ibcctrl, val);
1268 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1269 config1 = qib_read_kreg64(dd, kr_serdes_cfg1);
1272 * Force reset on, also set rxdetect enable. Must do before reading
1273 * serdesstatus at least for simulation, or some of the bits in
1274 * serdes status will come back as undefined and cause simulation
1277 val |= SYM_MASK(SerdesCfg0, ResetPLL) |
1278 SYM_MASK(SerdesCfg0, RxDetEnX) |
1279 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1280 SYM_MASK(SerdesCfg0, L1PwrDnB) |
1281 SYM_MASK(SerdesCfg0, L1PwrDnC) |
1282 SYM_MASK(SerdesCfg0, L1PwrDnD));
1283 qib_write_kreg(dd, kr_serdes_cfg0, val);
1284 /* be sure chip saw it */
1285 qib_read_kreg64(dd, kr_scratch);
1286 udelay(5); /* need pll reset set at least for a bit */
1288 * after PLL is reset, set the per-lane Resets and TxIdle and
1289 * clear the PLL reset and rxdetect (to get falling edge).
1290 * Leave L1PWR bits set (permanently)
1292 val &= ~(SYM_MASK(SerdesCfg0, RxDetEnX) |
1293 SYM_MASK(SerdesCfg0, ResetPLL) |
1294 (SYM_MASK(SerdesCfg0, L1PwrDnA) |
1295 SYM_MASK(SerdesCfg0, L1PwrDnB) |
1296 SYM_MASK(SerdesCfg0, L1PwrDnC) |
1297 SYM_MASK(SerdesCfg0, L1PwrDnD)));
1298 val |= (SYM_MASK(SerdesCfg0, ResetA) |
1299 SYM_MASK(SerdesCfg0, ResetB) |
1300 SYM_MASK(SerdesCfg0, ResetC) |
1301 SYM_MASK(SerdesCfg0, ResetD)) |
1302 SYM_MASK(SerdesCfg0, TxIdeEnX);
1303 qib_write_kreg(dd, kr_serdes_cfg0, val);
1304 /* be sure chip saw it */
1305 (void) qib_read_kreg64(dd, kr_scratch);
1306 /* need PLL reset clear for at least 11 usec before lane
1307 * resets cleared; give it a few more to be sure */
1309 val &= ~((SYM_MASK(SerdesCfg0, ResetA) |
1310 SYM_MASK(SerdesCfg0, ResetB) |
1311 SYM_MASK(SerdesCfg0, ResetC) |
1312 SYM_MASK(SerdesCfg0, ResetD)) |
1313 SYM_MASK(SerdesCfg0, TxIdeEnX));
1315 qib_write_kreg(dd, kr_serdes_cfg0, val);
1316 /* be sure chip saw it */
1317 (void) qib_read_kreg64(dd, kr_scratch);
1319 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1321 if (val & QLOGIC_IB_XGXS_RESET)
1322 val &= ~QLOGIC_IB_XGXS_RESET;
1323 if (SYM_FIELD(val, XGXSCfg, polarity_inv) != ppd->rx_pol_inv) {
1324 /* need to compensate for Tx inversion in partner */
1325 val &= ~SYM_MASK(XGXSCfg, polarity_inv);
1326 val |= (u64)ppd->rx_pol_inv << SYM_LSB(XGXSCfg, polarity_inv);
1328 if (val != prev_val)
1329 qib_write_kreg(dd, kr_xgxs_cfg, val);
1331 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1333 /* clear current and de-emphasis bits */
1334 config1 &= ~0x0ffffffff00ULL;
1335 /* set current to 20ma */
1336 config1 |= 0x00000000000ULL;
1337 /* set de-emphasis to -5.68dB */
1338 config1 |= 0x0cccc000000ULL;
1339 qib_write_kreg(dd, kr_serdes_cfg1, config1);
1341 /* base and port guid same for single port */
1342 ppd->guid = dd->base_guid;
1345 * the process of setting and un-resetting the serdes normally
1346 * causes a serdes PLL error, so check for that and clear it
1347 * here. Also clearr hwerr bit in errstatus, but not others.
1349 hwstat = qib_read_kreg64(dd, kr_hwerrstatus);
1351 /* should just have PLL, clear all set, in an case */
1352 qib_write_kreg(dd, kr_hwerrclear, hwstat);
1353 qib_write_kreg(dd, kr_errclear, ERR_MASK(HardwareErr));
1356 dd->control |= QLOGIC_IB_C_LINKENABLE;
1357 dd->control &= ~QLOGIC_IB_C_FREEZEMODE;
1358 qib_write_kreg(dd, kr_control, dd->control);
1364 * qib_6120_quiet_serdes - set serdes to txidle
1365 * @ppd: physical port of the qlogic_ib device
1366 * Called when driver is being unloaded
1368 static void qib_6120_quiet_serdes(struct qib_pportdata *ppd)
1370 struct qib_devdata *dd = ppd->dd;
1373 qib_set_ib_6120_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1376 dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1377 qib_write_kreg(dd, kr_control,
1378 dd->control | QLOGIC_IB_C_FREEZEMODE);
1380 if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta ||
1381 dd->cspec->ibdeltainprog) {
1384 /* enable counter writes */
1385 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1386 qib_write_kreg(dd, kr_hwdiagctrl,
1387 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1389 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) {
1390 val = read_6120_creg32(dd, cr_ibsymbolerr);
1391 if (dd->cspec->ibdeltainprog)
1392 val -= val - dd->cspec->ibsymsnap;
1393 val -= dd->cspec->ibsymdelta;
1394 write_6120_creg(dd, cr_ibsymbolerr, val);
1396 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) {
1397 val = read_6120_creg32(dd, cr_iblinkerrrecov);
1398 if (dd->cspec->ibdeltainprog)
1399 val -= val - dd->cspec->iblnkerrsnap;
1400 val -= dd->cspec->iblnkerrdelta;
1401 write_6120_creg(dd, cr_iblinkerrrecov, val);
1404 /* and disable counter writes */
1405 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1408 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1409 val |= SYM_MASK(SerdesCfg0, TxIdeEnX);
1410 qib_write_kreg(dd, kr_serdes_cfg0, val);
1414 * qib_6120_setup_setextled - set the state of the two external LEDs
1415 * @dd: the qlogic_ib device
1416 * @on: whether the link is up or not
1418 * The exact combo of LEDs if on is true is determined by looking
1421 * These LEDs indicate the physical and logical state of IB link.
1422 * For this chip (at least with recommended board pinouts), LED1
1423 * is Yellow (logical state) and LED2 is Green (physical state),
1425 * Note: We try to match the Mellanox HCA LED behavior as best
1426 * we can. Green indicates physical link state is OK (something is
1427 * plugged in, and we can train).
1428 * Amber indicates the link is logically up (ACTIVE).
1429 * Mellanox further blinks the amber LED to indicate data packet
1430 * activity, but we have no hardware support for that, so it would
1431 * require waking up every 10-20 msecs and checking the counters
1432 * on the chip, and then turning the LED off if appropriate. That's
1433 * visible overhead, so not something we will do.
1436 static void qib_6120_setup_setextled(struct qib_pportdata *ppd, u32 on)
1438 u64 extctl, val, lst, ltst;
1439 unsigned long flags;
1440 struct qib_devdata *dd = ppd->dd;
1443 * The diags use the LED to indicate diag info, so we leave
1444 * the external LED alone when the diags are running.
1446 if (dd->diag_client)
1449 /* Allow override of LED display for, e.g. Locating system in rack */
1450 if (ppd->led_override) {
1451 ltst = (ppd->led_override & QIB_LED_PHYS) ?
1452 IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1453 lst = (ppd->led_override & QIB_LED_LOG) ?
1454 IB_PORT_ACTIVE : IB_PORT_DOWN;
1456 val = qib_read_kreg64(dd, kr_ibcstatus);
1457 ltst = qib_6120_phys_portstate(val);
1458 lst = qib_6120_iblink_state(val);
1464 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1465 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1466 SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1468 if (ltst == IB_PHYSPORTSTATE_LINKUP)
1469 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1470 if (lst == IB_PORT_ACTIVE)
1471 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1472 dd->cspec->extctrl = extctl;
1473 qib_write_kreg(dd, kr_extctrl, extctl);
1474 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1478 * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff
1479 * @dd: the qlogic_ib device
1481 * This is called during driver unload.
1483 static void qib_6120_setup_cleanup(struct qib_devdata *dd)
1486 kfree(dd->cspec->cntrs);
1487 kfree(dd->cspec->portcntrs);
1488 if (dd->cspec->dummy_hdrq) {
1489 dma_free_coherent(&dd->pcidev->dev,
1490 ALIGN(dd->rcvhdrcnt *
1492 sizeof(u32), PAGE_SIZE),
1493 dd->cspec->dummy_hdrq,
1494 dd->cspec->dummy_hdrq_phys);
1495 dd->cspec->dummy_hdrq = NULL;
1499 static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint)
1501 unsigned long flags;
1503 spin_lock_irqsave(&dd->sendctrl_lock, flags);
1505 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail);
1507 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail);
1508 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1509 qib_write_kreg(dd, kr_scratch, 0ULL);
1510 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1514 * handle errors and unusual events first, separate function
1515 * to improve cache hits for fast path interrupt handling
1517 static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat)
1519 if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1520 qib_dev_err(dd, "interrupt with unknown interrupts %Lx set\n",
1521 istat & ~QLOGIC_IB_I_BITSEXTANT);
1523 if (istat & QLOGIC_IB_I_ERROR) {
1526 qib_stats.sps_errints++;
1527 estat = qib_read_kreg64(dd, kr_errstatus);
1529 qib_devinfo(dd->pcidev,
1530 "error interrupt (%Lx), but no error bits set!\n",
1532 handle_6120_errors(dd, estat);
1535 if (istat & QLOGIC_IB_I_GPIO) {
1540 * GPIO_3..5 on IBA6120 Rev2 chips indicate
1541 * errors that we need to count.
1543 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1544 /* First the error-counter case. */
1545 if (gpiostatus & GPIO_ERRINTR_MASK) {
1546 /* want to clear the bits we see asserted. */
1547 to_clear |= (gpiostatus & GPIO_ERRINTR_MASK);
1550 * Count appropriately, clear bits out of our copy,
1551 * as they have been "handled".
1553 if (gpiostatus & (1 << GPIO_RXUVL_BIT))
1554 dd->cspec->rxfc_unsupvl_errs++;
1555 if (gpiostatus & (1 << GPIO_OVRUN_BIT))
1556 dd->cspec->overrun_thresh_errs++;
1557 if (gpiostatus & (1 << GPIO_LLI_BIT))
1558 dd->cspec->lli_errs++;
1559 gpiostatus &= ~GPIO_ERRINTR_MASK;
1563 * Some unexpected bits remain. If they could have
1564 * caused the interrupt, complain and clear.
1565 * To avoid repetition of this condition, also clear
1566 * the mask. It is almost certainly due to error.
1568 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1571 * Also check that the chip reflects our shadow,
1572 * and report issues, If they caused the interrupt.
1573 * we will suppress by refreshing from the shadow.
1575 if (mask & gpiostatus) {
1576 to_clear |= (gpiostatus & mask);
1577 dd->cspec->gpio_mask &= ~(gpiostatus & mask);
1578 qib_write_kreg(dd, kr_gpio_mask,
1579 dd->cspec->gpio_mask);
1583 qib_write_kreg(dd, kr_gpio_clear, (u64) to_clear);
1587 static irqreturn_t qib_6120intr(int irq, void *data)
1589 struct qib_devdata *dd = data;
1591 u32 istat, ctxtrbits, rmask, crcs = 0;
1594 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1596 * This return value is not great, but we do not want the
1597 * interrupt core code to remove our interrupt handler
1598 * because we don't appear to be handling an interrupt
1599 * during a chip reset.
1605 istat = qib_read_kreg32(dd, kr_intstatus);
1607 if (unlikely(!istat)) {
1608 ret = IRQ_NONE; /* not our interrupt, or already handled */
1611 if (unlikely(istat == -1)) {
1612 qib_bad_intrstatus(dd);
1613 /* don't know if it was our interrupt or not */
1618 this_cpu_inc(*dd->int_counter);
1620 if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1621 QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1622 unlikely_6120_intr(dd, istat);
1625 * Clear the interrupt bits we found set, relatively early, so we
1626 * "know" know the chip will have seen this by the time we process
1627 * the queue, and will re-interrupt if necessary. The processor
1628 * itself won't take the interrupt again until we return.
1630 qib_write_kreg(dd, kr_intclear, istat);
1633 * Handle kernel receive queues before checking for pio buffers
1634 * available since receives can overflow; piobuf waiters can afford
1635 * a few extra cycles, since they were waiting anyway.
1638 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1639 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1641 rmask = (1U << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1642 (1U << QLOGIC_IB_I_RCVURG_SHIFT);
1643 for (i = 0; i < dd->first_user_ctxt; i++) {
1644 if (ctxtrbits & rmask) {
1645 ctxtrbits &= ~rmask;
1646 crcs += qib_kreceive(dd->rcd[i],
1647 &dd->cspec->lli_counter,
1653 u32 cntr = dd->cspec->lli_counter;
1657 if (cntr > dd->cspec->lli_thresh) {
1658 dd->cspec->lli_counter = 0;
1659 dd->cspec->lli_errs++;
1661 dd->cspec->lli_counter += cntr;
1668 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1669 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
1670 qib_handle_urcv(dd, ctxtrbits);
1674 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
1675 qib_ib_piobufavail(dd);
1683 * Set up our chip-specific interrupt handler
1684 * The interrupt type has already been setup, so
1685 * we just need to do the registration and error checking.
1687 static void qib_setup_6120_interrupt(struct qib_devdata *dd)
1692 * If the chip supports added error indication via GPIO pins,
1693 * enable interrupts on those bits so the interrupt routine
1694 * can count the events. Also set flag so interrupt routine
1695 * can know they are expected.
1697 if (SYM_FIELD(dd->revision, Revision_R,
1698 ChipRevMinor) > 1) {
1699 /* Rev2+ reports extra errors via internal GPIO pins */
1700 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK;
1701 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1704 ret = pci_request_irq(dd->pcidev, 0, qib_6120intr, NULL, dd,
1708 "Couldn't setup interrupt (irq=%d): %d\n",
1709 pci_irq_vector(dd->pcidev, 0), ret);
1713 * pe_boardname - fill in the board name
1714 * @dd: the qlogic_ib device
1716 * info is based on the board revision register
1718 static void pe_boardname(struct qib_devdata *dd)
1722 boardid = SYM_FIELD(dd->revision, Revision,
1727 dd->boardname = "InfiniPath_QLE7140";
1730 qib_dev_err(dd, "Unknown 6120 board with ID %u\n", boardid);
1731 dd->boardname = "Unknown_InfiniPath_6120";
1735 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2)
1737 "Unsupported InfiniPath hardware revision %u.%u!\n",
1738 dd->majrev, dd->minrev);
1740 snprintf(dd->boardversion, sizeof(dd->boardversion),
1741 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
1742 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
1743 (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch),
1744 dd->majrev, dd->minrev,
1745 (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW));
1749 * This routine sleeps, so it can only be called from user context, not
1750 * from interrupt context. If we need interrupt context, we can split
1751 * it into two routines.
1753 static int qib_6120_setup_reset(struct qib_devdata *dd)
1759 u8 int_line, clinesz;
1761 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
1763 /* Use ERROR so it shows up in logs, etc. */
1764 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
1766 /* no interrupts till re-initted */
1767 qib_6120_set_intr_state(dd, 0);
1769 dd->cspec->ibdeltainprog = 0;
1770 dd->cspec->ibsymdelta = 0;
1771 dd->cspec->iblnkerrdelta = 0;
1774 * Keep chip from being accessed until we are ready. Use
1775 * writeq() directly, to allow the write even though QIB_PRESENT
1778 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
1779 /* so we check interrupts work again */
1780 dd->z_int_counter = qib_int_counter(dd);
1781 val = dd->control | QLOGIC_IB_C_RESET;
1782 writeq(val, &dd->kregbase[kr_control]);
1783 mb(); /* prevent compiler re-ordering around actual reset */
1785 for (i = 1; i <= 5; i++) {
1787 * Allow MBIST, etc. to complete; longer on each retry.
1788 * We sometimes get machine checks from bus timeout if no
1789 * response, so for now, make it *really* long.
1791 msleep(1000 + (1 + i) * 2000);
1793 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
1796 * Use readq directly, so we don't need to mark it as PRESENT
1797 * until we get a successful indication that all is well.
1799 val = readq(&dd->kregbase[kr_revision]);
1800 if (val == dd->revision) {
1801 dd->flags |= QIB_PRESENT; /* it's back */
1802 ret = qib_reinit_intr(dd);
1806 ret = 0; /* failed */
1810 if (qib_pcie_params(dd, dd->lbus_width, NULL))
1812 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
1813 /* clear the reset error, init error/hwerror mask */
1814 qib_6120_init_hwerrors(dd);
1815 /* for Rev2 error interrupts; nop for rev 1 */
1816 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1817 /* clear the reset error, init error/hwerror mask */
1818 qib_6120_init_hwerrors(dd);
1824 * qib_6120_put_tid - write a TID in chip
1825 * @dd: the qlogic_ib device
1826 * @tidptr: pointer to the expected TID (in chip) to update
1827 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1829 * @pa: physical address of in memory buffer; tidinvalid if freeing
1831 * This exists as a separate routine to allow for special locking etc.
1832 * It's used for both the full cleanup on exit, as well as the normal
1833 * setup and teardown.
1835 static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
1836 u32 type, unsigned long pa)
1838 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1839 unsigned long flags;
1841 spinlock_t *tidlockp; /* select appropriate spinlock */
1846 if (pa != dd->tidinvalid) {
1847 if (pa & ((1U << 11) - 1)) {
1848 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1853 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1855 "Physical page address 0x%lx larger than supported\n",
1860 if (type == RCVHQ_RCV_TYPE_EAGER)
1861 pa |= dd->tidtemplate;
1862 else /* for now, always full 4KB page */
1867 * Avoid chip issue by writing the scratch register
1868 * before and after the TID, and with an io write barrier.
1869 * We use a spinlock around the writes, so they can't intermix
1870 * with other TID (eager or expected) writes (the chip problem
1871 * is triggered by back to back TID writes). Unfortunately, this
1872 * call can be done from interrupt level for the ctxt 0 eager TIDs,
1873 * so we have to use irqsave locks.
1876 * Assumes tidptr always > egrtidbase
1877 * if type == RCVHQ_RCV_TYPE_EAGER.
1879 tidx = tidptr - dd->egrtidbase;
1881 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt)
1882 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock;
1883 spin_lock_irqsave(tidlockp, flags);
1884 qib_write_kreg(dd, kr_scratch, 0xfeeddeaf);
1886 qib_write_kreg(dd, kr_scratch, 0xdeadbeef);
1888 spin_unlock_irqrestore(tidlockp, flags);
1892 * qib_6120_put_tid_2 - write a TID in chip, Revision 2 or higher
1893 * @dd: the qlogic_ib device
1894 * @tidptr: pointer to the expected TID (in chip) to update
1895 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0)
1897 * @pa: physical address of in memory buffer; tidinvalid if freeing
1899 * This exists as a separate routine to allow for selection of the
1900 * appropriate "flavor". The static calls in cleanup just use the
1901 * revision-agnostic form, as they are not performance critical.
1903 static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr,
1904 u32 type, unsigned long pa)
1906 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1911 if (pa != dd->tidinvalid) {
1912 if (pa & ((1U << 11) - 1)) {
1913 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
1918 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) {
1920 "Physical page address 0x%lx larger than supported\n",
1925 if (type == RCVHQ_RCV_TYPE_EAGER)
1926 pa |= dd->tidtemplate;
1927 else /* for now, always full 4KB page */
1936 * qib_6120_clear_tids - clear all TID entries for a context, expected and eager
1937 * @dd: the qlogic_ib device
1938 * @ctxt: the context
1940 * clear all TID entries for a context, expected and eager.
1941 * Used from qib_close(). On this chip, TIDs are only 32 bits,
1942 * not 64, but they are still on 64 bit boundaries, so tidbase
1943 * is declared as u64 * for the pointer math, even though we write 32 bits
1945 static void qib_6120_clear_tids(struct qib_devdata *dd,
1946 struct qib_ctxtdata *rcd)
1948 u64 __iomem *tidbase;
1949 unsigned long tidinv;
1953 if (!dd->kregbase || !rcd)
1958 tidinv = dd->tidinvalid;
1959 tidbase = (u64 __iomem *)
1960 ((char __iomem *)(dd->kregbase) +
1962 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
1964 for (i = 0; i < dd->rcvtidcnt; i++)
1965 /* use func pointer because could be one of two funcs */
1966 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1969 tidbase = (u64 __iomem *)
1970 ((char __iomem *)(dd->kregbase) +
1972 rcd->rcvegr_tid_base * sizeof(*tidbase));
1974 for (i = 0; i < rcd->rcvegrcnt; i++)
1975 /* use func pointer because could be one of two funcs */
1976 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1981 * qib_6120_tidtemplate - setup constants for TID updates
1982 * @dd: the qlogic_ib device
1984 * We setup stuff that we use a lot, to avoid calculating each time
1986 static void qib_6120_tidtemplate(struct qib_devdata *dd)
1988 u32 egrsize = dd->rcvegrbufsize;
1991 * For now, we always allocate 4KB buffers (at init) so we can
1992 * receive max size packets. We may want a module parameter to
1993 * specify 2KB or 4KB and/or make be per ctxt instead of per device
1994 * for those who want to reduce memory footprint. Note that the
1995 * rcvhdrentsize size must be large enough to hold the largest
1996 * IB header (currently 96 bytes) that we expect to handle (plus of
1997 * course the 2 dwords of RHF).
1999 if (egrsize == 2048)
2000 dd->tidtemplate = 1U << 29;
2001 else if (egrsize == 4096)
2002 dd->tidtemplate = 2U << 29;
2006 int __attribute__((weak)) qib_unordered_wc(void)
2012 * qib_6120_get_base_info - set chip-specific flags for user code
2013 * @rcd: the qlogic_ib ctxt
2014 * @kbase: qib_base_info pointer
2016 * We set the PCIE flag because the lower bandwidth on PCIe vs
2017 * HyperTransport can affect some user packet algorithms.
2019 static int qib_6120_get_base_info(struct qib_ctxtdata *rcd,
2020 struct qib_base_info *kinfo)
2022 if (qib_unordered_wc())
2023 kinfo->spi_runtime_flags |= QIB_RUNTIME_FORCE_WC_ORDER;
2025 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2026 QIB_RUNTIME_FORCE_PIOAVAIL | QIB_RUNTIME_PIO_REGSWAPPED;
2031 static struct qib_message_header *
2032 qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2034 return (struct qib_message_header *)
2035 &rhf_addr[sizeof(u64) / sizeof(u32)];
2038 static void qib_6120_config_ctxts(struct qib_devdata *dd)
2040 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt);
2041 if (qib_n_krcv_queues > 1) {
2042 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2043 if (dd->first_user_ctxt > dd->ctxtcnt)
2044 dd->first_user_ctxt = dd->ctxtcnt;
2045 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6;
2047 dd->first_user_ctxt = dd->num_pports;
2048 dd->n_krcv_queues = dd->first_user_ctxt;
2051 static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd,
2052 u32 updegr, u32 egrhd, u32 npkts)
2055 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2057 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2061 static u32 qib_6120_hdrqempty(struct qib_ctxtdata *rcd)
2065 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2066 if (rcd->rcvhdrtail_kvaddr)
2067 tail = qib_get_rcvhdrtail(rcd);
2069 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2070 return head == tail;
2074 * Used when we close any ctxt, for DMA already in flight
2075 * at close. Can't be done until we know hdrq size, so not
2076 * early in chip init.
2078 static void alloc_dummy_hdrq(struct qib_devdata *dd)
2080 dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev,
2081 dd->rcd[0]->rcvhdrq_size,
2082 &dd->cspec->dummy_hdrq_phys,
2083 GFP_ATOMIC | __GFP_COMP);
2084 if (!dd->cspec->dummy_hdrq) {
2085 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n");
2086 /* fallback to just 0'ing */
2087 dd->cspec->dummy_hdrq_phys = 0UL;
2092 * Modify the RCVCTRL register in chip-specific way. This
2093 * is a function because bit positions and (future) register
2094 * location is chip-specific, but the needed operations are
2095 * generic. <op> is a bit-mask because we often want to
2096 * do multiple modifications.
2098 static void rcvctrl_6120_mod(struct qib_pportdata *ppd, unsigned int op,
2101 struct qib_devdata *dd = ppd->dd;
2103 unsigned long flags;
2105 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2107 if (op & QIB_RCVCTRL_TAILUPD_ENB)
2108 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2109 if (op & QIB_RCVCTRL_TAILUPD_DIS)
2110 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT);
2111 if (op & QIB_RCVCTRL_PKEY_ENB)
2112 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2113 if (op & QIB_RCVCTRL_PKEY_DIS)
2114 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT);
2116 mask = (1ULL << dd->ctxtcnt) - 1;
2118 mask = (1ULL << ctxt);
2119 if (op & QIB_RCVCTRL_CTXT_ENB) {
2120 /* always done for specific ctxt */
2121 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2122 if (!(dd->flags & QIB_NODMA_RTAIL))
2123 dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT;
2124 /* Write these registers before the context is enabled. */
2125 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2126 dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2127 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2128 dd->rcd[ctxt]->rcvhdrq_phys);
2130 if (ctxt == 0 && !dd->cspec->dummy_hdrq)
2131 alloc_dummy_hdrq(dd);
2133 if (op & QIB_RCVCTRL_CTXT_DIS)
2134 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2135 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2136 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2137 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2138 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT);
2139 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2140 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2141 /* arm rcv interrupt */
2142 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2143 dd->rhdrhead_intr_off;
2144 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2146 if (op & QIB_RCVCTRL_CTXT_ENB) {
2148 * Init the context registers also; if we were
2149 * disabled, tail and head should both be zero
2150 * already from the enable, but since we don't
2151 * know, we have to do it explicitly.
2153 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2154 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2156 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2157 dd->rcd[ctxt]->head = val;
2158 /* If kctxt, interrupt on next receive. */
2159 if (ctxt < dd->first_user_ctxt)
2160 val |= dd->rhdrhead_intr_off;
2161 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2163 if (op & QIB_RCVCTRL_CTXT_DIS) {
2165 * Be paranoid, and never write 0's to these, just use an
2166 * unused page. Of course,
2167 * rcvhdraddr points to a large chunk of memory, so this
2168 * could still trash things, but at least it won't trash
2169 * page 0, and by disabling the ctxt, it should stop "soon",
2170 * even if a packet or two is in already in flight after we
2171 * disabled the ctxt. Only 6120 has this issue.
2174 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2175 dd->cspec->dummy_hdrq_phys);
2176 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2177 dd->cspec->dummy_hdrq_phys);
2181 for (i = 0; i < dd->cfgctxts; i++) {
2182 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2183 i, dd->cspec->dummy_hdrq_phys);
2184 qib_write_kreg_ctxt(dd, kr_rcvhdraddr,
2185 i, dd->cspec->dummy_hdrq_phys);
2189 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2193 * Modify the SENDCTRL register in chip-specific way. This
2194 * is a function there may be multiple such registers with
2195 * slightly different layouts. Only operations actually used
2196 * are implemented yet.
2197 * Chip requires no back-back sendctrl writes, so write
2198 * scratch register after writing sendctrl
2200 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op)
2202 struct qib_devdata *dd = ppd->dd;
2203 u64 tmp_dd_sendctrl;
2204 unsigned long flags;
2206 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2208 /* First the ones that are "sticky", saved in shadow */
2209 if (op & QIB_SENDCTRL_CLEAR)
2211 if (op & QIB_SENDCTRL_SEND_DIS)
2212 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable);
2213 else if (op & QIB_SENDCTRL_SEND_ENB)
2214 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable);
2215 if (op & QIB_SENDCTRL_AVAIL_DIS)
2216 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2217 else if (op & QIB_SENDCTRL_AVAIL_ENB)
2218 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd);
2220 if (op & QIB_SENDCTRL_DISARM_ALL) {
2223 tmp_dd_sendctrl = dd->sendctrl;
2225 * disarm any that are not yet launched, disabling sends
2226 * and updates until done.
2228 last = dd->piobcnt2k + dd->piobcnt4k;
2230 ~(SYM_MASK(SendCtrl, PIOEnable) |
2231 SYM_MASK(SendCtrl, PIOBufAvailUpd));
2232 for (i = 0; i < last; i++) {
2233 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl |
2234 SYM_MASK(SendCtrl, Disarm) | i);
2235 qib_write_kreg(dd, kr_scratch, 0);
2239 tmp_dd_sendctrl = dd->sendctrl;
2241 if (op & QIB_SENDCTRL_FLUSH)
2242 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2243 if (op & QIB_SENDCTRL_DISARM)
2244 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2245 ((op & QIB_6120_SendCtrl_DisarmPIOBuf_RMASK) <<
2246 SYM_LSB(SendCtrl, DisarmPIOBuf));
2247 if (op & QIB_SENDCTRL_AVAIL_BLIP)
2248 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd);
2250 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2251 qib_write_kreg(dd, kr_scratch, 0);
2253 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2254 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2255 qib_write_kreg(dd, kr_scratch, 0);
2258 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2260 if (op & QIB_SENDCTRL_FLUSH) {
2263 * ensure writes have hit chip, then do a few
2264 * more reads, to allow DMA of pioavail registers
2265 * to occur, so in-memory copy is in sync with
2266 * the chip. Not always safe to sleep.
2268 v = qib_read_kreg32(dd, kr_scratch);
2269 qib_write_kreg(dd, kr_scratch, v);
2270 v = qib_read_kreg32(dd, kr_scratch);
2271 qib_write_kreg(dd, kr_scratch, v);
2272 qib_read_kreg32(dd, kr_scratch);
2277 * qib_portcntr_6120 - read a per-port counter
2278 * @dd: the qlogic_ib device
2279 * @creg: the counter to snapshot
2281 static u64 qib_portcntr_6120(struct qib_pportdata *ppd, u32 reg)
2284 struct qib_devdata *dd = ppd->dd;
2286 /* 0xffff for unimplemented or synthesized counters */
2287 static const u16 xlator[] = {
2288 [QIBPORTCNTR_PKTSEND] = cr_pktsend,
2289 [QIBPORTCNTR_WORDSEND] = cr_wordsend,
2290 [QIBPORTCNTR_PSXMITDATA] = 0xffff,
2291 [QIBPORTCNTR_PSXMITPKTS] = 0xffff,
2292 [QIBPORTCNTR_PSXMITWAIT] = 0xffff,
2293 [QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2294 [QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2295 [QIBPORTCNTR_PSRCVDATA] = 0xffff,
2296 [QIBPORTCNTR_PSRCVPKTS] = 0xffff,
2297 [QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2298 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2299 [QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2300 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2301 [QIBPORTCNTR_RXLOCALPHYERR] = 0xffff,
2302 [QIBPORTCNTR_RXVLERR] = 0xffff,
2303 [QIBPORTCNTR_ERRICRC] = cr_erricrc,
2304 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2305 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2306 [QIBPORTCNTR_BADFORMAT] = cr_badformat,
2307 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2308 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2309 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2310 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2311 [QIBPORTCNTR_EXCESSBUFOVFL] = 0xffff,
2312 [QIBPORTCNTR_ERRLINK] = cr_errlink,
2313 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2314 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2315 [QIBPORTCNTR_LLI] = 0xffff,
2316 [QIBPORTCNTR_PSINTERVAL] = 0xffff,
2317 [QIBPORTCNTR_PSSTART] = 0xffff,
2318 [QIBPORTCNTR_PSSTAT] = 0xffff,
2319 [QIBPORTCNTR_VL15PKTDROP] = 0xffff,
2320 [QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2321 [QIBPORTCNTR_KHDROVFL] = 0xffff,
2324 if (reg >= ARRAY_SIZE(xlator)) {
2325 qib_devinfo(ppd->dd->pcidev,
2326 "Unimplemented portcounter %u\n", reg);
2331 /* handle counters requests not implemented as chip counters */
2332 if (reg == QIBPORTCNTR_LLI)
2333 ret = dd->cspec->lli_errs;
2334 else if (reg == QIBPORTCNTR_EXCESSBUFOVFL)
2335 ret = dd->cspec->overrun_thresh_errs;
2336 else if (reg == QIBPORTCNTR_KHDROVFL) {
2339 /* sum over all kernel contexts */
2340 for (i = 0; i < dd->first_user_ctxt; i++)
2341 ret += read_6120_creg32(dd, cr_portovfl + i);
2342 } else if (reg == QIBPORTCNTR_PSSTAT)
2343 ret = dd->cspec->pma_sample_status;
2348 * only fast incrementing counters are 64bit; use 32 bit reads to
2349 * avoid two independent reads when on opteron
2351 if (creg == cr_wordsend || creg == cr_wordrcv ||
2352 creg == cr_pktsend || creg == cr_pktrcv)
2353 ret = read_6120_creg(dd, creg);
2355 ret = read_6120_creg32(dd, creg);
2356 if (creg == cr_ibsymbolerr) {
2357 if (dd->cspec->ibdeltainprog)
2358 ret -= ret - dd->cspec->ibsymsnap;
2359 ret -= dd->cspec->ibsymdelta;
2360 } else if (creg == cr_iblinkerrrecov) {
2361 if (dd->cspec->ibdeltainprog)
2362 ret -= ret - dd->cspec->iblnkerrsnap;
2363 ret -= dd->cspec->iblnkerrdelta;
2365 if (reg == QIBPORTCNTR_RXDROPPKT) /* add special cased count */
2366 ret += dd->cspec->rxfc_unsupvl_errs;
2373 * Device counter names (not port-specific), one line per stat,
2374 * single string. Used by utilities like ipathstats to print the stats
2375 * in a way which works for different versions of drivers, without changing
2376 * the utility. Names need to be 12 chars or less (w/o newline), for proper
2377 * display by utility.
2378 * Non-error counters are first.
2379 * Start of "error" conters is indicated by a leading "E " on the first
2380 * "error" counter, and doesn't count in label length.
2381 * The EgrOvfl list needs to be last so we truncate them at the configured
2382 * context count for the device.
2383 * cntr6120indices contains the corresponding register indices.
2385 static const char cntr6120names[] =
2396 static const size_t cntr6120indices[] = {
2409 * same as cntr6120names and cntr6120indices, but for port-specific counters.
2410 * portcntr6120indices is somewhat complicated by some registers needing
2411 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
2413 static const char portcntr6120names[] =
2445 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
2446 static const size_t portcntr6120indices[] = {
2447 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
2449 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
2450 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
2452 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
2453 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
2455 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
2456 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
2457 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
2458 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
2459 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
2460 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
2461 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
2462 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
2463 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
2465 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
2466 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
2467 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
2468 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
2469 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
2470 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
2478 /* do all the setup to make the counter reads efficient later */
2479 static void init_6120_cntrnames(struct qib_devdata *dd)
2484 for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts;
2486 /* we always have at least one counter before the egrovfl */
2487 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
2489 s = strchr(s + 1, '\n');
2493 dd->cspec->ncntrs = i;
2495 /* full list; size is without terminating null */
2496 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1;
2498 dd->cspec->cntrnamelen = 1 + s - cntr6120names;
2499 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64),
2502 for (i = 0, s = (char *)portcntr6120names; s; i++)
2503 s = strchr(s + 1, '\n');
2504 dd->cspec->nportcntrs = i - 1;
2505 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1;
2506 dd->cspec->portcntrs = kmalloc_array(dd->cspec->nportcntrs,
2511 static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
2517 ret = dd->cspec->cntrnamelen;
2519 ret = 0; /* final read after getting everything */
2521 *namep = (char *)cntr6120names;
2523 u64 *cntr = dd->cspec->cntrs;
2526 ret = dd->cspec->ncntrs * sizeof(u64);
2527 if (!cntr || pos >= ret) {
2528 /* everything read, or couldn't get memory */
2533 ret = 0; /* final read after getting everything */
2537 for (i = 0; i < dd->cspec->ncntrs; i++)
2538 *cntr++ = read_6120_creg32(dd, cntr6120indices[i]);
2544 static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
2545 char **namep, u64 **cntrp)
2550 ret = dd->cspec->portcntrnamelen;
2552 ret = 0; /* final read after getting everything */
2554 *namep = (char *)portcntr6120names;
2556 u64 *cntr = dd->cspec->portcntrs;
2557 struct qib_pportdata *ppd = &dd->pport[port];
2560 ret = dd->cspec->nportcntrs * sizeof(u64);
2561 if (!cntr || pos >= ret) {
2562 /* everything read, or couldn't get memory */
2567 for (i = 0; i < dd->cspec->nportcntrs; i++) {
2568 if (portcntr6120indices[i] & _PORT_VIRT_FLAG)
2569 *cntr++ = qib_portcntr_6120(ppd,
2570 portcntr6120indices[i] &
2573 *cntr++ = read_6120_creg32(dd,
2574 portcntr6120indices[i]);
2581 static void qib_chk_6120_errormask(struct qib_devdata *dd)
2585 unsigned long errormask;
2586 unsigned long hwerrs;
2588 if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED))
2591 errormask = qib_read_kreg64(dd, kr_errmask);
2593 if (errormask == dd->cspec->errormask)
2597 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2598 ctrl = qib_read_kreg32(dd, kr_control);
2600 qib_write_kreg(dd, kr_errmask,
2601 dd->cspec->errormask);
2603 if ((hwerrs & dd->cspec->hwerrmask) ||
2604 (ctrl & QLOGIC_IB_C_FREEZEMODE)) {
2605 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2606 qib_write_kreg(dd, kr_errclear, 0ULL);
2607 /* force re-interrupt of pending events, just in case */
2608 qib_write_kreg(dd, kr_intclear, 0ULL);
2609 qib_devinfo(dd->pcidev,
2610 "errormask fixed(%u) %lx->%lx, ctrl %x hwerr %lx\n",
2611 fixed, errormask, (unsigned long)dd->cspec->errormask,
2617 * qib_get_faststats - get word counters from chip before they overflow
2618 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
2620 * This needs more work; in particular, decision on whether we really
2621 * need traffic_wds done the way it is
2622 * called from add_timer
2624 static void qib_get_6120_faststats(struct timer_list *t)
2626 struct qib_devdata *dd = from_timer(dd, t, stats_timer);
2627 struct qib_pportdata *ppd = dd->pport;
2628 unsigned long flags;
2632 * don't access the chip while running diags, or memory diags can
2635 if (!(dd->flags & QIB_INITTED) || dd->diag_client)
2636 /* but re-arm the timer, for diags case; won't hurt other */
2640 * We now try to maintain an activity timer, based on traffic
2641 * exceeding a threshold, so we need to check the word-counts
2642 * even if they are 64-bit.
2644 traffic_wds = qib_portcntr_6120(ppd, cr_wordsend) +
2645 qib_portcntr_6120(ppd, cr_wordrcv);
2646 spin_lock_irqsave(&dd->eep_st_lock, flags);
2647 traffic_wds -= dd->traffic_wds;
2648 dd->traffic_wds += traffic_wds;
2649 spin_unlock_irqrestore(&dd->eep_st_lock, flags);
2651 qib_chk_6120_errormask(dd);
2653 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
2656 /* no interrupt fallback for these chips */
2657 static int qib_6120_nointr_fallback(struct qib_devdata *dd)
2663 * reset the XGXS (between serdes and IBC). Slightly less intrusive
2664 * than resetting the IBC or external link state, and useful in some
2665 * cases to cause some retraining. To do this right, we reset IBC
2668 static void qib_6120_xgxs_reset(struct qib_pportdata *ppd)
2671 struct qib_devdata *dd = ppd->dd;
2673 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
2674 val = prev_val | QLOGIC_IB_XGXS_RESET;
2675 prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */
2676 qib_write_kreg(dd, kr_control,
2677 dd->control & ~QLOGIC_IB_C_LINKENABLE);
2678 qib_write_kreg(dd, kr_xgxs_cfg, val);
2679 qib_read_kreg32(dd, kr_scratch);
2680 qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
2681 qib_write_kreg(dd, kr_control, dd->control);
2684 static int qib_6120_get_ib_cfg(struct qib_pportdata *ppd, int which)
2689 case QIB_IB_CFG_LWID:
2690 ret = ppd->link_width_active;
2693 case QIB_IB_CFG_SPD:
2694 ret = ppd->link_speed_active;
2697 case QIB_IB_CFG_LWID_ENB:
2698 ret = ppd->link_width_enabled;
2701 case QIB_IB_CFG_SPD_ENB:
2702 ret = ppd->link_speed_enabled;
2705 case QIB_IB_CFG_OP_VLS:
2706 ret = ppd->vls_operational;
2709 case QIB_IB_CFG_VL_HIGH_CAP:
2713 case QIB_IB_CFG_VL_LOW_CAP:
2717 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2718 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2722 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2723 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl,
2727 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2728 /* will only take effect when the link state changes */
2729 ret = (ppd->dd->cspec->ibcctrl &
2730 SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2731 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2734 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2735 ret = 0; /* no heartbeat on this chip */
2738 case QIB_IB_CFG_PMA_TICKS:
2739 ret = 250; /* 1 usec. */
2750 * We assume range checking is already done, if needed.
2752 static int qib_6120_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2754 struct qib_devdata *dd = ppd->dd;
2760 case QIB_IB_CFG_LWID_ENB:
2761 ppd->link_width_enabled = val;
2764 case QIB_IB_CFG_SPD_ENB:
2765 ppd->link_speed_enabled = val;
2768 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2769 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2772 dd->cspec->ibcctrl &=
2773 ~SYM_MASK(IBCCtrl, OverrunThreshold);
2774 dd->cspec->ibcctrl |= (u64) val <<
2775 SYM_LSB(IBCCtrl, OverrunThreshold);
2776 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2777 qib_write_kreg(dd, kr_scratch, 0);
2781 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2782 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl,
2785 dd->cspec->ibcctrl &=
2786 ~SYM_MASK(IBCCtrl, PhyerrThreshold);
2787 dd->cspec->ibcctrl |= (u64) val <<
2788 SYM_LSB(IBCCtrl, PhyerrThreshold);
2789 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2790 qib_write_kreg(dd, kr_scratch, 0);
2794 case QIB_IB_CFG_PKEYS: /* update pkeys */
2795 val64 = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2796 ((u64) ppd->pkeys[2] << 32) |
2797 ((u64) ppd->pkeys[3] << 48);
2798 qib_write_kreg(dd, kr_partitionkey, val64);
2801 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2802 /* will only take effect when the link state changes */
2803 if (val == IB_LINKINITCMD_POLL)
2804 dd->cspec->ibcctrl &=
2805 ~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2807 dd->cspec->ibcctrl |=
2808 SYM_MASK(IBCCtrl, LinkDownDefaultState);
2809 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2810 qib_write_kreg(dd, kr_scratch, 0);
2813 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
2815 * Update our housekeeping variables, and set IBC max
2816 * size, same as init code; max IBC is max we allow in
2817 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2818 * Set even if it's unchanged, print debug message only
2821 val = (ppd->ibmaxlen >> 2) + 1;
2822 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2823 dd->cspec->ibcctrl |= (u64)val <<
2824 SYM_LSB(IBCCtrl, MaxPktLen);
2825 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl);
2826 qib_write_kreg(dd, kr_scratch, 0);
2829 case QIB_IB_CFG_LSTATE: /* set the IB link state */
2830 switch (val & 0xffff0000) {
2831 case IB_LINKCMD_DOWN:
2832 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2833 if (!dd->cspec->ibdeltainprog) {
2834 dd->cspec->ibdeltainprog = 1;
2835 dd->cspec->ibsymsnap =
2836 read_6120_creg32(dd, cr_ibsymbolerr);
2837 dd->cspec->iblnkerrsnap =
2838 read_6120_creg32(dd, cr_iblinkerrrecov);
2842 case IB_LINKCMD_ARMED:
2843 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2846 case IB_LINKCMD_ACTIVE:
2847 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2852 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2855 switch (val & 0xffff) {
2856 case IB_LINKINITCMD_NOP:
2860 case IB_LINKINITCMD_POLL:
2861 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2864 case IB_LINKINITCMD_SLEEP:
2865 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2868 case IB_LINKINITCMD_DISABLE:
2869 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2874 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2878 qib_set_ib_6120_lstate(ppd, lcmd, licmd);
2881 case QIB_IB_CFG_HRTBT:
2892 static int qib_6120_set_loopback(struct qib_pportdata *ppd, const char *what)
2896 if (!strncmp(what, "ibc", 3)) {
2897 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2898 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2899 ppd->dd->unit, ppd->port);
2900 } else if (!strncmp(what, "off", 3)) {
2901 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2902 qib_devinfo(ppd->dd->pcidev,
2903 "Disabling IB%u:%u IBC loopback (normal)\n",
2904 ppd->dd->unit, ppd->port);
2908 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl);
2909 qib_write_kreg(ppd->dd, kr_scratch, 0);
2914 static void pma_6120_timer(struct timer_list *t)
2916 struct qib_chip_specific *cs = from_timer(cs, t, pma_timer);
2917 struct qib_pportdata *ppd = cs->ppd;
2918 struct qib_ibport *ibp = &ppd->ibport_data;
2919 unsigned long flags;
2921 spin_lock_irqsave(&ibp->rvp.lock, flags);
2922 if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_STARTED) {
2923 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2924 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2925 &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2926 mod_timer(&cs->pma_timer,
2927 jiffies + usecs_to_jiffies(ibp->rvp.pma_sample_interval));
2928 } else if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_RUNNING) {
2929 u64 ta, tb, tc, td, te;
2931 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2932 qib_snapshot_counters(ppd, &ta, &tb, &tc, &td, &te);
2934 cs->sword = ta - cs->sword;
2935 cs->rword = tb - cs->rword;
2936 cs->spkts = tc - cs->spkts;
2937 cs->rpkts = td - cs->rpkts;
2938 cs->xmit_wait = te - cs->xmit_wait;
2940 spin_unlock_irqrestore(&ibp->rvp.lock, flags);
2944 * Note that the caller has the ibp->rvp.lock held.
2946 static void qib_set_cntr_6120_sample(struct qib_pportdata *ppd, u32 intv,
2949 struct qib_chip_specific *cs = ppd->dd->cspec;
2951 if (start && intv) {
2952 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_STARTED;
2953 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(start));
2955 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
2956 qib_snapshot_counters(ppd, &cs->sword, &cs->rword,
2957 &cs->spkts, &cs->rpkts, &cs->xmit_wait);
2958 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(intv));
2960 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
2969 static u32 qib_6120_iblink_state(u64 ibcs)
2971 u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
2974 case IB_6120_L_STATE_INIT:
2975 state = IB_PORT_INIT;
2977 case IB_6120_L_STATE_ARM:
2978 state = IB_PORT_ARMED;
2980 case IB_6120_L_STATE_ACTIVE:
2982 case IB_6120_L_STATE_ACT_DEFER:
2983 state = IB_PORT_ACTIVE;
2985 default: /* fall through */
2986 case IB_6120_L_STATE_DOWN:
2987 state = IB_PORT_DOWN;
2993 /* returns the IBTA port state, rather than the IBC link training state */
2994 static u8 qib_6120_phys_portstate(u64 ibcs)
2996 u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
2997 return qib_6120_physportstate[state];
3000 static int qib_6120_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
3002 unsigned long flags;
3004 spin_lock_irqsave(&ppd->lflags_lock, flags);
3005 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3006 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3009 if (ppd->dd->cspec->ibdeltainprog) {
3010 ppd->dd->cspec->ibdeltainprog = 0;
3011 ppd->dd->cspec->ibsymdelta +=
3012 read_6120_creg32(ppd->dd, cr_ibsymbolerr) -
3013 ppd->dd->cspec->ibsymsnap;
3014 ppd->dd->cspec->iblnkerrdelta +=
3015 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) -
3016 ppd->dd->cspec->iblnkerrsnap;
3020 ppd->dd->cspec->lli_counter = 0;
3021 if (!ppd->dd->cspec->ibdeltainprog) {
3022 ppd->dd->cspec->ibdeltainprog = 1;
3023 ppd->dd->cspec->ibsymsnap =
3024 read_6120_creg32(ppd->dd, cr_ibsymbolerr);
3025 ppd->dd->cspec->iblnkerrsnap =
3026 read_6120_creg32(ppd->dd, cr_iblinkerrrecov);
3031 qib_6120_setup_setextled(ppd, ibup);
3036 /* Does read/modify/write to appropriate registers to
3037 * set output and direction bits selected by mask.
3038 * these are in their canonical postions (e.g. lsb of
3039 * dir will end up in D48 of extctrl on existing chips).
3040 * returns contents of GP Inputs.
3042 static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3044 u64 read_val, new_out;
3045 unsigned long flags;
3048 /* some bits being written, lock access to GPIO */
3051 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3052 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3053 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3054 new_out = (dd->cspec->gpio_out & ~mask) | out;
3056 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3057 qib_write_kreg(dd, kr_gpio_out, new_out);
3058 dd->cspec->gpio_out = new_out;
3059 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3062 * It is unlikely that a read at this time would get valid
3063 * data on a pin whose direction line was set in the same
3064 * call to this function. We include the read here because
3065 * that allows us to potentially combine a change on one pin with
3066 * a read on another, and because the old code did something like
3069 read_val = qib_read_kreg64(dd, kr_extstatus);
3070 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3074 * Read fundamental info we need to use the chip. These are
3075 * the registers that describe chip capabilities, and are
3076 * saved in shadow registers.
3078 static void get_6120_chip_params(struct qib_devdata *dd)
3084 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3086 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3087 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3088 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3089 dd->palign = qib_read_kreg32(dd, kr_palign);
3090 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3091 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3093 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3095 val = qib_read_kreg64(dd, kr_sendpiosize);
3096 dd->piosize2k = val & ~0U;
3097 dd->piosize4k = val >> 32;
3099 mtu = ib_mtu_enum_to_int(qib_ibmtu);
3101 mtu = QIB_DEFAULT_MTU;
3102 dd->pport->ibmtu = (u32)mtu;
3104 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3105 dd->piobcnt2k = val & ~0U;
3106 dd->piobcnt4k = val >> 32;
3107 dd->last_pio = dd->piobcnt4k + dd->piobcnt2k - 1;
3108 /* these may be adjusted in init_chip_wc_pat() */
3109 dd->pio2kbase = (u32 __iomem *)
3110 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase);
3111 if (dd->piobcnt4k) {
3112 dd->pio4kbase = (u32 __iomem *)
3113 (((char __iomem *) dd->kregbase) +
3114 (dd->piobufbase >> 32));
3116 * 4K buffers take 2 pages; we use roundup just to be
3117 * paranoid; we calculate it once here, rather than on
3120 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3123 piobufs = dd->piobcnt4k + dd->piobcnt2k;
3125 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3126 (sizeof(u64) * BITS_PER_BYTE / 2);
3130 * The chip base addresses in cspec and cpspec have to be set
3131 * after possible init_chip_wc_pat(), rather than in
3132 * get_6120_chip_params(), so split out as separate function
3134 static void set_6120_baseaddrs(struct qib_devdata *dd)
3138 cregbase = qib_read_kreg32(dd, kr_counterregbase);
3139 dd->cspec->cregbase = (u64 __iomem *)
3140 ((char __iomem *) dd->kregbase + cregbase);
3142 dd->egrtidbase = (u64 __iomem *)
3143 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
3147 * Write the final few registers that depend on some of the
3148 * init setup. Done late in init, just before bringing up
3151 static int qib_late_6120_initreg(struct qib_devdata *dd)
3156 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3157 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3158 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3159 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3160 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3161 if (val != dd->pioavailregs_phys) {
3163 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
3164 (unsigned long) dd->pioavailregs_phys,
3165 (unsigned long long) val);
3171 static int init_6120_variables(struct qib_devdata *dd)
3174 struct qib_pportdata *ppd;
3177 ppd = (struct qib_pportdata *)(dd + 1);
3181 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports);
3182 dd->cspec->ppd = ppd;
3183 ppd->cpspec = NULL; /* not used in this chip */
3185 spin_lock_init(&dd->cspec->kernel_tid_lock);
3186 spin_lock_init(&dd->cspec->user_tid_lock);
3187 spin_lock_init(&dd->cspec->rcvmod_lock);
3188 spin_lock_init(&dd->cspec->gpio_lock);
3190 /* we haven't yet set QIB_PRESENT, so use read directly */
3191 dd->revision = readq(&dd->kregbase[kr_revision]);
3193 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
3195 "Revision register read failure, giving up initialization\n");
3199 dd->flags |= QIB_PRESENT; /* now register routines work */
3201 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3203 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
3206 get_6120_chip_params(dd);
3207 pe_boardname(dd); /* fill in boardname */
3210 * GPIO bits for TWSI data and clock,
3211 * used for serial EEPROM.
3213 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
3214 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
3215 dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV;
3217 if (qib_unordered_wc())
3218 dd->flags |= QIB_PIO_FLUSH_WC;
3220 ret = qib_init_pportdata(ppd, dd, 0, 1);
3223 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
3224 ppd->link_speed_supported = QIB_IB_SDR;
3225 ppd->link_width_enabled = IB_WIDTH_4X;
3226 ppd->link_speed_enabled = ppd->link_speed_supported;
3227 /* these can't change for this chip, so set once */
3228 ppd->link_width_active = ppd->link_width_enabled;
3229 ppd->link_speed_active = ppd->link_speed_enabled;
3230 ppd->vls_supported = IB_VL_VL0;
3231 ppd->vls_operational = ppd->vls_supported;
3233 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
3234 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
3237 /* we always allocate at least 2048 bytes for eager buffers */
3238 ret = ib_mtu_enum_to_int(qib_ibmtu);
3239 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
3240 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
3242 qib_6120_tidtemplate(dd);
3245 * We can request a receive interrupt for 1 or
3246 * more packets from current offset. For now, we set this
3247 * up for a single packet.
3249 dd->rhdrhead_intr_off = 1ULL << 32;
3251 /* setup the stats timer; the add_timer is done at end of init */
3252 timer_setup(&dd->stats_timer, qib_get_6120_faststats, 0);
3253 timer_setup(&dd->cspec->pma_timer, pma_6120_timer, 0);
3255 dd->ureg_align = qib_read_kreg32(dd, kr_palign);
3257 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
3258 qib_6120_config_ctxts(dd);
3259 qib_set_ctxtcnt(dd);
3261 ret = init_chip_wc_pat(dd, 0);
3264 set_6120_baseaddrs(dd); /* set chip access pointers now */
3270 qib_num_cfg_vls = 1; /* if any 6120's, only one VL */
3272 ret = qib_create_ctxts(dd);
3273 init_6120_cntrnames(dd);
3275 /* use all of 4KB buffers for the kernel, otherwise 16 */
3276 sbufs = dd->piobcnt4k ? dd->piobcnt4k : 16;
3278 dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs;
3279 dd->pbufsctxt = dd->lastctxt_piobuf /
3280 (dd->cfgctxts - dd->first_user_ctxt);
3289 * For this chip, we want to use the same buffer every time
3290 * when we are trying to bring the link up (they are always VL15
3291 * packets). At that link state the packet should always go out immediately
3292 * (or at least be discarded at the tx interface if the link is down).
3293 * If it doesn't, and the buffer isn't available, that means some other
3294 * sender has gotten ahead of us, and is preventing our packet from going
3295 * out. In that case, we flush all packets, and try again. If that still
3296 * fails, we fail the request, and hope things work the next time around.
3298 * We don't need very complicated heuristics on whether the packet had
3299 * time to go out or not, since even at SDR 1X, it goes out in very short
3300 * time periods, covered by the chip reads done here and as part of the
3303 static u32 __iomem *get_6120_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3306 u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1;
3309 * always blip to get avail list updated, since it's almost
3310 * always needed, and is fairly cheap.
3312 sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3313 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3314 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3318 sendctrl_6120_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
3319 QIB_SENDCTRL_AVAIL_BLIP);
3320 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */
3321 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3322 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3327 static u32 __iomem *qib_6120_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
3330 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
3331 struct qib_devdata *dd = ppd->dd;
3334 if (((pbc >> 32) & PBC_6120_VL15_SEND_CTRL) &&
3335 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
3336 buf = get_6120_link_buf(ppd, pbufnum);
3339 if ((plen + 1) > dd->piosize2kmax_dwords)
3340 first = dd->piobcnt2k;
3343 /* try 4k if all 2k busy, so same last for both sizes */
3344 last = dd->piobcnt2k + dd->piobcnt4k - 1;
3345 buf = qib_getsendbuf_range(dd, pbufnum, first, last);
3350 static int init_sdma_6120_regs(struct qib_pportdata *ppd)
3355 static u16 qib_sdma_6120_gethead(struct qib_pportdata *ppd)
3360 static int qib_sdma_6120_busy(struct qib_pportdata *ppd)
3365 static void qib_sdma_update_6120_tail(struct qib_pportdata *ppd, u16 tail)
3369 static void qib_6120_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
3373 static void qib_sdma_set_6120_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
3378 * the pbc doesn't need a VL15 indicator, but we need it for link_buf.
3379 * The chip ignores the bit if set.
3381 static u32 qib_6120_setpbc_control(struct qib_pportdata *ppd, u32 plen,
3384 return vl == 15 ? PBC_6120_VL15_SEND_CTRL : 0;
3387 static void qib_6120_initvl15_bufs(struct qib_devdata *dd)
3391 static void qib_6120_init_ctxt(struct qib_ctxtdata *rcd)
3393 rcd->rcvegrcnt = rcd->dd->rcvhdrcnt;
3394 rcd->rcvegr_tid_base = rcd->ctxt * rcd->rcvegrcnt;
3397 static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start,
3398 u32 len, u32 avail, struct qib_ctxtdata *rcd)
3402 static void writescratch(struct qib_devdata *dd, u32 val)
3404 (void) qib_write_kreg(dd, kr_scratch, val);
3407 static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum)
3412 #ifdef CONFIG_INFINIBAND_QIB_DCA
3413 static int qib_6120_notify_dca(struct qib_devdata *dd, unsigned long event)
3419 /* Dummy function, as 6120 boards never disable EEPROM Write */
3420 static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen)
3426 * qib_init_iba6120_funcs - set up the chip-specific function pointers
3427 * @pdev: pci_dev of the qlogic_ib device
3428 * @ent: pci_device_id matching this chip
3430 * This is global, and is called directly at init to set up the
3431 * chip-specific function pointers for later use.
3433 * It also allocates/partially-inits the qib_devdata struct for
3436 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev,
3437 const struct pci_device_id *ent)
3439 struct qib_devdata *dd;
3442 dd = qib_alloc_devdata(pdev, sizeof(struct qib_pportdata) +
3443 sizeof(struct qib_chip_specific));
3447 dd->f_bringup_serdes = qib_6120_bringup_serdes;
3448 dd->f_cleanup = qib_6120_setup_cleanup;
3449 dd->f_clear_tids = qib_6120_clear_tids;
3450 dd->f_free_irq = qib_free_irq;
3451 dd->f_get_base_info = qib_6120_get_base_info;
3452 dd->f_get_msgheader = qib_6120_get_msgheader;
3453 dd->f_getsendbuf = qib_6120_getsendbuf;
3454 dd->f_gpio_mod = gpio_6120_mod;
3455 dd->f_eeprom_wen = qib_6120_eeprom_wen;
3456 dd->f_hdrqempty = qib_6120_hdrqempty;
3457 dd->f_ib_updown = qib_6120_ib_updown;
3458 dd->f_init_ctxt = qib_6120_init_ctxt;
3459 dd->f_initvl15_bufs = qib_6120_initvl15_bufs;
3460 dd->f_intr_fallback = qib_6120_nointr_fallback;
3461 dd->f_late_initreg = qib_late_6120_initreg;
3462 dd->f_setpbc_control = qib_6120_setpbc_control;
3463 dd->f_portcntr = qib_portcntr_6120;
3464 dd->f_put_tid = (dd->minrev >= 2) ?
3465 qib_6120_put_tid_2 :
3467 dd->f_quiet_serdes = qib_6120_quiet_serdes;
3468 dd->f_rcvctrl = rcvctrl_6120_mod;
3469 dd->f_read_cntrs = qib_read_6120cntrs;
3470 dd->f_read_portcntrs = qib_read_6120portcntrs;
3471 dd->f_reset = qib_6120_setup_reset;
3472 dd->f_init_sdma_regs = init_sdma_6120_regs;
3473 dd->f_sdma_busy = qib_sdma_6120_busy;
3474 dd->f_sdma_gethead = qib_sdma_6120_gethead;
3475 dd->f_sdma_sendctrl = qib_6120_sdma_sendctrl;
3476 dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt;
3477 dd->f_sdma_update_tail = qib_sdma_update_6120_tail;
3478 dd->f_sendctrl = sendctrl_6120_mod;
3479 dd->f_set_armlaunch = qib_set_6120_armlaunch;
3480 dd->f_set_cntr_sample = qib_set_cntr_6120_sample;
3481 dd->f_iblink_state = qib_6120_iblink_state;
3482 dd->f_ibphys_portstate = qib_6120_phys_portstate;
3483 dd->f_get_ib_cfg = qib_6120_get_ib_cfg;
3484 dd->f_set_ib_cfg = qib_6120_set_ib_cfg;
3485 dd->f_set_ib_loopback = qib_6120_set_loopback;
3486 dd->f_set_intr_state = qib_6120_set_intr_state;
3487 dd->f_setextled = qib_6120_setup_setextled;
3488 dd->f_txchk_change = qib_6120_txchk_change;
3489 dd->f_update_usrhead = qib_update_6120_usrhead;
3490 dd->f_wantpiobuf_intr = qib_wantpiobuf_6120_intr;
3491 dd->f_xgxs_reset = qib_6120_xgxs_reset;
3492 dd->f_writescratch = writescratch;
3493 dd->f_tempsense_rd = qib_6120_tempsense_rd;
3494 #ifdef CONFIG_INFINIBAND_QIB_DCA
3495 dd->f_notify_dca = qib_6120_notify_dca;
3498 * Do remaining pcie setup and save pcie values in dd.
3499 * Any error printing is already done by the init code.
3500 * On return, we have the chip mapped and accessible,
3501 * but chip registers are not set up until start of
3502 * init_6120_variables.
3504 ret = qib_pcie_ddinit(dd, pdev, ent);
3508 /* initialize chip-specific variables */
3509 ret = init_6120_variables(dd);
3516 if (qib_pcie_params(dd, 8, NULL))
3518 "Failed to setup PCIe or interrupts; continuing anyway\n");
3519 /* clear diagctrl register, in case diags were running and crashed */
3520 qib_write_kreg(dd, kr_hwdiagctrl, 0);
3522 if (qib_read_kreg64(dd, kr_hwerrstatus) &
3523 QLOGIC_IB_HWE_SERDESPLLFAILED)
3524 qib_write_kreg(dd, kr_hwerrclear,
3525 QLOGIC_IB_HWE_SERDESPLLFAILED);
3527 /* setup interrupt handler (interrupt type handled above) */
3528 qib_setup_6120_interrupt(dd);
3529 /* Note that qpn_mask is set by qib_6120_config_ctxts() first */
3530 qib_6120_init_hwerrors(dd);
3535 qib_pcie_ddcleanup(dd);
3537 qib_free_devdata(dd);