2 * Copyright (c) 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2013 Cisco Systems. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/dma-mapping.h>
37 #include <linux/sched/signal.h>
38 #include <linux/sched/mm.h>
39 #include <linux/hugetlb.h>
40 #include <linux/iommu.h>
41 #include <linux/workqueue.h>
42 #include <linux/list.h>
43 #include <linux/pci.h>
44 #include <rdma/ib_verbs.h>
46 #include "usnic_log.h"
47 #include "usnic_uiom.h"
48 #include "usnic_uiom_interval_tree.h"
50 #define USNIC_UIOM_PAGE_CHUNK \
51 ((PAGE_SIZE - offsetof(struct usnic_uiom_chunk, page_list)) /\
52 ((void *) &((struct usnic_uiom_chunk *) 0)->page_list[1] - \
53 (void *) &((struct usnic_uiom_chunk *) 0)->page_list[0]))
55 static int usnic_uiom_dma_fault(struct iommu_domain *domain,
57 unsigned long iova, int flags,
60 usnic_err("Device %s iommu fault domain 0x%pK va 0x%lx flags 0x%x\n",
66 static void usnic_uiom_put_pages(struct list_head *chunk_list, int dirty)
68 struct usnic_uiom_chunk *chunk, *tmp;
70 struct scatterlist *sg;
74 list_for_each_entry_safe(chunk, tmp, chunk_list, list) {
75 for_each_sg(chunk->page_list, sg, chunk->nents, i) {
79 put_user_pages_dirty_lock(&page, 1);
82 usnic_dbg("pa: %pa\n", &pa);
88 static int usnic_uiom_get_pages(unsigned long addr, size_t size, int writable,
89 int dmasync, struct usnic_uiom_reg *uiomr)
91 struct list_head *chunk_list = &uiomr->chunk_list;
92 struct page **page_list;
93 struct scatterlist *sg;
94 struct usnic_uiom_chunk *chunk;
96 unsigned long lock_limit;
97 unsigned long cur_base;
104 unsigned int gup_flags;
105 struct mm_struct *mm;
108 * If the combination of the addr and size requested for this memory
109 * region causes an integer overflow, return error.
111 if (((addr + size) < addr) || PAGE_ALIGN(addr + size) < (addr + size))
120 INIT_LIST_HEAD(chunk_list);
122 page_list = (struct page **) __get_free_page(GFP_KERNEL);
126 npages = PAGE_ALIGN(size + (addr & ~PAGE_MASK)) >> PAGE_SHIFT;
128 uiomr->owning_mm = mm = current->mm;
129 down_read(&mm->mmap_sem);
131 locked = atomic64_add_return(npages, ¤t->mm->pinned_vm);
132 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
134 if ((locked > lock_limit) && !capable(CAP_IPC_LOCK)) {
139 flags = IOMMU_READ | IOMMU_CACHE;
140 flags |= (writable) ? IOMMU_WRITE : 0;
141 gup_flags = FOLL_WRITE;
142 gup_flags |= (writable) ? 0 : FOLL_FORCE;
143 cur_base = addr & PAGE_MASK;
147 ret = get_user_pages(cur_base,
148 min_t(unsigned long, npages,
149 PAGE_SIZE / sizeof(struct page *)),
150 gup_flags | FOLL_LONGTERM,
160 chunk = kmalloc(struct_size(chunk, page_list,
161 min_t(int, ret, USNIC_UIOM_PAGE_CHUNK)),
168 chunk->nents = min_t(int, ret, USNIC_UIOM_PAGE_CHUNK);
169 sg_init_table(chunk->page_list, chunk->nents);
170 for_each_sg(chunk->page_list, sg, chunk->nents, i) {
171 sg_set_page(sg, page_list[i + off],
174 usnic_dbg("va: 0x%lx pa: %pa\n",
175 cur_base + i*PAGE_SIZE, &pa);
177 cur_base += chunk->nents * PAGE_SIZE;
180 list_add_tail(&chunk->list, chunk_list);
188 usnic_uiom_put_pages(chunk_list, 0);
189 atomic64_sub(npages, ¤t->mm->pinned_vm);
191 mmgrab(uiomr->owning_mm);
193 up_read(&mm->mmap_sem);
194 free_page((unsigned long) page_list);
198 static void usnic_uiom_unmap_sorted_intervals(struct list_head *intervals,
199 struct usnic_uiom_pd *pd)
201 struct usnic_uiom_interval_node *interval, *tmp;
202 long unsigned va, size;
204 list_for_each_entry_safe(interval, tmp, intervals, link) {
205 va = interval->start << PAGE_SHIFT;
206 size = ((interval->last - interval->start) + 1) << PAGE_SHIFT;
208 /* Workaround for RH 970401 */
209 usnic_dbg("va 0x%lx size 0x%lx", va, PAGE_SIZE);
210 iommu_unmap(pd->domain, va, PAGE_SIZE);
217 static void __usnic_uiom_reg_release(struct usnic_uiom_pd *pd,
218 struct usnic_uiom_reg *uiomr,
222 unsigned long vpn_start, vpn_last;
223 struct usnic_uiom_interval_node *interval, *tmp;
225 LIST_HEAD(rm_intervals);
227 npages = PAGE_ALIGN(uiomr->length + uiomr->offset) >> PAGE_SHIFT;
228 vpn_start = (uiomr->va & PAGE_MASK) >> PAGE_SHIFT;
229 vpn_last = vpn_start + npages - 1;
231 spin_lock(&pd->lock);
232 usnic_uiom_remove_interval(&pd->root, vpn_start,
233 vpn_last, &rm_intervals);
234 usnic_uiom_unmap_sorted_intervals(&rm_intervals, pd);
236 list_for_each_entry_safe(interval, tmp, &rm_intervals, link) {
237 if (interval->flags & IOMMU_WRITE)
239 list_del(&interval->link);
243 usnic_uiom_put_pages(&uiomr->chunk_list, dirty & writable);
244 spin_unlock(&pd->lock);
247 static int usnic_uiom_map_sorted_intervals(struct list_head *intervals,
248 struct usnic_uiom_reg *uiomr)
252 struct usnic_uiom_chunk *chunk;
253 struct usnic_uiom_interval_node *interval_node;
255 dma_addr_t pa_start = 0;
256 dma_addr_t pa_end = 0;
257 long int va_start = -EINVAL;
258 struct usnic_uiom_pd *pd = uiomr->pd;
259 long int va = uiomr->va & PAGE_MASK;
260 int flags = IOMMU_READ | IOMMU_CACHE;
262 flags |= (uiomr->writable) ? IOMMU_WRITE : 0;
263 chunk = list_first_entry(&uiomr->chunk_list, struct usnic_uiom_chunk,
265 list_for_each_entry(interval_node, intervals, link) {
267 for (i = 0; i < chunk->nents; i++, va += PAGE_SIZE) {
268 pa = sg_phys(&chunk->page_list[i]);
269 if ((va >> PAGE_SHIFT) < interval_node->start)
272 if ((va >> PAGE_SHIFT) == interval_node->start) {
273 /* First page of the interval */
279 WARN_ON(va_start == -EINVAL);
281 if ((pa_end + PAGE_SIZE != pa) &&
283 /* PAs are not contiguous */
284 size = pa_end - pa_start + PAGE_SIZE;
285 usnic_dbg("va 0x%lx pa %pa size 0x%zx flags 0x%x",
286 va_start, &pa_start, size, flags);
287 err = iommu_map(pd->domain, va_start, pa_start,
290 usnic_err("Failed to map va 0x%lx pa %pa size 0x%zx with err %d\n",
291 va_start, &pa_start, size, err);
299 if ((va >> PAGE_SHIFT) == interval_node->last) {
300 /* Last page of the interval */
301 size = pa - pa_start + PAGE_SIZE;
302 usnic_dbg("va 0x%lx pa %pa size 0x%zx flags 0x%x\n",
303 va_start, &pa_start, size, flags);
304 err = iommu_map(pd->domain, va_start, pa_start,
307 usnic_err("Failed to map va 0x%lx pa %pa size 0x%zx with err %d\n",
308 va_start, &pa_start, size, err);
318 if (i == chunk->nents) {
320 * Hit last entry of the chunk,
321 * hence advance to next chunk
323 chunk = list_first_entry(&chunk->list,
324 struct usnic_uiom_chunk,
333 usnic_uiom_unmap_sorted_intervals(intervals, pd);
337 struct usnic_uiom_reg *usnic_uiom_reg_get(struct usnic_uiom_pd *pd,
338 unsigned long addr, size_t size,
339 int writable, int dmasync)
341 struct usnic_uiom_reg *uiomr;
342 unsigned long va_base, vpn_start, vpn_last;
343 unsigned long npages;
345 LIST_HEAD(sorted_diff_intervals);
348 * Intel IOMMU map throws an error if a translation entry is
349 * changed from read to write. This module may not unmap
350 * and then remap the entry after fixing the permission
351 * b/c this open up a small windows where hw DMA may page fault
352 * Hence, make all entries to be writable.
356 va_base = addr & PAGE_MASK;
357 offset = addr & ~PAGE_MASK;
358 npages = PAGE_ALIGN(size + offset) >> PAGE_SHIFT;
359 vpn_start = (addr & PAGE_MASK) >> PAGE_SHIFT;
360 vpn_last = vpn_start + npages - 1;
362 uiomr = kmalloc(sizeof(*uiomr), GFP_KERNEL);
364 return ERR_PTR(-ENOMEM);
367 uiomr->offset = offset;
368 uiomr->length = size;
369 uiomr->writable = writable;
372 err = usnic_uiom_get_pages(addr, size, writable, dmasync,
375 usnic_err("Failed get_pages vpn [0x%lx,0x%lx] err %d\n",
376 vpn_start, vpn_last, err);
380 spin_lock(&pd->lock);
381 err = usnic_uiom_get_intervals_diff(vpn_start, vpn_last,
382 (writable) ? IOMMU_WRITE : 0,
385 &sorted_diff_intervals);
387 usnic_err("Failed disjoint interval vpn [0x%lx,0x%lx] err %d\n",
388 vpn_start, vpn_last, err);
392 err = usnic_uiom_map_sorted_intervals(&sorted_diff_intervals, uiomr);
394 usnic_err("Failed map interval vpn [0x%lx,0x%lx] err %d\n",
395 vpn_start, vpn_last, err);
396 goto out_put_intervals;
400 err = usnic_uiom_insert_interval(&pd->root, vpn_start, vpn_last,
401 (writable) ? IOMMU_WRITE : 0);
403 usnic_err("Failed insert interval vpn [0x%lx,0x%lx] err %d\n",
404 vpn_start, vpn_last, err);
405 goto out_unmap_intervals;
408 usnic_uiom_put_interval_set(&sorted_diff_intervals);
409 spin_unlock(&pd->lock);
414 usnic_uiom_unmap_sorted_intervals(&sorted_diff_intervals, pd);
416 usnic_uiom_put_interval_set(&sorted_diff_intervals);
418 usnic_uiom_put_pages(&uiomr->chunk_list, 0);
419 spin_unlock(&pd->lock);
420 mmdrop(uiomr->owning_mm);
426 static void __usnic_uiom_release_tail(struct usnic_uiom_reg *uiomr)
428 mmdrop(uiomr->owning_mm);
432 static inline size_t usnic_uiom_num_pages(struct usnic_uiom_reg *uiomr)
434 return PAGE_ALIGN(uiomr->length + uiomr->offset) >> PAGE_SHIFT;
437 void usnic_uiom_reg_release(struct usnic_uiom_reg *uiomr)
439 __usnic_uiom_reg_release(uiomr->pd, uiomr, 1);
441 atomic64_sub(usnic_uiom_num_pages(uiomr), &uiomr->owning_mm->pinned_vm);
442 __usnic_uiom_release_tail(uiomr);
445 struct usnic_uiom_pd *usnic_uiom_alloc_pd(void)
447 struct usnic_uiom_pd *pd;
450 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
452 return ERR_PTR(-ENOMEM);
454 pd->domain = domain = iommu_domain_alloc(&pci_bus_type);
456 usnic_err("Failed to allocate IOMMU domain");
458 return ERR_PTR(-ENOMEM);
461 iommu_set_fault_handler(pd->domain, usnic_uiom_dma_fault, NULL);
463 spin_lock_init(&pd->lock);
464 INIT_LIST_HEAD(&pd->devs);
469 void usnic_uiom_dealloc_pd(struct usnic_uiom_pd *pd)
471 iommu_domain_free(pd->domain);
475 int usnic_uiom_attach_dev_to_pd(struct usnic_uiom_pd *pd, struct device *dev)
477 struct usnic_uiom_dev *uiom_dev;
480 uiom_dev = kzalloc(sizeof(*uiom_dev), GFP_ATOMIC);
485 err = iommu_attach_device(pd->domain, dev);
489 if (!iommu_capable(dev->bus, IOMMU_CAP_CACHE_COHERENCY)) {
490 usnic_err("IOMMU of %s does not support cache coherency\n",
493 goto out_detach_device;
496 spin_lock(&pd->lock);
497 list_add_tail(&uiom_dev->link, &pd->devs);
499 spin_unlock(&pd->lock);
504 iommu_detach_device(pd->domain, dev);
510 void usnic_uiom_detach_dev_from_pd(struct usnic_uiom_pd *pd, struct device *dev)
512 struct usnic_uiom_dev *uiom_dev;
515 spin_lock(&pd->lock);
516 list_for_each_entry(uiom_dev, &pd->devs, link) {
517 if (uiom_dev->dev == dev) {
524 usnic_err("Unable to free dev %s - not found\n",
526 spin_unlock(&pd->lock);
530 list_del(&uiom_dev->link);
532 spin_unlock(&pd->lock);
534 return iommu_detach_device(pd->domain, dev);
537 struct device **usnic_uiom_get_dev_list(struct usnic_uiom_pd *pd)
539 struct usnic_uiom_dev *uiom_dev;
540 struct device **devs;
543 spin_lock(&pd->lock);
544 devs = kcalloc(pd->dev_cnt + 1, sizeof(*devs), GFP_ATOMIC);
546 devs = ERR_PTR(-ENOMEM);
550 list_for_each_entry(uiom_dev, &pd->devs, link) {
551 devs[i++] = uiom_dev->dev;
554 spin_unlock(&pd->lock);
558 void usnic_uiom_free_dev_list(struct device **devs)
563 int usnic_uiom_init(char *drv_name)
565 if (!iommu_present(&pci_bus_type)) {
566 usnic_err("IOMMU required but not present or enabled. USNIC QPs will not function w/o enabling IOMMU\n");