1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/iommu-helper.h>
24 #include <linux/iommu.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/dma-contiguous.h>
32 #include <linux/irqdomain.h>
33 #include <linux/percpu.h>
34 #include <linux/iova.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/msidef.h>
40 #include <asm/proto.h>
41 #include <asm/iommu.h>
45 #include "amd_iommu_proto.h"
46 #include "amd_iommu_types.h"
47 #include "irq_remapping.h"
49 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51 #define LOOP_TIMEOUT 100000
53 /* IO virtual address start page frame number */
54 #define IOVA_START_PFN (1)
55 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
57 /* Reserved IOVA ranges */
58 #define MSI_RANGE_START (0xfee00000)
59 #define MSI_RANGE_END (0xfeefffff)
60 #define HT_RANGE_START (0xfd00000000ULL)
61 #define HT_RANGE_END (0xffffffffffULL)
64 * This bitmap is used to advertise the page sizes our hardware support
65 * to the IOMMU core, which will then use this information to split
66 * physically contiguous memory regions it is mapping into page sizes
69 * 512GB Pages are not supported due to a hardware bug
71 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
73 static DEFINE_SPINLOCK(pd_bitmap_lock);
75 /* List of all available dev_data structures */
76 static LLIST_HEAD(dev_data_list);
78 LIST_HEAD(ioapic_map);
80 LIST_HEAD(acpihid_map);
83 * Domain for untranslated devices - only allocated
84 * if iommu=pt passed on kernel cmd line.
86 const struct iommu_ops amd_iommu_ops;
88 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
89 int amd_iommu_max_glx_val = -1;
91 static const struct dma_map_ops amd_iommu_dma_ops;
94 * general struct to manage commands send to an IOMMU
100 struct kmem_cache *amd_iommu_irq_cache;
102 static void update_domain(struct protection_domain *domain);
103 static int protection_domain_init(struct protection_domain *domain);
104 static void detach_device(struct device *dev);
105 static void iova_domain_flush_tlb(struct iova_domain *iovad);
108 * Data container for a dma_ops specific protection domain
110 struct dma_ops_domain {
111 /* generic protection domain information */
112 struct protection_domain domain;
115 struct iova_domain iovad;
118 static struct iova_domain reserved_iova_ranges;
119 static struct lock_class_key reserved_rbtree_key;
121 /****************************************************************************
125 ****************************************************************************/
127 static inline u16 get_pci_device_id(struct device *dev)
129 struct pci_dev *pdev = to_pci_dev(dev);
131 return pci_dev_id(pdev);
134 static inline int get_acpihid_device_id(struct device *dev,
135 struct acpihid_map_entry **entry)
137 struct acpi_device *adev = ACPI_COMPANION(dev);
138 struct acpihid_map_entry *p;
143 list_for_each_entry(p, &acpihid_map, list) {
144 if (acpi_dev_hid_uid_match(adev, p->hid, p->uid)) {
153 static inline int get_device_id(struct device *dev)
158 devid = get_pci_device_id(dev);
160 devid = get_acpihid_device_id(dev, NULL);
165 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
167 return container_of(dom, struct protection_domain, domain);
170 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
172 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
173 return container_of(domain, struct dma_ops_domain, domain);
176 static struct iommu_dev_data *alloc_dev_data(u16 devid)
178 struct iommu_dev_data *dev_data;
180 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
184 spin_lock_init(&dev_data->lock);
185 dev_data->devid = devid;
186 ratelimit_default_init(&dev_data->rs);
188 llist_add(&dev_data->dev_data_list, &dev_data_list);
192 static struct iommu_dev_data *search_dev_data(u16 devid)
194 struct iommu_dev_data *dev_data;
195 struct llist_node *node;
197 if (llist_empty(&dev_data_list))
200 node = dev_data_list.first;
201 llist_for_each_entry(dev_data, node, dev_data_list) {
202 if (dev_data->devid == devid)
209 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
211 *(u16 *)data = alias;
215 static u16 get_alias(struct device *dev)
217 struct pci_dev *pdev = to_pci_dev(dev);
218 u16 devid, ivrs_alias, pci_alias;
220 /* The callers make sure that get_device_id() does not fail here */
221 devid = get_device_id(dev);
223 /* For ACPI HID devices, we simply return the devid as such */
224 if (!dev_is_pci(dev))
227 ivrs_alias = amd_iommu_alias_table[devid];
229 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
231 if (ivrs_alias == pci_alias)
237 * The IVRS is fairly reliable in telling us about aliases, but it
238 * can't know about every screwy device. If we don't have an IVRS
239 * reported alias, use the PCI reported alias. In that case we may
240 * still need to initialize the rlookup and dev_table entries if the
241 * alias is to a non-existent device.
243 if (ivrs_alias == devid) {
244 if (!amd_iommu_rlookup_table[pci_alias]) {
245 amd_iommu_rlookup_table[pci_alias] =
246 amd_iommu_rlookup_table[devid];
247 memcpy(amd_iommu_dev_table[pci_alias].data,
248 amd_iommu_dev_table[devid].data,
249 sizeof(amd_iommu_dev_table[pci_alias].data));
255 pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d "
256 "for device [%04x:%04x], kernel reported alias "
257 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
258 PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device,
259 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
260 PCI_FUNC(pci_alias));
263 * If we don't have a PCI DMA alias and the IVRS alias is on the same
264 * bus, then the IVRS table may know about a quirk that we don't.
266 if (pci_alias == devid &&
267 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
268 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
269 pci_info(pdev, "Added PCI DMA alias %02x.%d\n",
270 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias));
276 static struct iommu_dev_data *find_dev_data(u16 devid)
278 struct iommu_dev_data *dev_data;
279 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
281 dev_data = search_dev_data(devid);
283 if (dev_data == NULL) {
284 dev_data = alloc_dev_data(devid);
288 if (translation_pre_enabled(iommu))
289 dev_data->defer_attach = true;
295 struct iommu_dev_data *get_dev_data(struct device *dev)
297 return dev->archdata.iommu;
299 EXPORT_SYMBOL(get_dev_data);
302 * Find or create an IOMMU group for a acpihid device.
304 static struct iommu_group *acpihid_device_group(struct device *dev)
306 struct acpihid_map_entry *p, *entry = NULL;
309 devid = get_acpihid_device_id(dev, &entry);
311 return ERR_PTR(devid);
313 list_for_each_entry(p, &acpihid_map, list) {
314 if ((devid == p->devid) && p->group)
315 entry->group = p->group;
319 entry->group = generic_device_group(dev);
321 iommu_group_ref_get(entry->group);
326 static bool pci_iommuv2_capable(struct pci_dev *pdev)
328 static const int caps[] = {
331 PCI_EXT_CAP_ID_PASID,
335 if (pci_ats_disabled())
338 for (i = 0; i < 3; ++i) {
339 pos = pci_find_ext_capability(pdev, caps[i]);
347 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
349 struct iommu_dev_data *dev_data;
351 dev_data = get_dev_data(&pdev->dev);
353 return dev_data->errata & (1 << erratum) ? true : false;
357 * This function checks if the driver got a valid device from the caller to
358 * avoid dereferencing invalid pointers.
360 static bool check_device(struct device *dev)
364 if (!dev || !dev->dma_mask)
367 devid = get_device_id(dev);
371 /* Out of our scope? */
372 if (devid > amd_iommu_last_bdf)
375 if (amd_iommu_rlookup_table[devid] == NULL)
381 static void init_iommu_group(struct device *dev)
383 struct iommu_group *group;
385 group = iommu_group_get_for_dev(dev);
389 iommu_group_put(group);
392 static int iommu_init_device(struct device *dev)
394 struct iommu_dev_data *dev_data;
395 struct amd_iommu *iommu;
398 if (dev->archdata.iommu)
401 devid = get_device_id(dev);
405 iommu = amd_iommu_rlookup_table[devid];
407 dev_data = find_dev_data(devid);
411 dev_data->alias = get_alias(dev);
414 * By default we use passthrough mode for IOMMUv2 capable device.
415 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
416 * invalid address), we ignore the capability for the device so
417 * it'll be forced to go into translation mode.
419 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
420 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
421 struct amd_iommu *iommu;
423 iommu = amd_iommu_rlookup_table[dev_data->devid];
424 dev_data->iommu_v2 = iommu->is_iommu_v2;
427 dev->archdata.iommu = dev_data;
429 iommu_device_link(&iommu->iommu, dev);
434 static void iommu_ignore_device(struct device *dev)
439 devid = get_device_id(dev);
443 alias = get_alias(dev);
445 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
446 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
448 amd_iommu_rlookup_table[devid] = NULL;
449 amd_iommu_rlookup_table[alias] = NULL;
452 static void iommu_uninit_device(struct device *dev)
454 struct iommu_dev_data *dev_data;
455 struct amd_iommu *iommu;
458 devid = get_device_id(dev);
462 iommu = amd_iommu_rlookup_table[devid];
464 dev_data = search_dev_data(devid);
468 if (dev_data->domain)
471 iommu_device_unlink(&iommu->iommu, dev);
473 iommu_group_remove_device(dev);
479 * We keep dev_data around for unplugged devices and reuse it when the
480 * device is re-plugged - not doing so would introduce a ton of races.
485 * Helper function to get the first pte of a large mapping
487 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
488 unsigned long *count)
490 unsigned long pte_mask, pg_size, cnt;
493 pg_size = PTE_PAGE_SIZE(*pte);
494 cnt = PAGE_SIZE_PTE_COUNT(pg_size);
495 pte_mask = ~((cnt << 3) - 1);
496 fpte = (u64 *)(((unsigned long)pte) & pte_mask);
499 *page_size = pg_size;
507 /****************************************************************************
509 * Interrupt handling functions
511 ****************************************************************************/
513 static void dump_dte_entry(u16 devid)
517 for (i = 0; i < 4; ++i)
518 pr_err("DTE[%d]: %016llx\n", i,
519 amd_iommu_dev_table[devid].data[i]);
522 static void dump_command(unsigned long phys_addr)
524 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
527 for (i = 0; i < 4; ++i)
528 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
531 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
532 u64 address, int flags)
534 struct iommu_dev_data *dev_data = NULL;
535 struct pci_dev *pdev;
537 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
540 dev_data = get_dev_data(&pdev->dev);
542 if (dev_data && __ratelimit(&dev_data->rs)) {
543 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
544 domain_id, address, flags);
545 } else if (printk_ratelimit()) {
546 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
547 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
548 domain_id, address, flags);
555 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
557 struct device *dev = iommu->iommu.dev;
558 int type, devid, pasid, flags, tag;
559 volatile u32 *event = __evt;
564 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
565 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
566 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
567 (event[1] & EVENT_DOMID_MASK_LO);
568 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
569 address = (u64)(((u64)event[3]) << 32) | event[2];
572 /* Did we hit the erratum? */
573 if (++count == LOOP_TIMEOUT) {
574 pr_err("No event written to event log\n");
581 if (type == EVENT_TYPE_IO_FAULT) {
582 amd_iommu_report_page_fault(devid, pasid, address, flags);
587 case EVENT_TYPE_ILL_DEV:
588 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
589 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
590 pasid, address, flags);
591 dump_dte_entry(devid);
593 case EVENT_TYPE_DEV_TAB_ERR:
594 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
595 "address=0x%llx flags=0x%04x]\n",
596 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
599 case EVENT_TYPE_PAGE_TAB_ERR:
600 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
601 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
602 pasid, address, flags);
604 case EVENT_TYPE_ILL_CMD:
605 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
606 dump_command(address);
608 case EVENT_TYPE_CMD_HARD_ERR:
609 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
612 case EVENT_TYPE_IOTLB_INV_TO:
613 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
614 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
617 case EVENT_TYPE_INV_DEV_REQ:
618 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
619 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
620 pasid, address, flags);
622 case EVENT_TYPE_INV_PPR_REQ:
623 pasid = ((event[0] >> 16) & 0xFFFF)
624 | ((event[1] << 6) & 0xF0000);
625 tag = event[1] & 0x03FF;
626 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
627 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
628 pasid, address, flags, tag);
631 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
632 event[0], event[1], event[2], event[3]);
635 memset(__evt, 0, 4 * sizeof(u32));
638 static void iommu_poll_events(struct amd_iommu *iommu)
642 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
643 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
645 while (head != tail) {
646 iommu_print_event(iommu, iommu->evt_buf + head);
647 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
650 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
653 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
655 struct amd_iommu_fault fault;
657 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
658 pr_err_ratelimited("Unknown PPR request received\n");
662 fault.address = raw[1];
663 fault.pasid = PPR_PASID(raw[0]);
664 fault.device_id = PPR_DEVID(raw[0]);
665 fault.tag = PPR_TAG(raw[0]);
666 fault.flags = PPR_FLAGS(raw[0]);
668 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
671 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
675 if (iommu->ppr_log == NULL)
678 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
679 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
681 while (head != tail) {
686 raw = (u64 *)(iommu->ppr_log + head);
689 * Hardware bug: Interrupt may arrive before the entry is
690 * written to memory. If this happens we need to wait for the
693 for (i = 0; i < LOOP_TIMEOUT; ++i) {
694 if (PPR_REQ_TYPE(raw[0]) != 0)
699 /* Avoid memcpy function-call overhead */
704 * To detect the hardware bug we need to clear the entry
707 raw[0] = raw[1] = 0UL;
709 /* Update head pointer of hardware ring-buffer */
710 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
711 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
713 /* Handle PPR entry */
714 iommu_handle_ppr_entry(iommu, entry);
716 /* Refresh ring-buffer information */
717 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
718 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
722 #ifdef CONFIG_IRQ_REMAP
723 static int (*iommu_ga_log_notifier)(u32);
725 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
727 iommu_ga_log_notifier = notifier;
731 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
733 static void iommu_poll_ga_log(struct amd_iommu *iommu)
735 u32 head, tail, cnt = 0;
737 if (iommu->ga_log == NULL)
740 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
741 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
743 while (head != tail) {
747 raw = (u64 *)(iommu->ga_log + head);
750 /* Avoid memcpy function-call overhead */
753 /* Update head pointer of hardware ring-buffer */
754 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
755 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
757 /* Handle GA entry */
758 switch (GA_REQ_TYPE(log_entry)) {
760 if (!iommu_ga_log_notifier)
763 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
764 __func__, GA_DEVID(log_entry),
767 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
768 pr_err("GA log notifier failed.\n");
775 #endif /* CONFIG_IRQ_REMAP */
777 #define AMD_IOMMU_INT_MASK \
778 (MMIO_STATUS_EVT_INT_MASK | \
779 MMIO_STATUS_PPR_INT_MASK | \
780 MMIO_STATUS_GALOG_INT_MASK)
782 irqreturn_t amd_iommu_int_thread(int irq, void *data)
784 struct amd_iommu *iommu = (struct amd_iommu *) data;
785 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
787 while (status & AMD_IOMMU_INT_MASK) {
788 /* Enable EVT and PPR and GA interrupts again */
789 writel(AMD_IOMMU_INT_MASK,
790 iommu->mmio_base + MMIO_STATUS_OFFSET);
792 if (status & MMIO_STATUS_EVT_INT_MASK) {
793 pr_devel("Processing IOMMU Event Log\n");
794 iommu_poll_events(iommu);
797 if (status & MMIO_STATUS_PPR_INT_MASK) {
798 pr_devel("Processing IOMMU PPR Log\n");
799 iommu_poll_ppr_log(iommu);
802 #ifdef CONFIG_IRQ_REMAP
803 if (status & MMIO_STATUS_GALOG_INT_MASK) {
804 pr_devel("Processing IOMMU GA Log\n");
805 iommu_poll_ga_log(iommu);
810 * Hardware bug: ERBT1312
811 * When re-enabling interrupt (by writing 1
812 * to clear the bit), the hardware might also try to set
813 * the interrupt bit in the event status register.
814 * In this scenario, the bit will be set, and disable
815 * subsequent interrupts.
817 * Workaround: The IOMMU driver should read back the
818 * status register and check if the interrupt bits are cleared.
819 * If not, driver will need to go through the interrupt handler
820 * again and re-clear the bits
822 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
827 irqreturn_t amd_iommu_int_handler(int irq, void *data)
829 return IRQ_WAKE_THREAD;
832 /****************************************************************************
834 * IOMMU command queuing functions
836 ****************************************************************************/
838 static int wait_on_sem(volatile u64 *sem)
842 while (*sem == 0 && i < LOOP_TIMEOUT) {
847 if (i == LOOP_TIMEOUT) {
848 pr_alert("Completion-Wait loop timed out\n");
855 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
856 struct iommu_cmd *cmd)
860 target = iommu->cmd_buf + iommu->cmd_buf_tail;
862 iommu->cmd_buf_tail += sizeof(*cmd);
863 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
865 /* Copy command to buffer */
866 memcpy(target, cmd, sizeof(*cmd));
868 /* Tell the IOMMU about it */
869 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
872 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
874 u64 paddr = iommu_virt_to_phys((void *)address);
876 WARN_ON(address & 0x7ULL);
878 memset(cmd, 0, sizeof(*cmd));
879 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
880 cmd->data[1] = upper_32_bits(paddr);
882 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
885 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
887 memset(cmd, 0, sizeof(*cmd));
888 cmd->data[0] = devid;
889 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
892 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
893 size_t size, u16 domid, int pde)
898 pages = iommu_num_pages(address, size, PAGE_SIZE);
903 * If we have to flush more than one page, flush all
904 * TLB entries for this domain
906 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
910 address &= PAGE_MASK;
912 memset(cmd, 0, sizeof(*cmd));
913 cmd->data[1] |= domid;
914 cmd->data[2] = lower_32_bits(address);
915 cmd->data[3] = upper_32_bits(address);
916 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
917 if (s) /* size bit - we flush more than one 4kb page */
918 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
919 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
920 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
923 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
924 u64 address, size_t size)
929 pages = iommu_num_pages(address, size, PAGE_SIZE);
934 * If we have to flush more than one page, flush all
935 * TLB entries for this domain
937 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
941 address &= PAGE_MASK;
943 memset(cmd, 0, sizeof(*cmd));
944 cmd->data[0] = devid;
945 cmd->data[0] |= (qdep & 0xff) << 24;
946 cmd->data[1] = devid;
947 cmd->data[2] = lower_32_bits(address);
948 cmd->data[3] = upper_32_bits(address);
949 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
951 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
954 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
955 u64 address, bool size)
957 memset(cmd, 0, sizeof(*cmd));
959 address &= ~(0xfffULL);
961 cmd->data[0] = pasid;
962 cmd->data[1] = domid;
963 cmd->data[2] = lower_32_bits(address);
964 cmd->data[3] = upper_32_bits(address);
965 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
966 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
968 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
969 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
972 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
973 int qdep, u64 address, bool size)
975 memset(cmd, 0, sizeof(*cmd));
977 address &= ~(0xfffULL);
979 cmd->data[0] = devid;
980 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
981 cmd->data[0] |= (qdep & 0xff) << 24;
982 cmd->data[1] = devid;
983 cmd->data[1] |= (pasid & 0xff) << 16;
984 cmd->data[2] = lower_32_bits(address);
985 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
986 cmd->data[3] = upper_32_bits(address);
988 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
989 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
992 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
993 int status, int tag, bool gn)
995 memset(cmd, 0, sizeof(*cmd));
997 cmd->data[0] = devid;
999 cmd->data[1] = pasid;
1000 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1002 cmd->data[3] = tag & 0x1ff;
1003 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1005 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1008 static void build_inv_all(struct iommu_cmd *cmd)
1010 memset(cmd, 0, sizeof(*cmd));
1011 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1014 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1016 memset(cmd, 0, sizeof(*cmd));
1017 cmd->data[0] = devid;
1018 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1022 * Writes the command to the IOMMUs command buffer and informs the
1023 * hardware about the new command.
1025 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1026 struct iommu_cmd *cmd,
1029 unsigned int count = 0;
1030 u32 left, next_tail;
1032 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1034 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1037 /* Skip udelay() the first time around */
1039 if (count == LOOP_TIMEOUT) {
1040 pr_err("Command buffer timeout\n");
1047 /* Update head and recheck remaining space */
1048 iommu->cmd_buf_head = readl(iommu->mmio_base +
1049 MMIO_CMD_HEAD_OFFSET);
1054 copy_cmd_to_buffer(iommu, cmd);
1056 /* Do we need to make sure all commands are processed? */
1057 iommu->need_sync = sync;
1062 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1063 struct iommu_cmd *cmd,
1066 unsigned long flags;
1069 raw_spin_lock_irqsave(&iommu->lock, flags);
1070 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1071 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1076 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1078 return iommu_queue_command_sync(iommu, cmd, true);
1082 * This function queues a completion wait command into the command
1083 * buffer of an IOMMU
1085 static int iommu_completion_wait(struct amd_iommu *iommu)
1087 struct iommu_cmd cmd;
1088 unsigned long flags;
1091 if (!iommu->need_sync)
1095 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1097 raw_spin_lock_irqsave(&iommu->lock, flags);
1101 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1105 ret = wait_on_sem(&iommu->cmd_sem);
1108 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1113 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1115 struct iommu_cmd cmd;
1117 build_inv_dte(&cmd, devid);
1119 return iommu_queue_command(iommu, &cmd);
1122 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1126 for (devid = 0; devid <= 0xffff; ++devid)
1127 iommu_flush_dte(iommu, devid);
1129 iommu_completion_wait(iommu);
1133 * This function uses heavy locking and may disable irqs for some time. But
1134 * this is no issue because it is only called during resume.
1136 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1140 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1141 struct iommu_cmd cmd;
1142 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1144 iommu_queue_command(iommu, &cmd);
1147 iommu_completion_wait(iommu);
1150 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1152 struct iommu_cmd cmd;
1154 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1156 iommu_queue_command(iommu, &cmd);
1158 iommu_completion_wait(iommu);
1161 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1163 struct iommu_cmd cmd;
1165 build_inv_all(&cmd);
1167 iommu_queue_command(iommu, &cmd);
1168 iommu_completion_wait(iommu);
1171 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1173 struct iommu_cmd cmd;
1175 build_inv_irt(&cmd, devid);
1177 iommu_queue_command(iommu, &cmd);
1180 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1184 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1185 iommu_flush_irt(iommu, devid);
1187 iommu_completion_wait(iommu);
1190 void iommu_flush_all_caches(struct amd_iommu *iommu)
1192 if (iommu_feature(iommu, FEATURE_IA)) {
1193 amd_iommu_flush_all(iommu);
1195 amd_iommu_flush_dte_all(iommu);
1196 amd_iommu_flush_irt_all(iommu);
1197 amd_iommu_flush_tlb_all(iommu);
1202 * Command send function for flushing on-device TLB
1204 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1205 u64 address, size_t size)
1207 struct amd_iommu *iommu;
1208 struct iommu_cmd cmd;
1211 qdep = dev_data->ats.qdep;
1212 iommu = amd_iommu_rlookup_table[dev_data->devid];
1214 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1216 return iommu_queue_command(iommu, &cmd);
1220 * Command send function for invalidating a device table entry
1222 static int device_flush_dte(struct iommu_dev_data *dev_data)
1224 struct amd_iommu *iommu;
1228 iommu = amd_iommu_rlookup_table[dev_data->devid];
1229 alias = dev_data->alias;
1231 ret = iommu_flush_dte(iommu, dev_data->devid);
1232 if (!ret && alias != dev_data->devid)
1233 ret = iommu_flush_dte(iommu, alias);
1237 if (dev_data->ats.enabled)
1238 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1244 * TLB invalidation function which is called from the mapping functions.
1245 * It invalidates a single PTE if the range to flush is within a single
1246 * page. Otherwise it flushes the whole TLB of the IOMMU.
1248 static void __domain_flush_pages(struct protection_domain *domain,
1249 u64 address, size_t size, int pde)
1251 struct iommu_dev_data *dev_data;
1252 struct iommu_cmd cmd;
1255 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1257 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1258 if (!domain->dev_iommu[i])
1262 * Devices of this domain are behind this IOMMU
1263 * We need a TLB flush
1265 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1268 list_for_each_entry(dev_data, &domain->dev_list, list) {
1270 if (!dev_data->ats.enabled)
1273 ret |= device_flush_iotlb(dev_data, address, size);
1279 static void domain_flush_pages(struct protection_domain *domain,
1280 u64 address, size_t size)
1282 __domain_flush_pages(domain, address, size, 0);
1285 /* Flush the whole IO/TLB for a given protection domain */
1286 static void domain_flush_tlb(struct protection_domain *domain)
1288 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1291 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1292 static void domain_flush_tlb_pde(struct protection_domain *domain)
1294 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1297 static void domain_flush_complete(struct protection_domain *domain)
1301 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1302 if (domain && !domain->dev_iommu[i])
1306 * Devices of this domain are behind this IOMMU
1307 * We need to wait for completion of all commands.
1309 iommu_completion_wait(amd_iommus[i]);
1313 /* Flush the not present cache if it exists */
1314 static void domain_flush_np_cache(struct protection_domain *domain,
1315 dma_addr_t iova, size_t size)
1317 if (unlikely(amd_iommu_np_cache)) {
1318 unsigned long flags;
1320 spin_lock_irqsave(&domain->lock, flags);
1321 domain_flush_pages(domain, iova, size);
1322 domain_flush_complete(domain);
1323 spin_unlock_irqrestore(&domain->lock, flags);
1329 * This function flushes the DTEs for all devices in domain
1331 static void domain_flush_devices(struct protection_domain *domain)
1333 struct iommu_dev_data *dev_data;
1335 list_for_each_entry(dev_data, &domain->dev_list, list)
1336 device_flush_dte(dev_data);
1339 /****************************************************************************
1341 * The functions below are used the create the page table mappings for
1342 * unity mapped regions.
1344 ****************************************************************************/
1346 static void free_page_list(struct page *freelist)
1348 while (freelist != NULL) {
1349 unsigned long p = (unsigned long)page_address(freelist);
1350 freelist = freelist->freelist;
1355 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1357 struct page *p = virt_to_page((void *)pt);
1359 p->freelist = freelist;
1364 #define DEFINE_FREE_PT_FN(LVL, FN) \
1365 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1373 for (i = 0; i < 512; ++i) { \
1374 /* PTE present? */ \
1375 if (!IOMMU_PTE_PRESENT(pt[i])) \
1379 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1380 PM_PTE_LEVEL(pt[i]) == 7) \
1383 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1384 freelist = FN(p, freelist); \
1387 return free_pt_page((unsigned long)pt, freelist); \
1390 DEFINE_FREE_PT_FN(l2, free_pt_page)
1391 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1392 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1393 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1394 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1396 static struct page *free_sub_pt(unsigned long root, int mode,
1397 struct page *freelist)
1400 case PAGE_MODE_NONE:
1401 case PAGE_MODE_7_LEVEL:
1403 case PAGE_MODE_1_LEVEL:
1404 freelist = free_pt_page(root, freelist);
1406 case PAGE_MODE_2_LEVEL:
1407 freelist = free_pt_l2(root, freelist);
1409 case PAGE_MODE_3_LEVEL:
1410 freelist = free_pt_l3(root, freelist);
1412 case PAGE_MODE_4_LEVEL:
1413 freelist = free_pt_l4(root, freelist);
1415 case PAGE_MODE_5_LEVEL:
1416 freelist = free_pt_l5(root, freelist);
1418 case PAGE_MODE_6_LEVEL:
1419 freelist = free_pt_l6(root, freelist);
1428 static void free_pagetable(struct protection_domain *domain)
1430 unsigned long root = (unsigned long)domain->pt_root;
1431 struct page *freelist = NULL;
1433 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1434 domain->mode > PAGE_MODE_6_LEVEL);
1436 freelist = free_sub_pt(root, domain->mode, freelist);
1438 free_page_list(freelist);
1442 * This function is used to add another level to an IO page table. Adding
1443 * another level increases the size of the address space by 9 bits to a size up
1446 static bool increase_address_space(struct protection_domain *domain,
1447 unsigned long address,
1450 unsigned long flags;
1454 spin_lock_irqsave(&domain->lock, flags);
1456 if (address <= PM_LEVEL_SIZE(domain->mode) ||
1457 WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1460 pte = (void *)get_zeroed_page(gfp);
1464 *pte = PM_LEVEL_PDE(domain->mode,
1465 iommu_virt_to_phys(domain->pt_root));
1466 domain->pt_root = pte;
1472 spin_unlock_irqrestore(&domain->lock, flags);
1477 static u64 *alloc_pte(struct protection_domain *domain,
1478 unsigned long address,
1479 unsigned long page_size,
1487 BUG_ON(!is_power_of_2(page_size));
1489 while (address > PM_LEVEL_SIZE(domain->mode))
1490 *updated = increase_address_space(domain, address, gfp) || *updated;
1492 level = domain->mode - 1;
1493 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1494 address = PAGE_SIZE_ALIGN(address, page_size);
1495 end_lvl = PAGE_SIZE_LEVEL(page_size);
1497 while (level > end_lvl) {
1502 pte_level = PM_PTE_LEVEL(__pte);
1505 * If we replace a series of large PTEs, we need
1506 * to tear down all of them.
1508 if (IOMMU_PTE_PRESENT(__pte) &&
1509 pte_level == PAGE_MODE_7_LEVEL) {
1510 unsigned long count, i;
1513 lpte = first_pte_l7(pte, NULL, &count);
1516 * Unmap the replicated PTEs that still match the
1517 * original large mapping
1519 for (i = 0; i < count; ++i)
1520 cmpxchg64(&lpte[i], __pte, 0ULL);
1526 if (!IOMMU_PTE_PRESENT(__pte) ||
1527 pte_level == PAGE_MODE_NONE) {
1528 page = (u64 *)get_zeroed_page(gfp);
1533 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1535 /* pte could have been changed somewhere. */
1536 if (cmpxchg64(pte, __pte, __npte) != __pte)
1537 free_page((unsigned long)page);
1538 else if (IOMMU_PTE_PRESENT(__pte))
1544 /* No level skipping support yet */
1545 if (pte_level != level)
1550 pte = IOMMU_PTE_PAGE(__pte);
1552 if (pte_page && level == end_lvl)
1555 pte = &pte[PM_LEVEL_INDEX(level, address)];
1562 * This function checks if there is a PTE for a given dma address. If
1563 * there is one, it returns the pointer to it.
1565 static u64 *fetch_pte(struct protection_domain *domain,
1566 unsigned long address,
1567 unsigned long *page_size)
1574 if (address > PM_LEVEL_SIZE(domain->mode))
1577 level = domain->mode - 1;
1578 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1579 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1584 if (!IOMMU_PTE_PRESENT(*pte))
1588 if (PM_PTE_LEVEL(*pte) == 7 ||
1589 PM_PTE_LEVEL(*pte) == 0)
1592 /* No level skipping support yet */
1593 if (PM_PTE_LEVEL(*pte) != level)
1598 /* Walk to the next level */
1599 pte = IOMMU_PTE_PAGE(*pte);
1600 pte = &pte[PM_LEVEL_INDEX(level, address)];
1601 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1605 * If we have a series of large PTEs, make
1606 * sure to return a pointer to the first one.
1608 if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1609 pte = first_pte_l7(pte, page_size, NULL);
1614 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1619 while (cmpxchg64(pte, pteval, 0) != pteval) {
1620 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1624 if (!IOMMU_PTE_PRESENT(pteval))
1627 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1628 mode = IOMMU_PTE_MODE(pteval);
1630 return free_sub_pt(pt, mode, freelist);
1634 * Generic mapping functions. It maps a physical address into a DMA
1635 * address space. It allocates the page table pages if necessary.
1636 * In the future it can be extended to a generic mapping function
1637 * supporting all features of AMD IOMMU page tables like level skipping
1638 * and full 64 bit address spaces.
1640 static int iommu_map_page(struct protection_domain *dom,
1641 unsigned long bus_addr,
1642 unsigned long phys_addr,
1643 unsigned long page_size,
1647 struct page *freelist = NULL;
1648 bool updated = false;
1652 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1653 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1656 if (!(prot & IOMMU_PROT_MASK))
1659 count = PAGE_SIZE_PTE_COUNT(page_size);
1660 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1666 for (i = 0; i < count; ++i)
1667 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1669 if (freelist != NULL)
1673 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1674 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1676 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1678 if (prot & IOMMU_PROT_IR)
1679 __pte |= IOMMU_PTE_IR;
1680 if (prot & IOMMU_PROT_IW)
1681 __pte |= IOMMU_PTE_IW;
1683 for (i = 0; i < count; ++i)
1690 unsigned long flags;
1692 spin_lock_irqsave(&dom->lock, flags);
1694 spin_unlock_irqrestore(&dom->lock, flags);
1697 /* Everything flushed out, free pages now */
1698 free_page_list(freelist);
1703 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1704 unsigned long bus_addr,
1705 unsigned long page_size)
1707 unsigned long long unmapped;
1708 unsigned long unmap_size;
1711 BUG_ON(!is_power_of_2(page_size));
1715 while (unmapped < page_size) {
1717 pte = fetch_pte(dom, bus_addr, &unmap_size);
1722 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1723 for (i = 0; i < count; i++)
1727 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1728 unmapped += unmap_size;
1731 BUG_ON(unmapped && !is_power_of_2(unmapped));
1736 /****************************************************************************
1738 * The next functions belong to the address allocator for the dma_ops
1739 * interface functions.
1741 ****************************************************************************/
1744 static unsigned long dma_ops_alloc_iova(struct device *dev,
1745 struct dma_ops_domain *dma_dom,
1746 unsigned int pages, u64 dma_mask)
1748 unsigned long pfn = 0;
1750 pages = __roundup_pow_of_two(pages);
1752 if (dma_mask > DMA_BIT_MASK(32))
1753 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1754 IOVA_PFN(DMA_BIT_MASK(32)), false);
1757 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1758 IOVA_PFN(dma_mask), true);
1760 return (pfn << PAGE_SHIFT);
1763 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1764 unsigned long address,
1767 pages = __roundup_pow_of_two(pages);
1768 address >>= PAGE_SHIFT;
1770 free_iova_fast(&dma_dom->iovad, address, pages);
1773 /****************************************************************************
1775 * The next functions belong to the domain allocation. A domain is
1776 * allocated for every IOMMU as the default domain. If device isolation
1777 * is enabled, every device get its own domain. The most important thing
1778 * about domains is the page table mapping the DMA address space they
1781 ****************************************************************************/
1783 static u16 domain_id_alloc(void)
1787 spin_lock(&pd_bitmap_lock);
1788 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1790 if (id > 0 && id < MAX_DOMAIN_ID)
1791 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1794 spin_unlock(&pd_bitmap_lock);
1799 static void domain_id_free(int id)
1801 spin_lock(&pd_bitmap_lock);
1802 if (id > 0 && id < MAX_DOMAIN_ID)
1803 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1804 spin_unlock(&pd_bitmap_lock);
1807 static void free_gcr3_tbl_level1(u64 *tbl)
1812 for (i = 0; i < 512; ++i) {
1813 if (!(tbl[i] & GCR3_VALID))
1816 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1818 free_page((unsigned long)ptr);
1822 static void free_gcr3_tbl_level2(u64 *tbl)
1827 for (i = 0; i < 512; ++i) {
1828 if (!(tbl[i] & GCR3_VALID))
1831 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1833 free_gcr3_tbl_level1(ptr);
1837 static void free_gcr3_table(struct protection_domain *domain)
1839 if (domain->glx == 2)
1840 free_gcr3_tbl_level2(domain->gcr3_tbl);
1841 else if (domain->glx == 1)
1842 free_gcr3_tbl_level1(domain->gcr3_tbl);
1844 BUG_ON(domain->glx != 0);
1846 free_page((unsigned long)domain->gcr3_tbl);
1849 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1851 unsigned long flags;
1853 spin_lock_irqsave(&dom->domain.lock, flags);
1854 domain_flush_tlb(&dom->domain);
1855 domain_flush_complete(&dom->domain);
1856 spin_unlock_irqrestore(&dom->domain.lock, flags);
1859 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1861 struct dma_ops_domain *dom;
1863 dom = container_of(iovad, struct dma_ops_domain, iovad);
1865 dma_ops_domain_flush_tlb(dom);
1869 * Free a domain, only used if something went wrong in the
1870 * allocation path and we need to free an already allocated page table
1872 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1877 put_iova_domain(&dom->iovad);
1879 free_pagetable(&dom->domain);
1882 domain_id_free(dom->domain.id);
1888 * Allocates a new protection domain usable for the dma_ops functions.
1889 * It also initializes the page table and the address allocator data
1890 * structures required for the dma_ops interface
1892 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1894 struct dma_ops_domain *dma_dom;
1896 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1900 if (protection_domain_init(&dma_dom->domain))
1903 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1904 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1905 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1906 if (!dma_dom->domain.pt_root)
1909 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1911 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1914 /* Initialize reserved ranges */
1915 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1920 dma_ops_domain_free(dma_dom);
1926 * little helper function to check whether a given protection domain is a
1929 static bool dma_ops_domain(struct protection_domain *domain)
1931 return domain->flags & PD_DMA_OPS_MASK;
1934 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1941 if (domain->mode != PAGE_MODE_NONE)
1942 pte_root = iommu_virt_to_phys(domain->pt_root);
1944 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1945 << DEV_ENTRY_MODE_SHIFT;
1946 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1948 flags = amd_iommu_dev_table[devid].data[1];
1951 flags |= DTE_FLAG_IOTLB;
1954 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1956 if (iommu_feature(iommu, FEATURE_EPHSUP))
1957 pte_root |= 1ULL << DEV_ENTRY_PPR;
1960 if (domain->flags & PD_IOMMUV2_MASK) {
1961 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1962 u64 glx = domain->glx;
1965 pte_root |= DTE_FLAG_GV;
1966 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1968 /* First mask out possible old values for GCR3 table */
1969 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1972 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1975 /* Encode GCR3 table into DTE */
1976 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1979 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1982 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1986 flags &= ~DEV_DOMID_MASK;
1987 flags |= domain->id;
1989 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1990 amd_iommu_dev_table[devid].data[1] = flags;
1991 amd_iommu_dev_table[devid].data[0] = pte_root;
1994 * A kdump kernel might be replacing a domain ID that was copied from
1995 * the previous kernel--if so, it needs to flush the translation cache
1996 * entries for the old domain ID that is being overwritten
1999 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2001 amd_iommu_flush_tlb_domid(iommu, old_domid);
2005 static void clear_dte_entry(u16 devid)
2007 /* remove entry from the device table seen by the hardware */
2008 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
2009 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2011 amd_iommu_apply_erratum_63(devid);
2014 static void do_attach(struct iommu_dev_data *dev_data,
2015 struct protection_domain *domain)
2017 struct amd_iommu *iommu;
2021 iommu = amd_iommu_rlookup_table[dev_data->devid];
2022 alias = dev_data->alias;
2023 ats = dev_data->ats.enabled;
2025 /* Update data structures */
2026 dev_data->domain = domain;
2027 list_add(&dev_data->list, &domain->dev_list);
2029 /* Do reference counting */
2030 domain->dev_iommu[iommu->index] += 1;
2031 domain->dev_cnt += 1;
2033 /* Update device table */
2034 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
2035 if (alias != dev_data->devid)
2036 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
2038 device_flush_dte(dev_data);
2041 static void do_detach(struct iommu_dev_data *dev_data)
2043 struct protection_domain *domain = dev_data->domain;
2044 struct amd_iommu *iommu;
2047 iommu = amd_iommu_rlookup_table[dev_data->devid];
2048 alias = dev_data->alias;
2050 /* Update data structures */
2051 dev_data->domain = NULL;
2052 list_del(&dev_data->list);
2053 clear_dte_entry(dev_data->devid);
2054 if (alias != dev_data->devid)
2055 clear_dte_entry(alias);
2057 /* Flush the DTE entry */
2058 device_flush_dte(dev_data);
2061 domain_flush_tlb_pde(domain);
2063 /* Wait for the flushes to finish */
2064 domain_flush_complete(domain);
2066 /* decrease reference counters - needs to happen after the flushes */
2067 domain->dev_iommu[iommu->index] -= 1;
2068 domain->dev_cnt -= 1;
2071 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2073 pci_disable_ats(pdev);
2074 pci_disable_pri(pdev);
2075 pci_disable_pasid(pdev);
2078 /* FIXME: Change generic reset-function to do the same */
2079 static int pri_reset_while_enabled(struct pci_dev *pdev)
2084 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2088 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2089 control |= PCI_PRI_CTRL_RESET;
2090 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2095 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2100 /* FIXME: Hardcode number of outstanding requests for now */
2102 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2104 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2106 /* Only allow access to user-accessible pages */
2107 ret = pci_enable_pasid(pdev, 0);
2111 /* First reset the PRI state of the device */
2112 ret = pci_reset_pri(pdev);
2117 ret = pci_enable_pri(pdev, reqs);
2122 ret = pri_reset_while_enabled(pdev);
2127 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2134 pci_disable_pri(pdev);
2135 pci_disable_pasid(pdev);
2141 * If a device is not yet associated with a domain, this function makes the
2142 * device visible in the domain
2144 static int attach_device(struct device *dev,
2145 struct protection_domain *domain)
2147 struct pci_dev *pdev;
2148 struct iommu_dev_data *dev_data;
2149 unsigned long flags;
2152 spin_lock_irqsave(&domain->lock, flags);
2154 dev_data = get_dev_data(dev);
2156 spin_lock(&dev_data->lock);
2159 if (dev_data->domain != NULL)
2162 if (!dev_is_pci(dev))
2163 goto skip_ats_check;
2165 pdev = to_pci_dev(dev);
2166 if (domain->flags & PD_IOMMUV2_MASK) {
2168 if (!dev_data->passthrough)
2171 if (dev_data->iommu_v2) {
2172 if (pdev_iommuv2_enable(pdev) != 0)
2175 dev_data->ats.enabled = true;
2176 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2177 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2179 } else if (amd_iommu_iotlb_sup &&
2180 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2181 dev_data->ats.enabled = true;
2182 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2188 do_attach(dev_data, domain);
2191 * We might boot into a crash-kernel here. The crashed kernel
2192 * left the caches in the IOMMU dirty. So we have to flush
2193 * here to evict all dirty stuff.
2195 domain_flush_tlb_pde(domain);
2197 domain_flush_complete(domain);
2200 spin_unlock(&dev_data->lock);
2202 spin_unlock_irqrestore(&domain->lock, flags);
2208 * Removes a device from a protection domain (with devtable_lock held)
2210 static void detach_device(struct device *dev)
2212 struct protection_domain *domain;
2213 struct iommu_dev_data *dev_data;
2214 unsigned long flags;
2216 dev_data = get_dev_data(dev);
2217 domain = dev_data->domain;
2219 spin_lock_irqsave(&domain->lock, flags);
2221 spin_lock(&dev_data->lock);
2224 * First check if the device is still attached. It might already
2225 * be detached from its domain because the generic
2226 * iommu_detach_group code detached it and we try again here in
2227 * our alias handling.
2229 if (WARN_ON(!dev_data->domain))
2232 do_detach(dev_data);
2234 if (!dev_is_pci(dev))
2237 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2238 pdev_iommuv2_disable(to_pci_dev(dev));
2239 else if (dev_data->ats.enabled)
2240 pci_disable_ats(to_pci_dev(dev));
2242 dev_data->ats.enabled = false;
2245 spin_unlock(&dev_data->lock);
2247 spin_unlock_irqrestore(&domain->lock, flags);
2250 static int amd_iommu_add_device(struct device *dev)
2252 struct iommu_dev_data *dev_data;
2253 struct iommu_domain *domain;
2254 struct amd_iommu *iommu;
2257 if (!check_device(dev) || get_dev_data(dev))
2260 devid = get_device_id(dev);
2264 iommu = amd_iommu_rlookup_table[devid];
2266 ret = iommu_init_device(dev);
2268 if (ret != -ENOTSUPP)
2269 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2271 iommu_ignore_device(dev);
2272 dev->dma_ops = NULL;
2275 init_iommu_group(dev);
2277 dev_data = get_dev_data(dev);
2281 if (dev_data->iommu_v2)
2282 iommu_request_dm_for_dev(dev);
2284 /* Domains are initialized for this device - have a look what we ended up with */
2285 domain = iommu_get_domain_for_dev(dev);
2286 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2287 dev_data->passthrough = true;
2289 dev->dma_ops = &amd_iommu_dma_ops;
2292 iommu_completion_wait(iommu);
2297 static void amd_iommu_remove_device(struct device *dev)
2299 struct amd_iommu *iommu;
2302 if (!check_device(dev))
2305 devid = get_device_id(dev);
2309 iommu = amd_iommu_rlookup_table[devid];
2311 iommu_uninit_device(dev);
2312 iommu_completion_wait(iommu);
2315 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2317 if (dev_is_pci(dev))
2318 return pci_device_group(dev);
2320 return acpihid_device_group(dev);
2323 /*****************************************************************************
2325 * The next functions belong to the dma_ops mapping/unmapping code.
2327 *****************************************************************************/
2330 * In the dma_ops path we only have the struct device. This function
2331 * finds the corresponding IOMMU, the protection domain and the
2332 * requestor id for a given device.
2333 * If the device is not yet associated with a domain this is also done
2336 static struct protection_domain *get_domain(struct device *dev)
2338 struct protection_domain *domain;
2339 struct iommu_domain *io_domain;
2341 if (!check_device(dev))
2342 return ERR_PTR(-EINVAL);
2344 domain = get_dev_data(dev)->domain;
2345 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2346 get_dev_data(dev)->defer_attach = false;
2347 io_domain = iommu_get_domain_for_dev(dev);
2348 domain = to_pdomain(io_domain);
2349 attach_device(dev, domain);
2352 return ERR_PTR(-EBUSY);
2354 if (!dma_ops_domain(domain))
2355 return ERR_PTR(-EBUSY);
2360 static void update_device_table(struct protection_domain *domain)
2362 struct iommu_dev_data *dev_data;
2364 list_for_each_entry(dev_data, &domain->dev_list, list) {
2365 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2366 dev_data->iommu_v2);
2368 if (dev_data->devid == dev_data->alias)
2371 /* There is an alias, update device table entry for it */
2372 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2373 dev_data->iommu_v2);
2377 static void update_domain(struct protection_domain *domain)
2379 update_device_table(domain);
2381 domain_flush_devices(domain);
2382 domain_flush_tlb_pde(domain);
2385 static int dir2prot(enum dma_data_direction direction)
2387 if (direction == DMA_TO_DEVICE)
2388 return IOMMU_PROT_IR;
2389 else if (direction == DMA_FROM_DEVICE)
2390 return IOMMU_PROT_IW;
2391 else if (direction == DMA_BIDIRECTIONAL)
2392 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2398 * This function contains common code for mapping of a physically
2399 * contiguous memory region into DMA address space. It is used by all
2400 * mapping functions provided with this IOMMU driver.
2401 * Must be called with the domain lock held.
2403 static dma_addr_t __map_single(struct device *dev,
2404 struct dma_ops_domain *dma_dom,
2407 enum dma_data_direction direction,
2410 dma_addr_t offset = paddr & ~PAGE_MASK;
2411 dma_addr_t address, start, ret;
2412 unsigned long flags;
2417 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2420 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2424 prot = dir2prot(direction);
2427 for (i = 0; i < pages; ++i) {
2428 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2429 PAGE_SIZE, prot, GFP_ATOMIC);
2438 domain_flush_np_cache(&dma_dom->domain, address, size);
2445 for (--i; i >= 0; --i) {
2447 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2450 spin_lock_irqsave(&dma_dom->domain.lock, flags);
2451 domain_flush_tlb(&dma_dom->domain);
2452 domain_flush_complete(&dma_dom->domain);
2453 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
2455 dma_ops_free_iova(dma_dom, address, pages);
2457 return DMA_MAPPING_ERROR;
2461 * Does the reverse of the __map_single function. Must be called with
2462 * the domain lock held too
2464 static void __unmap_single(struct dma_ops_domain *dma_dom,
2465 dma_addr_t dma_addr,
2469 dma_addr_t i, start;
2472 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2473 dma_addr &= PAGE_MASK;
2476 for (i = 0; i < pages; ++i) {
2477 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2481 if (amd_iommu_unmap_flush) {
2482 unsigned long flags;
2484 spin_lock_irqsave(&dma_dom->domain.lock, flags);
2485 domain_flush_tlb(&dma_dom->domain);
2486 domain_flush_complete(&dma_dom->domain);
2487 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
2488 dma_ops_free_iova(dma_dom, dma_addr, pages);
2490 pages = __roundup_pow_of_two(pages);
2491 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2496 * The exported map_single function for dma_ops.
2498 static dma_addr_t map_page(struct device *dev, struct page *page,
2499 unsigned long offset, size_t size,
2500 enum dma_data_direction dir,
2501 unsigned long attrs)
2503 phys_addr_t paddr = page_to_phys(page) + offset;
2504 struct protection_domain *domain;
2505 struct dma_ops_domain *dma_dom;
2508 domain = get_domain(dev);
2509 if (PTR_ERR(domain) == -EINVAL)
2510 return (dma_addr_t)paddr;
2511 else if (IS_ERR(domain))
2512 return DMA_MAPPING_ERROR;
2514 dma_mask = *dev->dma_mask;
2515 dma_dom = to_dma_ops_domain(domain);
2517 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2521 * The exported unmap_single function for dma_ops.
2523 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2524 enum dma_data_direction dir, unsigned long attrs)
2526 struct protection_domain *domain;
2527 struct dma_ops_domain *dma_dom;
2529 domain = get_domain(dev);
2533 dma_dom = to_dma_ops_domain(domain);
2535 __unmap_single(dma_dom, dma_addr, size, dir);
2538 static int sg_num_pages(struct device *dev,
2539 struct scatterlist *sglist,
2542 unsigned long mask, boundary_size;
2543 struct scatterlist *s;
2546 mask = dma_get_seg_boundary(dev);
2547 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2548 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2550 for_each_sg(sglist, s, nelems, i) {
2553 s->dma_address = npages << PAGE_SHIFT;
2554 p = npages % boundary_size;
2555 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2556 if (p + n > boundary_size)
2557 npages += boundary_size - p;
2565 * The exported map_sg function for dma_ops (handles scatter-gather
2568 static int map_sg(struct device *dev, struct scatterlist *sglist,
2569 int nelems, enum dma_data_direction direction,
2570 unsigned long attrs)
2572 int mapped_pages = 0, npages = 0, prot = 0, i;
2573 struct protection_domain *domain;
2574 struct dma_ops_domain *dma_dom;
2575 struct scatterlist *s;
2576 unsigned long address;
2580 domain = get_domain(dev);
2584 dma_dom = to_dma_ops_domain(domain);
2585 dma_mask = *dev->dma_mask;
2587 npages = sg_num_pages(dev, sglist, nelems);
2589 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2593 prot = dir2prot(direction);
2595 /* Map all sg entries */
2596 for_each_sg(sglist, s, nelems, i) {
2597 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2599 for (j = 0; j < pages; ++j) {
2600 unsigned long bus_addr, phys_addr;
2602 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2603 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2604 ret = iommu_map_page(domain, bus_addr, phys_addr,
2606 GFP_ATOMIC | __GFP_NOWARN);
2614 /* Everything is mapped - write the right values into s->dma_address */
2615 for_each_sg(sglist, s, nelems, i) {
2617 * Add in the remaining piece of the scatter-gather offset that
2618 * was masked out when we were determining the physical address
2619 * via (sg_phys(s) & PAGE_MASK) earlier.
2621 s->dma_address += address + (s->offset & ~PAGE_MASK);
2622 s->dma_length = s->length;
2626 domain_flush_np_cache(domain, s->dma_address, s->dma_length);
2631 dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2634 for_each_sg(sglist, s, nelems, i) {
2635 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2637 for (j = 0; j < pages; ++j) {
2638 unsigned long bus_addr;
2640 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2641 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2643 if (--mapped_pages == 0)
2649 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2656 * The exported map_sg function for dma_ops (handles scatter-gather
2659 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2660 int nelems, enum dma_data_direction dir,
2661 unsigned long attrs)
2663 struct protection_domain *domain;
2664 struct dma_ops_domain *dma_dom;
2665 unsigned long startaddr;
2668 domain = get_domain(dev);
2672 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2673 dma_dom = to_dma_ops_domain(domain);
2674 npages = sg_num_pages(dev, sglist, nelems);
2676 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2680 * The exported alloc_coherent function for dma_ops.
2682 static void *alloc_coherent(struct device *dev, size_t size,
2683 dma_addr_t *dma_addr, gfp_t flag,
2684 unsigned long attrs)
2686 u64 dma_mask = dev->coherent_dma_mask;
2687 struct protection_domain *domain;
2688 struct dma_ops_domain *dma_dom;
2691 domain = get_domain(dev);
2692 if (PTR_ERR(domain) == -EINVAL) {
2693 page = alloc_pages(flag, get_order(size));
2694 *dma_addr = page_to_phys(page);
2695 return page_address(page);
2696 } else if (IS_ERR(domain))
2699 dma_dom = to_dma_ops_domain(domain);
2700 size = PAGE_ALIGN(size);
2701 dma_mask = dev->coherent_dma_mask;
2702 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2705 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2707 if (!gfpflags_allow_blocking(flag))
2710 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2711 get_order(size), flag & __GFP_NOWARN);
2717 dma_mask = *dev->dma_mask;
2719 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2720 size, DMA_BIDIRECTIONAL, dma_mask);
2722 if (*dma_addr == DMA_MAPPING_ERROR)
2725 return page_address(page);
2729 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2730 __free_pages(page, get_order(size));
2736 * The exported free_coherent function for dma_ops.
2738 static void free_coherent(struct device *dev, size_t size,
2739 void *virt_addr, dma_addr_t dma_addr,
2740 unsigned long attrs)
2742 struct protection_domain *domain;
2743 struct dma_ops_domain *dma_dom;
2746 page = virt_to_page(virt_addr);
2747 size = PAGE_ALIGN(size);
2749 domain = get_domain(dev);
2753 dma_dom = to_dma_ops_domain(domain);
2755 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2758 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2759 __free_pages(page, get_order(size));
2763 * This function is called by the DMA layer to find out if we can handle a
2764 * particular device. It is part of the dma_ops.
2766 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2768 if (!dma_direct_supported(dev, mask))
2770 return check_device(dev);
2773 static const struct dma_map_ops amd_iommu_dma_ops = {
2774 .alloc = alloc_coherent,
2775 .free = free_coherent,
2776 .map_page = map_page,
2777 .unmap_page = unmap_page,
2779 .unmap_sg = unmap_sg,
2780 .dma_supported = amd_iommu_dma_supported,
2781 .mmap = dma_common_mmap,
2782 .get_sgtable = dma_common_get_sgtable,
2785 static int init_reserved_iova_ranges(void)
2787 struct pci_dev *pdev = NULL;
2790 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2792 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2793 &reserved_rbtree_key);
2795 /* MSI memory range */
2796 val = reserve_iova(&reserved_iova_ranges,
2797 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2799 pr_err("Reserving MSI range failed\n");
2803 /* HT memory range */
2804 val = reserve_iova(&reserved_iova_ranges,
2805 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2807 pr_err("Reserving HT range failed\n");
2812 * Memory used for PCI resources
2813 * FIXME: Check whether we can reserve the PCI-hole completly
2815 for_each_pci_dev(pdev) {
2818 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2819 struct resource *r = &pdev->resource[i];
2821 if (!(r->flags & IORESOURCE_MEM))
2824 val = reserve_iova(&reserved_iova_ranges,
2828 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2837 int __init amd_iommu_init_api(void)
2841 ret = iova_cache_get();
2845 ret = init_reserved_iova_ranges();
2849 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2852 #ifdef CONFIG_ARM_AMBA
2853 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2857 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2864 int __init amd_iommu_init_dma_ops(void)
2866 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2869 if (amd_iommu_unmap_flush)
2870 pr_info("IO/TLB flush on unmap enabled\n");
2872 pr_info("Lazy IO/TLB flushing enabled\n");
2878 /*****************************************************************************
2880 * The following functions belong to the exported interface of AMD IOMMU
2882 * This interface allows access to lower level functions of the IOMMU
2883 * like protection domain handling and assignement of devices to domains
2884 * which is not possible with the dma_ops interface.
2886 *****************************************************************************/
2888 static void cleanup_domain(struct protection_domain *domain)
2890 struct iommu_dev_data *entry;
2891 unsigned long flags;
2893 spin_lock_irqsave(&domain->lock, flags);
2895 while (!list_empty(&domain->dev_list)) {
2896 entry = list_first_entry(&domain->dev_list,
2897 struct iommu_dev_data, list);
2898 BUG_ON(!entry->domain);
2902 spin_unlock_irqrestore(&domain->lock, flags);
2905 static void protection_domain_free(struct protection_domain *domain)
2911 domain_id_free(domain->id);
2916 static int protection_domain_init(struct protection_domain *domain)
2918 spin_lock_init(&domain->lock);
2919 mutex_init(&domain->api_lock);
2920 domain->id = domain_id_alloc();
2923 INIT_LIST_HEAD(&domain->dev_list);
2928 static struct protection_domain *protection_domain_alloc(void)
2930 struct protection_domain *domain;
2932 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2936 if (protection_domain_init(domain))
2947 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2949 struct protection_domain *pdomain;
2950 struct dma_ops_domain *dma_domain;
2953 case IOMMU_DOMAIN_UNMANAGED:
2954 pdomain = protection_domain_alloc();
2958 pdomain->mode = PAGE_MODE_3_LEVEL;
2959 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2960 if (!pdomain->pt_root) {
2961 protection_domain_free(pdomain);
2965 pdomain->domain.geometry.aperture_start = 0;
2966 pdomain->domain.geometry.aperture_end = ~0ULL;
2967 pdomain->domain.geometry.force_aperture = true;
2970 case IOMMU_DOMAIN_DMA:
2971 dma_domain = dma_ops_domain_alloc();
2973 pr_err("Failed to allocate\n");
2976 pdomain = &dma_domain->domain;
2978 case IOMMU_DOMAIN_IDENTITY:
2979 pdomain = protection_domain_alloc();
2983 pdomain->mode = PAGE_MODE_NONE;
2989 return &pdomain->domain;
2992 static void amd_iommu_domain_free(struct iommu_domain *dom)
2994 struct protection_domain *domain;
2995 struct dma_ops_domain *dma_dom;
2997 domain = to_pdomain(dom);
2999 if (domain->dev_cnt > 0)
3000 cleanup_domain(domain);
3002 BUG_ON(domain->dev_cnt != 0);
3007 switch (dom->type) {
3008 case IOMMU_DOMAIN_DMA:
3009 /* Now release the domain */
3010 dma_dom = to_dma_ops_domain(domain);
3011 dma_ops_domain_free(dma_dom);
3014 if (domain->mode != PAGE_MODE_NONE)
3015 free_pagetable(domain);
3017 if (domain->flags & PD_IOMMUV2_MASK)
3018 free_gcr3_table(domain);
3020 protection_domain_free(domain);
3025 static void amd_iommu_detach_device(struct iommu_domain *dom,
3028 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3029 struct amd_iommu *iommu;
3032 if (!check_device(dev))
3035 devid = get_device_id(dev);
3039 if (dev_data->domain != NULL)
3042 iommu = amd_iommu_rlookup_table[devid];
3046 #ifdef CONFIG_IRQ_REMAP
3047 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3048 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3049 dev_data->use_vapic = 0;
3052 iommu_completion_wait(iommu);
3055 static int amd_iommu_attach_device(struct iommu_domain *dom,
3058 struct protection_domain *domain = to_pdomain(dom);
3059 struct iommu_dev_data *dev_data;
3060 struct amd_iommu *iommu;
3063 if (!check_device(dev))
3066 dev_data = dev->archdata.iommu;
3068 iommu = amd_iommu_rlookup_table[dev_data->devid];
3072 if (dev_data->domain)
3075 ret = attach_device(dev, domain);
3077 #ifdef CONFIG_IRQ_REMAP
3078 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3079 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3080 dev_data->use_vapic = 1;
3082 dev_data->use_vapic = 0;
3086 iommu_completion_wait(iommu);
3091 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3092 phys_addr_t paddr, size_t page_size, int iommu_prot)
3094 struct protection_domain *domain = to_pdomain(dom);
3098 if (domain->mode == PAGE_MODE_NONE)
3101 if (iommu_prot & IOMMU_READ)
3102 prot |= IOMMU_PROT_IR;
3103 if (iommu_prot & IOMMU_WRITE)
3104 prot |= IOMMU_PROT_IW;
3106 mutex_lock(&domain->api_lock);
3107 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3108 mutex_unlock(&domain->api_lock);
3110 domain_flush_np_cache(domain, iova, page_size);
3115 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3117 struct iommu_iotlb_gather *gather)
3119 struct protection_domain *domain = to_pdomain(dom);
3122 if (domain->mode == PAGE_MODE_NONE)
3125 mutex_lock(&domain->api_lock);
3126 unmap_size = iommu_unmap_page(domain, iova, page_size);
3127 mutex_unlock(&domain->api_lock);
3132 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3135 struct protection_domain *domain = to_pdomain(dom);
3136 unsigned long offset_mask, pte_pgsize;
3139 if (domain->mode == PAGE_MODE_NONE)
3142 pte = fetch_pte(domain, iova, &pte_pgsize);
3144 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3147 offset_mask = pte_pgsize - 1;
3148 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3150 return (__pte & ~offset_mask) | (iova & offset_mask);
3153 static bool amd_iommu_capable(enum iommu_cap cap)
3156 case IOMMU_CAP_CACHE_COHERENCY:
3158 case IOMMU_CAP_INTR_REMAP:
3159 return (irq_remapping_enabled == 1);
3160 case IOMMU_CAP_NOEXEC:
3169 static void amd_iommu_get_resv_regions(struct device *dev,
3170 struct list_head *head)
3172 struct iommu_resv_region *region;
3173 struct unity_map_entry *entry;
3176 devid = get_device_id(dev);
3180 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3184 if (devid < entry->devid_start || devid > entry->devid_end)
3187 type = IOMMU_RESV_DIRECT;
3188 length = entry->address_end - entry->address_start;
3189 if (entry->prot & IOMMU_PROT_IR)
3191 if (entry->prot & IOMMU_PROT_IW)
3192 prot |= IOMMU_WRITE;
3193 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3194 /* Exclusion range */
3195 type = IOMMU_RESV_RESERVED;
3197 region = iommu_alloc_resv_region(entry->address_start,
3198 length, prot, type);
3200 dev_err(dev, "Out of memory allocating dm-regions\n");
3203 list_add_tail(®ion->list, head);
3206 region = iommu_alloc_resv_region(MSI_RANGE_START,
3207 MSI_RANGE_END - MSI_RANGE_START + 1,
3211 list_add_tail(®ion->list, head);
3213 region = iommu_alloc_resv_region(HT_RANGE_START,
3214 HT_RANGE_END - HT_RANGE_START + 1,
3215 0, IOMMU_RESV_RESERVED);
3218 list_add_tail(®ion->list, head);
3221 static void amd_iommu_put_resv_regions(struct device *dev,
3222 struct list_head *head)
3224 struct iommu_resv_region *entry, *next;
3226 list_for_each_entry_safe(entry, next, head, list)
3230 static void amd_iommu_apply_resv_region(struct device *dev,
3231 struct iommu_domain *domain,
3232 struct iommu_resv_region *region)
3234 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3235 unsigned long start, end;
3237 start = IOVA_PFN(region->start);
3238 end = IOVA_PFN(region->start + region->length - 1);
3240 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3243 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3246 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3247 return dev_data->defer_attach;
3250 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3252 struct protection_domain *dom = to_pdomain(domain);
3253 unsigned long flags;
3255 spin_lock_irqsave(&dom->lock, flags);
3256 domain_flush_tlb_pde(dom);
3257 domain_flush_complete(dom);
3258 spin_unlock_irqrestore(&dom->lock, flags);
3261 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
3262 struct iommu_iotlb_gather *gather)
3264 amd_iommu_flush_iotlb_all(domain);
3267 const struct iommu_ops amd_iommu_ops = {
3268 .capable = amd_iommu_capable,
3269 .domain_alloc = amd_iommu_domain_alloc,
3270 .domain_free = amd_iommu_domain_free,
3271 .attach_dev = amd_iommu_attach_device,
3272 .detach_dev = amd_iommu_detach_device,
3273 .map = amd_iommu_map,
3274 .unmap = amd_iommu_unmap,
3275 .iova_to_phys = amd_iommu_iova_to_phys,
3276 .add_device = amd_iommu_add_device,
3277 .remove_device = amd_iommu_remove_device,
3278 .device_group = amd_iommu_device_group,
3279 .get_resv_regions = amd_iommu_get_resv_regions,
3280 .put_resv_regions = amd_iommu_put_resv_regions,
3281 .apply_resv_region = amd_iommu_apply_resv_region,
3282 .is_attach_deferred = amd_iommu_is_attach_deferred,
3283 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3284 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3285 .iotlb_sync = amd_iommu_iotlb_sync,
3288 /*****************************************************************************
3290 * The next functions do a basic initialization of IOMMU for pass through
3293 * In passthrough mode the IOMMU is initialized and enabled but not used for
3294 * DMA-API translation.
3296 *****************************************************************************/
3298 /* IOMMUv2 specific functions */
3299 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3301 return atomic_notifier_chain_register(&ppr_notifier, nb);
3303 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3305 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3307 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3309 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3311 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3313 struct protection_domain *domain = to_pdomain(dom);
3314 unsigned long flags;
3316 spin_lock_irqsave(&domain->lock, flags);
3318 /* Update data structure */
3319 domain->mode = PAGE_MODE_NONE;
3321 /* Make changes visible to IOMMUs */
3322 update_domain(domain);
3324 /* Page-table is not visible to IOMMU anymore, so free it */
3325 free_pagetable(domain);
3327 spin_unlock_irqrestore(&domain->lock, flags);
3329 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3331 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3333 struct protection_domain *domain = to_pdomain(dom);
3334 unsigned long flags;
3337 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3340 /* Number of GCR3 table levels required */
3341 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3344 if (levels > amd_iommu_max_glx_val)
3347 spin_lock_irqsave(&domain->lock, flags);
3350 * Save us all sanity checks whether devices already in the
3351 * domain support IOMMUv2. Just force that the domain has no
3352 * devices attached when it is switched into IOMMUv2 mode.
3355 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3359 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3360 if (domain->gcr3_tbl == NULL)
3363 domain->glx = levels;
3364 domain->flags |= PD_IOMMUV2_MASK;
3366 update_domain(domain);
3371 spin_unlock_irqrestore(&domain->lock, flags);
3375 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3377 static int __flush_pasid(struct protection_domain *domain, int pasid,
3378 u64 address, bool size)
3380 struct iommu_dev_data *dev_data;
3381 struct iommu_cmd cmd;
3384 if (!(domain->flags & PD_IOMMUV2_MASK))
3387 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3390 * IOMMU TLB needs to be flushed before Device TLB to
3391 * prevent device TLB refill from IOMMU TLB
3393 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3394 if (domain->dev_iommu[i] == 0)
3397 ret = iommu_queue_command(amd_iommus[i], &cmd);
3402 /* Wait until IOMMU TLB flushes are complete */
3403 domain_flush_complete(domain);
3405 /* Now flush device TLBs */
3406 list_for_each_entry(dev_data, &domain->dev_list, list) {
3407 struct amd_iommu *iommu;
3411 There might be non-IOMMUv2 capable devices in an IOMMUv2
3414 if (!dev_data->ats.enabled)
3417 qdep = dev_data->ats.qdep;
3418 iommu = amd_iommu_rlookup_table[dev_data->devid];
3420 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3421 qdep, address, size);
3423 ret = iommu_queue_command(iommu, &cmd);
3428 /* Wait until all device TLBs are flushed */
3429 domain_flush_complete(domain);
3438 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3441 return __flush_pasid(domain, pasid, address, false);
3444 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3447 struct protection_domain *domain = to_pdomain(dom);
3448 unsigned long flags;
3451 spin_lock_irqsave(&domain->lock, flags);
3452 ret = __amd_iommu_flush_page(domain, pasid, address);
3453 spin_unlock_irqrestore(&domain->lock, flags);
3457 EXPORT_SYMBOL(amd_iommu_flush_page);
3459 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3461 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3465 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3467 struct protection_domain *domain = to_pdomain(dom);
3468 unsigned long flags;
3471 spin_lock_irqsave(&domain->lock, flags);
3472 ret = __amd_iommu_flush_tlb(domain, pasid);
3473 spin_unlock_irqrestore(&domain->lock, flags);
3477 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3479 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3486 index = (pasid >> (9 * level)) & 0x1ff;
3492 if (!(*pte & GCR3_VALID)) {
3496 root = (void *)get_zeroed_page(GFP_ATOMIC);
3500 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3503 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3511 static int __set_gcr3(struct protection_domain *domain, int pasid,
3516 if (domain->mode != PAGE_MODE_NONE)
3519 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3523 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3525 return __amd_iommu_flush_tlb(domain, pasid);
3528 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3532 if (domain->mode != PAGE_MODE_NONE)
3535 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3541 return __amd_iommu_flush_tlb(domain, pasid);
3544 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3547 struct protection_domain *domain = to_pdomain(dom);
3548 unsigned long flags;
3551 spin_lock_irqsave(&domain->lock, flags);
3552 ret = __set_gcr3(domain, pasid, cr3);
3553 spin_unlock_irqrestore(&domain->lock, flags);
3557 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3559 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3561 struct protection_domain *domain = to_pdomain(dom);
3562 unsigned long flags;
3565 spin_lock_irqsave(&domain->lock, flags);
3566 ret = __clear_gcr3(domain, pasid);
3567 spin_unlock_irqrestore(&domain->lock, flags);
3571 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3573 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3574 int status, int tag)
3576 struct iommu_dev_data *dev_data;
3577 struct amd_iommu *iommu;
3578 struct iommu_cmd cmd;
3580 dev_data = get_dev_data(&pdev->dev);
3581 iommu = amd_iommu_rlookup_table[dev_data->devid];
3583 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3584 tag, dev_data->pri_tlp);
3586 return iommu_queue_command(iommu, &cmd);
3588 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3590 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3592 struct protection_domain *pdomain;
3594 pdomain = get_domain(&pdev->dev);
3595 if (IS_ERR(pdomain))
3598 /* Only return IOMMUv2 domains */
3599 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3602 return &pdomain->domain;
3604 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3606 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3608 struct iommu_dev_data *dev_data;
3610 if (!amd_iommu_v2_supported())
3613 dev_data = get_dev_data(&pdev->dev);
3614 dev_data->errata |= (1 << erratum);
3616 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3618 int amd_iommu_device_info(struct pci_dev *pdev,
3619 struct amd_iommu_device_info *info)
3624 if (pdev == NULL || info == NULL)
3627 if (!amd_iommu_v2_supported())
3630 memset(info, 0, sizeof(*info));
3632 if (!pci_ats_disabled()) {
3633 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3635 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3638 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3640 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3642 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3646 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3647 max_pasids = min(max_pasids, (1 << 20));
3649 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3650 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3652 features = pci_pasid_features(pdev);
3653 if (features & PCI_PASID_CAP_EXEC)
3654 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3655 if (features & PCI_PASID_CAP_PRIV)
3656 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3661 EXPORT_SYMBOL(amd_iommu_device_info);
3663 #ifdef CONFIG_IRQ_REMAP
3665 /*****************************************************************************
3667 * Interrupt Remapping Implementation
3669 *****************************************************************************/
3671 static struct irq_chip amd_ir_chip;
3672 static DEFINE_SPINLOCK(iommu_table_lock);
3674 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3678 dte = amd_iommu_dev_table[devid].data[2];
3679 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3680 dte |= iommu_virt_to_phys(table->table);
3681 dte |= DTE_IRQ_REMAP_INTCTL;
3682 dte |= DTE_IRQ_TABLE_LEN;
3683 dte |= DTE_IRQ_REMAP_ENABLE;
3685 amd_iommu_dev_table[devid].data[2] = dte;
3688 static struct irq_remap_table *get_irq_table(u16 devid)
3690 struct irq_remap_table *table;
3692 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3693 "%s: no iommu for devid %x\n", __func__, devid))
3696 table = irq_lookup_table[devid];
3697 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3703 static struct irq_remap_table *__alloc_irq_table(void)
3705 struct irq_remap_table *table;
3707 table = kzalloc(sizeof(*table), GFP_KERNEL);
3711 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3712 if (!table->table) {
3716 raw_spin_lock_init(&table->lock);
3718 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3719 memset(table->table, 0,
3720 MAX_IRQS_PER_TABLE * sizeof(u32));
3722 memset(table->table, 0,
3723 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3727 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3728 struct irq_remap_table *table)
3730 irq_lookup_table[devid] = table;
3731 set_dte_irq_entry(devid, table);
3732 iommu_flush_dte(iommu, devid);
3735 static struct irq_remap_table *alloc_irq_table(u16 devid)
3737 struct irq_remap_table *table = NULL;
3738 struct irq_remap_table *new_table = NULL;
3739 struct amd_iommu *iommu;
3740 unsigned long flags;
3743 spin_lock_irqsave(&iommu_table_lock, flags);
3745 iommu = amd_iommu_rlookup_table[devid];
3749 table = irq_lookup_table[devid];
3753 alias = amd_iommu_alias_table[devid];
3754 table = irq_lookup_table[alias];
3756 set_remap_table_entry(iommu, devid, table);
3759 spin_unlock_irqrestore(&iommu_table_lock, flags);
3761 /* Nothing there yet, allocate new irq remapping table */
3762 new_table = __alloc_irq_table();
3766 spin_lock_irqsave(&iommu_table_lock, flags);
3768 table = irq_lookup_table[devid];
3772 table = irq_lookup_table[alias];
3774 set_remap_table_entry(iommu, devid, table);
3781 set_remap_table_entry(iommu, devid, table);
3783 set_remap_table_entry(iommu, alias, table);
3786 iommu_completion_wait(iommu);
3789 spin_unlock_irqrestore(&iommu_table_lock, flags);
3792 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3798 static int alloc_irq_index(u16 devid, int count, bool align)
3800 struct irq_remap_table *table;
3801 int index, c, alignment = 1;
3802 unsigned long flags;
3803 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3808 table = alloc_irq_table(devid);
3813 alignment = roundup_pow_of_two(count);
3815 raw_spin_lock_irqsave(&table->lock, flags);
3817 /* Scan table for free entries */
3818 for (index = ALIGN(table->min_index, alignment), c = 0;
3819 index < MAX_IRQS_PER_TABLE;) {
3820 if (!iommu->irte_ops->is_allocated(table, index)) {
3824 index = ALIGN(index + 1, alignment);
3830 iommu->irte_ops->set_allocated(table, index - c + 1);
3842 raw_spin_unlock_irqrestore(&table->lock, flags);
3847 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3848 struct amd_ir_data *data)
3850 struct irq_remap_table *table;
3851 struct amd_iommu *iommu;
3852 unsigned long flags;
3853 struct irte_ga *entry;
3855 iommu = amd_iommu_rlookup_table[devid];
3859 table = get_irq_table(devid);
3863 raw_spin_lock_irqsave(&table->lock, flags);
3865 entry = (struct irte_ga *)table->table;
3866 entry = &entry[index];
3867 entry->lo.fields_remap.valid = 0;
3868 entry->hi.val = irte->hi.val;
3869 entry->lo.val = irte->lo.val;
3870 entry->lo.fields_remap.valid = 1;
3874 raw_spin_unlock_irqrestore(&table->lock, flags);
3876 iommu_flush_irt(iommu, devid);
3877 iommu_completion_wait(iommu);
3882 static int modify_irte(u16 devid, int index, union irte *irte)
3884 struct irq_remap_table *table;
3885 struct amd_iommu *iommu;
3886 unsigned long flags;
3888 iommu = amd_iommu_rlookup_table[devid];
3892 table = get_irq_table(devid);
3896 raw_spin_lock_irqsave(&table->lock, flags);
3897 table->table[index] = irte->val;
3898 raw_spin_unlock_irqrestore(&table->lock, flags);
3900 iommu_flush_irt(iommu, devid);
3901 iommu_completion_wait(iommu);
3906 static void free_irte(u16 devid, int index)
3908 struct irq_remap_table *table;
3909 struct amd_iommu *iommu;
3910 unsigned long flags;
3912 iommu = amd_iommu_rlookup_table[devid];
3916 table = get_irq_table(devid);
3920 raw_spin_lock_irqsave(&table->lock, flags);
3921 iommu->irte_ops->clear_allocated(table, index);
3922 raw_spin_unlock_irqrestore(&table->lock, flags);
3924 iommu_flush_irt(iommu, devid);
3925 iommu_completion_wait(iommu);
3928 static void irte_prepare(void *entry,
3929 u32 delivery_mode, u32 dest_mode,
3930 u8 vector, u32 dest_apicid, int devid)
3932 union irte *irte = (union irte *) entry;
3935 irte->fields.vector = vector;
3936 irte->fields.int_type = delivery_mode;
3937 irte->fields.destination = dest_apicid;
3938 irte->fields.dm = dest_mode;
3939 irte->fields.valid = 1;
3942 static void irte_ga_prepare(void *entry,
3943 u32 delivery_mode, u32 dest_mode,
3944 u8 vector, u32 dest_apicid, int devid)
3946 struct irte_ga *irte = (struct irte_ga *) entry;
3950 irte->lo.fields_remap.int_type = delivery_mode;
3951 irte->lo.fields_remap.dm = dest_mode;
3952 irte->hi.fields.vector = vector;
3953 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3954 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3955 irte->lo.fields_remap.valid = 1;
3958 static void irte_activate(void *entry, u16 devid, u16 index)
3960 union irte *irte = (union irte *) entry;
3962 irte->fields.valid = 1;
3963 modify_irte(devid, index, irte);
3966 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3968 struct irte_ga *irte = (struct irte_ga *) entry;
3970 irte->lo.fields_remap.valid = 1;
3971 modify_irte_ga(devid, index, irte, NULL);
3974 static void irte_deactivate(void *entry, u16 devid, u16 index)
3976 union irte *irte = (union irte *) entry;
3978 irte->fields.valid = 0;
3979 modify_irte(devid, index, irte);
3982 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3984 struct irte_ga *irte = (struct irte_ga *) entry;
3986 irte->lo.fields_remap.valid = 0;
3987 modify_irte_ga(devid, index, irte, NULL);
3990 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3991 u8 vector, u32 dest_apicid)
3993 union irte *irte = (union irte *) entry;
3995 irte->fields.vector = vector;
3996 irte->fields.destination = dest_apicid;
3997 modify_irte(devid, index, irte);
4000 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
4001 u8 vector, u32 dest_apicid)
4003 struct irte_ga *irte = (struct irte_ga *) entry;
4005 if (!irte->lo.fields_remap.guest_mode) {
4006 irte->hi.fields.vector = vector;
4007 irte->lo.fields_remap.destination =
4008 APICID_TO_IRTE_DEST_LO(dest_apicid);
4009 irte->hi.fields.destination =
4010 APICID_TO_IRTE_DEST_HI(dest_apicid);
4011 modify_irte_ga(devid, index, irte, NULL);
4015 #define IRTE_ALLOCATED (~1U)
4016 static void irte_set_allocated(struct irq_remap_table *table, int index)
4018 table->table[index] = IRTE_ALLOCATED;
4021 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4023 struct irte_ga *ptr = (struct irte_ga *)table->table;
4024 struct irte_ga *irte = &ptr[index];
4026 memset(&irte->lo.val, 0, sizeof(u64));
4027 memset(&irte->hi.val, 0, sizeof(u64));
4028 irte->hi.fields.vector = 0xff;
4031 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4033 union irte *ptr = (union irte *)table->table;
4034 union irte *irte = &ptr[index];
4036 return irte->val != 0;
4039 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4041 struct irte_ga *ptr = (struct irte_ga *)table->table;
4042 struct irte_ga *irte = &ptr[index];
4044 return irte->hi.fields.vector != 0;
4047 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4049 table->table[index] = 0;
4052 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4054 struct irte_ga *ptr = (struct irte_ga *)table->table;
4055 struct irte_ga *irte = &ptr[index];
4057 memset(&irte->lo.val, 0, sizeof(u64));
4058 memset(&irte->hi.val, 0, sizeof(u64));
4061 static int get_devid(struct irq_alloc_info *info)
4065 switch (info->type) {
4066 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4067 devid = get_ioapic_devid(info->ioapic_id);
4069 case X86_IRQ_ALLOC_TYPE_HPET:
4070 devid = get_hpet_devid(info->hpet_id);
4072 case X86_IRQ_ALLOC_TYPE_MSI:
4073 case X86_IRQ_ALLOC_TYPE_MSIX:
4074 devid = get_device_id(&info->msi_dev->dev);
4084 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4086 struct amd_iommu *iommu;
4092 devid = get_devid(info);
4094 iommu = amd_iommu_rlookup_table[devid];
4096 return iommu->ir_domain;
4102 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4104 struct amd_iommu *iommu;
4110 switch (info->type) {
4111 case X86_IRQ_ALLOC_TYPE_MSI:
4112 case X86_IRQ_ALLOC_TYPE_MSIX:
4113 devid = get_device_id(&info->msi_dev->dev);
4117 iommu = amd_iommu_rlookup_table[devid];
4119 return iommu->msi_domain;
4128 struct irq_remap_ops amd_iommu_irq_ops = {
4129 .prepare = amd_iommu_prepare,
4130 .enable = amd_iommu_enable,
4131 .disable = amd_iommu_disable,
4132 .reenable = amd_iommu_reenable,
4133 .enable_faulting = amd_iommu_enable_faulting,
4134 .get_ir_irq_domain = get_ir_irq_domain,
4135 .get_irq_domain = get_irq_domain,
4138 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4139 struct irq_cfg *irq_cfg,
4140 struct irq_alloc_info *info,
4141 int devid, int index, int sub_handle)
4143 struct irq_2_irte *irte_info = &data->irq_2_irte;
4144 struct msi_msg *msg = &data->msi_entry;
4145 struct IO_APIC_route_entry *entry;
4146 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4151 data->irq_2_irte.devid = devid;
4152 data->irq_2_irte.index = index + sub_handle;
4153 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4154 apic->irq_dest_mode, irq_cfg->vector,
4155 irq_cfg->dest_apicid, devid);
4157 switch (info->type) {
4158 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4159 /* Setup IOAPIC entry */
4160 entry = info->ioapic_entry;
4161 info->ioapic_entry = NULL;
4162 memset(entry, 0, sizeof(*entry));
4163 entry->vector = index;
4165 entry->trigger = info->ioapic_trigger;
4166 entry->polarity = info->ioapic_polarity;
4167 /* Mask level triggered irqs. */
4168 if (info->ioapic_trigger)
4172 case X86_IRQ_ALLOC_TYPE_HPET:
4173 case X86_IRQ_ALLOC_TYPE_MSI:
4174 case X86_IRQ_ALLOC_TYPE_MSIX:
4175 msg->address_hi = MSI_ADDR_BASE_HI;
4176 msg->address_lo = MSI_ADDR_BASE_LO;
4177 msg->data = irte_info->index;
4186 struct amd_irte_ops irte_32_ops = {
4187 .prepare = irte_prepare,
4188 .activate = irte_activate,
4189 .deactivate = irte_deactivate,
4190 .set_affinity = irte_set_affinity,
4191 .set_allocated = irte_set_allocated,
4192 .is_allocated = irte_is_allocated,
4193 .clear_allocated = irte_clear_allocated,
4196 struct amd_irte_ops irte_128_ops = {
4197 .prepare = irte_ga_prepare,
4198 .activate = irte_ga_activate,
4199 .deactivate = irte_ga_deactivate,
4200 .set_affinity = irte_ga_set_affinity,
4201 .set_allocated = irte_ga_set_allocated,
4202 .is_allocated = irte_ga_is_allocated,
4203 .clear_allocated = irte_ga_clear_allocated,
4206 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4207 unsigned int nr_irqs, void *arg)
4209 struct irq_alloc_info *info = arg;
4210 struct irq_data *irq_data;
4211 struct amd_ir_data *data = NULL;
4212 struct irq_cfg *cfg;
4218 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4219 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4223 * With IRQ remapping enabled, don't need contiguous CPU vectors
4224 * to support multiple MSI interrupts.
4226 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4227 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4229 devid = get_devid(info);
4233 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4237 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4238 struct irq_remap_table *table;
4239 struct amd_iommu *iommu;
4241 table = alloc_irq_table(devid);
4243 if (!table->min_index) {
4245 * Keep the first 32 indexes free for IOAPIC
4248 table->min_index = 32;
4249 iommu = amd_iommu_rlookup_table[devid];
4250 for (i = 0; i < 32; ++i)
4251 iommu->irte_ops->set_allocated(table, i);
4253 WARN_ON(table->min_index != 32);
4254 index = info->ioapic_pin;
4259 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4261 index = alloc_irq_index(devid, nr_irqs, align);
4264 pr_warn("Failed to allocate IRTE\n");
4266 goto out_free_parent;
4269 for (i = 0; i < nr_irqs; i++) {
4270 irq_data = irq_domain_get_irq_data(domain, virq + i);
4271 cfg = irqd_cfg(irq_data);
4272 if (!irq_data || !cfg) {
4278 data = kzalloc(sizeof(*data), GFP_KERNEL);
4282 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4283 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4285 data->entry = kzalloc(sizeof(struct irte_ga),
4292 irq_data->hwirq = (devid << 16) + i;
4293 irq_data->chip_data = data;
4294 irq_data->chip = &amd_ir_chip;
4295 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4296 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4302 for (i--; i >= 0; i--) {
4303 irq_data = irq_domain_get_irq_data(domain, virq + i);
4305 kfree(irq_data->chip_data);
4307 for (i = 0; i < nr_irqs; i++)
4308 free_irte(devid, index + i);
4310 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4314 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4315 unsigned int nr_irqs)
4317 struct irq_2_irte *irte_info;
4318 struct irq_data *irq_data;
4319 struct amd_ir_data *data;
4322 for (i = 0; i < nr_irqs; i++) {
4323 irq_data = irq_domain_get_irq_data(domain, virq + i);
4324 if (irq_data && irq_data->chip_data) {
4325 data = irq_data->chip_data;
4326 irte_info = &data->irq_2_irte;
4327 free_irte(irte_info->devid, irte_info->index);
4332 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4335 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4336 struct amd_ir_data *ir_data,
4337 struct irq_2_irte *irte_info,
4338 struct irq_cfg *cfg);
4340 static int irq_remapping_activate(struct irq_domain *domain,
4341 struct irq_data *irq_data, bool reserve)
4343 struct amd_ir_data *data = irq_data->chip_data;
4344 struct irq_2_irte *irte_info = &data->irq_2_irte;
4345 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4346 struct irq_cfg *cfg = irqd_cfg(irq_data);
4351 iommu->irte_ops->activate(data->entry, irte_info->devid,
4353 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4357 static void irq_remapping_deactivate(struct irq_domain *domain,
4358 struct irq_data *irq_data)
4360 struct amd_ir_data *data = irq_data->chip_data;
4361 struct irq_2_irte *irte_info = &data->irq_2_irte;
4362 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4365 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4369 static const struct irq_domain_ops amd_ir_domain_ops = {
4370 .alloc = irq_remapping_alloc,
4371 .free = irq_remapping_free,
4372 .activate = irq_remapping_activate,
4373 .deactivate = irq_remapping_deactivate,
4376 int amd_iommu_activate_guest_mode(void *data)
4378 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4379 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4381 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4382 !entry || entry->lo.fields_vapic.guest_mode)
4388 entry->lo.fields_vapic.guest_mode = 1;
4389 entry->lo.fields_vapic.ga_log_intr = 1;
4390 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
4391 entry->hi.fields.vector = ir_data->ga_vector;
4392 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
4394 return modify_irte_ga(ir_data->irq_2_irte.devid,
4395 ir_data->irq_2_irte.index, entry, NULL);
4397 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
4399 int amd_iommu_deactivate_guest_mode(void *data)
4401 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4402 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4403 struct irq_cfg *cfg = ir_data->cfg;
4405 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4406 !entry || !entry->lo.fields_vapic.guest_mode)
4412 entry->lo.fields_remap.dm = apic->irq_dest_mode;
4413 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
4414 entry->hi.fields.vector = cfg->vector;
4415 entry->lo.fields_remap.destination =
4416 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4417 entry->hi.fields.destination =
4418 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4420 return modify_irte_ga(ir_data->irq_2_irte.devid,
4421 ir_data->irq_2_irte.index, entry, NULL);
4423 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
4425 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4428 struct amd_iommu *iommu;
4429 struct amd_iommu_pi_data *pi_data = vcpu_info;
4430 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4431 struct amd_ir_data *ir_data = data->chip_data;
4432 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4433 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4436 * This device has never been set up for guest mode.
4437 * we should not modify the IRTE
4439 if (!dev_data || !dev_data->use_vapic)
4442 ir_data->cfg = irqd_cfg(data);
4443 pi_data->ir_data = ir_data;
4446 * SVM tries to set up for VAPIC mode, but we are in
4447 * legacy mode. So, we force legacy mode instead.
4449 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4450 pr_debug("%s: Fall back to using intr legacy remap\n",
4452 pi_data->is_guest_mode = false;
4455 iommu = amd_iommu_rlookup_table[irte_info->devid];
4459 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4460 if (pi_data->is_guest_mode) {
4461 ir_data->ga_root_ptr = (pi_data->base >> 12);
4462 ir_data->ga_vector = vcpu_pi_info->vector;
4463 ir_data->ga_tag = pi_data->ga_tag;
4464 ret = amd_iommu_activate_guest_mode(ir_data);
4466 ir_data->cached_ga_tag = pi_data->ga_tag;
4468 ret = amd_iommu_deactivate_guest_mode(ir_data);
4471 * This communicates the ga_tag back to the caller
4472 * so that it can do all the necessary clean up.
4475 ir_data->cached_ga_tag = 0;
4482 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4483 struct amd_ir_data *ir_data,
4484 struct irq_2_irte *irte_info,
4485 struct irq_cfg *cfg)
4489 * Atomically updates the IRTE with the new destination, vector
4490 * and flushes the interrupt entry cache.
4492 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4493 irte_info->index, cfg->vector,
4497 static int amd_ir_set_affinity(struct irq_data *data,
4498 const struct cpumask *mask, bool force)
4500 struct amd_ir_data *ir_data = data->chip_data;
4501 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4502 struct irq_cfg *cfg = irqd_cfg(data);
4503 struct irq_data *parent = data->parent_data;
4504 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4510 ret = parent->chip->irq_set_affinity(parent, mask, force);
4511 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4514 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4516 * After this point, all the interrupts will start arriving
4517 * at the new destination. So, time to cleanup the previous
4518 * vector allocation.
4520 send_cleanup_vector(cfg);
4522 return IRQ_SET_MASK_OK_DONE;
4525 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4527 struct amd_ir_data *ir_data = irq_data->chip_data;
4529 *msg = ir_data->msi_entry;
4532 static struct irq_chip amd_ir_chip = {
4534 .irq_ack = apic_ack_irq,
4535 .irq_set_affinity = amd_ir_set_affinity,
4536 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4537 .irq_compose_msi_msg = ir_compose_msi_msg,
4540 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4542 struct fwnode_handle *fn;
4544 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4547 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4548 irq_domain_free_fwnode(fn);
4549 if (!iommu->ir_domain)
4552 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4553 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4559 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4561 unsigned long flags;
4562 struct amd_iommu *iommu;
4563 struct irq_remap_table *table;
4564 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4565 int devid = ir_data->irq_2_irte.devid;
4566 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4567 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4569 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4570 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4573 iommu = amd_iommu_rlookup_table[devid];
4577 table = get_irq_table(devid);
4581 raw_spin_lock_irqsave(&table->lock, flags);
4583 if (ref->lo.fields_vapic.guest_mode) {
4585 ref->lo.fields_vapic.destination =
4586 APICID_TO_IRTE_DEST_LO(cpu);
4587 ref->hi.fields.destination =
4588 APICID_TO_IRTE_DEST_HI(cpu);
4590 ref->lo.fields_vapic.is_run = is_run;
4594 raw_spin_unlock_irqrestore(&table->lock, flags);
4596 iommu_flush_irt(iommu, devid);
4597 iommu_completion_wait(iommu);
4600 EXPORT_SYMBOL(amd_iommu_update_ga);