2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #define pr_fmt(fmt) "AMD-Vi: " fmt
22 #include <linux/ratelimit.h>
23 #include <linux/pci.h>
24 #include <linux/acpi.h>
25 #include <linux/amba/bus.h>
26 #include <linux/platform_device.h>
27 #include <linux/pci-ats.h>
28 #include <linux/bitmap.h>
29 #include <linux/slab.h>
30 #include <linux/debugfs.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dma-direct.h>
34 #include <linux/iommu-helper.h>
35 #include <linux/iommu.h>
36 #include <linux/delay.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/notifier.h>
39 #include <linux/export.h>
40 #include <linux/irq.h>
41 #include <linux/msi.h>
42 #include <linux/dma-contiguous.h>
43 #include <linux/irqdomain.h>
44 #include <linux/percpu.h>
45 #include <linux/iova.h>
46 #include <asm/irq_remapping.h>
47 #include <asm/io_apic.h>
49 #include <asm/hw_irq.h>
50 #include <asm/msidef.h>
51 #include <asm/proto.h>
52 #include <asm/iommu.h>
56 #include "amd_iommu_proto.h"
57 #include "amd_iommu_types.h"
58 #include "irq_remapping.h"
60 #define AMD_IOMMU_MAPPING_ERROR 0
62 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
64 #define LOOP_TIMEOUT 100000
66 /* IO virtual address start page frame number */
67 #define IOVA_START_PFN (1)
68 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
70 /* Reserved IOVA ranges */
71 #define MSI_RANGE_START (0xfee00000)
72 #define MSI_RANGE_END (0xfeefffff)
73 #define HT_RANGE_START (0xfd00000000ULL)
74 #define HT_RANGE_END (0xffffffffffULL)
77 * This bitmap is used to advertise the page sizes our hardware support
78 * to the IOMMU core, which will then use this information to split
79 * physically contiguous memory regions it is mapping into page sizes
82 * 512GB Pages are not supported due to a hardware bug
84 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
86 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
87 static DEFINE_SPINLOCK(pd_bitmap_lock);
89 /* List of all available dev_data structures */
90 static LLIST_HEAD(dev_data_list);
92 LIST_HEAD(ioapic_map);
94 LIST_HEAD(acpihid_map);
97 * Domain for untranslated devices - only allocated
98 * if iommu=pt passed on kernel cmd line.
100 const struct iommu_ops amd_iommu_ops;
102 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
103 int amd_iommu_max_glx_val = -1;
105 static const struct dma_map_ops amd_iommu_dma_ops;
108 * general struct to manage commands send to an IOMMU
114 struct kmem_cache *amd_iommu_irq_cache;
116 static void update_domain(struct protection_domain *domain);
117 static int protection_domain_init(struct protection_domain *domain);
118 static void detach_device(struct device *dev);
119 static void iova_domain_flush_tlb(struct iova_domain *iovad);
122 * Data container for a dma_ops specific protection domain
124 struct dma_ops_domain {
125 /* generic protection domain information */
126 struct protection_domain domain;
129 struct iova_domain iovad;
132 static struct iova_domain reserved_iova_ranges;
133 static struct lock_class_key reserved_rbtree_key;
135 /****************************************************************************
139 ****************************************************************************/
141 static inline int match_hid_uid(struct device *dev,
142 struct acpihid_map_entry *entry)
144 const char *hid, *uid;
146 hid = acpi_device_hid(ACPI_COMPANION(dev));
147 uid = acpi_device_uid(ACPI_COMPANION(dev));
153 return strcmp(hid, entry->hid);
156 return strcmp(hid, entry->hid);
158 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
161 static inline u16 get_pci_device_id(struct device *dev)
163 struct pci_dev *pdev = to_pci_dev(dev);
165 return PCI_DEVID(pdev->bus->number, pdev->devfn);
168 static inline int get_acpihid_device_id(struct device *dev,
169 struct acpihid_map_entry **entry)
171 struct acpihid_map_entry *p;
173 list_for_each_entry(p, &acpihid_map, list) {
174 if (!match_hid_uid(dev, p)) {
183 static inline int get_device_id(struct device *dev)
188 devid = get_pci_device_id(dev);
190 devid = get_acpihid_device_id(dev, NULL);
195 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
197 return container_of(dom, struct protection_domain, domain);
200 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
202 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
203 return container_of(domain, struct dma_ops_domain, domain);
206 static struct iommu_dev_data *alloc_dev_data(u16 devid)
208 struct iommu_dev_data *dev_data;
210 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
214 dev_data->devid = devid;
215 ratelimit_default_init(&dev_data->rs);
217 llist_add(&dev_data->dev_data_list, &dev_data_list);
221 static struct iommu_dev_data *search_dev_data(u16 devid)
223 struct iommu_dev_data *dev_data;
224 struct llist_node *node;
226 if (llist_empty(&dev_data_list))
229 node = dev_data_list.first;
230 llist_for_each_entry(dev_data, node, dev_data_list) {
231 if (dev_data->devid == devid)
238 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
240 *(u16 *)data = alias;
244 static u16 get_alias(struct device *dev)
246 struct pci_dev *pdev = to_pci_dev(dev);
247 u16 devid, ivrs_alias, pci_alias;
249 /* The callers make sure that get_device_id() does not fail here */
250 devid = get_device_id(dev);
252 /* For ACPI HID devices, we simply return the devid as such */
253 if (!dev_is_pci(dev))
256 ivrs_alias = amd_iommu_alias_table[devid];
258 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
260 if (ivrs_alias == pci_alias)
266 * The IVRS is fairly reliable in telling us about aliases, but it
267 * can't know about every screwy device. If we don't have an IVRS
268 * reported alias, use the PCI reported alias. In that case we may
269 * still need to initialize the rlookup and dev_table entries if the
270 * alias is to a non-existent device.
272 if (ivrs_alias == devid) {
273 if (!amd_iommu_rlookup_table[pci_alias]) {
274 amd_iommu_rlookup_table[pci_alias] =
275 amd_iommu_rlookup_table[devid];
276 memcpy(amd_iommu_dev_table[pci_alias].data,
277 amd_iommu_dev_table[devid].data,
278 sizeof(amd_iommu_dev_table[pci_alias].data));
284 pr_info("Using IVRS reported alias %02x:%02x.%d "
285 "for device %s[%04x:%04x], kernel reported alias "
286 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
287 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
288 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
289 PCI_FUNC(pci_alias));
292 * If we don't have a PCI DMA alias and the IVRS alias is on the same
293 * bus, then the IVRS table may know about a quirk that we don't.
295 if (pci_alias == devid &&
296 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
297 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
298 pr_info("Added PCI DMA alias %02x.%d for %s\n",
299 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
306 static struct iommu_dev_data *find_dev_data(u16 devid)
308 struct iommu_dev_data *dev_data;
309 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
311 dev_data = search_dev_data(devid);
313 if (dev_data == NULL) {
314 dev_data = alloc_dev_data(devid);
318 if (translation_pre_enabled(iommu))
319 dev_data->defer_attach = true;
325 struct iommu_dev_data *get_dev_data(struct device *dev)
327 return dev->archdata.iommu;
329 EXPORT_SYMBOL(get_dev_data);
332 * Find or create an IOMMU group for a acpihid device.
334 static struct iommu_group *acpihid_device_group(struct device *dev)
336 struct acpihid_map_entry *p, *entry = NULL;
339 devid = get_acpihid_device_id(dev, &entry);
341 return ERR_PTR(devid);
343 list_for_each_entry(p, &acpihid_map, list) {
344 if ((devid == p->devid) && p->group)
345 entry->group = p->group;
349 entry->group = generic_device_group(dev);
351 iommu_group_ref_get(entry->group);
356 static bool pci_iommuv2_capable(struct pci_dev *pdev)
358 static const int caps[] = {
361 PCI_EXT_CAP_ID_PASID,
365 if (pci_ats_disabled())
368 for (i = 0; i < 3; ++i) {
369 pos = pci_find_ext_capability(pdev, caps[i]);
377 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
379 struct iommu_dev_data *dev_data;
381 dev_data = get_dev_data(&pdev->dev);
383 return dev_data->errata & (1 << erratum) ? true : false;
387 * This function checks if the driver got a valid device from the caller to
388 * avoid dereferencing invalid pointers.
390 static bool check_device(struct device *dev)
394 if (!dev || !dev->dma_mask)
397 devid = get_device_id(dev);
401 /* Out of our scope? */
402 if (devid > amd_iommu_last_bdf)
405 if (amd_iommu_rlookup_table[devid] == NULL)
411 static void init_iommu_group(struct device *dev)
413 struct iommu_group *group;
415 group = iommu_group_get_for_dev(dev);
419 iommu_group_put(group);
422 static int iommu_init_device(struct device *dev)
424 struct iommu_dev_data *dev_data;
425 struct amd_iommu *iommu;
428 if (dev->archdata.iommu)
431 devid = get_device_id(dev);
435 iommu = amd_iommu_rlookup_table[devid];
437 dev_data = find_dev_data(devid);
441 dev_data->alias = get_alias(dev);
443 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
444 struct amd_iommu *iommu;
446 iommu = amd_iommu_rlookup_table[dev_data->devid];
447 dev_data->iommu_v2 = iommu->is_iommu_v2;
450 dev->archdata.iommu = dev_data;
452 iommu_device_link(&iommu->iommu, dev);
457 static void iommu_ignore_device(struct device *dev)
462 devid = get_device_id(dev);
466 alias = get_alias(dev);
468 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
469 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
471 amd_iommu_rlookup_table[devid] = NULL;
472 amd_iommu_rlookup_table[alias] = NULL;
475 static void iommu_uninit_device(struct device *dev)
477 struct iommu_dev_data *dev_data;
478 struct amd_iommu *iommu;
481 devid = get_device_id(dev);
485 iommu = amd_iommu_rlookup_table[devid];
487 dev_data = search_dev_data(devid);
491 if (dev_data->domain)
494 iommu_device_unlink(&iommu->iommu, dev);
496 iommu_group_remove_device(dev);
502 * We keep dev_data around for unplugged devices and reuse it when the
503 * device is re-plugged - not doing so would introduce a ton of races.
507 /****************************************************************************
509 * Interrupt handling functions
511 ****************************************************************************/
513 static void dump_dte_entry(u16 devid)
517 for (i = 0; i < 4; ++i)
518 pr_err("DTE[%d]: %016llx\n", i,
519 amd_iommu_dev_table[devid].data[i]);
522 static void dump_command(unsigned long phys_addr)
524 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
527 for (i = 0; i < 4; ++i)
528 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
531 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
532 u64 address, int flags)
534 struct iommu_dev_data *dev_data = NULL;
535 struct pci_dev *pdev;
537 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
540 dev_data = get_dev_data(&pdev->dev);
542 if (dev_data && __ratelimit(&dev_data->rs)) {
543 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
544 domain_id, address, flags);
545 } else if (printk_ratelimit()) {
546 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
547 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
548 domain_id, address, flags);
555 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
557 struct device *dev = iommu->iommu.dev;
558 int type, devid, pasid, flags, tag;
559 volatile u32 *event = __evt;
564 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
565 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
566 pasid = PPR_PASID(*(u64 *)&event[0]);
567 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
568 address = (u64)(((u64)event[3]) << 32) | event[2];
571 /* Did we hit the erratum? */
572 if (++count == LOOP_TIMEOUT) {
573 pr_err("No event written to event log\n");
580 if (type == EVENT_TYPE_IO_FAULT) {
581 amd_iommu_report_page_fault(devid, pasid, address, flags);
584 dev_err(dev, "AMD-Vi: Event logged [");
588 case EVENT_TYPE_ILL_DEV:
589 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
590 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
591 pasid, address, flags);
592 dump_dte_entry(devid);
594 case EVENT_TYPE_DEV_TAB_ERR:
595 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
596 "address=0x%016llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
600 case EVENT_TYPE_PAGE_TAB_ERR:
601 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
602 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
603 pasid, address, flags);
605 case EVENT_TYPE_ILL_CMD:
606 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
607 dump_command(address);
609 case EVENT_TYPE_CMD_HARD_ERR:
610 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
613 case EVENT_TYPE_IOTLB_INV_TO:
614 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
618 case EVENT_TYPE_INV_DEV_REQ:
619 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 pasid, address, flags);
623 case EVENT_TYPE_INV_PPR_REQ:
624 pasid = ((event[0] >> 16) & 0xFFFF)
625 | ((event[1] << 6) & 0xF0000);
626 tag = event[1] & 0x03FF;
627 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
628 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
629 pasid, address, flags);
632 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
633 event[0], event[1], event[2], event[3]);
636 memset(__evt, 0, 4 * sizeof(u32));
639 static void iommu_poll_events(struct amd_iommu *iommu)
643 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
644 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
646 while (head != tail) {
647 iommu_print_event(iommu, iommu->evt_buf + head);
648 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
651 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
654 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
656 struct amd_iommu_fault fault;
658 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
659 pr_err_ratelimited("Unknown PPR request received\n");
663 fault.address = raw[1];
664 fault.pasid = PPR_PASID(raw[0]);
665 fault.device_id = PPR_DEVID(raw[0]);
666 fault.tag = PPR_TAG(raw[0]);
667 fault.flags = PPR_FLAGS(raw[0]);
669 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
672 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
676 if (iommu->ppr_log == NULL)
679 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
680 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
682 while (head != tail) {
687 raw = (u64 *)(iommu->ppr_log + head);
690 * Hardware bug: Interrupt may arrive before the entry is
691 * written to memory. If this happens we need to wait for the
694 for (i = 0; i < LOOP_TIMEOUT; ++i) {
695 if (PPR_REQ_TYPE(raw[0]) != 0)
700 /* Avoid memcpy function-call overhead */
705 * To detect the hardware bug we need to clear the entry
708 raw[0] = raw[1] = 0UL;
710 /* Update head pointer of hardware ring-buffer */
711 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
712 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
714 /* Handle PPR entry */
715 iommu_handle_ppr_entry(iommu, entry);
717 /* Refresh ring-buffer information */
718 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
719 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
723 #ifdef CONFIG_IRQ_REMAP
724 static int (*iommu_ga_log_notifier)(u32);
726 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
728 iommu_ga_log_notifier = notifier;
732 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
734 static void iommu_poll_ga_log(struct amd_iommu *iommu)
736 u32 head, tail, cnt = 0;
738 if (iommu->ga_log == NULL)
741 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
742 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
744 while (head != tail) {
748 raw = (u64 *)(iommu->ga_log + head);
751 /* Avoid memcpy function-call overhead */
754 /* Update head pointer of hardware ring-buffer */
755 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
756 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
758 /* Handle GA entry */
759 switch (GA_REQ_TYPE(log_entry)) {
761 if (!iommu_ga_log_notifier)
764 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
765 __func__, GA_DEVID(log_entry),
768 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
769 pr_err("GA log notifier failed.\n");
776 #endif /* CONFIG_IRQ_REMAP */
778 #define AMD_IOMMU_INT_MASK \
779 (MMIO_STATUS_EVT_INT_MASK | \
780 MMIO_STATUS_PPR_INT_MASK | \
781 MMIO_STATUS_GALOG_INT_MASK)
783 irqreturn_t amd_iommu_int_thread(int irq, void *data)
785 struct amd_iommu *iommu = (struct amd_iommu *) data;
786 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
788 while (status & AMD_IOMMU_INT_MASK) {
789 /* Enable EVT and PPR and GA interrupts again */
790 writel(AMD_IOMMU_INT_MASK,
791 iommu->mmio_base + MMIO_STATUS_OFFSET);
793 if (status & MMIO_STATUS_EVT_INT_MASK) {
794 pr_devel("Processing IOMMU Event Log\n");
795 iommu_poll_events(iommu);
798 if (status & MMIO_STATUS_PPR_INT_MASK) {
799 pr_devel("Processing IOMMU PPR Log\n");
800 iommu_poll_ppr_log(iommu);
803 #ifdef CONFIG_IRQ_REMAP
804 if (status & MMIO_STATUS_GALOG_INT_MASK) {
805 pr_devel("Processing IOMMU GA Log\n");
806 iommu_poll_ga_log(iommu);
811 * Hardware bug: ERBT1312
812 * When re-enabling interrupt (by writing 1
813 * to clear the bit), the hardware might also try to set
814 * the interrupt bit in the event status register.
815 * In this scenario, the bit will be set, and disable
816 * subsequent interrupts.
818 * Workaround: The IOMMU driver should read back the
819 * status register and check if the interrupt bits are cleared.
820 * If not, driver will need to go through the interrupt handler
821 * again and re-clear the bits
823 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
828 irqreturn_t amd_iommu_int_handler(int irq, void *data)
830 return IRQ_WAKE_THREAD;
833 /****************************************************************************
835 * IOMMU command queuing functions
837 ****************************************************************************/
839 static int wait_on_sem(volatile u64 *sem)
843 while (*sem == 0 && i < LOOP_TIMEOUT) {
848 if (i == LOOP_TIMEOUT) {
849 pr_alert("Completion-Wait loop timed out\n");
856 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
857 struct iommu_cmd *cmd)
861 target = iommu->cmd_buf + iommu->cmd_buf_tail;
863 iommu->cmd_buf_tail += sizeof(*cmd);
864 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
866 /* Copy command to buffer */
867 memcpy(target, cmd, sizeof(*cmd));
869 /* Tell the IOMMU about it */
870 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
873 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
875 u64 paddr = iommu_virt_to_phys((void *)address);
877 WARN_ON(address & 0x7ULL);
879 memset(cmd, 0, sizeof(*cmd));
880 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
881 cmd->data[1] = upper_32_bits(paddr);
883 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
886 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
888 memset(cmd, 0, sizeof(*cmd));
889 cmd->data[0] = devid;
890 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
893 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
894 size_t size, u16 domid, int pde)
899 pages = iommu_num_pages(address, size, PAGE_SIZE);
904 * If we have to flush more than one page, flush all
905 * TLB entries for this domain
907 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
911 address &= PAGE_MASK;
913 memset(cmd, 0, sizeof(*cmd));
914 cmd->data[1] |= domid;
915 cmd->data[2] = lower_32_bits(address);
916 cmd->data[3] = upper_32_bits(address);
917 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
918 if (s) /* size bit - we flush more than one 4kb page */
919 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
920 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
921 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
924 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
925 u64 address, size_t size)
930 pages = iommu_num_pages(address, size, PAGE_SIZE);
935 * If we have to flush more than one page, flush all
936 * TLB entries for this domain
938 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
942 address &= PAGE_MASK;
944 memset(cmd, 0, sizeof(*cmd));
945 cmd->data[0] = devid;
946 cmd->data[0] |= (qdep & 0xff) << 24;
947 cmd->data[1] = devid;
948 cmd->data[2] = lower_32_bits(address);
949 cmd->data[3] = upper_32_bits(address);
950 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
952 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
955 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
956 u64 address, bool size)
958 memset(cmd, 0, sizeof(*cmd));
960 address &= ~(0xfffULL);
962 cmd->data[0] = pasid;
963 cmd->data[1] = domid;
964 cmd->data[2] = lower_32_bits(address);
965 cmd->data[3] = upper_32_bits(address);
966 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
967 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
969 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
970 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
973 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
974 int qdep, u64 address, bool size)
976 memset(cmd, 0, sizeof(*cmd));
978 address &= ~(0xfffULL);
980 cmd->data[0] = devid;
981 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
982 cmd->data[0] |= (qdep & 0xff) << 24;
983 cmd->data[1] = devid;
984 cmd->data[1] |= (pasid & 0xff) << 16;
985 cmd->data[2] = lower_32_bits(address);
986 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
987 cmd->data[3] = upper_32_bits(address);
989 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
990 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
993 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
994 int status, int tag, bool gn)
996 memset(cmd, 0, sizeof(*cmd));
998 cmd->data[0] = devid;
1000 cmd->data[1] = pasid;
1001 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1003 cmd->data[3] = tag & 0x1ff;
1004 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1006 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1009 static void build_inv_all(struct iommu_cmd *cmd)
1011 memset(cmd, 0, sizeof(*cmd));
1012 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1015 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1017 memset(cmd, 0, sizeof(*cmd));
1018 cmd->data[0] = devid;
1019 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1023 * Writes the command to the IOMMUs command buffer and informs the
1024 * hardware about the new command.
1026 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1027 struct iommu_cmd *cmd,
1030 unsigned int count = 0;
1031 u32 left, next_tail;
1033 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1035 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1038 /* Skip udelay() the first time around */
1040 if (count == LOOP_TIMEOUT) {
1041 pr_err("Command buffer timeout\n");
1048 /* Update head and recheck remaining space */
1049 iommu->cmd_buf_head = readl(iommu->mmio_base +
1050 MMIO_CMD_HEAD_OFFSET);
1055 copy_cmd_to_buffer(iommu, cmd);
1057 /* Do we need to make sure all commands are processed? */
1058 iommu->need_sync = sync;
1063 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1064 struct iommu_cmd *cmd,
1067 unsigned long flags;
1070 raw_spin_lock_irqsave(&iommu->lock, flags);
1071 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1072 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1077 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1079 return iommu_queue_command_sync(iommu, cmd, true);
1083 * This function queues a completion wait command into the command
1084 * buffer of an IOMMU
1086 static int iommu_completion_wait(struct amd_iommu *iommu)
1088 struct iommu_cmd cmd;
1089 unsigned long flags;
1092 if (!iommu->need_sync)
1096 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1098 raw_spin_lock_irqsave(&iommu->lock, flags);
1102 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1106 ret = wait_on_sem(&iommu->cmd_sem);
1109 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1114 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1116 struct iommu_cmd cmd;
1118 build_inv_dte(&cmd, devid);
1120 return iommu_queue_command(iommu, &cmd);
1123 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1127 for (devid = 0; devid <= 0xffff; ++devid)
1128 iommu_flush_dte(iommu, devid);
1130 iommu_completion_wait(iommu);
1134 * This function uses heavy locking and may disable irqs for some time. But
1135 * this is no issue because it is only called during resume.
1137 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1141 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1142 struct iommu_cmd cmd;
1143 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1145 iommu_queue_command(iommu, &cmd);
1148 iommu_completion_wait(iommu);
1151 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1153 struct iommu_cmd cmd;
1155 build_inv_all(&cmd);
1157 iommu_queue_command(iommu, &cmd);
1158 iommu_completion_wait(iommu);
1161 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1163 struct iommu_cmd cmd;
1165 build_inv_irt(&cmd, devid);
1167 iommu_queue_command(iommu, &cmd);
1170 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1174 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1175 iommu_flush_irt(iommu, devid);
1177 iommu_completion_wait(iommu);
1180 void iommu_flush_all_caches(struct amd_iommu *iommu)
1182 if (iommu_feature(iommu, FEATURE_IA)) {
1183 amd_iommu_flush_all(iommu);
1185 amd_iommu_flush_dte_all(iommu);
1186 amd_iommu_flush_irt_all(iommu);
1187 amd_iommu_flush_tlb_all(iommu);
1192 * Command send function for flushing on-device TLB
1194 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1195 u64 address, size_t size)
1197 struct amd_iommu *iommu;
1198 struct iommu_cmd cmd;
1201 qdep = dev_data->ats.qdep;
1202 iommu = amd_iommu_rlookup_table[dev_data->devid];
1204 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1206 return iommu_queue_command(iommu, &cmd);
1210 * Command send function for invalidating a device table entry
1212 static int device_flush_dte(struct iommu_dev_data *dev_data)
1214 struct amd_iommu *iommu;
1218 iommu = amd_iommu_rlookup_table[dev_data->devid];
1219 alias = dev_data->alias;
1221 ret = iommu_flush_dte(iommu, dev_data->devid);
1222 if (!ret && alias != dev_data->devid)
1223 ret = iommu_flush_dte(iommu, alias);
1227 if (dev_data->ats.enabled)
1228 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1234 * TLB invalidation function which is called from the mapping functions.
1235 * It invalidates a single PTE if the range to flush is within a single
1236 * page. Otherwise it flushes the whole TLB of the IOMMU.
1238 static void __domain_flush_pages(struct protection_domain *domain,
1239 u64 address, size_t size, int pde)
1241 struct iommu_dev_data *dev_data;
1242 struct iommu_cmd cmd;
1245 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1247 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1248 if (!domain->dev_iommu[i])
1252 * Devices of this domain are behind this IOMMU
1253 * We need a TLB flush
1255 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1258 list_for_each_entry(dev_data, &domain->dev_list, list) {
1260 if (!dev_data->ats.enabled)
1263 ret |= device_flush_iotlb(dev_data, address, size);
1269 static void domain_flush_pages(struct protection_domain *domain,
1270 u64 address, size_t size)
1272 __domain_flush_pages(domain, address, size, 0);
1275 /* Flush the whole IO/TLB for a given protection domain */
1276 static void domain_flush_tlb(struct protection_domain *domain)
1278 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1281 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1282 static void domain_flush_tlb_pde(struct protection_domain *domain)
1284 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1287 static void domain_flush_complete(struct protection_domain *domain)
1291 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1292 if (domain && !domain->dev_iommu[i])
1296 * Devices of this domain are behind this IOMMU
1297 * We need to wait for completion of all commands.
1299 iommu_completion_wait(amd_iommus[i]);
1305 * This function flushes the DTEs for all devices in domain
1307 static void domain_flush_devices(struct protection_domain *domain)
1309 struct iommu_dev_data *dev_data;
1311 list_for_each_entry(dev_data, &domain->dev_list, list)
1312 device_flush_dte(dev_data);
1315 /****************************************************************************
1317 * The functions below are used the create the page table mappings for
1318 * unity mapped regions.
1320 ****************************************************************************/
1322 static void free_page_list(struct page *freelist)
1324 while (freelist != NULL) {
1325 unsigned long p = (unsigned long)page_address(freelist);
1326 freelist = freelist->freelist;
1331 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1333 struct page *p = virt_to_page((void *)pt);
1335 p->freelist = freelist;
1340 #define DEFINE_FREE_PT_FN(LVL, FN) \
1341 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1349 for (i = 0; i < 512; ++i) { \
1350 /* PTE present? */ \
1351 if (!IOMMU_PTE_PRESENT(pt[i])) \
1355 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1356 PM_PTE_LEVEL(pt[i]) == 7) \
1359 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1360 freelist = FN(p, freelist); \
1363 return free_pt_page((unsigned long)pt, freelist); \
1366 DEFINE_FREE_PT_FN(l2, free_pt_page)
1367 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1368 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1369 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1370 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1372 static struct page *free_sub_pt(unsigned long root, int mode,
1373 struct page *freelist)
1376 case PAGE_MODE_NONE:
1377 case PAGE_MODE_7_LEVEL:
1379 case PAGE_MODE_1_LEVEL:
1380 freelist = free_pt_page(root, freelist);
1382 case PAGE_MODE_2_LEVEL:
1383 freelist = free_pt_l2(root, freelist);
1385 case PAGE_MODE_3_LEVEL:
1386 freelist = free_pt_l3(root, freelist);
1388 case PAGE_MODE_4_LEVEL:
1389 freelist = free_pt_l4(root, freelist);
1391 case PAGE_MODE_5_LEVEL:
1392 freelist = free_pt_l5(root, freelist);
1394 case PAGE_MODE_6_LEVEL:
1395 freelist = free_pt_l6(root, freelist);
1404 static void free_pagetable(struct protection_domain *domain)
1406 unsigned long root = (unsigned long)domain->pt_root;
1407 struct page *freelist = NULL;
1409 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1410 domain->mode > PAGE_MODE_6_LEVEL);
1412 free_sub_pt(root, domain->mode, freelist);
1414 free_page_list(freelist);
1418 * This function is used to add another level to an IO page table. Adding
1419 * another level increases the size of the address space by 9 bits to a size up
1422 static bool increase_address_space(struct protection_domain *domain,
1427 if (domain->mode == PAGE_MODE_6_LEVEL)
1428 /* address space already 64 bit large */
1431 pte = (void *)get_zeroed_page(gfp);
1435 *pte = PM_LEVEL_PDE(domain->mode,
1436 iommu_virt_to_phys(domain->pt_root));
1437 domain->pt_root = pte;
1439 domain->updated = true;
1444 static u64 *alloc_pte(struct protection_domain *domain,
1445 unsigned long address,
1446 unsigned long page_size,
1453 BUG_ON(!is_power_of_2(page_size));
1455 while (address > PM_LEVEL_SIZE(domain->mode))
1456 increase_address_space(domain, gfp);
1458 level = domain->mode - 1;
1459 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1460 address = PAGE_SIZE_ALIGN(address, page_size);
1461 end_lvl = PAGE_SIZE_LEVEL(page_size);
1463 while (level > end_lvl) {
1468 pte_level = PM_PTE_LEVEL(__pte);
1470 if (!IOMMU_PTE_PRESENT(__pte) ||
1471 pte_level == PAGE_MODE_7_LEVEL) {
1472 page = (u64 *)get_zeroed_page(gfp);
1476 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1478 /* pte could have been changed somewhere. */
1479 if (cmpxchg64(pte, __pte, __npte) != __pte)
1480 free_page((unsigned long)page);
1481 else if (pte_level == PAGE_MODE_7_LEVEL)
1482 domain->updated = true;
1487 /* No level skipping support yet */
1488 if (pte_level != level)
1493 pte = IOMMU_PTE_PAGE(__pte);
1495 if (pte_page && level == end_lvl)
1498 pte = &pte[PM_LEVEL_INDEX(level, address)];
1505 * This function checks if there is a PTE for a given dma address. If
1506 * there is one, it returns the pointer to it.
1508 static u64 *fetch_pte(struct protection_domain *domain,
1509 unsigned long address,
1510 unsigned long *page_size)
1517 if (address > PM_LEVEL_SIZE(domain->mode))
1520 level = domain->mode - 1;
1521 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1522 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1527 if (!IOMMU_PTE_PRESENT(*pte))
1531 if (PM_PTE_LEVEL(*pte) == 7 ||
1532 PM_PTE_LEVEL(*pte) == 0)
1535 /* No level skipping support yet */
1536 if (PM_PTE_LEVEL(*pte) != level)
1541 /* Walk to the next level */
1542 pte = IOMMU_PTE_PAGE(*pte);
1543 pte = &pte[PM_LEVEL_INDEX(level, address)];
1544 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1547 if (PM_PTE_LEVEL(*pte) == 0x07) {
1548 unsigned long pte_mask;
1551 * If we have a series of large PTEs, make
1552 * sure to return a pointer to the first one.
1554 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1555 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1556 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1562 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1567 while (cmpxchg64(pte, pteval, 0) != pteval) {
1568 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1572 if (!IOMMU_PTE_PRESENT(pteval))
1575 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1576 mode = IOMMU_PTE_MODE(pteval);
1578 return free_sub_pt(pt, mode, freelist);
1582 * Generic mapping functions. It maps a physical address into a DMA
1583 * address space. It allocates the page table pages if necessary.
1584 * In the future it can be extended to a generic mapping function
1585 * supporting all features of AMD IOMMU page tables like level skipping
1586 * and full 64 bit address spaces.
1588 static int iommu_map_page(struct protection_domain *dom,
1589 unsigned long bus_addr,
1590 unsigned long phys_addr,
1591 unsigned long page_size,
1595 struct page *freelist = NULL;
1599 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1600 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1602 if (!(prot & IOMMU_PROT_MASK))
1605 count = PAGE_SIZE_PTE_COUNT(page_size);
1606 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1611 for (i = 0; i < count; ++i)
1612 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1614 if (freelist != NULL)
1615 dom->updated = true;
1618 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1619 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1621 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1623 if (prot & IOMMU_PROT_IR)
1624 __pte |= IOMMU_PTE_IR;
1625 if (prot & IOMMU_PROT_IW)
1626 __pte |= IOMMU_PTE_IW;
1628 for (i = 0; i < count; ++i)
1633 /* Everything flushed out, free pages now */
1634 free_page_list(freelist);
1639 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1640 unsigned long bus_addr,
1641 unsigned long page_size)
1643 unsigned long long unmapped;
1644 unsigned long unmap_size;
1647 BUG_ON(!is_power_of_2(page_size));
1651 while (unmapped < page_size) {
1653 pte = fetch_pte(dom, bus_addr, &unmap_size);
1658 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1659 for (i = 0; i < count; i++)
1663 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1664 unmapped += unmap_size;
1667 BUG_ON(unmapped && !is_power_of_2(unmapped));
1672 /****************************************************************************
1674 * The next functions belong to the address allocator for the dma_ops
1675 * interface functions.
1677 ****************************************************************************/
1680 static unsigned long dma_ops_alloc_iova(struct device *dev,
1681 struct dma_ops_domain *dma_dom,
1682 unsigned int pages, u64 dma_mask)
1684 unsigned long pfn = 0;
1686 pages = __roundup_pow_of_two(pages);
1688 if (dma_mask > DMA_BIT_MASK(32))
1689 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1690 IOVA_PFN(DMA_BIT_MASK(32)), false);
1693 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1694 IOVA_PFN(dma_mask), true);
1696 return (pfn << PAGE_SHIFT);
1699 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1700 unsigned long address,
1703 pages = __roundup_pow_of_two(pages);
1704 address >>= PAGE_SHIFT;
1706 free_iova_fast(&dma_dom->iovad, address, pages);
1709 /****************************************************************************
1711 * The next functions belong to the domain allocation. A domain is
1712 * allocated for every IOMMU as the default domain. If device isolation
1713 * is enabled, every device get its own domain. The most important thing
1714 * about domains is the page table mapping the DMA address space they
1717 ****************************************************************************/
1720 * This function adds a protection domain to the global protection domain list
1722 static void add_domain_to_list(struct protection_domain *domain)
1724 unsigned long flags;
1726 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1727 list_add(&domain->list, &amd_iommu_pd_list);
1728 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1732 * This function removes a protection domain to the global
1733 * protection domain list
1735 static void del_domain_from_list(struct protection_domain *domain)
1737 unsigned long flags;
1739 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1740 list_del(&domain->list);
1741 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1744 static u16 domain_id_alloc(void)
1748 spin_lock(&pd_bitmap_lock);
1749 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1751 if (id > 0 && id < MAX_DOMAIN_ID)
1752 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1755 spin_unlock(&pd_bitmap_lock);
1760 static void domain_id_free(int id)
1762 spin_lock(&pd_bitmap_lock);
1763 if (id > 0 && id < MAX_DOMAIN_ID)
1764 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1765 spin_unlock(&pd_bitmap_lock);
1768 static void free_gcr3_tbl_level1(u64 *tbl)
1773 for (i = 0; i < 512; ++i) {
1774 if (!(tbl[i] & GCR3_VALID))
1777 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1779 free_page((unsigned long)ptr);
1783 static void free_gcr3_tbl_level2(u64 *tbl)
1788 for (i = 0; i < 512; ++i) {
1789 if (!(tbl[i] & GCR3_VALID))
1792 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1794 free_gcr3_tbl_level1(ptr);
1798 static void free_gcr3_table(struct protection_domain *domain)
1800 if (domain->glx == 2)
1801 free_gcr3_tbl_level2(domain->gcr3_tbl);
1802 else if (domain->glx == 1)
1803 free_gcr3_tbl_level1(domain->gcr3_tbl);
1805 BUG_ON(domain->glx != 0);
1807 free_page((unsigned long)domain->gcr3_tbl);
1810 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1812 domain_flush_tlb(&dom->domain);
1813 domain_flush_complete(&dom->domain);
1816 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1818 struct dma_ops_domain *dom;
1820 dom = container_of(iovad, struct dma_ops_domain, iovad);
1822 dma_ops_domain_flush_tlb(dom);
1826 * Free a domain, only used if something went wrong in the
1827 * allocation path and we need to free an already allocated page table
1829 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1834 del_domain_from_list(&dom->domain);
1836 put_iova_domain(&dom->iovad);
1838 free_pagetable(&dom->domain);
1841 domain_id_free(dom->domain.id);
1847 * Allocates a new protection domain usable for the dma_ops functions.
1848 * It also initializes the page table and the address allocator data
1849 * structures required for the dma_ops interface
1851 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1853 struct dma_ops_domain *dma_dom;
1855 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1859 if (protection_domain_init(&dma_dom->domain))
1862 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1863 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1864 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1865 if (!dma_dom->domain.pt_root)
1868 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1870 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1873 /* Initialize reserved ranges */
1874 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1876 add_domain_to_list(&dma_dom->domain);
1881 dma_ops_domain_free(dma_dom);
1887 * little helper function to check whether a given protection domain is a
1890 static bool dma_ops_domain(struct protection_domain *domain)
1892 return domain->flags & PD_DMA_OPS_MASK;
1895 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1901 if (domain->mode != PAGE_MODE_NONE)
1902 pte_root = iommu_virt_to_phys(domain->pt_root);
1904 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1905 << DEV_ENTRY_MODE_SHIFT;
1906 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1908 flags = amd_iommu_dev_table[devid].data[1];
1911 flags |= DTE_FLAG_IOTLB;
1914 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1916 if (iommu_feature(iommu, FEATURE_EPHSUP))
1917 pte_root |= 1ULL << DEV_ENTRY_PPR;
1920 if (domain->flags & PD_IOMMUV2_MASK) {
1921 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1922 u64 glx = domain->glx;
1925 pte_root |= DTE_FLAG_GV;
1926 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1928 /* First mask out possible old values for GCR3 table */
1929 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1932 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1935 /* Encode GCR3 table into DTE */
1936 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1939 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1942 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1946 flags &= ~DEV_DOMID_MASK;
1947 flags |= domain->id;
1949 amd_iommu_dev_table[devid].data[1] = flags;
1950 amd_iommu_dev_table[devid].data[0] = pte_root;
1953 static void clear_dte_entry(u16 devid)
1955 /* remove entry from the device table seen by the hardware */
1956 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1957 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1959 amd_iommu_apply_erratum_63(devid);
1962 static void do_attach(struct iommu_dev_data *dev_data,
1963 struct protection_domain *domain)
1965 struct amd_iommu *iommu;
1969 iommu = amd_iommu_rlookup_table[dev_data->devid];
1970 alias = dev_data->alias;
1971 ats = dev_data->ats.enabled;
1973 /* Update data structures */
1974 dev_data->domain = domain;
1975 list_add(&dev_data->list, &domain->dev_list);
1977 /* Do reference counting */
1978 domain->dev_iommu[iommu->index] += 1;
1979 domain->dev_cnt += 1;
1981 /* Update device table */
1982 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1983 if (alias != dev_data->devid)
1984 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1986 device_flush_dte(dev_data);
1989 static void do_detach(struct iommu_dev_data *dev_data)
1991 struct amd_iommu *iommu;
1994 iommu = amd_iommu_rlookup_table[dev_data->devid];
1995 alias = dev_data->alias;
1997 /* decrease reference counters */
1998 dev_data->domain->dev_iommu[iommu->index] -= 1;
1999 dev_data->domain->dev_cnt -= 1;
2001 /* Update data structures */
2002 dev_data->domain = NULL;
2003 list_del(&dev_data->list);
2004 clear_dte_entry(dev_data->devid);
2005 if (alias != dev_data->devid)
2006 clear_dte_entry(alias);
2008 /* Flush the DTE entry */
2009 device_flush_dte(dev_data);
2013 * If a device is not yet associated with a domain, this function makes the
2014 * device visible in the domain
2016 static int __attach_device(struct iommu_dev_data *dev_data,
2017 struct protection_domain *domain)
2022 spin_lock(&domain->lock);
2025 if (dev_data->domain != NULL)
2028 /* Attach alias group root */
2029 do_attach(dev_data, domain);
2036 spin_unlock(&domain->lock);
2042 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2044 pci_disable_ats(pdev);
2045 pci_disable_pri(pdev);
2046 pci_disable_pasid(pdev);
2049 /* FIXME: Change generic reset-function to do the same */
2050 static int pri_reset_while_enabled(struct pci_dev *pdev)
2055 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2059 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2060 control |= PCI_PRI_CTRL_RESET;
2061 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2066 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2071 /* FIXME: Hardcode number of outstanding requests for now */
2073 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2075 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2077 /* Only allow access to user-accessible pages */
2078 ret = pci_enable_pasid(pdev, 0);
2082 /* First reset the PRI state of the device */
2083 ret = pci_reset_pri(pdev);
2088 ret = pci_enable_pri(pdev, reqs);
2093 ret = pri_reset_while_enabled(pdev);
2098 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2105 pci_disable_pri(pdev);
2106 pci_disable_pasid(pdev);
2111 /* FIXME: Move this to PCI code */
2112 #define PCI_PRI_TLP_OFF (1 << 15)
2114 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2119 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2123 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2125 return (status & PCI_PRI_TLP_OFF) ? true : false;
2129 * If a device is not yet associated with a domain, this function makes the
2130 * device visible in the domain
2132 static int attach_device(struct device *dev,
2133 struct protection_domain *domain)
2135 struct pci_dev *pdev;
2136 struct iommu_dev_data *dev_data;
2137 unsigned long flags;
2140 dev_data = get_dev_data(dev);
2142 if (!dev_is_pci(dev))
2143 goto skip_ats_check;
2145 pdev = to_pci_dev(dev);
2146 if (domain->flags & PD_IOMMUV2_MASK) {
2147 if (!dev_data->passthrough)
2150 if (dev_data->iommu_v2) {
2151 if (pdev_iommuv2_enable(pdev) != 0)
2154 dev_data->ats.enabled = true;
2155 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2156 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2158 } else if (amd_iommu_iotlb_sup &&
2159 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2160 dev_data->ats.enabled = true;
2161 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2165 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2166 ret = __attach_device(dev_data, domain);
2167 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2170 * We might boot into a crash-kernel here. The crashed kernel
2171 * left the caches in the IOMMU dirty. So we have to flush
2172 * here to evict all dirty stuff.
2174 domain_flush_tlb_pde(domain);
2180 * Removes a device from a protection domain (unlocked)
2182 static void __detach_device(struct iommu_dev_data *dev_data)
2184 struct protection_domain *domain;
2186 domain = dev_data->domain;
2188 spin_lock(&domain->lock);
2190 do_detach(dev_data);
2192 spin_unlock(&domain->lock);
2196 * Removes a device from a protection domain (with devtable_lock held)
2198 static void detach_device(struct device *dev)
2200 struct protection_domain *domain;
2201 struct iommu_dev_data *dev_data;
2202 unsigned long flags;
2204 dev_data = get_dev_data(dev);
2205 domain = dev_data->domain;
2208 * First check if the device is still attached. It might already
2209 * be detached from its domain because the generic
2210 * iommu_detach_group code detached it and we try again here in
2211 * our alias handling.
2213 if (WARN_ON(!dev_data->domain))
2216 /* lock device table */
2217 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2218 __detach_device(dev_data);
2219 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2221 if (!dev_is_pci(dev))
2224 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2225 pdev_iommuv2_disable(to_pci_dev(dev));
2226 else if (dev_data->ats.enabled)
2227 pci_disable_ats(to_pci_dev(dev));
2229 dev_data->ats.enabled = false;
2232 static int amd_iommu_add_device(struct device *dev)
2234 struct iommu_dev_data *dev_data;
2235 struct iommu_domain *domain;
2236 struct amd_iommu *iommu;
2239 if (!check_device(dev) || get_dev_data(dev))
2242 devid = get_device_id(dev);
2246 iommu = amd_iommu_rlookup_table[devid];
2248 ret = iommu_init_device(dev);
2250 if (ret != -ENOTSUPP)
2251 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2254 iommu_ignore_device(dev);
2255 dev->dma_ops = &dma_direct_ops;
2258 init_iommu_group(dev);
2260 dev_data = get_dev_data(dev);
2264 if (iommu_pass_through || dev_data->iommu_v2)
2265 iommu_request_dm_for_dev(dev);
2267 /* Domains are initialized for this device - have a look what we ended up with */
2268 domain = iommu_get_domain_for_dev(dev);
2269 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2270 dev_data->passthrough = true;
2272 dev->dma_ops = &amd_iommu_dma_ops;
2275 iommu_completion_wait(iommu);
2280 static void amd_iommu_remove_device(struct device *dev)
2282 struct amd_iommu *iommu;
2285 if (!check_device(dev))
2288 devid = get_device_id(dev);
2292 iommu = amd_iommu_rlookup_table[devid];
2294 iommu_uninit_device(dev);
2295 iommu_completion_wait(iommu);
2298 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2300 if (dev_is_pci(dev))
2301 return pci_device_group(dev);
2303 return acpihid_device_group(dev);
2306 /*****************************************************************************
2308 * The next functions belong to the dma_ops mapping/unmapping code.
2310 *****************************************************************************/
2313 * In the dma_ops path we only have the struct device. This function
2314 * finds the corresponding IOMMU, the protection domain and the
2315 * requestor id for a given device.
2316 * If the device is not yet associated with a domain this is also done
2319 static struct protection_domain *get_domain(struct device *dev)
2321 struct protection_domain *domain;
2322 struct iommu_domain *io_domain;
2324 if (!check_device(dev))
2325 return ERR_PTR(-EINVAL);
2327 domain = get_dev_data(dev)->domain;
2328 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2329 get_dev_data(dev)->defer_attach = false;
2330 io_domain = iommu_get_domain_for_dev(dev);
2331 domain = to_pdomain(io_domain);
2332 attach_device(dev, domain);
2335 return ERR_PTR(-EBUSY);
2337 if (!dma_ops_domain(domain))
2338 return ERR_PTR(-EBUSY);
2343 static void update_device_table(struct protection_domain *domain)
2345 struct iommu_dev_data *dev_data;
2347 list_for_each_entry(dev_data, &domain->dev_list, list) {
2348 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2349 dev_data->iommu_v2);
2351 if (dev_data->devid == dev_data->alias)
2354 /* There is an alias, update device table entry for it */
2355 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2356 dev_data->iommu_v2);
2360 static void update_domain(struct protection_domain *domain)
2362 if (!domain->updated)
2365 update_device_table(domain);
2367 domain_flush_devices(domain);
2368 domain_flush_tlb_pde(domain);
2370 domain->updated = false;
2373 static int dir2prot(enum dma_data_direction direction)
2375 if (direction == DMA_TO_DEVICE)
2376 return IOMMU_PROT_IR;
2377 else if (direction == DMA_FROM_DEVICE)
2378 return IOMMU_PROT_IW;
2379 else if (direction == DMA_BIDIRECTIONAL)
2380 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2386 * This function contains common code for mapping of a physically
2387 * contiguous memory region into DMA address space. It is used by all
2388 * mapping functions provided with this IOMMU driver.
2389 * Must be called with the domain lock held.
2391 static dma_addr_t __map_single(struct device *dev,
2392 struct dma_ops_domain *dma_dom,
2395 enum dma_data_direction direction,
2398 dma_addr_t offset = paddr & ~PAGE_MASK;
2399 dma_addr_t address, start, ret;
2404 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2407 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2408 if (address == AMD_IOMMU_MAPPING_ERROR)
2411 prot = dir2prot(direction);
2414 for (i = 0; i < pages; ++i) {
2415 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2416 PAGE_SIZE, prot, GFP_ATOMIC);
2425 if (unlikely(amd_iommu_np_cache)) {
2426 domain_flush_pages(&dma_dom->domain, address, size);
2427 domain_flush_complete(&dma_dom->domain);
2435 for (--i; i >= 0; --i) {
2437 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2440 domain_flush_tlb(&dma_dom->domain);
2441 domain_flush_complete(&dma_dom->domain);
2443 dma_ops_free_iova(dma_dom, address, pages);
2445 return AMD_IOMMU_MAPPING_ERROR;
2449 * Does the reverse of the __map_single function. Must be called with
2450 * the domain lock held too
2452 static void __unmap_single(struct dma_ops_domain *dma_dom,
2453 dma_addr_t dma_addr,
2457 dma_addr_t i, start;
2460 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2461 dma_addr &= PAGE_MASK;
2464 for (i = 0; i < pages; ++i) {
2465 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2469 if (amd_iommu_unmap_flush) {
2470 domain_flush_tlb(&dma_dom->domain);
2471 domain_flush_complete(&dma_dom->domain);
2472 dma_ops_free_iova(dma_dom, dma_addr, pages);
2474 pages = __roundup_pow_of_two(pages);
2475 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2480 * The exported map_single function for dma_ops.
2482 static dma_addr_t map_page(struct device *dev, struct page *page,
2483 unsigned long offset, size_t size,
2484 enum dma_data_direction dir,
2485 unsigned long attrs)
2487 phys_addr_t paddr = page_to_phys(page) + offset;
2488 struct protection_domain *domain;
2489 struct dma_ops_domain *dma_dom;
2492 domain = get_domain(dev);
2493 if (PTR_ERR(domain) == -EINVAL)
2494 return (dma_addr_t)paddr;
2495 else if (IS_ERR(domain))
2496 return AMD_IOMMU_MAPPING_ERROR;
2498 dma_mask = *dev->dma_mask;
2499 dma_dom = to_dma_ops_domain(domain);
2501 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2505 * The exported unmap_single function for dma_ops.
2507 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2508 enum dma_data_direction dir, unsigned long attrs)
2510 struct protection_domain *domain;
2511 struct dma_ops_domain *dma_dom;
2513 domain = get_domain(dev);
2517 dma_dom = to_dma_ops_domain(domain);
2519 __unmap_single(dma_dom, dma_addr, size, dir);
2522 static int sg_num_pages(struct device *dev,
2523 struct scatterlist *sglist,
2526 unsigned long mask, boundary_size;
2527 struct scatterlist *s;
2530 mask = dma_get_seg_boundary(dev);
2531 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2532 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2534 for_each_sg(sglist, s, nelems, i) {
2537 s->dma_address = npages << PAGE_SHIFT;
2538 p = npages % boundary_size;
2539 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2540 if (p + n > boundary_size)
2541 npages += boundary_size - p;
2549 * The exported map_sg function for dma_ops (handles scatter-gather
2552 static int map_sg(struct device *dev, struct scatterlist *sglist,
2553 int nelems, enum dma_data_direction direction,
2554 unsigned long attrs)
2556 int mapped_pages = 0, npages = 0, prot = 0, i;
2557 struct protection_domain *domain;
2558 struct dma_ops_domain *dma_dom;
2559 struct scatterlist *s;
2560 unsigned long address;
2563 domain = get_domain(dev);
2567 dma_dom = to_dma_ops_domain(domain);
2568 dma_mask = *dev->dma_mask;
2570 npages = sg_num_pages(dev, sglist, nelems);
2572 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2573 if (address == AMD_IOMMU_MAPPING_ERROR)
2576 prot = dir2prot(direction);
2578 /* Map all sg entries */
2579 for_each_sg(sglist, s, nelems, i) {
2580 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2582 for (j = 0; j < pages; ++j) {
2583 unsigned long bus_addr, phys_addr;
2586 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2587 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2588 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2596 /* Everything is mapped - write the right values into s->dma_address */
2597 for_each_sg(sglist, s, nelems, i) {
2598 s->dma_address += address + s->offset;
2599 s->dma_length = s->length;
2605 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2606 dev_name(dev), npages);
2608 for_each_sg(sglist, s, nelems, i) {
2609 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2611 for (j = 0; j < pages; ++j) {
2612 unsigned long bus_addr;
2614 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2615 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2623 free_iova_fast(&dma_dom->iovad, address, npages);
2630 * The exported map_sg function for dma_ops (handles scatter-gather
2633 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2634 int nelems, enum dma_data_direction dir,
2635 unsigned long attrs)
2637 struct protection_domain *domain;
2638 struct dma_ops_domain *dma_dom;
2639 unsigned long startaddr;
2642 domain = get_domain(dev);
2646 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2647 dma_dom = to_dma_ops_domain(domain);
2648 npages = sg_num_pages(dev, sglist, nelems);
2650 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2654 * The exported alloc_coherent function for dma_ops.
2656 static void *alloc_coherent(struct device *dev, size_t size,
2657 dma_addr_t *dma_addr, gfp_t flag,
2658 unsigned long attrs)
2660 u64 dma_mask = dev->coherent_dma_mask;
2661 struct protection_domain *domain;
2662 struct dma_ops_domain *dma_dom;
2665 domain = get_domain(dev);
2666 if (PTR_ERR(domain) == -EINVAL) {
2667 page = alloc_pages(flag, get_order(size));
2668 *dma_addr = page_to_phys(page);
2669 return page_address(page);
2670 } else if (IS_ERR(domain))
2673 dma_dom = to_dma_ops_domain(domain);
2674 size = PAGE_ALIGN(size);
2675 dma_mask = dev->coherent_dma_mask;
2676 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2679 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2681 if (!gfpflags_allow_blocking(flag))
2684 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2685 get_order(size), flag & __GFP_NOWARN);
2691 dma_mask = *dev->dma_mask;
2693 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2694 size, DMA_BIDIRECTIONAL, dma_mask);
2696 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2699 return page_address(page);
2703 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2704 __free_pages(page, get_order(size));
2710 * The exported free_coherent function for dma_ops.
2712 static void free_coherent(struct device *dev, size_t size,
2713 void *virt_addr, dma_addr_t dma_addr,
2714 unsigned long attrs)
2716 struct protection_domain *domain;
2717 struct dma_ops_domain *dma_dom;
2720 page = virt_to_page(virt_addr);
2721 size = PAGE_ALIGN(size);
2723 domain = get_domain(dev);
2727 dma_dom = to_dma_ops_domain(domain);
2729 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2732 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2733 __free_pages(page, get_order(size));
2737 * This function is called by the DMA layer to find out if we can handle a
2738 * particular device. It is part of the dma_ops.
2740 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2742 if (!dma_direct_supported(dev, mask))
2744 return check_device(dev);
2747 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2749 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2752 static const struct dma_map_ops amd_iommu_dma_ops = {
2753 .alloc = alloc_coherent,
2754 .free = free_coherent,
2755 .map_page = map_page,
2756 .unmap_page = unmap_page,
2758 .unmap_sg = unmap_sg,
2759 .dma_supported = amd_iommu_dma_supported,
2760 .mapping_error = amd_iommu_mapping_error,
2763 static int init_reserved_iova_ranges(void)
2765 struct pci_dev *pdev = NULL;
2768 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2770 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2771 &reserved_rbtree_key);
2773 /* MSI memory range */
2774 val = reserve_iova(&reserved_iova_ranges,
2775 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2777 pr_err("Reserving MSI range failed\n");
2781 /* HT memory range */
2782 val = reserve_iova(&reserved_iova_ranges,
2783 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2785 pr_err("Reserving HT range failed\n");
2790 * Memory used for PCI resources
2791 * FIXME: Check whether we can reserve the PCI-hole completly
2793 for_each_pci_dev(pdev) {
2796 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2797 struct resource *r = &pdev->resource[i];
2799 if (!(r->flags & IORESOURCE_MEM))
2802 val = reserve_iova(&reserved_iova_ranges,
2806 pr_err("Reserve pci-resource range failed\n");
2815 int __init amd_iommu_init_api(void)
2819 ret = iova_cache_get();
2823 ret = init_reserved_iova_ranges();
2827 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2830 #ifdef CONFIG_ARM_AMBA
2831 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2835 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2842 int __init amd_iommu_init_dma_ops(void)
2844 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2848 * In case we don't initialize SWIOTLB (actually the common case
2849 * when AMD IOMMU is enabled and SME is not active), make sure there
2850 * are global dma_ops set as a fall-back for devices not handled by
2851 * this driver (for example non-PCI devices). When SME is active,
2852 * make sure that swiotlb variable remains set so the global dma_ops
2853 * continue to be SWIOTLB.
2856 dma_ops = &dma_direct_ops;
2858 if (amd_iommu_unmap_flush)
2859 pr_info("IO/TLB flush on unmap enabled\n");
2861 pr_info("Lazy IO/TLB flushing enabled\n");
2867 /*****************************************************************************
2869 * The following functions belong to the exported interface of AMD IOMMU
2871 * This interface allows access to lower level functions of the IOMMU
2872 * like protection domain handling and assignement of devices to domains
2873 * which is not possible with the dma_ops interface.
2875 *****************************************************************************/
2877 static void cleanup_domain(struct protection_domain *domain)
2879 struct iommu_dev_data *entry;
2880 unsigned long flags;
2882 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2884 while (!list_empty(&domain->dev_list)) {
2885 entry = list_first_entry(&domain->dev_list,
2886 struct iommu_dev_data, list);
2887 BUG_ON(!entry->domain);
2888 __detach_device(entry);
2891 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2894 static void protection_domain_free(struct protection_domain *domain)
2899 del_domain_from_list(domain);
2902 domain_id_free(domain->id);
2907 static int protection_domain_init(struct protection_domain *domain)
2909 spin_lock_init(&domain->lock);
2910 mutex_init(&domain->api_lock);
2911 domain->id = domain_id_alloc();
2914 INIT_LIST_HEAD(&domain->dev_list);
2919 static struct protection_domain *protection_domain_alloc(void)
2921 struct protection_domain *domain;
2923 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2927 if (protection_domain_init(domain))
2930 add_domain_to_list(domain);
2940 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2942 struct protection_domain *pdomain;
2943 struct dma_ops_domain *dma_domain;
2946 case IOMMU_DOMAIN_UNMANAGED:
2947 pdomain = protection_domain_alloc();
2951 pdomain->mode = PAGE_MODE_3_LEVEL;
2952 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2953 if (!pdomain->pt_root) {
2954 protection_domain_free(pdomain);
2958 pdomain->domain.geometry.aperture_start = 0;
2959 pdomain->domain.geometry.aperture_end = ~0ULL;
2960 pdomain->domain.geometry.force_aperture = true;
2963 case IOMMU_DOMAIN_DMA:
2964 dma_domain = dma_ops_domain_alloc();
2966 pr_err("Failed to allocate\n");
2969 pdomain = &dma_domain->domain;
2971 case IOMMU_DOMAIN_IDENTITY:
2972 pdomain = protection_domain_alloc();
2976 pdomain->mode = PAGE_MODE_NONE;
2982 return &pdomain->domain;
2985 static void amd_iommu_domain_free(struct iommu_domain *dom)
2987 struct protection_domain *domain;
2988 struct dma_ops_domain *dma_dom;
2990 domain = to_pdomain(dom);
2992 if (domain->dev_cnt > 0)
2993 cleanup_domain(domain);
2995 BUG_ON(domain->dev_cnt != 0);
3000 switch (dom->type) {
3001 case IOMMU_DOMAIN_DMA:
3002 /* Now release the domain */
3003 dma_dom = to_dma_ops_domain(domain);
3004 dma_ops_domain_free(dma_dom);
3007 if (domain->mode != PAGE_MODE_NONE)
3008 free_pagetable(domain);
3010 if (domain->flags & PD_IOMMUV2_MASK)
3011 free_gcr3_table(domain);
3013 protection_domain_free(domain);
3018 static void amd_iommu_detach_device(struct iommu_domain *dom,
3021 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3022 struct amd_iommu *iommu;
3025 if (!check_device(dev))
3028 devid = get_device_id(dev);
3032 if (dev_data->domain != NULL)
3035 iommu = amd_iommu_rlookup_table[devid];
3039 #ifdef CONFIG_IRQ_REMAP
3040 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3041 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3042 dev_data->use_vapic = 0;
3045 iommu_completion_wait(iommu);
3048 static int amd_iommu_attach_device(struct iommu_domain *dom,
3051 struct protection_domain *domain = to_pdomain(dom);
3052 struct iommu_dev_data *dev_data;
3053 struct amd_iommu *iommu;
3056 if (!check_device(dev))
3059 dev_data = dev->archdata.iommu;
3061 iommu = amd_iommu_rlookup_table[dev_data->devid];
3065 if (dev_data->domain)
3068 ret = attach_device(dev, domain);
3070 #ifdef CONFIG_IRQ_REMAP
3071 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3072 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3073 dev_data->use_vapic = 1;
3075 dev_data->use_vapic = 0;
3079 iommu_completion_wait(iommu);
3084 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3085 phys_addr_t paddr, size_t page_size, int iommu_prot)
3087 struct protection_domain *domain = to_pdomain(dom);
3091 if (domain->mode == PAGE_MODE_NONE)
3094 if (iommu_prot & IOMMU_READ)
3095 prot |= IOMMU_PROT_IR;
3096 if (iommu_prot & IOMMU_WRITE)
3097 prot |= IOMMU_PROT_IW;
3099 mutex_lock(&domain->api_lock);
3100 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3101 mutex_unlock(&domain->api_lock);
3106 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3109 struct protection_domain *domain = to_pdomain(dom);
3112 if (domain->mode == PAGE_MODE_NONE)
3115 mutex_lock(&domain->api_lock);
3116 unmap_size = iommu_unmap_page(domain, iova, page_size);
3117 mutex_unlock(&domain->api_lock);
3122 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3125 struct protection_domain *domain = to_pdomain(dom);
3126 unsigned long offset_mask, pte_pgsize;
3129 if (domain->mode == PAGE_MODE_NONE)
3132 pte = fetch_pte(domain, iova, &pte_pgsize);
3134 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3137 offset_mask = pte_pgsize - 1;
3138 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3140 return (__pte & ~offset_mask) | (iova & offset_mask);
3143 static bool amd_iommu_capable(enum iommu_cap cap)
3146 case IOMMU_CAP_CACHE_COHERENCY:
3148 case IOMMU_CAP_INTR_REMAP:
3149 return (irq_remapping_enabled == 1);
3150 case IOMMU_CAP_NOEXEC:
3159 static void amd_iommu_get_resv_regions(struct device *dev,
3160 struct list_head *head)
3162 struct iommu_resv_region *region;
3163 struct unity_map_entry *entry;
3166 devid = get_device_id(dev);
3170 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3174 if (devid < entry->devid_start || devid > entry->devid_end)
3177 length = entry->address_end - entry->address_start;
3178 if (entry->prot & IOMMU_PROT_IR)
3180 if (entry->prot & IOMMU_PROT_IW)
3181 prot |= IOMMU_WRITE;
3183 region = iommu_alloc_resv_region(entry->address_start,
3187 pr_err("Out of memory allocating dm-regions for %s\n",
3191 list_add_tail(®ion->list, head);
3194 region = iommu_alloc_resv_region(MSI_RANGE_START,
3195 MSI_RANGE_END - MSI_RANGE_START + 1,
3199 list_add_tail(®ion->list, head);
3201 region = iommu_alloc_resv_region(HT_RANGE_START,
3202 HT_RANGE_END - HT_RANGE_START + 1,
3203 0, IOMMU_RESV_RESERVED);
3206 list_add_tail(®ion->list, head);
3209 static void amd_iommu_put_resv_regions(struct device *dev,
3210 struct list_head *head)
3212 struct iommu_resv_region *entry, *next;
3214 list_for_each_entry_safe(entry, next, head, list)
3218 static void amd_iommu_apply_resv_region(struct device *dev,
3219 struct iommu_domain *domain,
3220 struct iommu_resv_region *region)
3222 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3223 unsigned long start, end;
3225 start = IOVA_PFN(region->start);
3226 end = IOVA_PFN(region->start + region->length - 1);
3228 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3231 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3234 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3235 return dev_data->defer_attach;
3238 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3240 struct protection_domain *dom = to_pdomain(domain);
3242 domain_flush_tlb_pde(dom);
3243 domain_flush_complete(dom);
3246 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3247 unsigned long iova, size_t size)
3251 const struct iommu_ops amd_iommu_ops = {
3252 .capable = amd_iommu_capable,
3253 .domain_alloc = amd_iommu_domain_alloc,
3254 .domain_free = amd_iommu_domain_free,
3255 .attach_dev = amd_iommu_attach_device,
3256 .detach_dev = amd_iommu_detach_device,
3257 .map = amd_iommu_map,
3258 .unmap = amd_iommu_unmap,
3259 .iova_to_phys = amd_iommu_iova_to_phys,
3260 .add_device = amd_iommu_add_device,
3261 .remove_device = amd_iommu_remove_device,
3262 .device_group = amd_iommu_device_group,
3263 .get_resv_regions = amd_iommu_get_resv_regions,
3264 .put_resv_regions = amd_iommu_put_resv_regions,
3265 .apply_resv_region = amd_iommu_apply_resv_region,
3266 .is_attach_deferred = amd_iommu_is_attach_deferred,
3267 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3268 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3269 .iotlb_range_add = amd_iommu_iotlb_range_add,
3270 .iotlb_sync = amd_iommu_flush_iotlb_all,
3273 /*****************************************************************************
3275 * The next functions do a basic initialization of IOMMU for pass through
3278 * In passthrough mode the IOMMU is initialized and enabled but not used for
3279 * DMA-API translation.
3281 *****************************************************************************/
3283 /* IOMMUv2 specific functions */
3284 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3286 return atomic_notifier_chain_register(&ppr_notifier, nb);
3288 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3290 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3292 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3294 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3296 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3298 struct protection_domain *domain = to_pdomain(dom);
3299 unsigned long flags;
3301 spin_lock_irqsave(&domain->lock, flags);
3303 /* Update data structure */
3304 domain->mode = PAGE_MODE_NONE;
3305 domain->updated = true;
3307 /* Make changes visible to IOMMUs */
3308 update_domain(domain);
3310 /* Page-table is not visible to IOMMU anymore, so free it */
3311 free_pagetable(domain);
3313 spin_unlock_irqrestore(&domain->lock, flags);
3315 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3317 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3319 struct protection_domain *domain = to_pdomain(dom);
3320 unsigned long flags;
3323 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3326 /* Number of GCR3 table levels required */
3327 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3330 if (levels > amd_iommu_max_glx_val)
3333 spin_lock_irqsave(&domain->lock, flags);
3336 * Save us all sanity checks whether devices already in the
3337 * domain support IOMMUv2. Just force that the domain has no
3338 * devices attached when it is switched into IOMMUv2 mode.
3341 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3345 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3346 if (domain->gcr3_tbl == NULL)
3349 domain->glx = levels;
3350 domain->flags |= PD_IOMMUV2_MASK;
3351 domain->updated = true;
3353 update_domain(domain);
3358 spin_unlock_irqrestore(&domain->lock, flags);
3362 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3364 static int __flush_pasid(struct protection_domain *domain, int pasid,
3365 u64 address, bool size)
3367 struct iommu_dev_data *dev_data;
3368 struct iommu_cmd cmd;
3371 if (!(domain->flags & PD_IOMMUV2_MASK))
3374 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3377 * IOMMU TLB needs to be flushed before Device TLB to
3378 * prevent device TLB refill from IOMMU TLB
3380 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3381 if (domain->dev_iommu[i] == 0)
3384 ret = iommu_queue_command(amd_iommus[i], &cmd);
3389 /* Wait until IOMMU TLB flushes are complete */
3390 domain_flush_complete(domain);
3392 /* Now flush device TLBs */
3393 list_for_each_entry(dev_data, &domain->dev_list, list) {
3394 struct amd_iommu *iommu;
3398 There might be non-IOMMUv2 capable devices in an IOMMUv2
3401 if (!dev_data->ats.enabled)
3404 qdep = dev_data->ats.qdep;
3405 iommu = amd_iommu_rlookup_table[dev_data->devid];
3407 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3408 qdep, address, size);
3410 ret = iommu_queue_command(iommu, &cmd);
3415 /* Wait until all device TLBs are flushed */
3416 domain_flush_complete(domain);
3425 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3428 return __flush_pasid(domain, pasid, address, false);
3431 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3434 struct protection_domain *domain = to_pdomain(dom);
3435 unsigned long flags;
3438 spin_lock_irqsave(&domain->lock, flags);
3439 ret = __amd_iommu_flush_page(domain, pasid, address);
3440 spin_unlock_irqrestore(&domain->lock, flags);
3444 EXPORT_SYMBOL(amd_iommu_flush_page);
3446 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3448 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3452 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3454 struct protection_domain *domain = to_pdomain(dom);
3455 unsigned long flags;
3458 spin_lock_irqsave(&domain->lock, flags);
3459 ret = __amd_iommu_flush_tlb(domain, pasid);
3460 spin_unlock_irqrestore(&domain->lock, flags);
3464 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3466 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3473 index = (pasid >> (9 * level)) & 0x1ff;
3479 if (!(*pte & GCR3_VALID)) {
3483 root = (void *)get_zeroed_page(GFP_ATOMIC);
3487 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3490 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3498 static int __set_gcr3(struct protection_domain *domain, int pasid,
3503 if (domain->mode != PAGE_MODE_NONE)
3506 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3510 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3512 return __amd_iommu_flush_tlb(domain, pasid);
3515 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3519 if (domain->mode != PAGE_MODE_NONE)
3522 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3528 return __amd_iommu_flush_tlb(domain, pasid);
3531 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3534 struct protection_domain *domain = to_pdomain(dom);
3535 unsigned long flags;
3538 spin_lock_irqsave(&domain->lock, flags);
3539 ret = __set_gcr3(domain, pasid, cr3);
3540 spin_unlock_irqrestore(&domain->lock, flags);
3544 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3546 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3548 struct protection_domain *domain = to_pdomain(dom);
3549 unsigned long flags;
3552 spin_lock_irqsave(&domain->lock, flags);
3553 ret = __clear_gcr3(domain, pasid);
3554 spin_unlock_irqrestore(&domain->lock, flags);
3558 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3560 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3561 int status, int tag)
3563 struct iommu_dev_data *dev_data;
3564 struct amd_iommu *iommu;
3565 struct iommu_cmd cmd;
3567 dev_data = get_dev_data(&pdev->dev);
3568 iommu = amd_iommu_rlookup_table[dev_data->devid];
3570 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3571 tag, dev_data->pri_tlp);
3573 return iommu_queue_command(iommu, &cmd);
3575 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3577 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3579 struct protection_domain *pdomain;
3581 pdomain = get_domain(&pdev->dev);
3582 if (IS_ERR(pdomain))
3585 /* Only return IOMMUv2 domains */
3586 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3589 return &pdomain->domain;
3591 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3593 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3595 struct iommu_dev_data *dev_data;
3597 if (!amd_iommu_v2_supported())
3600 dev_data = get_dev_data(&pdev->dev);
3601 dev_data->errata |= (1 << erratum);
3603 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3605 int amd_iommu_device_info(struct pci_dev *pdev,
3606 struct amd_iommu_device_info *info)
3611 if (pdev == NULL || info == NULL)
3614 if (!amd_iommu_v2_supported())
3617 memset(info, 0, sizeof(*info));
3619 if (!pci_ats_disabled()) {
3620 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3622 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3625 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3627 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3629 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3633 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3634 max_pasids = min(max_pasids, (1 << 20));
3636 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3637 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3639 features = pci_pasid_features(pdev);
3640 if (features & PCI_PASID_CAP_EXEC)
3641 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3642 if (features & PCI_PASID_CAP_PRIV)
3643 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3648 EXPORT_SYMBOL(amd_iommu_device_info);
3650 #ifdef CONFIG_IRQ_REMAP
3652 /*****************************************************************************
3654 * Interrupt Remapping Implementation
3656 *****************************************************************************/
3658 static struct irq_chip amd_ir_chip;
3659 static DEFINE_SPINLOCK(iommu_table_lock);
3661 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3665 dte = amd_iommu_dev_table[devid].data[2];
3666 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3667 dte |= iommu_virt_to_phys(table->table);
3668 dte |= DTE_IRQ_REMAP_INTCTL;
3669 dte |= DTE_IRQ_TABLE_LEN;
3670 dte |= DTE_IRQ_REMAP_ENABLE;
3672 amd_iommu_dev_table[devid].data[2] = dte;
3675 static struct irq_remap_table *get_irq_table(u16 devid)
3677 struct irq_remap_table *table;
3679 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3680 "%s: no iommu for devid %x\n", __func__, devid))
3683 table = irq_lookup_table[devid];
3684 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3690 static struct irq_remap_table *__alloc_irq_table(void)
3692 struct irq_remap_table *table;
3694 table = kzalloc(sizeof(*table), GFP_KERNEL);
3698 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3699 if (!table->table) {
3703 raw_spin_lock_init(&table->lock);
3705 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3706 memset(table->table, 0,
3707 MAX_IRQS_PER_TABLE * sizeof(u32));
3709 memset(table->table, 0,
3710 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3714 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3715 struct irq_remap_table *table)
3717 irq_lookup_table[devid] = table;
3718 set_dte_irq_entry(devid, table);
3719 iommu_flush_dte(iommu, devid);
3722 static struct irq_remap_table *alloc_irq_table(u16 devid)
3724 struct irq_remap_table *table = NULL;
3725 struct irq_remap_table *new_table = NULL;
3726 struct amd_iommu *iommu;
3727 unsigned long flags;
3730 spin_lock_irqsave(&iommu_table_lock, flags);
3732 iommu = amd_iommu_rlookup_table[devid];
3736 table = irq_lookup_table[devid];
3740 alias = amd_iommu_alias_table[devid];
3741 table = irq_lookup_table[alias];
3743 set_remap_table_entry(iommu, devid, table);
3746 spin_unlock_irqrestore(&iommu_table_lock, flags);
3748 /* Nothing there yet, allocate new irq remapping table */
3749 new_table = __alloc_irq_table();
3753 spin_lock_irqsave(&iommu_table_lock, flags);
3755 table = irq_lookup_table[devid];
3759 table = irq_lookup_table[alias];
3761 set_remap_table_entry(iommu, devid, table);
3768 set_remap_table_entry(iommu, devid, table);
3770 set_remap_table_entry(iommu, alias, table);
3773 iommu_completion_wait(iommu);
3776 spin_unlock_irqrestore(&iommu_table_lock, flags);
3779 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3785 static int alloc_irq_index(u16 devid, int count, bool align)
3787 struct irq_remap_table *table;
3788 int index, c, alignment = 1;
3789 unsigned long flags;
3790 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3795 table = alloc_irq_table(devid);
3800 alignment = roundup_pow_of_two(count);
3802 raw_spin_lock_irqsave(&table->lock, flags);
3804 /* Scan table for free entries */
3805 for (index = ALIGN(table->min_index, alignment), c = 0;
3806 index < MAX_IRQS_PER_TABLE;) {
3807 if (!iommu->irte_ops->is_allocated(table, index)) {
3811 index = ALIGN(index + 1, alignment);
3817 iommu->irte_ops->set_allocated(table, index - c + 1);
3829 raw_spin_unlock_irqrestore(&table->lock, flags);
3834 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3835 struct amd_ir_data *data)
3837 struct irq_remap_table *table;
3838 struct amd_iommu *iommu;
3839 unsigned long flags;
3840 struct irte_ga *entry;
3842 iommu = amd_iommu_rlookup_table[devid];
3846 table = get_irq_table(devid);
3850 raw_spin_lock_irqsave(&table->lock, flags);
3852 entry = (struct irte_ga *)table->table;
3853 entry = &entry[index];
3854 entry->lo.fields_remap.valid = 0;
3855 entry->hi.val = irte->hi.val;
3856 entry->lo.val = irte->lo.val;
3857 entry->lo.fields_remap.valid = 1;
3861 raw_spin_unlock_irqrestore(&table->lock, flags);
3863 iommu_flush_irt(iommu, devid);
3864 iommu_completion_wait(iommu);
3869 static int modify_irte(u16 devid, int index, union irte *irte)
3871 struct irq_remap_table *table;
3872 struct amd_iommu *iommu;
3873 unsigned long flags;
3875 iommu = amd_iommu_rlookup_table[devid];
3879 table = get_irq_table(devid);
3883 raw_spin_lock_irqsave(&table->lock, flags);
3884 table->table[index] = irte->val;
3885 raw_spin_unlock_irqrestore(&table->lock, flags);
3887 iommu_flush_irt(iommu, devid);
3888 iommu_completion_wait(iommu);
3893 static void free_irte(u16 devid, int index)
3895 struct irq_remap_table *table;
3896 struct amd_iommu *iommu;
3897 unsigned long flags;
3899 iommu = amd_iommu_rlookup_table[devid];
3903 table = get_irq_table(devid);
3907 raw_spin_lock_irqsave(&table->lock, flags);
3908 iommu->irte_ops->clear_allocated(table, index);
3909 raw_spin_unlock_irqrestore(&table->lock, flags);
3911 iommu_flush_irt(iommu, devid);
3912 iommu_completion_wait(iommu);
3915 static void irte_prepare(void *entry,
3916 u32 delivery_mode, u32 dest_mode,
3917 u8 vector, u32 dest_apicid, int devid)
3919 union irte *irte = (union irte *) entry;
3922 irte->fields.vector = vector;
3923 irte->fields.int_type = delivery_mode;
3924 irte->fields.destination = dest_apicid;
3925 irte->fields.dm = dest_mode;
3926 irte->fields.valid = 1;
3929 static void irte_ga_prepare(void *entry,
3930 u32 delivery_mode, u32 dest_mode,
3931 u8 vector, u32 dest_apicid, int devid)
3933 struct irte_ga *irte = (struct irte_ga *) entry;
3937 irte->lo.fields_remap.int_type = delivery_mode;
3938 irte->lo.fields_remap.dm = dest_mode;
3939 irte->hi.fields.vector = vector;
3940 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3941 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3942 irte->lo.fields_remap.valid = 1;
3945 static void irte_activate(void *entry, u16 devid, u16 index)
3947 union irte *irte = (union irte *) entry;
3949 irte->fields.valid = 1;
3950 modify_irte(devid, index, irte);
3953 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3955 struct irte_ga *irte = (struct irte_ga *) entry;
3957 irte->lo.fields_remap.valid = 1;
3958 modify_irte_ga(devid, index, irte, NULL);
3961 static void irte_deactivate(void *entry, u16 devid, u16 index)
3963 union irte *irte = (union irte *) entry;
3965 irte->fields.valid = 0;
3966 modify_irte(devid, index, irte);
3969 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3971 struct irte_ga *irte = (struct irte_ga *) entry;
3973 irte->lo.fields_remap.valid = 0;
3974 modify_irte_ga(devid, index, irte, NULL);
3977 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3978 u8 vector, u32 dest_apicid)
3980 union irte *irte = (union irte *) entry;
3982 irte->fields.vector = vector;
3983 irte->fields.destination = dest_apicid;
3984 modify_irte(devid, index, irte);
3987 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3988 u8 vector, u32 dest_apicid)
3990 struct irte_ga *irte = (struct irte_ga *) entry;
3992 if (!irte->lo.fields_remap.guest_mode) {
3993 irte->hi.fields.vector = vector;
3994 irte->lo.fields_remap.destination =
3995 APICID_TO_IRTE_DEST_LO(dest_apicid);
3996 irte->hi.fields.destination =
3997 APICID_TO_IRTE_DEST_HI(dest_apicid);
3998 modify_irte_ga(devid, index, irte, NULL);
4002 #define IRTE_ALLOCATED (~1U)
4003 static void irte_set_allocated(struct irq_remap_table *table, int index)
4005 table->table[index] = IRTE_ALLOCATED;
4008 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4010 struct irte_ga *ptr = (struct irte_ga *)table->table;
4011 struct irte_ga *irte = &ptr[index];
4013 memset(&irte->lo.val, 0, sizeof(u64));
4014 memset(&irte->hi.val, 0, sizeof(u64));
4015 irte->hi.fields.vector = 0xff;
4018 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4020 union irte *ptr = (union irte *)table->table;
4021 union irte *irte = &ptr[index];
4023 return irte->val != 0;
4026 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4028 struct irte_ga *ptr = (struct irte_ga *)table->table;
4029 struct irte_ga *irte = &ptr[index];
4031 return irte->hi.fields.vector != 0;
4034 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4036 table->table[index] = 0;
4039 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4041 struct irte_ga *ptr = (struct irte_ga *)table->table;
4042 struct irte_ga *irte = &ptr[index];
4044 memset(&irte->lo.val, 0, sizeof(u64));
4045 memset(&irte->hi.val, 0, sizeof(u64));
4048 static int get_devid(struct irq_alloc_info *info)
4052 switch (info->type) {
4053 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4054 devid = get_ioapic_devid(info->ioapic_id);
4056 case X86_IRQ_ALLOC_TYPE_HPET:
4057 devid = get_hpet_devid(info->hpet_id);
4059 case X86_IRQ_ALLOC_TYPE_MSI:
4060 case X86_IRQ_ALLOC_TYPE_MSIX:
4061 devid = get_device_id(&info->msi_dev->dev);
4071 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4073 struct amd_iommu *iommu;
4079 devid = get_devid(info);
4081 iommu = amd_iommu_rlookup_table[devid];
4083 return iommu->ir_domain;
4089 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4091 struct amd_iommu *iommu;
4097 switch (info->type) {
4098 case X86_IRQ_ALLOC_TYPE_MSI:
4099 case X86_IRQ_ALLOC_TYPE_MSIX:
4100 devid = get_device_id(&info->msi_dev->dev);
4104 iommu = amd_iommu_rlookup_table[devid];
4106 return iommu->msi_domain;
4115 struct irq_remap_ops amd_iommu_irq_ops = {
4116 .prepare = amd_iommu_prepare,
4117 .enable = amd_iommu_enable,
4118 .disable = amd_iommu_disable,
4119 .reenable = amd_iommu_reenable,
4120 .enable_faulting = amd_iommu_enable_faulting,
4121 .get_ir_irq_domain = get_ir_irq_domain,
4122 .get_irq_domain = get_irq_domain,
4125 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4126 struct irq_cfg *irq_cfg,
4127 struct irq_alloc_info *info,
4128 int devid, int index, int sub_handle)
4130 struct irq_2_irte *irte_info = &data->irq_2_irte;
4131 struct msi_msg *msg = &data->msi_entry;
4132 struct IO_APIC_route_entry *entry;
4133 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4138 data->irq_2_irte.devid = devid;
4139 data->irq_2_irte.index = index + sub_handle;
4140 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4141 apic->irq_dest_mode, irq_cfg->vector,
4142 irq_cfg->dest_apicid, devid);
4144 switch (info->type) {
4145 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4146 /* Setup IOAPIC entry */
4147 entry = info->ioapic_entry;
4148 info->ioapic_entry = NULL;
4149 memset(entry, 0, sizeof(*entry));
4150 entry->vector = index;
4152 entry->trigger = info->ioapic_trigger;
4153 entry->polarity = info->ioapic_polarity;
4154 /* Mask level triggered irqs. */
4155 if (info->ioapic_trigger)
4159 case X86_IRQ_ALLOC_TYPE_HPET:
4160 case X86_IRQ_ALLOC_TYPE_MSI:
4161 case X86_IRQ_ALLOC_TYPE_MSIX:
4162 msg->address_hi = MSI_ADDR_BASE_HI;
4163 msg->address_lo = MSI_ADDR_BASE_LO;
4164 msg->data = irte_info->index;
4173 struct amd_irte_ops irte_32_ops = {
4174 .prepare = irte_prepare,
4175 .activate = irte_activate,
4176 .deactivate = irte_deactivate,
4177 .set_affinity = irte_set_affinity,
4178 .set_allocated = irte_set_allocated,
4179 .is_allocated = irte_is_allocated,
4180 .clear_allocated = irte_clear_allocated,
4183 struct amd_irte_ops irte_128_ops = {
4184 .prepare = irte_ga_prepare,
4185 .activate = irte_ga_activate,
4186 .deactivate = irte_ga_deactivate,
4187 .set_affinity = irte_ga_set_affinity,
4188 .set_allocated = irte_ga_set_allocated,
4189 .is_allocated = irte_ga_is_allocated,
4190 .clear_allocated = irte_ga_clear_allocated,
4193 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4194 unsigned int nr_irqs, void *arg)
4196 struct irq_alloc_info *info = arg;
4197 struct irq_data *irq_data;
4198 struct amd_ir_data *data = NULL;
4199 struct irq_cfg *cfg;
4205 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4206 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4210 * With IRQ remapping enabled, don't need contiguous CPU vectors
4211 * to support multiple MSI interrupts.
4213 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4214 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4216 devid = get_devid(info);
4220 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4224 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4225 struct irq_remap_table *table;
4226 struct amd_iommu *iommu;
4228 table = alloc_irq_table(devid);
4230 if (!table->min_index) {
4232 * Keep the first 32 indexes free for IOAPIC
4235 table->min_index = 32;
4236 iommu = amd_iommu_rlookup_table[devid];
4237 for (i = 0; i < 32; ++i)
4238 iommu->irte_ops->set_allocated(table, i);
4240 WARN_ON(table->min_index != 32);
4241 index = info->ioapic_pin;
4246 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4248 index = alloc_irq_index(devid, nr_irqs, align);
4251 pr_warn("Failed to allocate IRTE\n");
4253 goto out_free_parent;
4256 for (i = 0; i < nr_irqs; i++) {
4257 irq_data = irq_domain_get_irq_data(domain, virq + i);
4258 cfg = irqd_cfg(irq_data);
4259 if (!irq_data || !cfg) {
4265 data = kzalloc(sizeof(*data), GFP_KERNEL);
4269 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4270 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4272 data->entry = kzalloc(sizeof(struct irte_ga),
4279 irq_data->hwirq = (devid << 16) + i;
4280 irq_data->chip_data = data;
4281 irq_data->chip = &amd_ir_chip;
4282 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4283 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4289 for (i--; i >= 0; i--) {
4290 irq_data = irq_domain_get_irq_data(domain, virq + i);
4292 kfree(irq_data->chip_data);
4294 for (i = 0; i < nr_irqs; i++)
4295 free_irte(devid, index + i);
4297 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4301 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4302 unsigned int nr_irqs)
4304 struct irq_2_irte *irte_info;
4305 struct irq_data *irq_data;
4306 struct amd_ir_data *data;
4309 for (i = 0; i < nr_irqs; i++) {
4310 irq_data = irq_domain_get_irq_data(domain, virq + i);
4311 if (irq_data && irq_data->chip_data) {
4312 data = irq_data->chip_data;
4313 irte_info = &data->irq_2_irte;
4314 free_irte(irte_info->devid, irte_info->index);
4319 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4322 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4323 struct amd_ir_data *ir_data,
4324 struct irq_2_irte *irte_info,
4325 struct irq_cfg *cfg);
4327 static int irq_remapping_activate(struct irq_domain *domain,
4328 struct irq_data *irq_data, bool reserve)
4330 struct amd_ir_data *data = irq_data->chip_data;
4331 struct irq_2_irte *irte_info = &data->irq_2_irte;
4332 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4333 struct irq_cfg *cfg = irqd_cfg(irq_data);
4338 iommu->irte_ops->activate(data->entry, irte_info->devid,
4340 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4344 static void irq_remapping_deactivate(struct irq_domain *domain,
4345 struct irq_data *irq_data)
4347 struct amd_ir_data *data = irq_data->chip_data;
4348 struct irq_2_irte *irte_info = &data->irq_2_irte;
4349 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4352 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4356 static const struct irq_domain_ops amd_ir_domain_ops = {
4357 .alloc = irq_remapping_alloc,
4358 .free = irq_remapping_free,
4359 .activate = irq_remapping_activate,
4360 .deactivate = irq_remapping_deactivate,
4363 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4365 struct amd_iommu *iommu;
4366 struct amd_iommu_pi_data *pi_data = vcpu_info;
4367 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4368 struct amd_ir_data *ir_data = data->chip_data;
4369 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4370 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4371 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4374 * This device has never been set up for guest mode.
4375 * we should not modify the IRTE
4377 if (!dev_data || !dev_data->use_vapic)
4380 pi_data->ir_data = ir_data;
4383 * SVM tries to set up for VAPIC mode, but we are in
4384 * legacy mode. So, we force legacy mode instead.
4386 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4387 pr_debug("%s: Fall back to using intr legacy remap\n",
4389 pi_data->is_guest_mode = false;
4392 iommu = amd_iommu_rlookup_table[irte_info->devid];
4396 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4397 if (pi_data->is_guest_mode) {
4399 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4400 irte->hi.fields.vector = vcpu_pi_info->vector;
4401 irte->lo.fields_vapic.ga_log_intr = 1;
4402 irte->lo.fields_vapic.guest_mode = 1;
4403 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4405 ir_data->cached_ga_tag = pi_data->ga_tag;
4408 struct irq_cfg *cfg = irqd_cfg(data);
4412 irte->hi.fields.vector = cfg->vector;
4413 irte->lo.fields_remap.guest_mode = 0;
4414 irte->lo.fields_remap.destination =
4415 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4416 irte->hi.fields.destination =
4417 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4418 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4419 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4422 * This communicates the ga_tag back to the caller
4423 * so that it can do all the necessary clean up.
4425 ir_data->cached_ga_tag = 0;
4428 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4432 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4433 struct amd_ir_data *ir_data,
4434 struct irq_2_irte *irte_info,
4435 struct irq_cfg *cfg)
4439 * Atomically updates the IRTE with the new destination, vector
4440 * and flushes the interrupt entry cache.
4442 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4443 irte_info->index, cfg->vector,
4447 static int amd_ir_set_affinity(struct irq_data *data,
4448 const struct cpumask *mask, bool force)
4450 struct amd_ir_data *ir_data = data->chip_data;
4451 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4452 struct irq_cfg *cfg = irqd_cfg(data);
4453 struct irq_data *parent = data->parent_data;
4454 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4460 ret = parent->chip->irq_set_affinity(parent, mask, force);
4461 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4464 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4466 * After this point, all the interrupts will start arriving
4467 * at the new destination. So, time to cleanup the previous
4468 * vector allocation.
4470 send_cleanup_vector(cfg);
4472 return IRQ_SET_MASK_OK_DONE;
4475 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4477 struct amd_ir_data *ir_data = irq_data->chip_data;
4479 *msg = ir_data->msi_entry;
4482 static struct irq_chip amd_ir_chip = {
4484 .irq_ack = apic_ack_irq,
4485 .irq_set_affinity = amd_ir_set_affinity,
4486 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4487 .irq_compose_msi_msg = ir_compose_msi_msg,
4490 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4492 struct fwnode_handle *fn;
4494 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4497 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4498 irq_domain_free_fwnode(fn);
4499 if (!iommu->ir_domain)
4502 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4503 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4509 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4511 unsigned long flags;
4512 struct amd_iommu *iommu;
4513 struct irq_remap_table *table;
4514 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4515 int devid = ir_data->irq_2_irte.devid;
4516 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4517 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4519 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4520 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4523 iommu = amd_iommu_rlookup_table[devid];
4527 table = get_irq_table(devid);
4531 raw_spin_lock_irqsave(&table->lock, flags);
4533 if (ref->lo.fields_vapic.guest_mode) {
4535 ref->lo.fields_vapic.destination =
4536 APICID_TO_IRTE_DEST_LO(cpu);
4537 ref->hi.fields.destination =
4538 APICID_TO_IRTE_DEST_HI(cpu);
4540 ref->lo.fields_vapic.is_run = is_run;
4544 raw_spin_unlock_irqrestore(&table->lock, flags);
4546 iommu_flush_irt(iommu, devid);
4547 iommu_completion_wait(iommu);
4550 EXPORT_SYMBOL(amd_iommu_update_ga);