1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/iommu-helper.h>
24 #include <linux/iommu.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/dma-contiguous.h>
32 #include <linux/irqdomain.h>
33 #include <linux/percpu.h>
34 #include <linux/iova.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/msidef.h>
40 #include <asm/proto.h>
41 #include <asm/iommu.h>
45 #include "amd_iommu_proto.h"
46 #include "amd_iommu_types.h"
47 #include "irq_remapping.h"
49 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51 #define LOOP_TIMEOUT 100000
53 /* IO virtual address start page frame number */
54 #define IOVA_START_PFN (1)
55 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
57 /* Reserved IOVA ranges */
58 #define MSI_RANGE_START (0xfee00000)
59 #define MSI_RANGE_END (0xfeefffff)
60 #define HT_RANGE_START (0xfd00000000ULL)
61 #define HT_RANGE_END (0xffffffffffULL)
64 * This bitmap is used to advertise the page sizes our hardware support
65 * to the IOMMU core, which will then use this information to split
66 * physically contiguous memory regions it is mapping into page sizes
69 * 512GB Pages are not supported due to a hardware bug
71 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
73 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
74 static DEFINE_SPINLOCK(pd_bitmap_lock);
76 /* List of all available dev_data structures */
77 static LLIST_HEAD(dev_data_list);
79 LIST_HEAD(ioapic_map);
81 LIST_HEAD(acpihid_map);
84 * Domain for untranslated devices - only allocated
85 * if iommu=pt passed on kernel cmd line.
87 const struct iommu_ops amd_iommu_ops;
89 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
90 int amd_iommu_max_glx_val = -1;
92 static const struct dma_map_ops amd_iommu_dma_ops;
95 * general struct to manage commands send to an IOMMU
101 struct kmem_cache *amd_iommu_irq_cache;
103 static void update_domain(struct protection_domain *domain);
104 static int protection_domain_init(struct protection_domain *domain);
105 static void detach_device(struct device *dev);
106 static void iova_domain_flush_tlb(struct iova_domain *iovad);
109 * Data container for a dma_ops specific protection domain
111 struct dma_ops_domain {
112 /* generic protection domain information */
113 struct protection_domain domain;
116 struct iova_domain iovad;
119 static struct iova_domain reserved_iova_ranges;
120 static struct lock_class_key reserved_rbtree_key;
122 /****************************************************************************
126 ****************************************************************************/
128 static inline int match_hid_uid(struct device *dev,
129 struct acpihid_map_entry *entry)
131 struct acpi_device *adev = ACPI_COMPANION(dev);
132 const char *hid, *uid;
137 hid = acpi_device_hid(adev);
138 uid = acpi_device_uid(adev);
144 return strcmp(hid, entry->hid);
147 return strcmp(hid, entry->hid);
149 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
152 static inline u16 get_pci_device_id(struct device *dev)
154 struct pci_dev *pdev = to_pci_dev(dev);
156 return pci_dev_id(pdev);
159 static inline int get_acpihid_device_id(struct device *dev,
160 struct acpihid_map_entry **entry)
162 struct acpihid_map_entry *p;
164 list_for_each_entry(p, &acpihid_map, list) {
165 if (!match_hid_uid(dev, p)) {
174 static inline int get_device_id(struct device *dev)
179 devid = get_pci_device_id(dev);
181 devid = get_acpihid_device_id(dev, NULL);
186 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
188 return container_of(dom, struct protection_domain, domain);
191 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
193 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
194 return container_of(domain, struct dma_ops_domain, domain);
197 static struct iommu_dev_data *alloc_dev_data(u16 devid)
199 struct iommu_dev_data *dev_data;
201 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
205 dev_data->devid = devid;
206 ratelimit_default_init(&dev_data->rs);
208 llist_add(&dev_data->dev_data_list, &dev_data_list);
212 static struct iommu_dev_data *search_dev_data(u16 devid)
214 struct iommu_dev_data *dev_data;
215 struct llist_node *node;
217 if (llist_empty(&dev_data_list))
220 node = dev_data_list.first;
221 llist_for_each_entry(dev_data, node, dev_data_list) {
222 if (dev_data->devid == devid)
229 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
231 *(u16 *)data = alias;
235 static u16 get_alias(struct device *dev)
237 struct pci_dev *pdev = to_pci_dev(dev);
238 u16 devid, ivrs_alias, pci_alias;
240 /* The callers make sure that get_device_id() does not fail here */
241 devid = get_device_id(dev);
243 /* For ACPI HID devices, we simply return the devid as such */
244 if (!dev_is_pci(dev))
247 ivrs_alias = amd_iommu_alias_table[devid];
249 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
251 if (ivrs_alias == pci_alias)
257 * The IVRS is fairly reliable in telling us about aliases, but it
258 * can't know about every screwy device. If we don't have an IVRS
259 * reported alias, use the PCI reported alias. In that case we may
260 * still need to initialize the rlookup and dev_table entries if the
261 * alias is to a non-existent device.
263 if (ivrs_alias == devid) {
264 if (!amd_iommu_rlookup_table[pci_alias]) {
265 amd_iommu_rlookup_table[pci_alias] =
266 amd_iommu_rlookup_table[devid];
267 memcpy(amd_iommu_dev_table[pci_alias].data,
268 amd_iommu_dev_table[devid].data,
269 sizeof(amd_iommu_dev_table[pci_alias].data));
275 pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d "
276 "for device [%04x:%04x], kernel reported alias "
277 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
278 PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device,
279 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
280 PCI_FUNC(pci_alias));
283 * If we don't have a PCI DMA alias and the IVRS alias is on the same
284 * bus, then the IVRS table may know about a quirk that we don't.
286 if (pci_alias == devid &&
287 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
288 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
289 pci_info(pdev, "Added PCI DMA alias %02x.%d\n",
290 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias));
296 static struct iommu_dev_data *find_dev_data(u16 devid)
298 struct iommu_dev_data *dev_data;
299 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
301 dev_data = search_dev_data(devid);
303 if (dev_data == NULL) {
304 dev_data = alloc_dev_data(devid);
308 if (translation_pre_enabled(iommu))
309 dev_data->defer_attach = true;
315 struct iommu_dev_data *get_dev_data(struct device *dev)
317 return dev->archdata.iommu;
319 EXPORT_SYMBOL(get_dev_data);
322 * Find or create an IOMMU group for a acpihid device.
324 static struct iommu_group *acpihid_device_group(struct device *dev)
326 struct acpihid_map_entry *p, *entry = NULL;
329 devid = get_acpihid_device_id(dev, &entry);
331 return ERR_PTR(devid);
333 list_for_each_entry(p, &acpihid_map, list) {
334 if ((devid == p->devid) && p->group)
335 entry->group = p->group;
339 entry->group = generic_device_group(dev);
341 iommu_group_ref_get(entry->group);
346 static bool pci_iommuv2_capable(struct pci_dev *pdev)
348 static const int caps[] = {
351 PCI_EXT_CAP_ID_PASID,
355 if (pci_ats_disabled())
358 for (i = 0; i < 3; ++i) {
359 pos = pci_find_ext_capability(pdev, caps[i]);
367 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
369 struct iommu_dev_data *dev_data;
371 dev_data = get_dev_data(&pdev->dev);
373 return dev_data->errata & (1 << erratum) ? true : false;
377 * This function checks if the driver got a valid device from the caller to
378 * avoid dereferencing invalid pointers.
380 static bool check_device(struct device *dev)
384 if (!dev || !dev->dma_mask)
387 devid = get_device_id(dev);
391 /* Out of our scope? */
392 if (devid > amd_iommu_last_bdf)
395 if (amd_iommu_rlookup_table[devid] == NULL)
401 static void init_iommu_group(struct device *dev)
403 struct iommu_group *group;
405 group = iommu_group_get_for_dev(dev);
409 iommu_group_put(group);
412 static int iommu_init_device(struct device *dev)
414 struct iommu_dev_data *dev_data;
415 struct amd_iommu *iommu;
418 if (dev->archdata.iommu)
421 devid = get_device_id(dev);
425 iommu = amd_iommu_rlookup_table[devid];
427 dev_data = find_dev_data(devid);
431 dev_data->alias = get_alias(dev);
434 * By default we use passthrough mode for IOMMUv2 capable device.
435 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
436 * invalid address), we ignore the capability for the device so
437 * it'll be forced to go into translation mode.
439 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
440 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
441 struct amd_iommu *iommu;
443 iommu = amd_iommu_rlookup_table[dev_data->devid];
444 dev_data->iommu_v2 = iommu->is_iommu_v2;
447 dev->archdata.iommu = dev_data;
449 iommu_device_link(&iommu->iommu, dev);
454 static void iommu_ignore_device(struct device *dev)
459 devid = get_device_id(dev);
463 alias = get_alias(dev);
465 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
466 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
468 amd_iommu_rlookup_table[devid] = NULL;
469 amd_iommu_rlookup_table[alias] = NULL;
472 static void iommu_uninit_device(struct device *dev)
474 struct iommu_dev_data *dev_data;
475 struct amd_iommu *iommu;
478 devid = get_device_id(dev);
482 iommu = amd_iommu_rlookup_table[devid];
484 dev_data = search_dev_data(devid);
488 if (dev_data->domain)
491 iommu_device_unlink(&iommu->iommu, dev);
493 iommu_group_remove_device(dev);
499 * We keep dev_data around for unplugged devices and reuse it when the
500 * device is re-plugged - not doing so would introduce a ton of races.
504 /****************************************************************************
506 * Interrupt handling functions
508 ****************************************************************************/
510 static void dump_dte_entry(u16 devid)
514 for (i = 0; i < 4; ++i)
515 pr_err("DTE[%d]: %016llx\n", i,
516 amd_iommu_dev_table[devid].data[i]);
519 static void dump_command(unsigned long phys_addr)
521 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
524 for (i = 0; i < 4; ++i)
525 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
528 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
529 u64 address, int flags)
531 struct iommu_dev_data *dev_data = NULL;
532 struct pci_dev *pdev;
534 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
537 dev_data = get_dev_data(&pdev->dev);
539 if (dev_data && __ratelimit(&dev_data->rs)) {
540 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
541 domain_id, address, flags);
542 } else if (printk_ratelimit()) {
543 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
544 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
545 domain_id, address, flags);
552 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
554 struct device *dev = iommu->iommu.dev;
555 int type, devid, pasid, flags, tag;
556 volatile u32 *event = __evt;
561 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
562 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
563 pasid = PPR_PASID(*(u64 *)&event[0]);
564 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
565 address = (u64)(((u64)event[3]) << 32) | event[2];
568 /* Did we hit the erratum? */
569 if (++count == LOOP_TIMEOUT) {
570 pr_err("No event written to event log\n");
577 if (type == EVENT_TYPE_IO_FAULT) {
578 amd_iommu_report_page_fault(devid, pasid, address, flags);
583 case EVENT_TYPE_ILL_DEV:
584 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
586 pasid, address, flags);
587 dump_dte_entry(devid);
589 case EVENT_TYPE_DEV_TAB_ERR:
590 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
591 "address=0x%llx flags=0x%04x]\n",
592 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
595 case EVENT_TYPE_PAGE_TAB_ERR:
596 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 pasid, address, flags);
600 case EVENT_TYPE_ILL_CMD:
601 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
602 dump_command(address);
604 case EVENT_TYPE_CMD_HARD_ERR:
605 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
608 case EVENT_TYPE_IOTLB_INV_TO:
609 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
613 case EVENT_TYPE_INV_DEV_REQ:
614 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
616 pasid, address, flags);
618 case EVENT_TYPE_INV_PPR_REQ:
619 pasid = ((event[0] >> 16) & 0xFFFF)
620 | ((event[1] << 6) & 0xF0000);
621 tag = event[1] & 0x03FF;
622 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
623 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
624 pasid, address, flags, tag);
627 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
628 event[0], event[1], event[2], event[3]);
631 memset(__evt, 0, 4 * sizeof(u32));
634 static void iommu_poll_events(struct amd_iommu *iommu)
638 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
639 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
641 while (head != tail) {
642 iommu_print_event(iommu, iommu->evt_buf + head);
643 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
646 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
649 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
651 struct amd_iommu_fault fault;
653 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
654 pr_err_ratelimited("Unknown PPR request received\n");
658 fault.address = raw[1];
659 fault.pasid = PPR_PASID(raw[0]);
660 fault.device_id = PPR_DEVID(raw[0]);
661 fault.tag = PPR_TAG(raw[0]);
662 fault.flags = PPR_FLAGS(raw[0]);
664 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
667 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
671 if (iommu->ppr_log == NULL)
674 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
675 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
677 while (head != tail) {
682 raw = (u64 *)(iommu->ppr_log + head);
685 * Hardware bug: Interrupt may arrive before the entry is
686 * written to memory. If this happens we need to wait for the
689 for (i = 0; i < LOOP_TIMEOUT; ++i) {
690 if (PPR_REQ_TYPE(raw[0]) != 0)
695 /* Avoid memcpy function-call overhead */
700 * To detect the hardware bug we need to clear the entry
703 raw[0] = raw[1] = 0UL;
705 /* Update head pointer of hardware ring-buffer */
706 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
707 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
709 /* Handle PPR entry */
710 iommu_handle_ppr_entry(iommu, entry);
712 /* Refresh ring-buffer information */
713 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
714 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
718 #ifdef CONFIG_IRQ_REMAP
719 static int (*iommu_ga_log_notifier)(u32);
721 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
723 iommu_ga_log_notifier = notifier;
727 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
729 static void iommu_poll_ga_log(struct amd_iommu *iommu)
731 u32 head, tail, cnt = 0;
733 if (iommu->ga_log == NULL)
736 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
737 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
739 while (head != tail) {
743 raw = (u64 *)(iommu->ga_log + head);
746 /* Avoid memcpy function-call overhead */
749 /* Update head pointer of hardware ring-buffer */
750 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
751 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
753 /* Handle GA entry */
754 switch (GA_REQ_TYPE(log_entry)) {
756 if (!iommu_ga_log_notifier)
759 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
760 __func__, GA_DEVID(log_entry),
763 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
764 pr_err("GA log notifier failed.\n");
771 #endif /* CONFIG_IRQ_REMAP */
773 #define AMD_IOMMU_INT_MASK \
774 (MMIO_STATUS_EVT_INT_MASK | \
775 MMIO_STATUS_PPR_INT_MASK | \
776 MMIO_STATUS_GALOG_INT_MASK)
778 irqreturn_t amd_iommu_int_thread(int irq, void *data)
780 struct amd_iommu *iommu = (struct amd_iommu *) data;
781 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
783 while (status & AMD_IOMMU_INT_MASK) {
784 /* Enable EVT and PPR and GA interrupts again */
785 writel(AMD_IOMMU_INT_MASK,
786 iommu->mmio_base + MMIO_STATUS_OFFSET);
788 if (status & MMIO_STATUS_EVT_INT_MASK) {
789 pr_devel("Processing IOMMU Event Log\n");
790 iommu_poll_events(iommu);
793 if (status & MMIO_STATUS_PPR_INT_MASK) {
794 pr_devel("Processing IOMMU PPR Log\n");
795 iommu_poll_ppr_log(iommu);
798 #ifdef CONFIG_IRQ_REMAP
799 if (status & MMIO_STATUS_GALOG_INT_MASK) {
800 pr_devel("Processing IOMMU GA Log\n");
801 iommu_poll_ga_log(iommu);
806 * Hardware bug: ERBT1312
807 * When re-enabling interrupt (by writing 1
808 * to clear the bit), the hardware might also try to set
809 * the interrupt bit in the event status register.
810 * In this scenario, the bit will be set, and disable
811 * subsequent interrupts.
813 * Workaround: The IOMMU driver should read back the
814 * status register and check if the interrupt bits are cleared.
815 * If not, driver will need to go through the interrupt handler
816 * again and re-clear the bits
818 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
823 irqreturn_t amd_iommu_int_handler(int irq, void *data)
825 return IRQ_WAKE_THREAD;
828 /****************************************************************************
830 * IOMMU command queuing functions
832 ****************************************************************************/
834 static int wait_on_sem(volatile u64 *sem)
838 while (*sem == 0 && i < LOOP_TIMEOUT) {
843 if (i == LOOP_TIMEOUT) {
844 pr_alert("Completion-Wait loop timed out\n");
851 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
852 struct iommu_cmd *cmd)
856 target = iommu->cmd_buf + iommu->cmd_buf_tail;
858 iommu->cmd_buf_tail += sizeof(*cmd);
859 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
861 /* Copy command to buffer */
862 memcpy(target, cmd, sizeof(*cmd));
864 /* Tell the IOMMU about it */
865 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
868 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
870 u64 paddr = iommu_virt_to_phys((void *)address);
872 WARN_ON(address & 0x7ULL);
874 memset(cmd, 0, sizeof(*cmd));
875 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
876 cmd->data[1] = upper_32_bits(paddr);
878 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
881 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
883 memset(cmd, 0, sizeof(*cmd));
884 cmd->data[0] = devid;
885 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
888 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
889 size_t size, u16 domid, int pde)
894 pages = iommu_num_pages(address, size, PAGE_SIZE);
899 * If we have to flush more than one page, flush all
900 * TLB entries for this domain
902 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
906 address &= PAGE_MASK;
908 memset(cmd, 0, sizeof(*cmd));
909 cmd->data[1] |= domid;
910 cmd->data[2] = lower_32_bits(address);
911 cmd->data[3] = upper_32_bits(address);
912 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
913 if (s) /* size bit - we flush more than one 4kb page */
914 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
915 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
916 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
919 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
920 u64 address, size_t size)
925 pages = iommu_num_pages(address, size, PAGE_SIZE);
930 * If we have to flush more than one page, flush all
931 * TLB entries for this domain
933 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
937 address &= PAGE_MASK;
939 memset(cmd, 0, sizeof(*cmd));
940 cmd->data[0] = devid;
941 cmd->data[0] |= (qdep & 0xff) << 24;
942 cmd->data[1] = devid;
943 cmd->data[2] = lower_32_bits(address);
944 cmd->data[3] = upper_32_bits(address);
945 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
947 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
950 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
951 u64 address, bool size)
953 memset(cmd, 0, sizeof(*cmd));
955 address &= ~(0xfffULL);
957 cmd->data[0] = pasid;
958 cmd->data[1] = domid;
959 cmd->data[2] = lower_32_bits(address);
960 cmd->data[3] = upper_32_bits(address);
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
962 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
965 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
968 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
969 int qdep, u64 address, bool size)
971 memset(cmd, 0, sizeof(*cmd));
973 address &= ~(0xfffULL);
975 cmd->data[0] = devid;
976 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
977 cmd->data[0] |= (qdep & 0xff) << 24;
978 cmd->data[1] = devid;
979 cmd->data[1] |= (pasid & 0xff) << 16;
980 cmd->data[2] = lower_32_bits(address);
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
982 cmd->data[3] = upper_32_bits(address);
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
985 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
988 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
989 int status, int tag, bool gn)
991 memset(cmd, 0, sizeof(*cmd));
993 cmd->data[0] = devid;
995 cmd->data[1] = pasid;
996 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
998 cmd->data[3] = tag & 0x1ff;
999 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1001 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1004 static void build_inv_all(struct iommu_cmd *cmd)
1006 memset(cmd, 0, sizeof(*cmd));
1007 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1010 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1012 memset(cmd, 0, sizeof(*cmd));
1013 cmd->data[0] = devid;
1014 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1018 * Writes the command to the IOMMUs command buffer and informs the
1019 * hardware about the new command.
1021 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1022 struct iommu_cmd *cmd,
1025 unsigned int count = 0;
1026 u32 left, next_tail;
1028 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1030 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1033 /* Skip udelay() the first time around */
1035 if (count == LOOP_TIMEOUT) {
1036 pr_err("Command buffer timeout\n");
1043 /* Update head and recheck remaining space */
1044 iommu->cmd_buf_head = readl(iommu->mmio_base +
1045 MMIO_CMD_HEAD_OFFSET);
1050 copy_cmd_to_buffer(iommu, cmd);
1052 /* Do we need to make sure all commands are processed? */
1053 iommu->need_sync = sync;
1058 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1059 struct iommu_cmd *cmd,
1062 unsigned long flags;
1065 raw_spin_lock_irqsave(&iommu->lock, flags);
1066 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1067 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1072 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1074 return iommu_queue_command_sync(iommu, cmd, true);
1078 * This function queues a completion wait command into the command
1079 * buffer of an IOMMU
1081 static int iommu_completion_wait(struct amd_iommu *iommu)
1083 struct iommu_cmd cmd;
1084 unsigned long flags;
1087 if (!iommu->need_sync)
1091 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1093 raw_spin_lock_irqsave(&iommu->lock, flags);
1097 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1101 ret = wait_on_sem(&iommu->cmd_sem);
1104 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1109 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1111 struct iommu_cmd cmd;
1113 build_inv_dte(&cmd, devid);
1115 return iommu_queue_command(iommu, &cmd);
1118 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1122 for (devid = 0; devid <= 0xffff; ++devid)
1123 iommu_flush_dte(iommu, devid);
1125 iommu_completion_wait(iommu);
1129 * This function uses heavy locking and may disable irqs for some time. But
1130 * this is no issue because it is only called during resume.
1132 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1136 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1137 struct iommu_cmd cmd;
1138 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1140 iommu_queue_command(iommu, &cmd);
1143 iommu_completion_wait(iommu);
1146 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1148 struct iommu_cmd cmd;
1150 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1152 iommu_queue_command(iommu, &cmd);
1154 iommu_completion_wait(iommu);
1157 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1159 struct iommu_cmd cmd;
1161 build_inv_all(&cmd);
1163 iommu_queue_command(iommu, &cmd);
1164 iommu_completion_wait(iommu);
1167 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1169 struct iommu_cmd cmd;
1171 build_inv_irt(&cmd, devid);
1173 iommu_queue_command(iommu, &cmd);
1176 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1180 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1181 iommu_flush_irt(iommu, devid);
1183 iommu_completion_wait(iommu);
1186 void iommu_flush_all_caches(struct amd_iommu *iommu)
1188 if (iommu_feature(iommu, FEATURE_IA)) {
1189 amd_iommu_flush_all(iommu);
1191 amd_iommu_flush_dte_all(iommu);
1192 amd_iommu_flush_irt_all(iommu);
1193 amd_iommu_flush_tlb_all(iommu);
1198 * Command send function for flushing on-device TLB
1200 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1201 u64 address, size_t size)
1203 struct amd_iommu *iommu;
1204 struct iommu_cmd cmd;
1207 qdep = dev_data->ats.qdep;
1208 iommu = amd_iommu_rlookup_table[dev_data->devid];
1210 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1212 return iommu_queue_command(iommu, &cmd);
1216 * Command send function for invalidating a device table entry
1218 static int device_flush_dte(struct iommu_dev_data *dev_data)
1220 struct amd_iommu *iommu;
1224 iommu = amd_iommu_rlookup_table[dev_data->devid];
1225 alias = dev_data->alias;
1227 ret = iommu_flush_dte(iommu, dev_data->devid);
1228 if (!ret && alias != dev_data->devid)
1229 ret = iommu_flush_dte(iommu, alias);
1233 if (dev_data->ats.enabled)
1234 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1240 * TLB invalidation function which is called from the mapping functions.
1241 * It invalidates a single PTE if the range to flush is within a single
1242 * page. Otherwise it flushes the whole TLB of the IOMMU.
1244 static void __domain_flush_pages(struct protection_domain *domain,
1245 u64 address, size_t size, int pde)
1247 struct iommu_dev_data *dev_data;
1248 struct iommu_cmd cmd;
1251 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1253 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1254 if (!domain->dev_iommu[i])
1258 * Devices of this domain are behind this IOMMU
1259 * We need a TLB flush
1261 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1264 list_for_each_entry(dev_data, &domain->dev_list, list) {
1266 if (!dev_data->ats.enabled)
1269 ret |= device_flush_iotlb(dev_data, address, size);
1275 static void domain_flush_pages(struct protection_domain *domain,
1276 u64 address, size_t size)
1278 __domain_flush_pages(domain, address, size, 0);
1281 /* Flush the whole IO/TLB for a given protection domain */
1282 static void domain_flush_tlb(struct protection_domain *domain)
1284 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1287 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1288 static void domain_flush_tlb_pde(struct protection_domain *domain)
1290 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1293 static void domain_flush_complete(struct protection_domain *domain)
1297 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1298 if (domain && !domain->dev_iommu[i])
1302 * Devices of this domain are behind this IOMMU
1303 * We need to wait for completion of all commands.
1305 iommu_completion_wait(amd_iommus[i]);
1309 /* Flush the not present cache if it exists */
1310 static void domain_flush_np_cache(struct protection_domain *domain,
1311 dma_addr_t iova, size_t size)
1313 if (unlikely(amd_iommu_np_cache)) {
1314 domain_flush_pages(domain, iova, size);
1315 domain_flush_complete(domain);
1321 * This function flushes the DTEs for all devices in domain
1323 static void domain_flush_devices(struct protection_domain *domain)
1325 struct iommu_dev_data *dev_data;
1327 list_for_each_entry(dev_data, &domain->dev_list, list)
1328 device_flush_dte(dev_data);
1331 /****************************************************************************
1333 * The functions below are used the create the page table mappings for
1334 * unity mapped regions.
1336 ****************************************************************************/
1338 static void free_page_list(struct page *freelist)
1340 while (freelist != NULL) {
1341 unsigned long p = (unsigned long)page_address(freelist);
1342 freelist = freelist->freelist;
1347 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1349 struct page *p = virt_to_page((void *)pt);
1351 p->freelist = freelist;
1356 #define DEFINE_FREE_PT_FN(LVL, FN) \
1357 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1365 for (i = 0; i < 512; ++i) { \
1366 /* PTE present? */ \
1367 if (!IOMMU_PTE_PRESENT(pt[i])) \
1371 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1372 PM_PTE_LEVEL(pt[i]) == 7) \
1375 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1376 freelist = FN(p, freelist); \
1379 return free_pt_page((unsigned long)pt, freelist); \
1382 DEFINE_FREE_PT_FN(l2, free_pt_page)
1383 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1384 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1385 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1386 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1388 static struct page *free_sub_pt(unsigned long root, int mode,
1389 struct page *freelist)
1392 case PAGE_MODE_NONE:
1393 case PAGE_MODE_7_LEVEL:
1395 case PAGE_MODE_1_LEVEL:
1396 freelist = free_pt_page(root, freelist);
1398 case PAGE_MODE_2_LEVEL:
1399 freelist = free_pt_l2(root, freelist);
1401 case PAGE_MODE_3_LEVEL:
1402 freelist = free_pt_l3(root, freelist);
1404 case PAGE_MODE_4_LEVEL:
1405 freelist = free_pt_l4(root, freelist);
1407 case PAGE_MODE_5_LEVEL:
1408 freelist = free_pt_l5(root, freelist);
1410 case PAGE_MODE_6_LEVEL:
1411 freelist = free_pt_l6(root, freelist);
1420 static void free_pagetable(struct protection_domain *domain)
1422 unsigned long root = (unsigned long)domain->pt_root;
1423 struct page *freelist = NULL;
1425 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1426 domain->mode > PAGE_MODE_6_LEVEL);
1428 free_sub_pt(root, domain->mode, freelist);
1430 free_page_list(freelist);
1434 * This function is used to add another level to an IO page table. Adding
1435 * another level increases the size of the address space by 9 bits to a size up
1438 static void increase_address_space(struct protection_domain *domain,
1441 unsigned long flags;
1444 spin_lock_irqsave(&domain->lock, flags);
1446 if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1447 /* address space already 64 bit large */
1450 pte = (void *)get_zeroed_page(gfp);
1454 *pte = PM_LEVEL_PDE(domain->mode,
1455 iommu_virt_to_phys(domain->pt_root));
1456 domain->pt_root = pte;
1458 domain->updated = true;
1461 spin_unlock_irqrestore(&domain->lock, flags);
1466 static u64 *alloc_pte(struct protection_domain *domain,
1467 unsigned long address,
1468 unsigned long page_size,
1475 BUG_ON(!is_power_of_2(page_size));
1477 while (address > PM_LEVEL_SIZE(domain->mode))
1478 increase_address_space(domain, gfp);
1480 level = domain->mode - 1;
1481 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1482 address = PAGE_SIZE_ALIGN(address, page_size);
1483 end_lvl = PAGE_SIZE_LEVEL(page_size);
1485 while (level > end_lvl) {
1490 pte_level = PM_PTE_LEVEL(__pte);
1492 if (!IOMMU_PTE_PRESENT(__pte) ||
1493 pte_level == PAGE_MODE_7_LEVEL) {
1494 page = (u64 *)get_zeroed_page(gfp);
1498 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1500 /* pte could have been changed somewhere. */
1501 if (cmpxchg64(pte, __pte, __npte) != __pte)
1502 free_page((unsigned long)page);
1503 else if (pte_level == PAGE_MODE_7_LEVEL)
1504 domain->updated = true;
1509 /* No level skipping support yet */
1510 if (pte_level != level)
1515 pte = IOMMU_PTE_PAGE(__pte);
1517 if (pte_page && level == end_lvl)
1520 pte = &pte[PM_LEVEL_INDEX(level, address)];
1527 * This function checks if there is a PTE for a given dma address. If
1528 * there is one, it returns the pointer to it.
1530 static u64 *fetch_pte(struct protection_domain *domain,
1531 unsigned long address,
1532 unsigned long *page_size)
1539 if (address > PM_LEVEL_SIZE(domain->mode))
1542 level = domain->mode - 1;
1543 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1544 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1549 if (!IOMMU_PTE_PRESENT(*pte))
1553 if (PM_PTE_LEVEL(*pte) == 7 ||
1554 PM_PTE_LEVEL(*pte) == 0)
1557 /* No level skipping support yet */
1558 if (PM_PTE_LEVEL(*pte) != level)
1563 /* Walk to the next level */
1564 pte = IOMMU_PTE_PAGE(*pte);
1565 pte = &pte[PM_LEVEL_INDEX(level, address)];
1566 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1569 if (PM_PTE_LEVEL(*pte) == 0x07) {
1570 unsigned long pte_mask;
1573 * If we have a series of large PTEs, make
1574 * sure to return a pointer to the first one.
1576 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1577 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1578 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1584 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1589 while (cmpxchg64(pte, pteval, 0) != pteval) {
1590 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1594 if (!IOMMU_PTE_PRESENT(pteval))
1597 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1598 mode = IOMMU_PTE_MODE(pteval);
1600 return free_sub_pt(pt, mode, freelist);
1604 * Generic mapping functions. It maps a physical address into a DMA
1605 * address space. It allocates the page table pages if necessary.
1606 * In the future it can be extended to a generic mapping function
1607 * supporting all features of AMD IOMMU page tables like level skipping
1608 * and full 64 bit address spaces.
1610 static int iommu_map_page(struct protection_domain *dom,
1611 unsigned long bus_addr,
1612 unsigned long phys_addr,
1613 unsigned long page_size,
1617 struct page *freelist = NULL;
1621 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1622 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1624 if (!(prot & IOMMU_PROT_MASK))
1627 count = PAGE_SIZE_PTE_COUNT(page_size);
1628 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1633 for (i = 0; i < count; ++i)
1634 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1636 if (freelist != NULL)
1637 dom->updated = true;
1640 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1641 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1643 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1645 if (prot & IOMMU_PROT_IR)
1646 __pte |= IOMMU_PTE_IR;
1647 if (prot & IOMMU_PROT_IW)
1648 __pte |= IOMMU_PTE_IW;
1650 for (i = 0; i < count; ++i)
1655 /* Everything flushed out, free pages now */
1656 free_page_list(freelist);
1661 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1662 unsigned long bus_addr,
1663 unsigned long page_size)
1665 unsigned long long unmapped;
1666 unsigned long unmap_size;
1669 BUG_ON(!is_power_of_2(page_size));
1673 while (unmapped < page_size) {
1675 pte = fetch_pte(dom, bus_addr, &unmap_size);
1680 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1681 for (i = 0; i < count; i++)
1685 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1686 unmapped += unmap_size;
1689 BUG_ON(unmapped && !is_power_of_2(unmapped));
1694 /****************************************************************************
1696 * The next functions belong to the address allocator for the dma_ops
1697 * interface functions.
1699 ****************************************************************************/
1702 static unsigned long dma_ops_alloc_iova(struct device *dev,
1703 struct dma_ops_domain *dma_dom,
1704 unsigned int pages, u64 dma_mask)
1706 unsigned long pfn = 0;
1708 pages = __roundup_pow_of_two(pages);
1710 if (dma_mask > DMA_BIT_MASK(32))
1711 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1712 IOVA_PFN(DMA_BIT_MASK(32)), false);
1715 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1716 IOVA_PFN(dma_mask), true);
1718 return (pfn << PAGE_SHIFT);
1721 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1722 unsigned long address,
1725 pages = __roundup_pow_of_two(pages);
1726 address >>= PAGE_SHIFT;
1728 free_iova_fast(&dma_dom->iovad, address, pages);
1731 /****************************************************************************
1733 * The next functions belong to the domain allocation. A domain is
1734 * allocated for every IOMMU as the default domain. If device isolation
1735 * is enabled, every device get its own domain. The most important thing
1736 * about domains is the page table mapping the DMA address space they
1739 ****************************************************************************/
1741 static u16 domain_id_alloc(void)
1745 spin_lock(&pd_bitmap_lock);
1746 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1748 if (id > 0 && id < MAX_DOMAIN_ID)
1749 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1752 spin_unlock(&pd_bitmap_lock);
1757 static void domain_id_free(int id)
1759 spin_lock(&pd_bitmap_lock);
1760 if (id > 0 && id < MAX_DOMAIN_ID)
1761 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1762 spin_unlock(&pd_bitmap_lock);
1765 static void free_gcr3_tbl_level1(u64 *tbl)
1770 for (i = 0; i < 512; ++i) {
1771 if (!(tbl[i] & GCR3_VALID))
1774 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1776 free_page((unsigned long)ptr);
1780 static void free_gcr3_tbl_level2(u64 *tbl)
1785 for (i = 0; i < 512; ++i) {
1786 if (!(tbl[i] & GCR3_VALID))
1789 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1791 free_gcr3_tbl_level1(ptr);
1795 static void free_gcr3_table(struct protection_domain *domain)
1797 if (domain->glx == 2)
1798 free_gcr3_tbl_level2(domain->gcr3_tbl);
1799 else if (domain->glx == 1)
1800 free_gcr3_tbl_level1(domain->gcr3_tbl);
1802 BUG_ON(domain->glx != 0);
1804 free_page((unsigned long)domain->gcr3_tbl);
1807 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1809 domain_flush_tlb(&dom->domain);
1810 domain_flush_complete(&dom->domain);
1813 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1815 struct dma_ops_domain *dom;
1817 dom = container_of(iovad, struct dma_ops_domain, iovad);
1819 dma_ops_domain_flush_tlb(dom);
1823 * Free a domain, only used if something went wrong in the
1824 * allocation path and we need to free an already allocated page table
1826 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1831 put_iova_domain(&dom->iovad);
1833 free_pagetable(&dom->domain);
1836 domain_id_free(dom->domain.id);
1842 * Allocates a new protection domain usable for the dma_ops functions.
1843 * It also initializes the page table and the address allocator data
1844 * structures required for the dma_ops interface
1846 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1848 struct dma_ops_domain *dma_dom;
1850 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1854 if (protection_domain_init(&dma_dom->domain))
1857 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1858 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1859 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1860 if (!dma_dom->domain.pt_root)
1863 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1865 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1868 /* Initialize reserved ranges */
1869 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1874 dma_ops_domain_free(dma_dom);
1880 * little helper function to check whether a given protection domain is a
1883 static bool dma_ops_domain(struct protection_domain *domain)
1885 return domain->flags & PD_DMA_OPS_MASK;
1888 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1895 if (domain->mode != PAGE_MODE_NONE)
1896 pte_root = iommu_virt_to_phys(domain->pt_root);
1898 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1899 << DEV_ENTRY_MODE_SHIFT;
1900 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1902 flags = amd_iommu_dev_table[devid].data[1];
1905 flags |= DTE_FLAG_IOTLB;
1908 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1910 if (iommu_feature(iommu, FEATURE_EPHSUP))
1911 pte_root |= 1ULL << DEV_ENTRY_PPR;
1914 if (domain->flags & PD_IOMMUV2_MASK) {
1915 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1916 u64 glx = domain->glx;
1919 pte_root |= DTE_FLAG_GV;
1920 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1922 /* First mask out possible old values for GCR3 table */
1923 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1926 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1929 /* Encode GCR3 table into DTE */
1930 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1933 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1936 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1940 flags &= ~DEV_DOMID_MASK;
1941 flags |= domain->id;
1943 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1944 amd_iommu_dev_table[devid].data[1] = flags;
1945 amd_iommu_dev_table[devid].data[0] = pte_root;
1948 * A kdump kernel might be replacing a domain ID that was copied from
1949 * the previous kernel--if so, it needs to flush the translation cache
1950 * entries for the old domain ID that is being overwritten
1953 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1955 amd_iommu_flush_tlb_domid(iommu, old_domid);
1959 static void clear_dte_entry(u16 devid)
1961 /* remove entry from the device table seen by the hardware */
1962 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1963 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1965 amd_iommu_apply_erratum_63(devid);
1968 static void do_attach(struct iommu_dev_data *dev_data,
1969 struct protection_domain *domain)
1971 struct amd_iommu *iommu;
1975 iommu = amd_iommu_rlookup_table[dev_data->devid];
1976 alias = dev_data->alias;
1977 ats = dev_data->ats.enabled;
1979 /* Update data structures */
1980 dev_data->domain = domain;
1981 list_add(&dev_data->list, &domain->dev_list);
1983 /* Do reference counting */
1984 domain->dev_iommu[iommu->index] += 1;
1985 domain->dev_cnt += 1;
1987 /* Update device table */
1988 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1989 if (alias != dev_data->devid)
1990 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1992 device_flush_dte(dev_data);
1995 static void do_detach(struct iommu_dev_data *dev_data)
1997 struct protection_domain *domain = dev_data->domain;
1998 struct amd_iommu *iommu;
2001 iommu = amd_iommu_rlookup_table[dev_data->devid];
2002 alias = dev_data->alias;
2004 /* Update data structures */
2005 dev_data->domain = NULL;
2006 list_del(&dev_data->list);
2007 clear_dte_entry(dev_data->devid);
2008 if (alias != dev_data->devid)
2009 clear_dte_entry(alias);
2011 /* Flush the DTE entry */
2012 device_flush_dte(dev_data);
2015 domain_flush_tlb_pde(domain);
2017 /* Wait for the flushes to finish */
2018 domain_flush_complete(domain);
2020 /* decrease reference counters - needs to happen after the flushes */
2021 domain->dev_iommu[iommu->index] -= 1;
2022 domain->dev_cnt -= 1;
2026 * If a device is not yet associated with a domain, this function makes the
2027 * device visible in the domain
2029 static int __attach_device(struct iommu_dev_data *dev_data,
2030 struct protection_domain *domain)
2035 spin_lock(&domain->lock);
2038 if (dev_data->domain != NULL)
2041 /* Attach alias group root */
2042 do_attach(dev_data, domain);
2049 spin_unlock(&domain->lock);
2055 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2057 pci_disable_ats(pdev);
2058 pci_disable_pri(pdev);
2059 pci_disable_pasid(pdev);
2062 /* FIXME: Change generic reset-function to do the same */
2063 static int pri_reset_while_enabled(struct pci_dev *pdev)
2068 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2072 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2073 control |= PCI_PRI_CTRL_RESET;
2074 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2079 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2084 /* FIXME: Hardcode number of outstanding requests for now */
2086 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2088 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2090 /* Only allow access to user-accessible pages */
2091 ret = pci_enable_pasid(pdev, 0);
2095 /* First reset the PRI state of the device */
2096 ret = pci_reset_pri(pdev);
2101 ret = pci_enable_pri(pdev, reqs);
2106 ret = pri_reset_while_enabled(pdev);
2111 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2118 pci_disable_pri(pdev);
2119 pci_disable_pasid(pdev);
2125 * If a device is not yet associated with a domain, this function makes the
2126 * device visible in the domain
2128 static int attach_device(struct device *dev,
2129 struct protection_domain *domain)
2131 struct pci_dev *pdev;
2132 struct iommu_dev_data *dev_data;
2133 unsigned long flags;
2136 dev_data = get_dev_data(dev);
2138 if (!dev_is_pci(dev))
2139 goto skip_ats_check;
2141 pdev = to_pci_dev(dev);
2142 if (domain->flags & PD_IOMMUV2_MASK) {
2143 if (!dev_data->passthrough)
2146 if (dev_data->iommu_v2) {
2147 if (pdev_iommuv2_enable(pdev) != 0)
2150 dev_data->ats.enabled = true;
2151 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2152 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2154 } else if (amd_iommu_iotlb_sup &&
2155 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2156 dev_data->ats.enabled = true;
2157 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2161 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2162 ret = __attach_device(dev_data, domain);
2163 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2166 * We might boot into a crash-kernel here. The crashed kernel
2167 * left the caches in the IOMMU dirty. So we have to flush
2168 * here to evict all dirty stuff.
2170 domain_flush_tlb_pde(domain);
2176 * Removes a device from a protection domain (unlocked)
2178 static void __detach_device(struct iommu_dev_data *dev_data)
2180 struct protection_domain *domain;
2182 domain = dev_data->domain;
2184 spin_lock(&domain->lock);
2186 do_detach(dev_data);
2188 spin_unlock(&domain->lock);
2192 * Removes a device from a protection domain (with devtable_lock held)
2194 static void detach_device(struct device *dev)
2196 struct protection_domain *domain;
2197 struct iommu_dev_data *dev_data;
2198 unsigned long flags;
2200 dev_data = get_dev_data(dev);
2201 domain = dev_data->domain;
2204 * First check if the device is still attached. It might already
2205 * be detached from its domain because the generic
2206 * iommu_detach_group code detached it and we try again here in
2207 * our alias handling.
2209 if (WARN_ON(!dev_data->domain))
2212 /* lock device table */
2213 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2214 __detach_device(dev_data);
2215 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2217 if (!dev_is_pci(dev))
2220 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2221 pdev_iommuv2_disable(to_pci_dev(dev));
2222 else if (dev_data->ats.enabled)
2223 pci_disable_ats(to_pci_dev(dev));
2225 dev_data->ats.enabled = false;
2228 static int amd_iommu_add_device(struct device *dev)
2230 struct iommu_dev_data *dev_data;
2231 struct iommu_domain *domain;
2232 struct amd_iommu *iommu;
2235 if (!check_device(dev) || get_dev_data(dev))
2238 devid = get_device_id(dev);
2242 iommu = amd_iommu_rlookup_table[devid];
2244 ret = iommu_init_device(dev);
2246 if (ret != -ENOTSUPP)
2247 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2249 iommu_ignore_device(dev);
2250 dev->dma_ops = NULL;
2253 init_iommu_group(dev);
2255 dev_data = get_dev_data(dev);
2259 if (dev_data->iommu_v2)
2260 iommu_request_dm_for_dev(dev);
2262 /* Domains are initialized for this device - have a look what we ended up with */
2263 domain = iommu_get_domain_for_dev(dev);
2264 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2265 dev_data->passthrough = true;
2267 dev->dma_ops = &amd_iommu_dma_ops;
2270 iommu_completion_wait(iommu);
2275 static void amd_iommu_remove_device(struct device *dev)
2277 struct amd_iommu *iommu;
2280 if (!check_device(dev))
2283 devid = get_device_id(dev);
2287 iommu = amd_iommu_rlookup_table[devid];
2289 iommu_uninit_device(dev);
2290 iommu_completion_wait(iommu);
2293 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2295 if (dev_is_pci(dev))
2296 return pci_device_group(dev);
2298 return acpihid_device_group(dev);
2301 /*****************************************************************************
2303 * The next functions belong to the dma_ops mapping/unmapping code.
2305 *****************************************************************************/
2308 * In the dma_ops path we only have the struct device. This function
2309 * finds the corresponding IOMMU, the protection domain and the
2310 * requestor id for a given device.
2311 * If the device is not yet associated with a domain this is also done
2314 static struct protection_domain *get_domain(struct device *dev)
2316 struct protection_domain *domain;
2317 struct iommu_domain *io_domain;
2319 if (!check_device(dev))
2320 return ERR_PTR(-EINVAL);
2322 domain = get_dev_data(dev)->domain;
2323 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2324 get_dev_data(dev)->defer_attach = false;
2325 io_domain = iommu_get_domain_for_dev(dev);
2326 domain = to_pdomain(io_domain);
2327 attach_device(dev, domain);
2330 return ERR_PTR(-EBUSY);
2332 if (!dma_ops_domain(domain))
2333 return ERR_PTR(-EBUSY);
2338 static void update_device_table(struct protection_domain *domain)
2340 struct iommu_dev_data *dev_data;
2342 list_for_each_entry(dev_data, &domain->dev_list, list) {
2343 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2344 dev_data->iommu_v2);
2346 if (dev_data->devid == dev_data->alias)
2349 /* There is an alias, update device table entry for it */
2350 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2351 dev_data->iommu_v2);
2355 static void update_domain(struct protection_domain *domain)
2357 if (!domain->updated)
2360 update_device_table(domain);
2362 domain_flush_devices(domain);
2363 domain_flush_tlb_pde(domain);
2365 domain->updated = false;
2368 static int dir2prot(enum dma_data_direction direction)
2370 if (direction == DMA_TO_DEVICE)
2371 return IOMMU_PROT_IR;
2372 else if (direction == DMA_FROM_DEVICE)
2373 return IOMMU_PROT_IW;
2374 else if (direction == DMA_BIDIRECTIONAL)
2375 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2381 * This function contains common code for mapping of a physically
2382 * contiguous memory region into DMA address space. It is used by all
2383 * mapping functions provided with this IOMMU driver.
2384 * Must be called with the domain lock held.
2386 static dma_addr_t __map_single(struct device *dev,
2387 struct dma_ops_domain *dma_dom,
2390 enum dma_data_direction direction,
2393 dma_addr_t offset = paddr & ~PAGE_MASK;
2394 dma_addr_t address, start, ret;
2399 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2402 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2406 prot = dir2prot(direction);
2409 for (i = 0; i < pages; ++i) {
2410 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2411 PAGE_SIZE, prot, GFP_ATOMIC);
2420 domain_flush_np_cache(&dma_dom->domain, address, size);
2427 for (--i; i >= 0; --i) {
2429 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2432 domain_flush_tlb(&dma_dom->domain);
2433 domain_flush_complete(&dma_dom->domain);
2435 dma_ops_free_iova(dma_dom, address, pages);
2437 return DMA_MAPPING_ERROR;
2441 * Does the reverse of the __map_single function. Must be called with
2442 * the domain lock held too
2444 static void __unmap_single(struct dma_ops_domain *dma_dom,
2445 dma_addr_t dma_addr,
2449 dma_addr_t i, start;
2452 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2453 dma_addr &= PAGE_MASK;
2456 for (i = 0; i < pages; ++i) {
2457 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2461 if (amd_iommu_unmap_flush) {
2462 domain_flush_tlb(&dma_dom->domain);
2463 domain_flush_complete(&dma_dom->domain);
2464 dma_ops_free_iova(dma_dom, dma_addr, pages);
2466 pages = __roundup_pow_of_two(pages);
2467 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2472 * The exported map_single function for dma_ops.
2474 static dma_addr_t map_page(struct device *dev, struct page *page,
2475 unsigned long offset, size_t size,
2476 enum dma_data_direction dir,
2477 unsigned long attrs)
2479 phys_addr_t paddr = page_to_phys(page) + offset;
2480 struct protection_domain *domain;
2481 struct dma_ops_domain *dma_dom;
2484 domain = get_domain(dev);
2485 if (PTR_ERR(domain) == -EINVAL)
2486 return (dma_addr_t)paddr;
2487 else if (IS_ERR(domain))
2488 return DMA_MAPPING_ERROR;
2490 dma_mask = *dev->dma_mask;
2491 dma_dom = to_dma_ops_domain(domain);
2493 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2497 * The exported unmap_single function for dma_ops.
2499 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2500 enum dma_data_direction dir, unsigned long attrs)
2502 struct protection_domain *domain;
2503 struct dma_ops_domain *dma_dom;
2505 domain = get_domain(dev);
2509 dma_dom = to_dma_ops_domain(domain);
2511 __unmap_single(dma_dom, dma_addr, size, dir);
2514 static int sg_num_pages(struct device *dev,
2515 struct scatterlist *sglist,
2518 unsigned long mask, boundary_size;
2519 struct scatterlist *s;
2522 mask = dma_get_seg_boundary(dev);
2523 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2524 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2526 for_each_sg(sglist, s, nelems, i) {
2529 s->dma_address = npages << PAGE_SHIFT;
2530 p = npages % boundary_size;
2531 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2532 if (p + n > boundary_size)
2533 npages += boundary_size - p;
2541 * The exported map_sg function for dma_ops (handles scatter-gather
2544 static int map_sg(struct device *dev, struct scatterlist *sglist,
2545 int nelems, enum dma_data_direction direction,
2546 unsigned long attrs)
2548 int mapped_pages = 0, npages = 0, prot = 0, i;
2549 struct protection_domain *domain;
2550 struct dma_ops_domain *dma_dom;
2551 struct scatterlist *s;
2552 unsigned long address;
2556 domain = get_domain(dev);
2560 dma_dom = to_dma_ops_domain(domain);
2561 dma_mask = *dev->dma_mask;
2563 npages = sg_num_pages(dev, sglist, nelems);
2565 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2569 prot = dir2prot(direction);
2571 /* Map all sg entries */
2572 for_each_sg(sglist, s, nelems, i) {
2573 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2575 for (j = 0; j < pages; ++j) {
2576 unsigned long bus_addr, phys_addr;
2578 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2579 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2580 ret = iommu_map_page(domain, bus_addr, phys_addr,
2582 GFP_ATOMIC | __GFP_NOWARN);
2590 /* Everything is mapped - write the right values into s->dma_address */
2591 for_each_sg(sglist, s, nelems, i) {
2593 * Add in the remaining piece of the scatter-gather offset that
2594 * was masked out when we were determining the physical address
2595 * via (sg_phys(s) & PAGE_MASK) earlier.
2597 s->dma_address += address + (s->offset & ~PAGE_MASK);
2598 s->dma_length = s->length;
2602 domain_flush_np_cache(domain, s->dma_address, s->dma_length);
2607 dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2610 for_each_sg(sglist, s, nelems, i) {
2611 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2613 for (j = 0; j < pages; ++j) {
2614 unsigned long bus_addr;
2616 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2617 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2619 if (--mapped_pages == 0)
2625 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2632 * The exported map_sg function for dma_ops (handles scatter-gather
2635 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2636 int nelems, enum dma_data_direction dir,
2637 unsigned long attrs)
2639 struct protection_domain *domain;
2640 struct dma_ops_domain *dma_dom;
2641 unsigned long startaddr;
2644 domain = get_domain(dev);
2648 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2649 dma_dom = to_dma_ops_domain(domain);
2650 npages = sg_num_pages(dev, sglist, nelems);
2652 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2656 * The exported alloc_coherent function for dma_ops.
2658 static void *alloc_coherent(struct device *dev, size_t size,
2659 dma_addr_t *dma_addr, gfp_t flag,
2660 unsigned long attrs)
2662 u64 dma_mask = dev->coherent_dma_mask;
2663 struct protection_domain *domain;
2664 struct dma_ops_domain *dma_dom;
2667 domain = get_domain(dev);
2668 if (PTR_ERR(domain) == -EINVAL) {
2669 page = alloc_pages(flag, get_order(size));
2670 *dma_addr = page_to_phys(page);
2671 return page_address(page);
2672 } else if (IS_ERR(domain))
2675 dma_dom = to_dma_ops_domain(domain);
2676 size = PAGE_ALIGN(size);
2677 dma_mask = dev->coherent_dma_mask;
2678 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2681 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2683 if (!gfpflags_allow_blocking(flag))
2686 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2687 get_order(size), flag & __GFP_NOWARN);
2693 dma_mask = *dev->dma_mask;
2695 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2696 size, DMA_BIDIRECTIONAL, dma_mask);
2698 if (*dma_addr == DMA_MAPPING_ERROR)
2701 return page_address(page);
2705 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2706 __free_pages(page, get_order(size));
2712 * The exported free_coherent function for dma_ops.
2714 static void free_coherent(struct device *dev, size_t size,
2715 void *virt_addr, dma_addr_t dma_addr,
2716 unsigned long attrs)
2718 struct protection_domain *domain;
2719 struct dma_ops_domain *dma_dom;
2722 page = virt_to_page(virt_addr);
2723 size = PAGE_ALIGN(size);
2725 domain = get_domain(dev);
2729 dma_dom = to_dma_ops_domain(domain);
2731 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2734 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2735 __free_pages(page, get_order(size));
2739 * This function is called by the DMA layer to find out if we can handle a
2740 * particular device. It is part of the dma_ops.
2742 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2744 if (!dma_direct_supported(dev, mask))
2746 return check_device(dev);
2749 static const struct dma_map_ops amd_iommu_dma_ops = {
2750 .alloc = alloc_coherent,
2751 .free = free_coherent,
2752 .map_page = map_page,
2753 .unmap_page = unmap_page,
2755 .unmap_sg = unmap_sg,
2756 .dma_supported = amd_iommu_dma_supported,
2757 .mmap = dma_common_mmap,
2758 .get_sgtable = dma_common_get_sgtable,
2761 static int init_reserved_iova_ranges(void)
2763 struct pci_dev *pdev = NULL;
2766 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2768 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2769 &reserved_rbtree_key);
2771 /* MSI memory range */
2772 val = reserve_iova(&reserved_iova_ranges,
2773 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2775 pr_err("Reserving MSI range failed\n");
2779 /* HT memory range */
2780 val = reserve_iova(&reserved_iova_ranges,
2781 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2783 pr_err("Reserving HT range failed\n");
2788 * Memory used for PCI resources
2789 * FIXME: Check whether we can reserve the PCI-hole completly
2791 for_each_pci_dev(pdev) {
2794 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2795 struct resource *r = &pdev->resource[i];
2797 if (!(r->flags & IORESOURCE_MEM))
2800 val = reserve_iova(&reserved_iova_ranges,
2804 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2813 int __init amd_iommu_init_api(void)
2817 ret = iova_cache_get();
2821 ret = init_reserved_iova_ranges();
2825 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2828 #ifdef CONFIG_ARM_AMBA
2829 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2833 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2840 int __init amd_iommu_init_dma_ops(void)
2842 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2845 if (amd_iommu_unmap_flush)
2846 pr_info("IO/TLB flush on unmap enabled\n");
2848 pr_info("Lazy IO/TLB flushing enabled\n");
2854 /*****************************************************************************
2856 * The following functions belong to the exported interface of AMD IOMMU
2858 * This interface allows access to lower level functions of the IOMMU
2859 * like protection domain handling and assignement of devices to domains
2860 * which is not possible with the dma_ops interface.
2862 *****************************************************************************/
2864 static void cleanup_domain(struct protection_domain *domain)
2866 struct iommu_dev_data *entry;
2867 unsigned long flags;
2869 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2871 while (!list_empty(&domain->dev_list)) {
2872 entry = list_first_entry(&domain->dev_list,
2873 struct iommu_dev_data, list);
2874 BUG_ON(!entry->domain);
2875 __detach_device(entry);
2878 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2881 static void protection_domain_free(struct protection_domain *domain)
2887 domain_id_free(domain->id);
2892 static int protection_domain_init(struct protection_domain *domain)
2894 spin_lock_init(&domain->lock);
2895 mutex_init(&domain->api_lock);
2896 domain->id = domain_id_alloc();
2899 INIT_LIST_HEAD(&domain->dev_list);
2904 static struct protection_domain *protection_domain_alloc(void)
2906 struct protection_domain *domain;
2908 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2912 if (protection_domain_init(domain))
2923 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2925 struct protection_domain *pdomain;
2926 struct dma_ops_domain *dma_domain;
2929 case IOMMU_DOMAIN_UNMANAGED:
2930 pdomain = protection_domain_alloc();
2934 pdomain->mode = PAGE_MODE_3_LEVEL;
2935 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2936 if (!pdomain->pt_root) {
2937 protection_domain_free(pdomain);
2941 pdomain->domain.geometry.aperture_start = 0;
2942 pdomain->domain.geometry.aperture_end = ~0ULL;
2943 pdomain->domain.geometry.force_aperture = true;
2946 case IOMMU_DOMAIN_DMA:
2947 dma_domain = dma_ops_domain_alloc();
2949 pr_err("Failed to allocate\n");
2952 pdomain = &dma_domain->domain;
2954 case IOMMU_DOMAIN_IDENTITY:
2955 pdomain = protection_domain_alloc();
2959 pdomain->mode = PAGE_MODE_NONE;
2965 return &pdomain->domain;
2968 static void amd_iommu_domain_free(struct iommu_domain *dom)
2970 struct protection_domain *domain;
2971 struct dma_ops_domain *dma_dom;
2973 domain = to_pdomain(dom);
2975 if (domain->dev_cnt > 0)
2976 cleanup_domain(domain);
2978 BUG_ON(domain->dev_cnt != 0);
2983 switch (dom->type) {
2984 case IOMMU_DOMAIN_DMA:
2985 /* Now release the domain */
2986 dma_dom = to_dma_ops_domain(domain);
2987 dma_ops_domain_free(dma_dom);
2990 if (domain->mode != PAGE_MODE_NONE)
2991 free_pagetable(domain);
2993 if (domain->flags & PD_IOMMUV2_MASK)
2994 free_gcr3_table(domain);
2996 protection_domain_free(domain);
3001 static void amd_iommu_detach_device(struct iommu_domain *dom,
3004 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3005 struct amd_iommu *iommu;
3008 if (!check_device(dev))
3011 devid = get_device_id(dev);
3015 if (dev_data->domain != NULL)
3018 iommu = amd_iommu_rlookup_table[devid];
3022 #ifdef CONFIG_IRQ_REMAP
3023 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3024 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3025 dev_data->use_vapic = 0;
3028 iommu_completion_wait(iommu);
3031 static int amd_iommu_attach_device(struct iommu_domain *dom,
3034 struct protection_domain *domain = to_pdomain(dom);
3035 struct iommu_dev_data *dev_data;
3036 struct amd_iommu *iommu;
3039 if (!check_device(dev))
3042 dev_data = dev->archdata.iommu;
3044 iommu = amd_iommu_rlookup_table[dev_data->devid];
3048 if (dev_data->domain)
3051 ret = attach_device(dev, domain);
3053 #ifdef CONFIG_IRQ_REMAP
3054 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3055 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3056 dev_data->use_vapic = 1;
3058 dev_data->use_vapic = 0;
3062 iommu_completion_wait(iommu);
3067 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3068 phys_addr_t paddr, size_t page_size, int iommu_prot)
3070 struct protection_domain *domain = to_pdomain(dom);
3074 if (domain->mode == PAGE_MODE_NONE)
3077 if (iommu_prot & IOMMU_READ)
3078 prot |= IOMMU_PROT_IR;
3079 if (iommu_prot & IOMMU_WRITE)
3080 prot |= IOMMU_PROT_IW;
3082 mutex_lock(&domain->api_lock);
3083 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3084 mutex_unlock(&domain->api_lock);
3086 domain_flush_np_cache(domain, iova, page_size);
3091 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3093 struct iommu_iotlb_gather *gather)
3095 struct protection_domain *domain = to_pdomain(dom);
3098 if (domain->mode == PAGE_MODE_NONE)
3101 mutex_lock(&domain->api_lock);
3102 unmap_size = iommu_unmap_page(domain, iova, page_size);
3103 mutex_unlock(&domain->api_lock);
3108 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3111 struct protection_domain *domain = to_pdomain(dom);
3112 unsigned long offset_mask, pte_pgsize;
3115 if (domain->mode == PAGE_MODE_NONE)
3118 pte = fetch_pte(domain, iova, &pte_pgsize);
3120 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3123 offset_mask = pte_pgsize - 1;
3124 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3126 return (__pte & ~offset_mask) | (iova & offset_mask);
3129 static bool amd_iommu_capable(enum iommu_cap cap)
3132 case IOMMU_CAP_CACHE_COHERENCY:
3134 case IOMMU_CAP_INTR_REMAP:
3135 return (irq_remapping_enabled == 1);
3136 case IOMMU_CAP_NOEXEC:
3145 static void amd_iommu_get_resv_regions(struct device *dev,
3146 struct list_head *head)
3148 struct iommu_resv_region *region;
3149 struct unity_map_entry *entry;
3152 devid = get_device_id(dev);
3156 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3160 if (devid < entry->devid_start || devid > entry->devid_end)
3163 type = IOMMU_RESV_DIRECT;
3164 length = entry->address_end - entry->address_start;
3165 if (entry->prot & IOMMU_PROT_IR)
3167 if (entry->prot & IOMMU_PROT_IW)
3168 prot |= IOMMU_WRITE;
3169 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3170 /* Exclusion range */
3171 type = IOMMU_RESV_RESERVED;
3173 region = iommu_alloc_resv_region(entry->address_start,
3174 length, prot, type);
3176 dev_err(dev, "Out of memory allocating dm-regions\n");
3179 list_add_tail(®ion->list, head);
3182 region = iommu_alloc_resv_region(MSI_RANGE_START,
3183 MSI_RANGE_END - MSI_RANGE_START + 1,
3187 list_add_tail(®ion->list, head);
3189 region = iommu_alloc_resv_region(HT_RANGE_START,
3190 HT_RANGE_END - HT_RANGE_START + 1,
3191 0, IOMMU_RESV_RESERVED);
3194 list_add_tail(®ion->list, head);
3197 static void amd_iommu_put_resv_regions(struct device *dev,
3198 struct list_head *head)
3200 struct iommu_resv_region *entry, *next;
3202 list_for_each_entry_safe(entry, next, head, list)
3206 static void amd_iommu_apply_resv_region(struct device *dev,
3207 struct iommu_domain *domain,
3208 struct iommu_resv_region *region)
3210 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3211 unsigned long start, end;
3213 start = IOVA_PFN(region->start);
3214 end = IOVA_PFN(region->start + region->length - 1);
3216 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3219 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3222 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3223 return dev_data->defer_attach;
3226 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3228 struct protection_domain *dom = to_pdomain(domain);
3230 domain_flush_tlb_pde(dom);
3231 domain_flush_complete(dom);
3234 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
3235 struct iommu_iotlb_gather *gather)
3237 amd_iommu_flush_iotlb_all(domain);
3240 const struct iommu_ops amd_iommu_ops = {
3241 .capable = amd_iommu_capable,
3242 .domain_alloc = amd_iommu_domain_alloc,
3243 .domain_free = amd_iommu_domain_free,
3244 .attach_dev = amd_iommu_attach_device,
3245 .detach_dev = amd_iommu_detach_device,
3246 .map = amd_iommu_map,
3247 .unmap = amd_iommu_unmap,
3248 .iova_to_phys = amd_iommu_iova_to_phys,
3249 .add_device = amd_iommu_add_device,
3250 .remove_device = amd_iommu_remove_device,
3251 .device_group = amd_iommu_device_group,
3252 .get_resv_regions = amd_iommu_get_resv_regions,
3253 .put_resv_regions = amd_iommu_put_resv_regions,
3254 .apply_resv_region = amd_iommu_apply_resv_region,
3255 .is_attach_deferred = amd_iommu_is_attach_deferred,
3256 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3257 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3258 .iotlb_sync = amd_iommu_iotlb_sync,
3261 /*****************************************************************************
3263 * The next functions do a basic initialization of IOMMU for pass through
3266 * In passthrough mode the IOMMU is initialized and enabled but not used for
3267 * DMA-API translation.
3269 *****************************************************************************/
3271 /* IOMMUv2 specific functions */
3272 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3274 return atomic_notifier_chain_register(&ppr_notifier, nb);
3276 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3278 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3280 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3282 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3284 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3286 struct protection_domain *domain = to_pdomain(dom);
3287 unsigned long flags;
3289 spin_lock_irqsave(&domain->lock, flags);
3291 /* Update data structure */
3292 domain->mode = PAGE_MODE_NONE;
3293 domain->updated = true;
3295 /* Make changes visible to IOMMUs */
3296 update_domain(domain);
3298 /* Page-table is not visible to IOMMU anymore, so free it */
3299 free_pagetable(domain);
3301 spin_unlock_irqrestore(&domain->lock, flags);
3303 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3305 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3307 struct protection_domain *domain = to_pdomain(dom);
3308 unsigned long flags;
3311 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3314 /* Number of GCR3 table levels required */
3315 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3318 if (levels > amd_iommu_max_glx_val)
3321 spin_lock_irqsave(&domain->lock, flags);
3324 * Save us all sanity checks whether devices already in the
3325 * domain support IOMMUv2. Just force that the domain has no
3326 * devices attached when it is switched into IOMMUv2 mode.
3329 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3333 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3334 if (domain->gcr3_tbl == NULL)
3337 domain->glx = levels;
3338 domain->flags |= PD_IOMMUV2_MASK;
3339 domain->updated = true;
3341 update_domain(domain);
3346 spin_unlock_irqrestore(&domain->lock, flags);
3350 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3352 static int __flush_pasid(struct protection_domain *domain, int pasid,
3353 u64 address, bool size)
3355 struct iommu_dev_data *dev_data;
3356 struct iommu_cmd cmd;
3359 if (!(domain->flags & PD_IOMMUV2_MASK))
3362 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3365 * IOMMU TLB needs to be flushed before Device TLB to
3366 * prevent device TLB refill from IOMMU TLB
3368 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3369 if (domain->dev_iommu[i] == 0)
3372 ret = iommu_queue_command(amd_iommus[i], &cmd);
3377 /* Wait until IOMMU TLB flushes are complete */
3378 domain_flush_complete(domain);
3380 /* Now flush device TLBs */
3381 list_for_each_entry(dev_data, &domain->dev_list, list) {
3382 struct amd_iommu *iommu;
3386 There might be non-IOMMUv2 capable devices in an IOMMUv2
3389 if (!dev_data->ats.enabled)
3392 qdep = dev_data->ats.qdep;
3393 iommu = amd_iommu_rlookup_table[dev_data->devid];
3395 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3396 qdep, address, size);
3398 ret = iommu_queue_command(iommu, &cmd);
3403 /* Wait until all device TLBs are flushed */
3404 domain_flush_complete(domain);
3413 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3416 return __flush_pasid(domain, pasid, address, false);
3419 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3422 struct protection_domain *domain = to_pdomain(dom);
3423 unsigned long flags;
3426 spin_lock_irqsave(&domain->lock, flags);
3427 ret = __amd_iommu_flush_page(domain, pasid, address);
3428 spin_unlock_irqrestore(&domain->lock, flags);
3432 EXPORT_SYMBOL(amd_iommu_flush_page);
3434 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3436 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3440 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3442 struct protection_domain *domain = to_pdomain(dom);
3443 unsigned long flags;
3446 spin_lock_irqsave(&domain->lock, flags);
3447 ret = __amd_iommu_flush_tlb(domain, pasid);
3448 spin_unlock_irqrestore(&domain->lock, flags);
3452 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3454 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3461 index = (pasid >> (9 * level)) & 0x1ff;
3467 if (!(*pte & GCR3_VALID)) {
3471 root = (void *)get_zeroed_page(GFP_ATOMIC);
3475 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3478 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3486 static int __set_gcr3(struct protection_domain *domain, int pasid,
3491 if (domain->mode != PAGE_MODE_NONE)
3494 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3498 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3500 return __amd_iommu_flush_tlb(domain, pasid);
3503 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3507 if (domain->mode != PAGE_MODE_NONE)
3510 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3516 return __amd_iommu_flush_tlb(domain, pasid);
3519 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3522 struct protection_domain *domain = to_pdomain(dom);
3523 unsigned long flags;
3526 spin_lock_irqsave(&domain->lock, flags);
3527 ret = __set_gcr3(domain, pasid, cr3);
3528 spin_unlock_irqrestore(&domain->lock, flags);
3532 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3534 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3536 struct protection_domain *domain = to_pdomain(dom);
3537 unsigned long flags;
3540 spin_lock_irqsave(&domain->lock, flags);
3541 ret = __clear_gcr3(domain, pasid);
3542 spin_unlock_irqrestore(&domain->lock, flags);
3546 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3548 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3549 int status, int tag)
3551 struct iommu_dev_data *dev_data;
3552 struct amd_iommu *iommu;
3553 struct iommu_cmd cmd;
3555 dev_data = get_dev_data(&pdev->dev);
3556 iommu = amd_iommu_rlookup_table[dev_data->devid];
3558 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3559 tag, dev_data->pri_tlp);
3561 return iommu_queue_command(iommu, &cmd);
3563 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3565 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3567 struct protection_domain *pdomain;
3569 pdomain = get_domain(&pdev->dev);
3570 if (IS_ERR(pdomain))
3573 /* Only return IOMMUv2 domains */
3574 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3577 return &pdomain->domain;
3579 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3581 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3583 struct iommu_dev_data *dev_data;
3585 if (!amd_iommu_v2_supported())
3588 dev_data = get_dev_data(&pdev->dev);
3589 dev_data->errata |= (1 << erratum);
3591 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3593 int amd_iommu_device_info(struct pci_dev *pdev,
3594 struct amd_iommu_device_info *info)
3599 if (pdev == NULL || info == NULL)
3602 if (!amd_iommu_v2_supported())
3605 memset(info, 0, sizeof(*info));
3607 if (!pci_ats_disabled()) {
3608 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3610 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3613 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3615 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3617 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3621 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3622 max_pasids = min(max_pasids, (1 << 20));
3624 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3625 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3627 features = pci_pasid_features(pdev);
3628 if (features & PCI_PASID_CAP_EXEC)
3629 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3630 if (features & PCI_PASID_CAP_PRIV)
3631 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3636 EXPORT_SYMBOL(amd_iommu_device_info);
3638 #ifdef CONFIG_IRQ_REMAP
3640 /*****************************************************************************
3642 * Interrupt Remapping Implementation
3644 *****************************************************************************/
3646 static struct irq_chip amd_ir_chip;
3647 static DEFINE_SPINLOCK(iommu_table_lock);
3649 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3653 dte = amd_iommu_dev_table[devid].data[2];
3654 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3655 dte |= iommu_virt_to_phys(table->table);
3656 dte |= DTE_IRQ_REMAP_INTCTL;
3657 dte |= DTE_IRQ_TABLE_LEN;
3658 dte |= DTE_IRQ_REMAP_ENABLE;
3660 amd_iommu_dev_table[devid].data[2] = dte;
3663 static struct irq_remap_table *get_irq_table(u16 devid)
3665 struct irq_remap_table *table;
3667 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3668 "%s: no iommu for devid %x\n", __func__, devid))
3671 table = irq_lookup_table[devid];
3672 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3678 static struct irq_remap_table *__alloc_irq_table(void)
3680 struct irq_remap_table *table;
3682 table = kzalloc(sizeof(*table), GFP_KERNEL);
3686 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3687 if (!table->table) {
3691 raw_spin_lock_init(&table->lock);
3693 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3694 memset(table->table, 0,
3695 MAX_IRQS_PER_TABLE * sizeof(u32));
3697 memset(table->table, 0,
3698 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3702 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3703 struct irq_remap_table *table)
3705 irq_lookup_table[devid] = table;
3706 set_dte_irq_entry(devid, table);
3707 iommu_flush_dte(iommu, devid);
3710 static struct irq_remap_table *alloc_irq_table(u16 devid)
3712 struct irq_remap_table *table = NULL;
3713 struct irq_remap_table *new_table = NULL;
3714 struct amd_iommu *iommu;
3715 unsigned long flags;
3718 spin_lock_irqsave(&iommu_table_lock, flags);
3720 iommu = amd_iommu_rlookup_table[devid];
3724 table = irq_lookup_table[devid];
3728 alias = amd_iommu_alias_table[devid];
3729 table = irq_lookup_table[alias];
3731 set_remap_table_entry(iommu, devid, table);
3734 spin_unlock_irqrestore(&iommu_table_lock, flags);
3736 /* Nothing there yet, allocate new irq remapping table */
3737 new_table = __alloc_irq_table();
3741 spin_lock_irqsave(&iommu_table_lock, flags);
3743 table = irq_lookup_table[devid];
3747 table = irq_lookup_table[alias];
3749 set_remap_table_entry(iommu, devid, table);
3756 set_remap_table_entry(iommu, devid, table);
3758 set_remap_table_entry(iommu, alias, table);
3761 iommu_completion_wait(iommu);
3764 spin_unlock_irqrestore(&iommu_table_lock, flags);
3767 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3773 static int alloc_irq_index(u16 devid, int count, bool align)
3775 struct irq_remap_table *table;
3776 int index, c, alignment = 1;
3777 unsigned long flags;
3778 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3783 table = alloc_irq_table(devid);
3788 alignment = roundup_pow_of_two(count);
3790 raw_spin_lock_irqsave(&table->lock, flags);
3792 /* Scan table for free entries */
3793 for (index = ALIGN(table->min_index, alignment), c = 0;
3794 index < MAX_IRQS_PER_TABLE;) {
3795 if (!iommu->irte_ops->is_allocated(table, index)) {
3799 index = ALIGN(index + 1, alignment);
3805 iommu->irte_ops->set_allocated(table, index - c + 1);
3817 raw_spin_unlock_irqrestore(&table->lock, flags);
3822 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3823 struct amd_ir_data *data)
3825 struct irq_remap_table *table;
3826 struct amd_iommu *iommu;
3827 unsigned long flags;
3828 struct irte_ga *entry;
3830 iommu = amd_iommu_rlookup_table[devid];
3834 table = get_irq_table(devid);
3838 raw_spin_lock_irqsave(&table->lock, flags);
3840 entry = (struct irte_ga *)table->table;
3841 entry = &entry[index];
3842 entry->lo.fields_remap.valid = 0;
3843 entry->hi.val = irte->hi.val;
3844 entry->lo.val = irte->lo.val;
3845 entry->lo.fields_remap.valid = 1;
3849 raw_spin_unlock_irqrestore(&table->lock, flags);
3851 iommu_flush_irt(iommu, devid);
3852 iommu_completion_wait(iommu);
3857 static int modify_irte(u16 devid, int index, union irte *irte)
3859 struct irq_remap_table *table;
3860 struct amd_iommu *iommu;
3861 unsigned long flags;
3863 iommu = amd_iommu_rlookup_table[devid];
3867 table = get_irq_table(devid);
3871 raw_spin_lock_irqsave(&table->lock, flags);
3872 table->table[index] = irte->val;
3873 raw_spin_unlock_irqrestore(&table->lock, flags);
3875 iommu_flush_irt(iommu, devid);
3876 iommu_completion_wait(iommu);
3881 static void free_irte(u16 devid, int index)
3883 struct irq_remap_table *table;
3884 struct amd_iommu *iommu;
3885 unsigned long flags;
3887 iommu = amd_iommu_rlookup_table[devid];
3891 table = get_irq_table(devid);
3895 raw_spin_lock_irqsave(&table->lock, flags);
3896 iommu->irte_ops->clear_allocated(table, index);
3897 raw_spin_unlock_irqrestore(&table->lock, flags);
3899 iommu_flush_irt(iommu, devid);
3900 iommu_completion_wait(iommu);
3903 static void irte_prepare(void *entry,
3904 u32 delivery_mode, u32 dest_mode,
3905 u8 vector, u32 dest_apicid, int devid)
3907 union irte *irte = (union irte *) entry;
3910 irte->fields.vector = vector;
3911 irte->fields.int_type = delivery_mode;
3912 irte->fields.destination = dest_apicid;
3913 irte->fields.dm = dest_mode;
3914 irte->fields.valid = 1;
3917 static void irte_ga_prepare(void *entry,
3918 u32 delivery_mode, u32 dest_mode,
3919 u8 vector, u32 dest_apicid, int devid)
3921 struct irte_ga *irte = (struct irte_ga *) entry;
3925 irte->lo.fields_remap.int_type = delivery_mode;
3926 irte->lo.fields_remap.dm = dest_mode;
3927 irte->hi.fields.vector = vector;
3928 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3929 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3930 irte->lo.fields_remap.valid = 1;
3933 static void irte_activate(void *entry, u16 devid, u16 index)
3935 union irte *irte = (union irte *) entry;
3937 irte->fields.valid = 1;
3938 modify_irte(devid, index, irte);
3941 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3943 struct irte_ga *irte = (struct irte_ga *) entry;
3945 irte->lo.fields_remap.valid = 1;
3946 modify_irte_ga(devid, index, irte, NULL);
3949 static void irte_deactivate(void *entry, u16 devid, u16 index)
3951 union irte *irte = (union irte *) entry;
3953 irte->fields.valid = 0;
3954 modify_irte(devid, index, irte);
3957 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3959 struct irte_ga *irte = (struct irte_ga *) entry;
3961 irte->lo.fields_remap.valid = 0;
3962 modify_irte_ga(devid, index, irte, NULL);
3965 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3966 u8 vector, u32 dest_apicid)
3968 union irte *irte = (union irte *) entry;
3970 irte->fields.vector = vector;
3971 irte->fields.destination = dest_apicid;
3972 modify_irte(devid, index, irte);
3975 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3976 u8 vector, u32 dest_apicid)
3978 struct irte_ga *irte = (struct irte_ga *) entry;
3980 if (!irte->lo.fields_remap.guest_mode) {
3981 irte->hi.fields.vector = vector;
3982 irte->lo.fields_remap.destination =
3983 APICID_TO_IRTE_DEST_LO(dest_apicid);
3984 irte->hi.fields.destination =
3985 APICID_TO_IRTE_DEST_HI(dest_apicid);
3986 modify_irte_ga(devid, index, irte, NULL);
3990 #define IRTE_ALLOCATED (~1U)
3991 static void irte_set_allocated(struct irq_remap_table *table, int index)
3993 table->table[index] = IRTE_ALLOCATED;
3996 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3998 struct irte_ga *ptr = (struct irte_ga *)table->table;
3999 struct irte_ga *irte = &ptr[index];
4001 memset(&irte->lo.val, 0, sizeof(u64));
4002 memset(&irte->hi.val, 0, sizeof(u64));
4003 irte->hi.fields.vector = 0xff;
4006 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4008 union irte *ptr = (union irte *)table->table;
4009 union irte *irte = &ptr[index];
4011 return irte->val != 0;
4014 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4016 struct irte_ga *ptr = (struct irte_ga *)table->table;
4017 struct irte_ga *irte = &ptr[index];
4019 return irte->hi.fields.vector != 0;
4022 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4024 table->table[index] = 0;
4027 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4029 struct irte_ga *ptr = (struct irte_ga *)table->table;
4030 struct irte_ga *irte = &ptr[index];
4032 memset(&irte->lo.val, 0, sizeof(u64));
4033 memset(&irte->hi.val, 0, sizeof(u64));
4036 static int get_devid(struct irq_alloc_info *info)
4040 switch (info->type) {
4041 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4042 devid = get_ioapic_devid(info->ioapic_id);
4044 case X86_IRQ_ALLOC_TYPE_HPET:
4045 devid = get_hpet_devid(info->hpet_id);
4047 case X86_IRQ_ALLOC_TYPE_MSI:
4048 case X86_IRQ_ALLOC_TYPE_MSIX:
4049 devid = get_device_id(&info->msi_dev->dev);
4059 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4061 struct amd_iommu *iommu;
4067 devid = get_devid(info);
4069 iommu = amd_iommu_rlookup_table[devid];
4071 return iommu->ir_domain;
4077 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4079 struct amd_iommu *iommu;
4085 switch (info->type) {
4086 case X86_IRQ_ALLOC_TYPE_MSI:
4087 case X86_IRQ_ALLOC_TYPE_MSIX:
4088 devid = get_device_id(&info->msi_dev->dev);
4092 iommu = amd_iommu_rlookup_table[devid];
4094 return iommu->msi_domain;
4103 struct irq_remap_ops amd_iommu_irq_ops = {
4104 .prepare = amd_iommu_prepare,
4105 .enable = amd_iommu_enable,
4106 .disable = amd_iommu_disable,
4107 .reenable = amd_iommu_reenable,
4108 .enable_faulting = amd_iommu_enable_faulting,
4109 .get_ir_irq_domain = get_ir_irq_domain,
4110 .get_irq_domain = get_irq_domain,
4113 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4114 struct irq_cfg *irq_cfg,
4115 struct irq_alloc_info *info,
4116 int devid, int index, int sub_handle)
4118 struct irq_2_irte *irte_info = &data->irq_2_irte;
4119 struct msi_msg *msg = &data->msi_entry;
4120 struct IO_APIC_route_entry *entry;
4121 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4126 data->irq_2_irte.devid = devid;
4127 data->irq_2_irte.index = index + sub_handle;
4128 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4129 apic->irq_dest_mode, irq_cfg->vector,
4130 irq_cfg->dest_apicid, devid);
4132 switch (info->type) {
4133 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4134 /* Setup IOAPIC entry */
4135 entry = info->ioapic_entry;
4136 info->ioapic_entry = NULL;
4137 memset(entry, 0, sizeof(*entry));
4138 entry->vector = index;
4140 entry->trigger = info->ioapic_trigger;
4141 entry->polarity = info->ioapic_polarity;
4142 /* Mask level triggered irqs. */
4143 if (info->ioapic_trigger)
4147 case X86_IRQ_ALLOC_TYPE_HPET:
4148 case X86_IRQ_ALLOC_TYPE_MSI:
4149 case X86_IRQ_ALLOC_TYPE_MSIX:
4150 msg->address_hi = MSI_ADDR_BASE_HI;
4151 msg->address_lo = MSI_ADDR_BASE_LO;
4152 msg->data = irte_info->index;
4161 struct amd_irte_ops irte_32_ops = {
4162 .prepare = irte_prepare,
4163 .activate = irte_activate,
4164 .deactivate = irte_deactivate,
4165 .set_affinity = irte_set_affinity,
4166 .set_allocated = irte_set_allocated,
4167 .is_allocated = irte_is_allocated,
4168 .clear_allocated = irte_clear_allocated,
4171 struct amd_irte_ops irte_128_ops = {
4172 .prepare = irte_ga_prepare,
4173 .activate = irte_ga_activate,
4174 .deactivate = irte_ga_deactivate,
4175 .set_affinity = irte_ga_set_affinity,
4176 .set_allocated = irte_ga_set_allocated,
4177 .is_allocated = irte_ga_is_allocated,
4178 .clear_allocated = irte_ga_clear_allocated,
4181 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4182 unsigned int nr_irqs, void *arg)
4184 struct irq_alloc_info *info = arg;
4185 struct irq_data *irq_data;
4186 struct amd_ir_data *data = NULL;
4187 struct irq_cfg *cfg;
4193 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4194 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4198 * With IRQ remapping enabled, don't need contiguous CPU vectors
4199 * to support multiple MSI interrupts.
4201 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4202 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4204 devid = get_devid(info);
4208 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4212 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4213 struct irq_remap_table *table;
4214 struct amd_iommu *iommu;
4216 table = alloc_irq_table(devid);
4218 if (!table->min_index) {
4220 * Keep the first 32 indexes free for IOAPIC
4223 table->min_index = 32;
4224 iommu = amd_iommu_rlookup_table[devid];
4225 for (i = 0; i < 32; ++i)
4226 iommu->irte_ops->set_allocated(table, i);
4228 WARN_ON(table->min_index != 32);
4229 index = info->ioapic_pin;
4234 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4236 index = alloc_irq_index(devid, nr_irqs, align);
4239 pr_warn("Failed to allocate IRTE\n");
4241 goto out_free_parent;
4244 for (i = 0; i < nr_irqs; i++) {
4245 irq_data = irq_domain_get_irq_data(domain, virq + i);
4246 cfg = irqd_cfg(irq_data);
4247 if (!irq_data || !cfg) {
4253 data = kzalloc(sizeof(*data), GFP_KERNEL);
4257 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4258 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4260 data->entry = kzalloc(sizeof(struct irte_ga),
4267 irq_data->hwirq = (devid << 16) + i;
4268 irq_data->chip_data = data;
4269 irq_data->chip = &amd_ir_chip;
4270 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4271 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4277 for (i--; i >= 0; i--) {
4278 irq_data = irq_domain_get_irq_data(domain, virq + i);
4280 kfree(irq_data->chip_data);
4282 for (i = 0; i < nr_irqs; i++)
4283 free_irte(devid, index + i);
4285 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4289 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4290 unsigned int nr_irqs)
4292 struct irq_2_irte *irte_info;
4293 struct irq_data *irq_data;
4294 struct amd_ir_data *data;
4297 for (i = 0; i < nr_irqs; i++) {
4298 irq_data = irq_domain_get_irq_data(domain, virq + i);
4299 if (irq_data && irq_data->chip_data) {
4300 data = irq_data->chip_data;
4301 irte_info = &data->irq_2_irte;
4302 free_irte(irte_info->devid, irte_info->index);
4307 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4310 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4311 struct amd_ir_data *ir_data,
4312 struct irq_2_irte *irte_info,
4313 struct irq_cfg *cfg);
4315 static int irq_remapping_activate(struct irq_domain *domain,
4316 struct irq_data *irq_data, bool reserve)
4318 struct amd_ir_data *data = irq_data->chip_data;
4319 struct irq_2_irte *irte_info = &data->irq_2_irte;
4320 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4321 struct irq_cfg *cfg = irqd_cfg(irq_data);
4326 iommu->irte_ops->activate(data->entry, irte_info->devid,
4328 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4332 static void irq_remapping_deactivate(struct irq_domain *domain,
4333 struct irq_data *irq_data)
4335 struct amd_ir_data *data = irq_data->chip_data;
4336 struct irq_2_irte *irte_info = &data->irq_2_irte;
4337 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4340 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4344 static const struct irq_domain_ops amd_ir_domain_ops = {
4345 .alloc = irq_remapping_alloc,
4346 .free = irq_remapping_free,
4347 .activate = irq_remapping_activate,
4348 .deactivate = irq_remapping_deactivate,
4351 int amd_iommu_activate_guest_mode(void *data)
4353 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4354 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4356 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4357 !entry || entry->lo.fields_vapic.guest_mode)
4363 entry->lo.fields_vapic.guest_mode = 1;
4364 entry->lo.fields_vapic.ga_log_intr = 1;
4365 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
4366 entry->hi.fields.vector = ir_data->ga_vector;
4367 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
4369 return modify_irte_ga(ir_data->irq_2_irte.devid,
4370 ir_data->irq_2_irte.index, entry, NULL);
4372 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
4374 int amd_iommu_deactivate_guest_mode(void *data)
4376 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4377 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4378 struct irq_cfg *cfg = ir_data->cfg;
4380 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4381 !entry || !entry->lo.fields_vapic.guest_mode)
4387 entry->lo.fields_remap.dm = apic->irq_dest_mode;
4388 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
4389 entry->hi.fields.vector = cfg->vector;
4390 entry->lo.fields_remap.destination =
4391 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4392 entry->hi.fields.destination =
4393 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4395 return modify_irte_ga(ir_data->irq_2_irte.devid,
4396 ir_data->irq_2_irte.index, entry, NULL);
4398 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
4400 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4403 struct amd_iommu *iommu;
4404 struct amd_iommu_pi_data *pi_data = vcpu_info;
4405 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4406 struct amd_ir_data *ir_data = data->chip_data;
4407 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4408 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4411 * This device has never been set up for guest mode.
4412 * we should not modify the IRTE
4414 if (!dev_data || !dev_data->use_vapic)
4417 ir_data->cfg = irqd_cfg(data);
4418 pi_data->ir_data = ir_data;
4421 * SVM tries to set up for VAPIC mode, but we are in
4422 * legacy mode. So, we force legacy mode instead.
4424 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4425 pr_debug("%s: Fall back to using intr legacy remap\n",
4427 pi_data->is_guest_mode = false;
4430 iommu = amd_iommu_rlookup_table[irte_info->devid];
4434 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4435 if (pi_data->is_guest_mode) {
4436 ir_data->ga_root_ptr = (pi_data->base >> 12);
4437 ir_data->ga_vector = vcpu_pi_info->vector;
4438 ir_data->ga_tag = pi_data->ga_tag;
4439 ret = amd_iommu_activate_guest_mode(ir_data);
4441 ir_data->cached_ga_tag = pi_data->ga_tag;
4443 ret = amd_iommu_deactivate_guest_mode(ir_data);
4446 * This communicates the ga_tag back to the caller
4447 * so that it can do all the necessary clean up.
4450 ir_data->cached_ga_tag = 0;
4457 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4458 struct amd_ir_data *ir_data,
4459 struct irq_2_irte *irte_info,
4460 struct irq_cfg *cfg)
4464 * Atomically updates the IRTE with the new destination, vector
4465 * and flushes the interrupt entry cache.
4467 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4468 irte_info->index, cfg->vector,
4472 static int amd_ir_set_affinity(struct irq_data *data,
4473 const struct cpumask *mask, bool force)
4475 struct amd_ir_data *ir_data = data->chip_data;
4476 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4477 struct irq_cfg *cfg = irqd_cfg(data);
4478 struct irq_data *parent = data->parent_data;
4479 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4485 ret = parent->chip->irq_set_affinity(parent, mask, force);
4486 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4489 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4491 * After this point, all the interrupts will start arriving
4492 * at the new destination. So, time to cleanup the previous
4493 * vector allocation.
4495 send_cleanup_vector(cfg);
4497 return IRQ_SET_MASK_OK_DONE;
4500 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4502 struct amd_ir_data *ir_data = irq_data->chip_data;
4504 *msg = ir_data->msi_entry;
4507 static struct irq_chip amd_ir_chip = {
4509 .irq_ack = apic_ack_irq,
4510 .irq_set_affinity = amd_ir_set_affinity,
4511 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4512 .irq_compose_msi_msg = ir_compose_msi_msg,
4515 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4517 struct fwnode_handle *fn;
4519 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4522 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4523 irq_domain_free_fwnode(fn);
4524 if (!iommu->ir_domain)
4527 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4528 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4534 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4536 unsigned long flags;
4537 struct amd_iommu *iommu;
4538 struct irq_remap_table *table;
4539 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4540 int devid = ir_data->irq_2_irte.devid;
4541 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4542 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4544 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4545 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4548 iommu = amd_iommu_rlookup_table[devid];
4552 table = get_irq_table(devid);
4556 raw_spin_lock_irqsave(&table->lock, flags);
4558 if (ref->lo.fields_vapic.guest_mode) {
4560 ref->lo.fields_vapic.destination =
4561 APICID_TO_IRTE_DEST_LO(cpu);
4562 ref->hi.fields.destination =
4563 APICID_TO_IRTE_DEST_HI(cpu);
4565 ref->lo.fields_vapic.is_run = is_run;
4569 raw_spin_unlock_irqrestore(&table->lock, flags);
4571 iommu_flush_irt(iommu, devid);
4572 iommu_completion_wait(iommu);
4575 EXPORT_SYMBOL(amd_iommu_update_ga);