2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
57 #define AMD_IOMMU_MAPPING_ERROR 0
59 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61 #define LOOP_TIMEOUT 100000
63 /* IO virtual address start page frame number */
64 #define IOVA_START_PFN (1)
65 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
66 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
80 * 512GB Pages are not supported due to a hardware bug
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
84 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
86 /* List of all available dev_data structures */
87 static LIST_HEAD(dev_data_list);
88 static DEFINE_SPINLOCK(dev_data_list_lock);
90 LIST_HEAD(ioapic_map);
92 LIST_HEAD(acpihid_map);
94 #define FLUSH_QUEUE_SIZE 256
96 struct flush_queue_entry {
97 unsigned long iova_pfn;
99 struct dma_ops_domain *dma_dom;
105 struct flush_queue_entry *entries;
108 static DEFINE_PER_CPU(struct flush_queue, flush_queue);
110 static atomic_t queue_timer_on;
111 static struct timer_list queue_timer;
114 * Domain for untranslated devices - only allocated
115 * if iommu=pt passed on kernel cmd line.
117 const struct iommu_ops amd_iommu_ops;
119 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
120 int amd_iommu_max_glx_val = -1;
122 static const struct dma_map_ops amd_iommu_dma_ops;
125 * This struct contains device specific data for the IOMMU
127 struct iommu_dev_data {
128 struct list_head list; /* For domain->dev_list */
129 struct list_head dev_data_list; /* For global dev_data_list */
130 struct protection_domain *domain; /* Domain the device is bound to */
131 u16 devid; /* PCI Device ID */
132 u16 alias; /* Alias Device ID */
133 bool iommu_v2; /* Device can make use of IOMMUv2 */
134 bool passthrough; /* Device is identity mapped */
138 } ats; /* ATS state */
139 bool pri_tlp; /* PASID TLB required for
141 u32 errata; /* Bitmap for errata to apply */
142 bool use_vapic; /* Enable device to use vapic mode */
146 * general struct to manage commands send to an IOMMU
152 struct kmem_cache *amd_iommu_irq_cache;
154 static void update_domain(struct protection_domain *domain);
155 static int protection_domain_init(struct protection_domain *domain);
156 static void detach_device(struct device *dev);
159 * Data container for a dma_ops specific protection domain
161 struct dma_ops_domain {
162 /* generic protection domain information */
163 struct protection_domain domain;
166 struct iova_domain iovad;
169 static struct iova_domain reserved_iova_ranges;
170 static struct lock_class_key reserved_rbtree_key;
172 /****************************************************************************
176 ****************************************************************************/
178 static inline int match_hid_uid(struct device *dev,
179 struct acpihid_map_entry *entry)
181 const char *hid, *uid;
183 hid = acpi_device_hid(ACPI_COMPANION(dev));
184 uid = acpi_device_uid(ACPI_COMPANION(dev));
190 return strcmp(hid, entry->hid);
193 return strcmp(hid, entry->hid);
195 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
198 static inline u16 get_pci_device_id(struct device *dev)
200 struct pci_dev *pdev = to_pci_dev(dev);
202 return PCI_DEVID(pdev->bus->number, pdev->devfn);
205 static inline int get_acpihid_device_id(struct device *dev,
206 struct acpihid_map_entry **entry)
208 struct acpihid_map_entry *p;
210 list_for_each_entry(p, &acpihid_map, list) {
211 if (!match_hid_uid(dev, p)) {
220 static inline int get_device_id(struct device *dev)
225 devid = get_pci_device_id(dev);
227 devid = get_acpihid_device_id(dev, NULL);
232 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
234 return container_of(dom, struct protection_domain, domain);
237 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
239 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
240 return container_of(domain, struct dma_ops_domain, domain);
243 static struct iommu_dev_data *alloc_dev_data(u16 devid)
245 struct iommu_dev_data *dev_data;
248 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
252 dev_data->devid = devid;
254 spin_lock_irqsave(&dev_data_list_lock, flags);
255 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
256 spin_unlock_irqrestore(&dev_data_list_lock, flags);
261 static struct iommu_dev_data *search_dev_data(u16 devid)
263 struct iommu_dev_data *dev_data;
266 spin_lock_irqsave(&dev_data_list_lock, flags);
267 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
268 if (dev_data->devid == devid)
275 spin_unlock_irqrestore(&dev_data_list_lock, flags);
280 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
282 *(u16 *)data = alias;
286 static u16 get_alias(struct device *dev)
288 struct pci_dev *pdev = to_pci_dev(dev);
289 u16 devid, ivrs_alias, pci_alias;
291 /* The callers make sure that get_device_id() does not fail here */
292 devid = get_device_id(dev);
293 ivrs_alias = amd_iommu_alias_table[devid];
294 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
296 if (ivrs_alias == pci_alias)
302 * The IVRS is fairly reliable in telling us about aliases, but it
303 * can't know about every screwy device. If we don't have an IVRS
304 * reported alias, use the PCI reported alias. In that case we may
305 * still need to initialize the rlookup and dev_table entries if the
306 * alias is to a non-existent device.
308 if (ivrs_alias == devid) {
309 if (!amd_iommu_rlookup_table[pci_alias]) {
310 amd_iommu_rlookup_table[pci_alias] =
311 amd_iommu_rlookup_table[devid];
312 memcpy(amd_iommu_dev_table[pci_alias].data,
313 amd_iommu_dev_table[devid].data,
314 sizeof(amd_iommu_dev_table[pci_alias].data));
320 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
321 "for device %s[%04x:%04x], kernel reported alias "
322 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
323 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
324 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
325 PCI_FUNC(pci_alias));
328 * If we don't have a PCI DMA alias and the IVRS alias is on the same
329 * bus, then the IVRS table may know about a quirk that we don't.
331 if (pci_alias == devid &&
332 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
333 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
334 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
335 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
342 static struct iommu_dev_data *find_dev_data(u16 devid)
344 struct iommu_dev_data *dev_data;
346 dev_data = search_dev_data(devid);
348 if (dev_data == NULL)
349 dev_data = alloc_dev_data(devid);
354 static struct iommu_dev_data *get_dev_data(struct device *dev)
356 return dev->archdata.iommu;
360 * Find or create an IOMMU group for a acpihid device.
362 static struct iommu_group *acpihid_device_group(struct device *dev)
364 struct acpihid_map_entry *p, *entry = NULL;
367 devid = get_acpihid_device_id(dev, &entry);
369 return ERR_PTR(devid);
371 list_for_each_entry(p, &acpihid_map, list) {
372 if ((devid == p->devid) && p->group)
373 entry->group = p->group;
377 entry->group = generic_device_group(dev);
379 iommu_group_ref_get(entry->group);
384 static bool pci_iommuv2_capable(struct pci_dev *pdev)
386 static const int caps[] = {
389 PCI_EXT_CAP_ID_PASID,
393 for (i = 0; i < 3; ++i) {
394 pos = pci_find_ext_capability(pdev, caps[i]);
402 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
404 struct iommu_dev_data *dev_data;
406 dev_data = get_dev_data(&pdev->dev);
408 return dev_data->errata & (1 << erratum) ? true : false;
412 * This function checks if the driver got a valid device from the caller to
413 * avoid dereferencing invalid pointers.
415 static bool check_device(struct device *dev)
419 if (!dev || !dev->dma_mask)
422 devid = get_device_id(dev);
426 /* Out of our scope? */
427 if (devid > amd_iommu_last_bdf)
430 if (amd_iommu_rlookup_table[devid] == NULL)
436 static void init_iommu_group(struct device *dev)
438 struct iommu_group *group;
440 group = iommu_group_get_for_dev(dev);
444 iommu_group_put(group);
447 static int iommu_init_device(struct device *dev)
449 struct iommu_dev_data *dev_data;
450 struct amd_iommu *iommu;
453 if (dev->archdata.iommu)
456 devid = get_device_id(dev);
460 iommu = amd_iommu_rlookup_table[devid];
462 dev_data = find_dev_data(devid);
466 dev_data->alias = get_alias(dev);
468 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
469 struct amd_iommu *iommu;
471 iommu = amd_iommu_rlookup_table[dev_data->devid];
472 dev_data->iommu_v2 = iommu->is_iommu_v2;
475 dev->archdata.iommu = dev_data;
477 iommu_device_link(&iommu->iommu, dev);
482 static void iommu_ignore_device(struct device *dev)
487 devid = get_device_id(dev);
491 alias = get_alias(dev);
493 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
494 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
496 amd_iommu_rlookup_table[devid] = NULL;
497 amd_iommu_rlookup_table[alias] = NULL;
500 static void iommu_uninit_device(struct device *dev)
502 struct iommu_dev_data *dev_data;
503 struct amd_iommu *iommu;
506 devid = get_device_id(dev);
510 iommu = amd_iommu_rlookup_table[devid];
512 dev_data = search_dev_data(devid);
516 if (dev_data->domain)
519 iommu_device_unlink(&iommu->iommu, dev);
521 iommu_group_remove_device(dev);
527 * We keep dev_data around for unplugged devices and reuse it when the
528 * device is re-plugged - not doing so would introduce a ton of races.
532 /****************************************************************************
534 * Interrupt handling functions
536 ****************************************************************************/
538 static void dump_dte_entry(u16 devid)
542 for (i = 0; i < 4; ++i)
543 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
544 amd_iommu_dev_table[devid].data[i]);
547 static void dump_command(unsigned long phys_addr)
549 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
552 for (i = 0; i < 4; ++i)
553 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
556 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
558 int type, devid, domid, flags;
559 volatile u32 *event = __evt;
564 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
565 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
566 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
567 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
568 address = (u64)(((u64)event[3]) << 32) | event[2];
571 /* Did we hit the erratum? */
572 if (++count == LOOP_TIMEOUT) {
573 pr_err("AMD-Vi: No event written to event log\n");
580 printk(KERN_ERR "AMD-Vi: Event logged [");
583 case EVENT_TYPE_ILL_DEV:
584 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
585 "address=0x%016llx flags=0x%04x]\n",
586 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
588 dump_dte_entry(devid);
590 case EVENT_TYPE_IO_FAULT:
591 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
592 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
593 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
594 domid, address, flags);
596 case EVENT_TYPE_DEV_TAB_ERR:
597 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
598 "address=0x%016llx flags=0x%04x]\n",
599 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
602 case EVENT_TYPE_PAGE_TAB_ERR:
603 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
604 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
605 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
606 domid, address, flags);
608 case EVENT_TYPE_ILL_CMD:
609 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
610 dump_command(address);
612 case EVENT_TYPE_CMD_HARD_ERR:
613 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
614 "flags=0x%04x]\n", address, flags);
616 case EVENT_TYPE_IOTLB_INV_TO:
617 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
618 "address=0x%016llx]\n",
619 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
622 case EVENT_TYPE_INV_DEV_REQ:
623 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
624 "address=0x%016llx flags=0x%04x]\n",
625 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
629 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
632 memset(__evt, 0, 4 * sizeof(u32));
635 static void iommu_poll_events(struct amd_iommu *iommu)
639 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
640 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
642 while (head != tail) {
643 iommu_print_event(iommu, iommu->evt_buf + head);
644 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
647 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
650 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
652 struct amd_iommu_fault fault;
654 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
655 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
659 fault.address = raw[1];
660 fault.pasid = PPR_PASID(raw[0]);
661 fault.device_id = PPR_DEVID(raw[0]);
662 fault.tag = PPR_TAG(raw[0]);
663 fault.flags = PPR_FLAGS(raw[0]);
665 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
668 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
672 if (iommu->ppr_log == NULL)
675 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
676 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
678 while (head != tail) {
683 raw = (u64 *)(iommu->ppr_log + head);
686 * Hardware bug: Interrupt may arrive before the entry is
687 * written to memory. If this happens we need to wait for the
690 for (i = 0; i < LOOP_TIMEOUT; ++i) {
691 if (PPR_REQ_TYPE(raw[0]) != 0)
696 /* Avoid memcpy function-call overhead */
701 * To detect the hardware bug we need to clear the entry
704 raw[0] = raw[1] = 0UL;
706 /* Update head pointer of hardware ring-buffer */
707 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
708 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
710 /* Handle PPR entry */
711 iommu_handle_ppr_entry(iommu, entry);
713 /* Refresh ring-buffer information */
714 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
715 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
719 #ifdef CONFIG_IRQ_REMAP
720 static int (*iommu_ga_log_notifier)(u32);
722 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
724 iommu_ga_log_notifier = notifier;
728 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
730 static void iommu_poll_ga_log(struct amd_iommu *iommu)
732 u32 head, tail, cnt = 0;
734 if (iommu->ga_log == NULL)
737 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
738 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
740 while (head != tail) {
744 raw = (u64 *)(iommu->ga_log + head);
747 /* Avoid memcpy function-call overhead */
750 /* Update head pointer of hardware ring-buffer */
751 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
752 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
754 /* Handle GA entry */
755 switch (GA_REQ_TYPE(log_entry)) {
757 if (!iommu_ga_log_notifier)
760 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
761 __func__, GA_DEVID(log_entry),
764 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
765 pr_err("AMD-Vi: GA log notifier failed.\n");
772 #endif /* CONFIG_IRQ_REMAP */
774 #define AMD_IOMMU_INT_MASK \
775 (MMIO_STATUS_EVT_INT_MASK | \
776 MMIO_STATUS_PPR_INT_MASK | \
777 MMIO_STATUS_GALOG_INT_MASK)
779 irqreturn_t amd_iommu_int_thread(int irq, void *data)
781 struct amd_iommu *iommu = (struct amd_iommu *) data;
782 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
784 while (status & AMD_IOMMU_INT_MASK) {
785 /* Enable EVT and PPR and GA interrupts again */
786 writel(AMD_IOMMU_INT_MASK,
787 iommu->mmio_base + MMIO_STATUS_OFFSET);
789 if (status & MMIO_STATUS_EVT_INT_MASK) {
790 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
791 iommu_poll_events(iommu);
794 if (status & MMIO_STATUS_PPR_INT_MASK) {
795 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
796 iommu_poll_ppr_log(iommu);
799 #ifdef CONFIG_IRQ_REMAP
800 if (status & MMIO_STATUS_GALOG_INT_MASK) {
801 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
802 iommu_poll_ga_log(iommu);
807 * Hardware bug: ERBT1312
808 * When re-enabling interrupt (by writing 1
809 * to clear the bit), the hardware might also try to set
810 * the interrupt bit in the event status register.
811 * In this scenario, the bit will be set, and disable
812 * subsequent interrupts.
814 * Workaround: The IOMMU driver should read back the
815 * status register and check if the interrupt bits are cleared.
816 * If not, driver will need to go through the interrupt handler
817 * again and re-clear the bits
819 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
824 irqreturn_t amd_iommu_int_handler(int irq, void *data)
826 return IRQ_WAKE_THREAD;
829 /****************************************************************************
831 * IOMMU command queuing functions
833 ****************************************************************************/
835 static int wait_on_sem(volatile u64 *sem)
839 while (*sem == 0 && i < LOOP_TIMEOUT) {
844 if (i == LOOP_TIMEOUT) {
845 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
852 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
853 struct iommu_cmd *cmd,
858 target = iommu->cmd_buf + tail;
859 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
861 /* Copy command to buffer */
862 memcpy(target, cmd, sizeof(*cmd));
864 /* Tell the IOMMU about it */
865 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
868 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
870 WARN_ON(address & 0x7ULL);
872 memset(cmd, 0, sizeof(*cmd));
873 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
874 cmd->data[1] = upper_32_bits(__pa(address));
876 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
879 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
881 memset(cmd, 0, sizeof(*cmd));
882 cmd->data[0] = devid;
883 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
886 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
887 size_t size, u16 domid, int pde)
892 pages = iommu_num_pages(address, size, PAGE_SIZE);
897 * If we have to flush more than one page, flush all
898 * TLB entries for this domain
900 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
904 address &= PAGE_MASK;
906 memset(cmd, 0, sizeof(*cmd));
907 cmd->data[1] |= domid;
908 cmd->data[2] = lower_32_bits(address);
909 cmd->data[3] = upper_32_bits(address);
910 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
911 if (s) /* size bit - we flush more than one 4kb page */
912 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
913 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
914 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
917 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
918 u64 address, size_t size)
923 pages = iommu_num_pages(address, size, PAGE_SIZE);
928 * If we have to flush more than one page, flush all
929 * TLB entries for this domain
931 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
935 address &= PAGE_MASK;
937 memset(cmd, 0, sizeof(*cmd));
938 cmd->data[0] = devid;
939 cmd->data[0] |= (qdep & 0xff) << 24;
940 cmd->data[1] = devid;
941 cmd->data[2] = lower_32_bits(address);
942 cmd->data[3] = upper_32_bits(address);
943 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
945 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
948 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
949 u64 address, bool size)
951 memset(cmd, 0, sizeof(*cmd));
953 address &= ~(0xfffULL);
955 cmd->data[0] = pasid;
956 cmd->data[1] = domid;
957 cmd->data[2] = lower_32_bits(address);
958 cmd->data[3] = upper_32_bits(address);
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
960 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
962 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
963 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
966 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
967 int qdep, u64 address, bool size)
969 memset(cmd, 0, sizeof(*cmd));
971 address &= ~(0xfffULL);
973 cmd->data[0] = devid;
974 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
975 cmd->data[0] |= (qdep & 0xff) << 24;
976 cmd->data[1] = devid;
977 cmd->data[1] |= (pasid & 0xff) << 16;
978 cmd->data[2] = lower_32_bits(address);
979 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
980 cmd->data[3] = upper_32_bits(address);
982 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
983 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
986 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
987 int status, int tag, bool gn)
989 memset(cmd, 0, sizeof(*cmd));
991 cmd->data[0] = devid;
993 cmd->data[1] = pasid;
994 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
996 cmd->data[3] = tag & 0x1ff;
997 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
999 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1002 static void build_inv_all(struct iommu_cmd *cmd)
1004 memset(cmd, 0, sizeof(*cmd));
1005 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1008 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1010 memset(cmd, 0, sizeof(*cmd));
1011 cmd->data[0] = devid;
1012 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1016 * Writes the command to the IOMMUs command buffer and informs the
1017 * hardware about the new command.
1019 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1020 struct iommu_cmd *cmd,
1023 u32 left, tail, head, next_tail;
1027 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1028 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1029 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1030 left = (head - next_tail) % CMD_BUFFER_SIZE;
1033 struct iommu_cmd sync_cmd;
1038 build_completion_wait(&sync_cmd, (u64)&iommu->cmd_sem);
1039 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1041 if ((ret = wait_on_sem(&iommu->cmd_sem)) != 0)
1047 copy_cmd_to_buffer(iommu, cmd, tail);
1049 /* We need to sync now to make sure all commands are processed */
1050 iommu->need_sync = sync;
1055 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1056 struct iommu_cmd *cmd,
1059 unsigned long flags;
1062 spin_lock_irqsave(&iommu->lock, flags);
1063 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1064 spin_unlock_irqrestore(&iommu->lock, flags);
1069 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1071 return iommu_queue_command_sync(iommu, cmd, true);
1075 * This function queues a completion wait command into the command
1076 * buffer of an IOMMU
1078 static int iommu_completion_wait(struct amd_iommu *iommu)
1080 struct iommu_cmd cmd;
1081 unsigned long flags;
1084 if (!iommu->need_sync)
1088 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1090 spin_lock_irqsave(&iommu->lock, flags);
1094 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1098 ret = wait_on_sem(&iommu->cmd_sem);
1101 spin_unlock_irqrestore(&iommu->lock, flags);
1106 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1108 struct iommu_cmd cmd;
1110 build_inv_dte(&cmd, devid);
1112 return iommu_queue_command(iommu, &cmd);
1115 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1119 for (devid = 0; devid <= 0xffff; ++devid)
1120 iommu_flush_dte(iommu, devid);
1122 iommu_completion_wait(iommu);
1126 * This function uses heavy locking and may disable irqs for some time. But
1127 * this is no issue because it is only called during resume.
1129 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1133 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1134 struct iommu_cmd cmd;
1135 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1137 iommu_queue_command(iommu, &cmd);
1140 iommu_completion_wait(iommu);
1143 static void iommu_flush_all(struct amd_iommu *iommu)
1145 struct iommu_cmd cmd;
1147 build_inv_all(&cmd);
1149 iommu_queue_command(iommu, &cmd);
1150 iommu_completion_wait(iommu);
1153 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1155 struct iommu_cmd cmd;
1157 build_inv_irt(&cmd, devid);
1159 iommu_queue_command(iommu, &cmd);
1162 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1166 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1167 iommu_flush_irt(iommu, devid);
1169 iommu_completion_wait(iommu);
1172 void iommu_flush_all_caches(struct amd_iommu *iommu)
1174 if (iommu_feature(iommu, FEATURE_IA)) {
1175 iommu_flush_all(iommu);
1177 iommu_flush_dte_all(iommu);
1178 iommu_flush_irt_all(iommu);
1179 iommu_flush_tlb_all(iommu);
1184 * Command send function for flushing on-device TLB
1186 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1187 u64 address, size_t size)
1189 struct amd_iommu *iommu;
1190 struct iommu_cmd cmd;
1193 qdep = dev_data->ats.qdep;
1194 iommu = amd_iommu_rlookup_table[dev_data->devid];
1196 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1198 return iommu_queue_command(iommu, &cmd);
1202 * Command send function for invalidating a device table entry
1204 static int device_flush_dte(struct iommu_dev_data *dev_data)
1206 struct amd_iommu *iommu;
1210 iommu = amd_iommu_rlookup_table[dev_data->devid];
1211 alias = dev_data->alias;
1213 ret = iommu_flush_dte(iommu, dev_data->devid);
1214 if (!ret && alias != dev_data->devid)
1215 ret = iommu_flush_dte(iommu, alias);
1219 if (dev_data->ats.enabled)
1220 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1226 * TLB invalidation function which is called from the mapping functions.
1227 * It invalidates a single PTE if the range to flush is within a single
1228 * page. Otherwise it flushes the whole TLB of the IOMMU.
1230 static void __domain_flush_pages(struct protection_domain *domain,
1231 u64 address, size_t size, int pde)
1233 struct iommu_dev_data *dev_data;
1234 struct iommu_cmd cmd;
1237 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1239 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1240 if (!domain->dev_iommu[i])
1244 * Devices of this domain are behind this IOMMU
1245 * We need a TLB flush
1247 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1250 list_for_each_entry(dev_data, &domain->dev_list, list) {
1252 if (!dev_data->ats.enabled)
1255 ret |= device_flush_iotlb(dev_data, address, size);
1261 static void domain_flush_pages(struct protection_domain *domain,
1262 u64 address, size_t size)
1264 __domain_flush_pages(domain, address, size, 0);
1267 /* Flush the whole IO/TLB for a given protection domain */
1268 static void domain_flush_tlb(struct protection_domain *domain)
1270 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1273 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1274 static void domain_flush_tlb_pde(struct protection_domain *domain)
1276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1279 static void domain_flush_complete(struct protection_domain *domain)
1283 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1284 if (domain && !domain->dev_iommu[i])
1288 * Devices of this domain are behind this IOMMU
1289 * We need to wait for completion of all commands.
1291 iommu_completion_wait(amd_iommus[i]);
1297 * This function flushes the DTEs for all devices in domain
1299 static void domain_flush_devices(struct protection_domain *domain)
1301 struct iommu_dev_data *dev_data;
1303 list_for_each_entry(dev_data, &domain->dev_list, list)
1304 device_flush_dte(dev_data);
1307 /****************************************************************************
1309 * The functions below are used the create the page table mappings for
1310 * unity mapped regions.
1312 ****************************************************************************/
1315 * This function is used to add another level to an IO page table. Adding
1316 * another level increases the size of the address space by 9 bits to a size up
1319 static bool increase_address_space(struct protection_domain *domain,
1324 if (domain->mode == PAGE_MODE_6_LEVEL)
1325 /* address space already 64 bit large */
1328 pte = (void *)get_zeroed_page(gfp);
1332 *pte = PM_LEVEL_PDE(domain->mode,
1333 virt_to_phys(domain->pt_root));
1334 domain->pt_root = pte;
1336 domain->updated = true;
1341 static u64 *alloc_pte(struct protection_domain *domain,
1342 unsigned long address,
1343 unsigned long page_size,
1350 BUG_ON(!is_power_of_2(page_size));
1352 while (address > PM_LEVEL_SIZE(domain->mode))
1353 increase_address_space(domain, gfp);
1355 level = domain->mode - 1;
1356 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1357 address = PAGE_SIZE_ALIGN(address, page_size);
1358 end_lvl = PAGE_SIZE_LEVEL(page_size);
1360 while (level > end_lvl) {
1365 if (!IOMMU_PTE_PRESENT(__pte)) {
1366 page = (u64 *)get_zeroed_page(gfp);
1370 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1372 /* pte could have been changed somewhere. */
1373 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1374 free_page((unsigned long)page);
1379 /* No level skipping support yet */
1380 if (PM_PTE_LEVEL(*pte) != level)
1385 pte = IOMMU_PTE_PAGE(*pte);
1387 if (pte_page && level == end_lvl)
1390 pte = &pte[PM_LEVEL_INDEX(level, address)];
1397 * This function checks if there is a PTE for a given dma address. If
1398 * there is one, it returns the pointer to it.
1400 static u64 *fetch_pte(struct protection_domain *domain,
1401 unsigned long address,
1402 unsigned long *page_size)
1407 if (address > PM_LEVEL_SIZE(domain->mode))
1410 level = domain->mode - 1;
1411 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1412 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1417 if (!IOMMU_PTE_PRESENT(*pte))
1421 if (PM_PTE_LEVEL(*pte) == 7 ||
1422 PM_PTE_LEVEL(*pte) == 0)
1425 /* No level skipping support yet */
1426 if (PM_PTE_LEVEL(*pte) != level)
1431 /* Walk to the next level */
1432 pte = IOMMU_PTE_PAGE(*pte);
1433 pte = &pte[PM_LEVEL_INDEX(level, address)];
1434 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1437 if (PM_PTE_LEVEL(*pte) == 0x07) {
1438 unsigned long pte_mask;
1441 * If we have a series of large PTEs, make
1442 * sure to return a pointer to the first one.
1444 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1445 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1446 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1453 * Generic mapping functions. It maps a physical address into a DMA
1454 * address space. It allocates the page table pages if necessary.
1455 * In the future it can be extended to a generic mapping function
1456 * supporting all features of AMD IOMMU page tables like level skipping
1457 * and full 64 bit address spaces.
1459 static int iommu_map_page(struct protection_domain *dom,
1460 unsigned long bus_addr,
1461 unsigned long phys_addr,
1462 unsigned long page_size,
1469 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1470 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1472 if (!(prot & IOMMU_PROT_MASK))
1475 count = PAGE_SIZE_PTE_COUNT(page_size);
1476 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1481 for (i = 0; i < count; ++i)
1482 if (IOMMU_PTE_PRESENT(pte[i]))
1486 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1487 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1489 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1491 if (prot & IOMMU_PROT_IR)
1492 __pte |= IOMMU_PTE_IR;
1493 if (prot & IOMMU_PROT_IW)
1494 __pte |= IOMMU_PTE_IW;
1496 for (i = 0; i < count; ++i)
1504 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1505 unsigned long bus_addr,
1506 unsigned long page_size)
1508 unsigned long long unmapped;
1509 unsigned long unmap_size;
1512 BUG_ON(!is_power_of_2(page_size));
1516 while (unmapped < page_size) {
1518 pte = fetch_pte(dom, bus_addr, &unmap_size);
1523 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1524 for (i = 0; i < count; i++)
1528 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1529 unmapped += unmap_size;
1532 BUG_ON(unmapped && !is_power_of_2(unmapped));
1537 /****************************************************************************
1539 * The next functions belong to the address allocator for the dma_ops
1540 * interface functions.
1542 ****************************************************************************/
1545 static unsigned long dma_ops_alloc_iova(struct device *dev,
1546 struct dma_ops_domain *dma_dom,
1547 unsigned int pages, u64 dma_mask)
1549 unsigned long pfn = 0;
1551 pages = __roundup_pow_of_two(pages);
1553 if (dma_mask > DMA_BIT_MASK(32))
1554 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1555 IOVA_PFN(DMA_BIT_MASK(32)));
1558 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1560 return (pfn << PAGE_SHIFT);
1563 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1564 unsigned long address,
1567 pages = __roundup_pow_of_two(pages);
1568 address >>= PAGE_SHIFT;
1570 free_iova_fast(&dma_dom->iovad, address, pages);
1573 /****************************************************************************
1575 * The next functions belong to the domain allocation. A domain is
1576 * allocated for every IOMMU as the default domain. If device isolation
1577 * is enabled, every device get its own domain. The most important thing
1578 * about domains is the page table mapping the DMA address space they
1581 ****************************************************************************/
1584 * This function adds a protection domain to the global protection domain list
1586 static void add_domain_to_list(struct protection_domain *domain)
1588 unsigned long flags;
1590 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1591 list_add(&domain->list, &amd_iommu_pd_list);
1592 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1596 * This function removes a protection domain to the global
1597 * protection domain list
1599 static void del_domain_from_list(struct protection_domain *domain)
1601 unsigned long flags;
1603 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1604 list_del(&domain->list);
1605 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1608 static u16 domain_id_alloc(void)
1610 unsigned long flags;
1613 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1614 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1616 if (id > 0 && id < MAX_DOMAIN_ID)
1617 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1620 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1625 static void domain_id_free(int id)
1627 unsigned long flags;
1629 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1630 if (id > 0 && id < MAX_DOMAIN_ID)
1631 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1632 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1635 #define DEFINE_FREE_PT_FN(LVL, FN) \
1636 static void free_pt_##LVL (unsigned long __pt) \
1644 for (i = 0; i < 512; ++i) { \
1645 /* PTE present? */ \
1646 if (!IOMMU_PTE_PRESENT(pt[i])) \
1650 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1651 PM_PTE_LEVEL(pt[i]) == 7) \
1654 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1657 free_page((unsigned long)pt); \
1660 DEFINE_FREE_PT_FN(l2, free_page)
1661 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1662 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1663 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1664 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1666 static void free_pagetable(struct protection_domain *domain)
1668 unsigned long root = (unsigned long)domain->pt_root;
1670 switch (domain->mode) {
1671 case PAGE_MODE_NONE:
1673 case PAGE_MODE_1_LEVEL:
1676 case PAGE_MODE_2_LEVEL:
1679 case PAGE_MODE_3_LEVEL:
1682 case PAGE_MODE_4_LEVEL:
1685 case PAGE_MODE_5_LEVEL:
1688 case PAGE_MODE_6_LEVEL:
1696 static void free_gcr3_tbl_level1(u64 *tbl)
1701 for (i = 0; i < 512; ++i) {
1702 if (!(tbl[i] & GCR3_VALID))
1705 ptr = __va(tbl[i] & PAGE_MASK);
1707 free_page((unsigned long)ptr);
1711 static void free_gcr3_tbl_level2(u64 *tbl)
1716 for (i = 0; i < 512; ++i) {
1717 if (!(tbl[i] & GCR3_VALID))
1720 ptr = __va(tbl[i] & PAGE_MASK);
1722 free_gcr3_tbl_level1(ptr);
1726 static void free_gcr3_table(struct protection_domain *domain)
1728 if (domain->glx == 2)
1729 free_gcr3_tbl_level2(domain->gcr3_tbl);
1730 else if (domain->glx == 1)
1731 free_gcr3_tbl_level1(domain->gcr3_tbl);
1733 BUG_ON(domain->glx != 0);
1735 free_page((unsigned long)domain->gcr3_tbl);
1739 * Free a domain, only used if something went wrong in the
1740 * allocation path and we need to free an already allocated page table
1742 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1747 del_domain_from_list(&dom->domain);
1749 put_iova_domain(&dom->iovad);
1751 free_pagetable(&dom->domain);
1754 domain_id_free(dom->domain.id);
1760 * Allocates a new protection domain usable for the dma_ops functions.
1761 * It also initializes the page table and the address allocator data
1762 * structures required for the dma_ops interface
1764 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1766 struct dma_ops_domain *dma_dom;
1768 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1772 if (protection_domain_init(&dma_dom->domain))
1775 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1776 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1777 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1778 if (!dma_dom->domain.pt_root)
1781 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1782 IOVA_START_PFN, DMA_32BIT_PFN);
1784 /* Initialize reserved ranges */
1785 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1787 add_domain_to_list(&dma_dom->domain);
1792 dma_ops_domain_free(dma_dom);
1798 * little helper function to check whether a given protection domain is a
1801 static bool dma_ops_domain(struct protection_domain *domain)
1803 return domain->flags & PD_DMA_OPS_MASK;
1806 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1811 if (domain->mode != PAGE_MODE_NONE)
1812 pte_root = virt_to_phys(domain->pt_root);
1814 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1815 << DEV_ENTRY_MODE_SHIFT;
1816 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1818 flags = amd_iommu_dev_table[devid].data[1];
1821 flags |= DTE_FLAG_IOTLB;
1823 if (domain->flags & PD_IOMMUV2_MASK) {
1824 u64 gcr3 = __pa(domain->gcr3_tbl);
1825 u64 glx = domain->glx;
1828 pte_root |= DTE_FLAG_GV;
1829 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1831 /* First mask out possible old values for GCR3 table */
1832 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1835 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1838 /* Encode GCR3 table into DTE */
1839 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1842 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1845 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1849 flags &= ~(0xffffUL);
1850 flags |= domain->id;
1852 amd_iommu_dev_table[devid].data[1] = flags;
1853 amd_iommu_dev_table[devid].data[0] = pte_root;
1856 static void clear_dte_entry(u16 devid)
1858 /* remove entry from the device table seen by the hardware */
1859 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1860 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1862 amd_iommu_apply_erratum_63(devid);
1865 static void do_attach(struct iommu_dev_data *dev_data,
1866 struct protection_domain *domain)
1868 struct amd_iommu *iommu;
1872 iommu = amd_iommu_rlookup_table[dev_data->devid];
1873 alias = dev_data->alias;
1874 ats = dev_data->ats.enabled;
1876 /* Update data structures */
1877 dev_data->domain = domain;
1878 list_add(&dev_data->list, &domain->dev_list);
1880 /* Do reference counting */
1881 domain->dev_iommu[iommu->index] += 1;
1882 domain->dev_cnt += 1;
1884 /* Update device table */
1885 set_dte_entry(dev_data->devid, domain, ats);
1886 if (alias != dev_data->devid)
1887 set_dte_entry(alias, domain, ats);
1889 device_flush_dte(dev_data);
1892 static void do_detach(struct iommu_dev_data *dev_data)
1894 struct amd_iommu *iommu;
1898 * First check if the device is still attached. It might already
1899 * be detached from its domain because the generic
1900 * iommu_detach_group code detached it and we try again here in
1901 * our alias handling.
1903 if (!dev_data->domain)
1906 iommu = amd_iommu_rlookup_table[dev_data->devid];
1907 alias = dev_data->alias;
1909 /* decrease reference counters */
1910 dev_data->domain->dev_iommu[iommu->index] -= 1;
1911 dev_data->domain->dev_cnt -= 1;
1913 /* Update data structures */
1914 dev_data->domain = NULL;
1915 list_del(&dev_data->list);
1916 clear_dte_entry(dev_data->devid);
1917 if (alias != dev_data->devid)
1918 clear_dte_entry(alias);
1920 /* Flush the DTE entry */
1921 device_flush_dte(dev_data);
1925 * If a device is not yet associated with a domain, this function does
1926 * assigns it visible for the hardware
1928 static int __attach_device(struct iommu_dev_data *dev_data,
1929 struct protection_domain *domain)
1934 * Must be called with IRQs disabled. Warn here to detect early
1937 WARN_ON(!irqs_disabled());
1940 spin_lock(&domain->lock);
1943 if (dev_data->domain != NULL)
1946 /* Attach alias group root */
1947 do_attach(dev_data, domain);
1954 spin_unlock(&domain->lock);
1960 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1962 pci_disable_ats(pdev);
1963 pci_disable_pri(pdev);
1964 pci_disable_pasid(pdev);
1967 /* FIXME: Change generic reset-function to do the same */
1968 static int pri_reset_while_enabled(struct pci_dev *pdev)
1973 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1977 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1978 control |= PCI_PRI_CTRL_RESET;
1979 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1984 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1989 /* FIXME: Hardcode number of outstanding requests for now */
1991 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1993 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1995 /* Only allow access to user-accessible pages */
1996 ret = pci_enable_pasid(pdev, 0);
2000 /* First reset the PRI state of the device */
2001 ret = pci_reset_pri(pdev);
2006 ret = pci_enable_pri(pdev, reqs);
2011 ret = pri_reset_while_enabled(pdev);
2016 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2023 pci_disable_pri(pdev);
2024 pci_disable_pasid(pdev);
2029 /* FIXME: Move this to PCI code */
2030 #define PCI_PRI_TLP_OFF (1 << 15)
2032 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2037 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2041 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2043 return (status & PCI_PRI_TLP_OFF) ? true : false;
2047 * If a device is not yet associated with a domain, this function
2048 * assigns it visible for the hardware
2050 static int attach_device(struct device *dev,
2051 struct protection_domain *domain)
2053 struct pci_dev *pdev;
2054 struct iommu_dev_data *dev_data;
2055 unsigned long flags;
2058 dev_data = get_dev_data(dev);
2060 if (!dev_is_pci(dev))
2061 goto skip_ats_check;
2063 pdev = to_pci_dev(dev);
2064 if (domain->flags & PD_IOMMUV2_MASK) {
2065 if (!dev_data->passthrough)
2068 if (dev_data->iommu_v2) {
2069 if (pdev_iommuv2_enable(pdev) != 0)
2072 dev_data->ats.enabled = true;
2073 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2074 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2076 } else if (amd_iommu_iotlb_sup &&
2077 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2078 dev_data->ats.enabled = true;
2079 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2083 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2084 ret = __attach_device(dev_data, domain);
2085 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2088 * We might boot into a crash-kernel here. The crashed kernel
2089 * left the caches in the IOMMU dirty. So we have to flush
2090 * here to evict all dirty stuff.
2092 domain_flush_tlb_pde(domain);
2098 * Removes a device from a protection domain (unlocked)
2100 static void __detach_device(struct iommu_dev_data *dev_data)
2102 struct protection_domain *domain;
2105 * Must be called with IRQs disabled. Warn here to detect early
2108 WARN_ON(!irqs_disabled());
2110 if (WARN_ON(!dev_data->domain))
2113 domain = dev_data->domain;
2115 spin_lock(&domain->lock);
2117 do_detach(dev_data);
2119 spin_unlock(&domain->lock);
2123 * Removes a device from a protection domain (with devtable_lock held)
2125 static void detach_device(struct device *dev)
2127 struct protection_domain *domain;
2128 struct iommu_dev_data *dev_data;
2129 unsigned long flags;
2131 dev_data = get_dev_data(dev);
2132 domain = dev_data->domain;
2134 /* lock device table */
2135 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2136 __detach_device(dev_data);
2137 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2139 if (!dev_is_pci(dev))
2142 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2143 pdev_iommuv2_disable(to_pci_dev(dev));
2144 else if (dev_data->ats.enabled)
2145 pci_disable_ats(to_pci_dev(dev));
2147 dev_data->ats.enabled = false;
2150 static int amd_iommu_add_device(struct device *dev)
2152 struct iommu_dev_data *dev_data;
2153 struct iommu_domain *domain;
2154 struct amd_iommu *iommu;
2157 if (!check_device(dev) || get_dev_data(dev))
2160 devid = get_device_id(dev);
2164 iommu = amd_iommu_rlookup_table[devid];
2166 ret = iommu_init_device(dev);
2168 if (ret != -ENOTSUPP)
2169 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2172 iommu_ignore_device(dev);
2173 dev->dma_ops = &nommu_dma_ops;
2176 init_iommu_group(dev);
2178 dev_data = get_dev_data(dev);
2182 if (iommu_pass_through || dev_data->iommu_v2)
2183 iommu_request_dm_for_dev(dev);
2185 /* Domains are initialized for this device - have a look what we ended up with */
2186 domain = iommu_get_domain_for_dev(dev);
2187 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2188 dev_data->passthrough = true;
2190 dev->dma_ops = &amd_iommu_dma_ops;
2193 iommu_completion_wait(iommu);
2198 static void amd_iommu_remove_device(struct device *dev)
2200 struct amd_iommu *iommu;
2203 if (!check_device(dev))
2206 devid = get_device_id(dev);
2210 iommu = amd_iommu_rlookup_table[devid];
2212 iommu_uninit_device(dev);
2213 iommu_completion_wait(iommu);
2216 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2218 if (dev_is_pci(dev))
2219 return pci_device_group(dev);
2221 return acpihid_device_group(dev);
2224 /*****************************************************************************
2226 * The next functions belong to the dma_ops mapping/unmapping code.
2228 *****************************************************************************/
2230 static void __queue_flush(struct flush_queue *queue)
2232 struct protection_domain *domain;
2233 unsigned long flags;
2236 /* First flush TLB of all known domains */
2237 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
2238 list_for_each_entry(domain, &amd_iommu_pd_list, list)
2239 domain_flush_tlb(domain);
2240 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
2242 /* Wait until flushes have completed */
2243 domain_flush_complete(NULL);
2245 for (idx = 0; idx < queue->next; ++idx) {
2246 struct flush_queue_entry *entry;
2248 entry = queue->entries + idx;
2250 free_iova_fast(&entry->dma_dom->iovad,
2254 /* Not really necessary, just to make sure we catch any bugs */
2255 entry->dma_dom = NULL;
2261 static void queue_flush_all(void)
2265 for_each_possible_cpu(cpu) {
2266 struct flush_queue *queue;
2267 unsigned long flags;
2269 queue = per_cpu_ptr(&flush_queue, cpu);
2270 spin_lock_irqsave(&queue->lock, flags);
2271 if (queue->next > 0)
2272 __queue_flush(queue);
2273 spin_unlock_irqrestore(&queue->lock, flags);
2277 static void queue_flush_timeout(unsigned long unsused)
2279 atomic_set(&queue_timer_on, 0);
2283 static void queue_add(struct dma_ops_domain *dma_dom,
2284 unsigned long address, unsigned long pages)
2286 struct flush_queue_entry *entry;
2287 struct flush_queue *queue;
2288 unsigned long flags;
2291 pages = __roundup_pow_of_two(pages);
2292 address >>= PAGE_SHIFT;
2294 queue = get_cpu_ptr(&flush_queue);
2295 spin_lock_irqsave(&queue->lock, flags);
2297 if (queue->next == FLUSH_QUEUE_SIZE)
2298 __queue_flush(queue);
2300 idx = queue->next++;
2301 entry = queue->entries + idx;
2303 entry->iova_pfn = address;
2304 entry->pages = pages;
2305 entry->dma_dom = dma_dom;
2307 spin_unlock_irqrestore(&queue->lock, flags);
2309 if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0)
2310 mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10));
2312 put_cpu_ptr(&flush_queue);
2317 * In the dma_ops path we only have the struct device. This function
2318 * finds the corresponding IOMMU, the protection domain and the
2319 * requestor id for a given device.
2320 * If the device is not yet associated with a domain this is also done
2323 static struct protection_domain *get_domain(struct device *dev)
2325 struct protection_domain *domain;
2327 if (!check_device(dev))
2328 return ERR_PTR(-EINVAL);
2330 domain = get_dev_data(dev)->domain;
2331 if (!dma_ops_domain(domain))
2332 return ERR_PTR(-EBUSY);
2337 static void update_device_table(struct protection_domain *domain)
2339 struct iommu_dev_data *dev_data;
2341 list_for_each_entry(dev_data, &domain->dev_list, list) {
2342 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2344 if (dev_data->devid == dev_data->alias)
2347 /* There is an alias, update device table entry for it */
2348 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2352 static void update_domain(struct protection_domain *domain)
2354 if (!domain->updated)
2357 update_device_table(domain);
2359 domain_flush_devices(domain);
2360 domain_flush_tlb_pde(domain);
2362 domain->updated = false;
2365 static int dir2prot(enum dma_data_direction direction)
2367 if (direction == DMA_TO_DEVICE)
2368 return IOMMU_PROT_IR;
2369 else if (direction == DMA_FROM_DEVICE)
2370 return IOMMU_PROT_IW;
2371 else if (direction == DMA_BIDIRECTIONAL)
2372 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2377 * This function contains common code for mapping of a physically
2378 * contiguous memory region into DMA address space. It is used by all
2379 * mapping functions provided with this IOMMU driver.
2380 * Must be called with the domain lock held.
2382 static dma_addr_t __map_single(struct device *dev,
2383 struct dma_ops_domain *dma_dom,
2386 enum dma_data_direction direction,
2389 dma_addr_t offset = paddr & ~PAGE_MASK;
2390 dma_addr_t address, start, ret;
2395 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2398 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2399 if (address == AMD_IOMMU_MAPPING_ERROR)
2402 prot = dir2prot(direction);
2405 for (i = 0; i < pages; ++i) {
2406 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2407 PAGE_SIZE, prot, GFP_ATOMIC);
2416 if (unlikely(amd_iommu_np_cache)) {
2417 domain_flush_pages(&dma_dom->domain, address, size);
2418 domain_flush_complete(&dma_dom->domain);
2426 for (--i; i >= 0; --i) {
2428 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2431 domain_flush_tlb(&dma_dom->domain);
2432 domain_flush_complete(&dma_dom->domain);
2434 dma_ops_free_iova(dma_dom, address, pages);
2436 return AMD_IOMMU_MAPPING_ERROR;
2440 * Does the reverse of the __map_single function. Must be called with
2441 * the domain lock held too
2443 static void __unmap_single(struct dma_ops_domain *dma_dom,
2444 dma_addr_t dma_addr,
2448 dma_addr_t flush_addr;
2449 dma_addr_t i, start;
2452 flush_addr = dma_addr;
2453 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2454 dma_addr &= PAGE_MASK;
2457 for (i = 0; i < pages; ++i) {
2458 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2462 if (amd_iommu_unmap_flush) {
2463 dma_ops_free_iova(dma_dom, dma_addr, pages);
2464 domain_flush_tlb(&dma_dom->domain);
2465 domain_flush_complete(&dma_dom->domain);
2467 queue_add(dma_dom, dma_addr, pages);
2472 * The exported map_single function for dma_ops.
2474 static dma_addr_t map_page(struct device *dev, struct page *page,
2475 unsigned long offset, size_t size,
2476 enum dma_data_direction dir,
2477 unsigned long attrs)
2479 phys_addr_t paddr = page_to_phys(page) + offset;
2480 struct protection_domain *domain;
2481 struct dma_ops_domain *dma_dom;
2484 domain = get_domain(dev);
2485 if (PTR_ERR(domain) == -EINVAL)
2486 return (dma_addr_t)paddr;
2487 else if (IS_ERR(domain))
2488 return AMD_IOMMU_MAPPING_ERROR;
2490 dma_mask = *dev->dma_mask;
2491 dma_dom = to_dma_ops_domain(domain);
2493 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2497 * The exported unmap_single function for dma_ops.
2499 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2500 enum dma_data_direction dir, unsigned long attrs)
2502 struct protection_domain *domain;
2503 struct dma_ops_domain *dma_dom;
2505 domain = get_domain(dev);
2509 dma_dom = to_dma_ops_domain(domain);
2511 __unmap_single(dma_dom, dma_addr, size, dir);
2514 static int sg_num_pages(struct device *dev,
2515 struct scatterlist *sglist,
2518 unsigned long mask, boundary_size;
2519 struct scatterlist *s;
2522 mask = dma_get_seg_boundary(dev);
2523 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2524 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2526 for_each_sg(sglist, s, nelems, i) {
2529 s->dma_address = npages << PAGE_SHIFT;
2530 p = npages % boundary_size;
2531 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2532 if (p + n > boundary_size)
2533 npages += boundary_size - p;
2541 * The exported map_sg function for dma_ops (handles scatter-gather
2544 static int map_sg(struct device *dev, struct scatterlist *sglist,
2545 int nelems, enum dma_data_direction direction,
2546 unsigned long attrs)
2548 int mapped_pages = 0, npages = 0, prot = 0, i;
2549 struct protection_domain *domain;
2550 struct dma_ops_domain *dma_dom;
2551 struct scatterlist *s;
2552 unsigned long address;
2555 domain = get_domain(dev);
2559 dma_dom = to_dma_ops_domain(domain);
2560 dma_mask = *dev->dma_mask;
2562 npages = sg_num_pages(dev, sglist, nelems);
2564 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2565 if (address == AMD_IOMMU_MAPPING_ERROR)
2568 prot = dir2prot(direction);
2570 /* Map all sg entries */
2571 for_each_sg(sglist, s, nelems, i) {
2572 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2574 for (j = 0; j < pages; ++j) {
2575 unsigned long bus_addr, phys_addr;
2578 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2579 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2580 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2588 /* Everything is mapped - write the right values into s->dma_address */
2589 for_each_sg(sglist, s, nelems, i) {
2590 s->dma_address += address + s->offset;
2591 s->dma_length = s->length;
2597 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2598 dev_name(dev), npages);
2600 for_each_sg(sglist, s, nelems, i) {
2601 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2603 for (j = 0; j < pages; ++j) {
2604 unsigned long bus_addr;
2606 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2607 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2615 free_iova_fast(&dma_dom->iovad, address, npages);
2622 * The exported map_sg function for dma_ops (handles scatter-gather
2625 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2626 int nelems, enum dma_data_direction dir,
2627 unsigned long attrs)
2629 struct protection_domain *domain;
2630 struct dma_ops_domain *dma_dom;
2631 unsigned long startaddr;
2634 domain = get_domain(dev);
2638 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2639 dma_dom = to_dma_ops_domain(domain);
2640 npages = sg_num_pages(dev, sglist, nelems);
2642 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2646 * The exported alloc_coherent function for dma_ops.
2648 static void *alloc_coherent(struct device *dev, size_t size,
2649 dma_addr_t *dma_addr, gfp_t flag,
2650 unsigned long attrs)
2652 u64 dma_mask = dev->coherent_dma_mask;
2653 struct protection_domain *domain;
2654 struct dma_ops_domain *dma_dom;
2657 domain = get_domain(dev);
2658 if (PTR_ERR(domain) == -EINVAL) {
2659 page = alloc_pages(flag, get_order(size));
2660 *dma_addr = page_to_phys(page);
2661 return page_address(page);
2662 } else if (IS_ERR(domain))
2665 dma_dom = to_dma_ops_domain(domain);
2666 size = PAGE_ALIGN(size);
2667 dma_mask = dev->coherent_dma_mask;
2668 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2671 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2673 if (!gfpflags_allow_blocking(flag))
2676 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2677 get_order(size), flag);
2683 dma_mask = *dev->dma_mask;
2685 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2686 size, DMA_BIDIRECTIONAL, dma_mask);
2688 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2691 return page_address(page);
2695 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2696 __free_pages(page, get_order(size));
2702 * The exported free_coherent function for dma_ops.
2704 static void free_coherent(struct device *dev, size_t size,
2705 void *virt_addr, dma_addr_t dma_addr,
2706 unsigned long attrs)
2708 struct protection_domain *domain;
2709 struct dma_ops_domain *dma_dom;
2712 page = virt_to_page(virt_addr);
2713 size = PAGE_ALIGN(size);
2715 domain = get_domain(dev);
2719 dma_dom = to_dma_ops_domain(domain);
2721 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2724 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2725 __free_pages(page, get_order(size));
2729 * This function is called by the DMA layer to find out if we can handle a
2730 * particular device. It is part of the dma_ops.
2732 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2734 if (!x86_dma_supported(dev, mask))
2736 return check_device(dev);
2739 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2741 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2744 static const struct dma_map_ops amd_iommu_dma_ops = {
2745 .alloc = alloc_coherent,
2746 .free = free_coherent,
2747 .map_page = map_page,
2748 .unmap_page = unmap_page,
2750 .unmap_sg = unmap_sg,
2751 .dma_supported = amd_iommu_dma_supported,
2752 .mapping_error = amd_iommu_mapping_error,
2755 static int init_reserved_iova_ranges(void)
2757 struct pci_dev *pdev = NULL;
2760 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2761 IOVA_START_PFN, DMA_32BIT_PFN);
2763 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2764 &reserved_rbtree_key);
2766 /* MSI memory range */
2767 val = reserve_iova(&reserved_iova_ranges,
2768 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2770 pr_err("Reserving MSI range failed\n");
2774 /* HT memory range */
2775 val = reserve_iova(&reserved_iova_ranges,
2776 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2778 pr_err("Reserving HT range failed\n");
2783 * Memory used for PCI resources
2784 * FIXME: Check whether we can reserve the PCI-hole completly
2786 for_each_pci_dev(pdev) {
2789 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2790 struct resource *r = &pdev->resource[i];
2792 if (!(r->flags & IORESOURCE_MEM))
2795 val = reserve_iova(&reserved_iova_ranges,
2799 pr_err("Reserve pci-resource range failed\n");
2808 int __init amd_iommu_init_api(void)
2810 int ret, cpu, err = 0;
2812 ret = iova_cache_get();
2816 ret = init_reserved_iova_ranges();
2820 for_each_possible_cpu(cpu) {
2821 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2823 queue->entries = kzalloc(FLUSH_QUEUE_SIZE *
2824 sizeof(*queue->entries),
2826 if (!queue->entries)
2829 spin_lock_init(&queue->lock);
2832 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2835 #ifdef CONFIG_ARM_AMBA
2836 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2840 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2846 for_each_possible_cpu(cpu) {
2847 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2849 kfree(queue->entries);
2855 int __init amd_iommu_init_dma_ops(void)
2857 setup_timer(&queue_timer, queue_flush_timeout, 0);
2858 atomic_set(&queue_timer_on, 0);
2860 swiotlb = iommu_pass_through ? 1 : 0;
2864 * In case we don't initialize SWIOTLB (actually the common case
2865 * when AMD IOMMU is enabled), make sure there are global
2866 * dma_ops set as a fall-back for devices not handled by this
2867 * driver (for example non-PCI devices).
2870 dma_ops = &nommu_dma_ops;
2872 if (amd_iommu_unmap_flush)
2873 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2875 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2881 /*****************************************************************************
2883 * The following functions belong to the exported interface of AMD IOMMU
2885 * This interface allows access to lower level functions of the IOMMU
2886 * like protection domain handling and assignement of devices to domains
2887 * which is not possible with the dma_ops interface.
2889 *****************************************************************************/
2891 static void cleanup_domain(struct protection_domain *domain)
2893 struct iommu_dev_data *entry;
2894 unsigned long flags;
2896 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2898 while (!list_empty(&domain->dev_list)) {
2899 entry = list_first_entry(&domain->dev_list,
2900 struct iommu_dev_data, list);
2901 __detach_device(entry);
2904 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2907 static void protection_domain_free(struct protection_domain *domain)
2912 del_domain_from_list(domain);
2915 domain_id_free(domain->id);
2920 static int protection_domain_init(struct protection_domain *domain)
2922 spin_lock_init(&domain->lock);
2923 mutex_init(&domain->api_lock);
2924 domain->id = domain_id_alloc();
2927 INIT_LIST_HEAD(&domain->dev_list);
2932 static struct protection_domain *protection_domain_alloc(void)
2934 struct protection_domain *domain;
2936 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2940 if (protection_domain_init(domain))
2943 add_domain_to_list(domain);
2953 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2955 struct protection_domain *pdomain;
2956 struct dma_ops_domain *dma_domain;
2959 case IOMMU_DOMAIN_UNMANAGED:
2960 pdomain = protection_domain_alloc();
2964 pdomain->mode = PAGE_MODE_3_LEVEL;
2965 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2966 if (!pdomain->pt_root) {
2967 protection_domain_free(pdomain);
2971 pdomain->domain.geometry.aperture_start = 0;
2972 pdomain->domain.geometry.aperture_end = ~0ULL;
2973 pdomain->domain.geometry.force_aperture = true;
2976 case IOMMU_DOMAIN_DMA:
2977 dma_domain = dma_ops_domain_alloc();
2979 pr_err("AMD-Vi: Failed to allocate\n");
2982 pdomain = &dma_domain->domain;
2984 case IOMMU_DOMAIN_IDENTITY:
2985 pdomain = protection_domain_alloc();
2989 pdomain->mode = PAGE_MODE_NONE;
2995 return &pdomain->domain;
2998 static void amd_iommu_domain_free(struct iommu_domain *dom)
3000 struct protection_domain *domain;
3001 struct dma_ops_domain *dma_dom;
3003 domain = to_pdomain(dom);
3005 if (domain->dev_cnt > 0)
3006 cleanup_domain(domain);
3008 BUG_ON(domain->dev_cnt != 0);
3013 switch (dom->type) {
3014 case IOMMU_DOMAIN_DMA:
3016 * First make sure the domain is no longer referenced from the
3021 /* Now release the domain */
3022 dma_dom = to_dma_ops_domain(domain);
3023 dma_ops_domain_free(dma_dom);
3026 if (domain->mode != PAGE_MODE_NONE)
3027 free_pagetable(domain);
3029 if (domain->flags & PD_IOMMUV2_MASK)
3030 free_gcr3_table(domain);
3032 protection_domain_free(domain);
3037 static void amd_iommu_detach_device(struct iommu_domain *dom,
3040 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3041 struct amd_iommu *iommu;
3044 if (!check_device(dev))
3047 devid = get_device_id(dev);
3051 if (dev_data->domain != NULL)
3054 iommu = amd_iommu_rlookup_table[devid];
3058 #ifdef CONFIG_IRQ_REMAP
3059 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3060 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3061 dev_data->use_vapic = 0;
3064 iommu_completion_wait(iommu);
3067 static int amd_iommu_attach_device(struct iommu_domain *dom,
3070 struct protection_domain *domain = to_pdomain(dom);
3071 struct iommu_dev_data *dev_data;
3072 struct amd_iommu *iommu;
3075 if (!check_device(dev))
3078 dev_data = dev->archdata.iommu;
3080 iommu = amd_iommu_rlookup_table[dev_data->devid];
3084 if (dev_data->domain)
3087 ret = attach_device(dev, domain);
3089 #ifdef CONFIG_IRQ_REMAP
3090 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3091 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3092 dev_data->use_vapic = 1;
3094 dev_data->use_vapic = 0;
3098 iommu_completion_wait(iommu);
3103 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3104 phys_addr_t paddr, size_t page_size, int iommu_prot)
3106 struct protection_domain *domain = to_pdomain(dom);
3110 if (domain->mode == PAGE_MODE_NONE)
3113 if (iommu_prot & IOMMU_READ)
3114 prot |= IOMMU_PROT_IR;
3115 if (iommu_prot & IOMMU_WRITE)
3116 prot |= IOMMU_PROT_IW;
3118 mutex_lock(&domain->api_lock);
3119 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3120 mutex_unlock(&domain->api_lock);
3125 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3128 struct protection_domain *domain = to_pdomain(dom);
3131 if (domain->mode == PAGE_MODE_NONE)
3134 mutex_lock(&domain->api_lock);
3135 unmap_size = iommu_unmap_page(domain, iova, page_size);
3136 mutex_unlock(&domain->api_lock);
3138 domain_flush_tlb_pde(domain);
3143 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3146 struct protection_domain *domain = to_pdomain(dom);
3147 unsigned long offset_mask, pte_pgsize;
3150 if (domain->mode == PAGE_MODE_NONE)
3153 pte = fetch_pte(domain, iova, &pte_pgsize);
3155 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3158 offset_mask = pte_pgsize - 1;
3159 __pte = *pte & PM_ADDR_MASK;
3161 return (__pte & ~offset_mask) | (iova & offset_mask);
3164 static bool amd_iommu_capable(enum iommu_cap cap)
3167 case IOMMU_CAP_CACHE_COHERENCY:
3169 case IOMMU_CAP_INTR_REMAP:
3170 return (irq_remapping_enabled == 1);
3171 case IOMMU_CAP_NOEXEC:
3178 static void amd_iommu_get_resv_regions(struct device *dev,
3179 struct list_head *head)
3181 struct iommu_resv_region *region;
3182 struct unity_map_entry *entry;
3185 devid = get_device_id(dev);
3189 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3193 if (devid < entry->devid_start || devid > entry->devid_end)
3196 length = entry->address_end - entry->address_start;
3197 if (entry->prot & IOMMU_PROT_IR)
3199 if (entry->prot & IOMMU_PROT_IW)
3200 prot |= IOMMU_WRITE;
3202 region = iommu_alloc_resv_region(entry->address_start,
3206 pr_err("Out of memory allocating dm-regions for %s\n",
3210 list_add_tail(®ion->list, head);
3213 region = iommu_alloc_resv_region(MSI_RANGE_START,
3214 MSI_RANGE_END - MSI_RANGE_START + 1,
3218 list_add_tail(®ion->list, head);
3220 region = iommu_alloc_resv_region(HT_RANGE_START,
3221 HT_RANGE_END - HT_RANGE_START + 1,
3222 0, IOMMU_RESV_RESERVED);
3225 list_add_tail(®ion->list, head);
3228 static void amd_iommu_put_resv_regions(struct device *dev,
3229 struct list_head *head)
3231 struct iommu_resv_region *entry, *next;
3233 list_for_each_entry_safe(entry, next, head, list)
3237 static void amd_iommu_apply_resv_region(struct device *dev,
3238 struct iommu_domain *domain,
3239 struct iommu_resv_region *region)
3241 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3242 unsigned long start, end;
3244 start = IOVA_PFN(region->start);
3245 end = IOVA_PFN(region->start + region->length);
3247 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3250 const struct iommu_ops amd_iommu_ops = {
3251 .capable = amd_iommu_capable,
3252 .domain_alloc = amd_iommu_domain_alloc,
3253 .domain_free = amd_iommu_domain_free,
3254 .attach_dev = amd_iommu_attach_device,
3255 .detach_dev = amd_iommu_detach_device,
3256 .map = amd_iommu_map,
3257 .unmap = amd_iommu_unmap,
3258 .map_sg = default_iommu_map_sg,
3259 .iova_to_phys = amd_iommu_iova_to_phys,
3260 .add_device = amd_iommu_add_device,
3261 .remove_device = amd_iommu_remove_device,
3262 .device_group = amd_iommu_device_group,
3263 .get_resv_regions = amd_iommu_get_resv_regions,
3264 .put_resv_regions = amd_iommu_put_resv_regions,
3265 .apply_resv_region = amd_iommu_apply_resv_region,
3266 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3269 /*****************************************************************************
3271 * The next functions do a basic initialization of IOMMU for pass through
3274 * In passthrough mode the IOMMU is initialized and enabled but not used for
3275 * DMA-API translation.
3277 *****************************************************************************/
3279 /* IOMMUv2 specific functions */
3280 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3282 return atomic_notifier_chain_register(&ppr_notifier, nb);
3284 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3286 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3288 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3290 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3292 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3294 struct protection_domain *domain = to_pdomain(dom);
3295 unsigned long flags;
3297 spin_lock_irqsave(&domain->lock, flags);
3299 /* Update data structure */
3300 domain->mode = PAGE_MODE_NONE;
3301 domain->updated = true;
3303 /* Make changes visible to IOMMUs */
3304 update_domain(domain);
3306 /* Page-table is not visible to IOMMU anymore, so free it */
3307 free_pagetable(domain);
3309 spin_unlock_irqrestore(&domain->lock, flags);
3311 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3313 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3315 struct protection_domain *domain = to_pdomain(dom);
3316 unsigned long flags;
3319 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3322 /* Number of GCR3 table levels required */
3323 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3326 if (levels > amd_iommu_max_glx_val)
3329 spin_lock_irqsave(&domain->lock, flags);
3332 * Save us all sanity checks whether devices already in the
3333 * domain support IOMMUv2. Just force that the domain has no
3334 * devices attached when it is switched into IOMMUv2 mode.
3337 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3341 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3342 if (domain->gcr3_tbl == NULL)
3345 domain->glx = levels;
3346 domain->flags |= PD_IOMMUV2_MASK;
3347 domain->updated = true;
3349 update_domain(domain);
3354 spin_unlock_irqrestore(&domain->lock, flags);
3358 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3360 static int __flush_pasid(struct protection_domain *domain, int pasid,
3361 u64 address, bool size)
3363 struct iommu_dev_data *dev_data;
3364 struct iommu_cmd cmd;
3367 if (!(domain->flags & PD_IOMMUV2_MASK))
3370 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3373 * IOMMU TLB needs to be flushed before Device TLB to
3374 * prevent device TLB refill from IOMMU TLB
3376 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3377 if (domain->dev_iommu[i] == 0)
3380 ret = iommu_queue_command(amd_iommus[i], &cmd);
3385 /* Wait until IOMMU TLB flushes are complete */
3386 domain_flush_complete(domain);
3388 /* Now flush device TLBs */
3389 list_for_each_entry(dev_data, &domain->dev_list, list) {
3390 struct amd_iommu *iommu;
3394 There might be non-IOMMUv2 capable devices in an IOMMUv2
3397 if (!dev_data->ats.enabled)
3400 qdep = dev_data->ats.qdep;
3401 iommu = amd_iommu_rlookup_table[dev_data->devid];
3403 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3404 qdep, address, size);
3406 ret = iommu_queue_command(iommu, &cmd);
3411 /* Wait until all device TLBs are flushed */
3412 domain_flush_complete(domain);
3421 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3424 return __flush_pasid(domain, pasid, address, false);
3427 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3430 struct protection_domain *domain = to_pdomain(dom);
3431 unsigned long flags;
3434 spin_lock_irqsave(&domain->lock, flags);
3435 ret = __amd_iommu_flush_page(domain, pasid, address);
3436 spin_unlock_irqrestore(&domain->lock, flags);
3440 EXPORT_SYMBOL(amd_iommu_flush_page);
3442 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3444 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3448 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3450 struct protection_domain *domain = to_pdomain(dom);
3451 unsigned long flags;
3454 spin_lock_irqsave(&domain->lock, flags);
3455 ret = __amd_iommu_flush_tlb(domain, pasid);
3456 spin_unlock_irqrestore(&domain->lock, flags);
3460 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3462 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3469 index = (pasid >> (9 * level)) & 0x1ff;
3475 if (!(*pte & GCR3_VALID)) {
3479 root = (void *)get_zeroed_page(GFP_ATOMIC);
3483 *pte = __pa(root) | GCR3_VALID;
3486 root = __va(*pte & PAGE_MASK);
3494 static int __set_gcr3(struct protection_domain *domain, int pasid,
3499 if (domain->mode != PAGE_MODE_NONE)
3502 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3506 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3508 return __amd_iommu_flush_tlb(domain, pasid);
3511 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3515 if (domain->mode != PAGE_MODE_NONE)
3518 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3524 return __amd_iommu_flush_tlb(domain, pasid);
3527 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3530 struct protection_domain *domain = to_pdomain(dom);
3531 unsigned long flags;
3534 spin_lock_irqsave(&domain->lock, flags);
3535 ret = __set_gcr3(domain, pasid, cr3);
3536 spin_unlock_irqrestore(&domain->lock, flags);
3540 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3542 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3544 struct protection_domain *domain = to_pdomain(dom);
3545 unsigned long flags;
3548 spin_lock_irqsave(&domain->lock, flags);
3549 ret = __clear_gcr3(domain, pasid);
3550 spin_unlock_irqrestore(&domain->lock, flags);
3554 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3556 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3557 int status, int tag)
3559 struct iommu_dev_data *dev_data;
3560 struct amd_iommu *iommu;
3561 struct iommu_cmd cmd;
3563 dev_data = get_dev_data(&pdev->dev);
3564 iommu = amd_iommu_rlookup_table[dev_data->devid];
3566 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3567 tag, dev_data->pri_tlp);
3569 return iommu_queue_command(iommu, &cmd);
3571 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3573 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3575 struct protection_domain *pdomain;
3577 pdomain = get_domain(&pdev->dev);
3578 if (IS_ERR(pdomain))
3581 /* Only return IOMMUv2 domains */
3582 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3585 return &pdomain->domain;
3587 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3589 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3591 struct iommu_dev_data *dev_data;
3593 if (!amd_iommu_v2_supported())
3596 dev_data = get_dev_data(&pdev->dev);
3597 dev_data->errata |= (1 << erratum);
3599 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3601 int amd_iommu_device_info(struct pci_dev *pdev,
3602 struct amd_iommu_device_info *info)
3607 if (pdev == NULL || info == NULL)
3610 if (!amd_iommu_v2_supported())
3613 memset(info, 0, sizeof(*info));
3615 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3617 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3619 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3621 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3623 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3627 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3628 max_pasids = min(max_pasids, (1 << 20));
3630 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3631 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3633 features = pci_pasid_features(pdev);
3634 if (features & PCI_PASID_CAP_EXEC)
3635 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3636 if (features & PCI_PASID_CAP_PRIV)
3637 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3642 EXPORT_SYMBOL(amd_iommu_device_info);
3644 #ifdef CONFIG_IRQ_REMAP
3646 /*****************************************************************************
3648 * Interrupt Remapping Implementation
3650 *****************************************************************************/
3652 static struct irq_chip amd_ir_chip;
3654 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3655 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3656 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3657 #define DTE_IRQ_REMAP_ENABLE 1ULL
3659 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3663 dte = amd_iommu_dev_table[devid].data[2];
3664 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3665 dte |= virt_to_phys(table->table);
3666 dte |= DTE_IRQ_REMAP_INTCTL;
3667 dte |= DTE_IRQ_TABLE_LEN;
3668 dte |= DTE_IRQ_REMAP_ENABLE;
3670 amd_iommu_dev_table[devid].data[2] = dte;
3673 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3675 struct irq_remap_table *table = NULL;
3676 struct amd_iommu *iommu;
3677 unsigned long flags;
3680 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3682 iommu = amd_iommu_rlookup_table[devid];
3686 table = irq_lookup_table[devid];
3690 alias = amd_iommu_alias_table[devid];
3691 table = irq_lookup_table[alias];
3693 irq_lookup_table[devid] = table;
3694 set_dte_irq_entry(devid, table);
3695 iommu_flush_dte(iommu, devid);
3699 /* Nothing there yet, allocate new irq remapping table */
3700 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3704 /* Initialize table spin-lock */
3705 spin_lock_init(&table->lock);
3708 /* Keep the first 32 indexes free for IOAPIC interrupts */
3709 table->min_index = 32;
3711 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3712 if (!table->table) {
3718 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3719 memset(table->table, 0,
3720 MAX_IRQS_PER_TABLE * sizeof(u32));
3722 memset(table->table, 0,
3723 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3728 for (i = 0; i < 32; ++i)
3729 iommu->irte_ops->set_allocated(table, i);
3732 irq_lookup_table[devid] = table;
3733 set_dte_irq_entry(devid, table);
3734 iommu_flush_dte(iommu, devid);
3735 if (devid != alias) {
3736 irq_lookup_table[alias] = table;
3737 set_dte_irq_entry(alias, table);
3738 iommu_flush_dte(iommu, alias);
3742 iommu_completion_wait(iommu);
3745 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3750 static int alloc_irq_index(u16 devid, int count)
3752 struct irq_remap_table *table;
3753 unsigned long flags;
3755 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3760 table = get_irq_table(devid, false);
3764 spin_lock_irqsave(&table->lock, flags);
3766 /* Scan table for free entries */
3767 for (c = 0, index = table->min_index;
3768 index < MAX_IRQS_PER_TABLE;
3770 if (!iommu->irte_ops->is_allocated(table, index))
3777 iommu->irte_ops->set_allocated(table, index - c + 1);
3787 spin_unlock_irqrestore(&table->lock, flags);
3792 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3793 struct amd_ir_data *data)
3795 struct irq_remap_table *table;
3796 struct amd_iommu *iommu;
3797 unsigned long flags;
3798 struct irte_ga *entry;
3800 iommu = amd_iommu_rlookup_table[devid];
3804 table = get_irq_table(devid, false);
3808 spin_lock_irqsave(&table->lock, flags);
3810 entry = (struct irte_ga *)table->table;
3811 entry = &entry[index];
3812 entry->lo.fields_remap.valid = 0;
3813 entry->hi.val = irte->hi.val;
3814 entry->lo.val = irte->lo.val;
3815 entry->lo.fields_remap.valid = 1;
3819 spin_unlock_irqrestore(&table->lock, flags);
3821 iommu_flush_irt(iommu, devid);
3822 iommu_completion_wait(iommu);
3827 static int modify_irte(u16 devid, int index, union irte *irte)
3829 struct irq_remap_table *table;
3830 struct amd_iommu *iommu;
3831 unsigned long flags;
3833 iommu = amd_iommu_rlookup_table[devid];
3837 table = get_irq_table(devid, false);
3841 spin_lock_irqsave(&table->lock, flags);
3842 table->table[index] = irte->val;
3843 spin_unlock_irqrestore(&table->lock, flags);
3845 iommu_flush_irt(iommu, devid);
3846 iommu_completion_wait(iommu);
3851 static void free_irte(u16 devid, int index)
3853 struct irq_remap_table *table;
3854 struct amd_iommu *iommu;
3855 unsigned long flags;
3857 iommu = amd_iommu_rlookup_table[devid];
3861 table = get_irq_table(devid, false);
3865 spin_lock_irqsave(&table->lock, flags);
3866 iommu->irte_ops->clear_allocated(table, index);
3867 spin_unlock_irqrestore(&table->lock, flags);
3869 iommu_flush_irt(iommu, devid);
3870 iommu_completion_wait(iommu);
3873 static void irte_prepare(void *entry,
3874 u32 delivery_mode, u32 dest_mode,
3875 u8 vector, u32 dest_apicid, int devid)
3877 union irte *irte = (union irte *) entry;
3880 irte->fields.vector = vector;
3881 irte->fields.int_type = delivery_mode;
3882 irte->fields.destination = dest_apicid;
3883 irte->fields.dm = dest_mode;
3884 irte->fields.valid = 1;
3887 static void irte_ga_prepare(void *entry,
3888 u32 delivery_mode, u32 dest_mode,
3889 u8 vector, u32 dest_apicid, int devid)
3891 struct irte_ga *irte = (struct irte_ga *) entry;
3895 irte->lo.fields_remap.int_type = delivery_mode;
3896 irte->lo.fields_remap.dm = dest_mode;
3897 irte->hi.fields.vector = vector;
3898 irte->lo.fields_remap.destination = dest_apicid;
3899 irte->lo.fields_remap.valid = 1;
3902 static void irte_activate(void *entry, u16 devid, u16 index)
3904 union irte *irte = (union irte *) entry;
3906 irte->fields.valid = 1;
3907 modify_irte(devid, index, irte);
3910 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3912 struct irte_ga *irte = (struct irte_ga *) entry;
3914 irte->lo.fields_remap.valid = 1;
3915 modify_irte_ga(devid, index, irte, NULL);
3918 static void irte_deactivate(void *entry, u16 devid, u16 index)
3920 union irte *irte = (union irte *) entry;
3922 irte->fields.valid = 0;
3923 modify_irte(devid, index, irte);
3926 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3928 struct irte_ga *irte = (struct irte_ga *) entry;
3930 irte->lo.fields_remap.valid = 0;
3931 modify_irte_ga(devid, index, irte, NULL);
3934 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3935 u8 vector, u32 dest_apicid)
3937 union irte *irte = (union irte *) entry;
3939 irte->fields.vector = vector;
3940 irte->fields.destination = dest_apicid;
3941 modify_irte(devid, index, irte);
3944 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3945 u8 vector, u32 dest_apicid)
3947 struct irte_ga *irte = (struct irte_ga *) entry;
3948 struct iommu_dev_data *dev_data = search_dev_data(devid);
3950 if (!dev_data || !dev_data->use_vapic ||
3951 !irte->lo.fields_remap.guest_mode) {
3952 irte->hi.fields.vector = vector;
3953 irte->lo.fields_remap.destination = dest_apicid;
3954 modify_irte_ga(devid, index, irte, NULL);
3958 #define IRTE_ALLOCATED (~1U)
3959 static void irte_set_allocated(struct irq_remap_table *table, int index)
3961 table->table[index] = IRTE_ALLOCATED;
3964 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3966 struct irte_ga *ptr = (struct irte_ga *)table->table;
3967 struct irte_ga *irte = &ptr[index];
3969 memset(&irte->lo.val, 0, sizeof(u64));
3970 memset(&irte->hi.val, 0, sizeof(u64));
3971 irte->hi.fields.vector = 0xff;
3974 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3976 union irte *ptr = (union irte *)table->table;
3977 union irte *irte = &ptr[index];
3979 return irte->val != 0;
3982 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3984 struct irte_ga *ptr = (struct irte_ga *)table->table;
3985 struct irte_ga *irte = &ptr[index];
3987 return irte->hi.fields.vector != 0;
3990 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3992 table->table[index] = 0;
3995 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3997 struct irte_ga *ptr = (struct irte_ga *)table->table;
3998 struct irte_ga *irte = &ptr[index];
4000 memset(&irte->lo.val, 0, sizeof(u64));
4001 memset(&irte->hi.val, 0, sizeof(u64));
4004 static int get_devid(struct irq_alloc_info *info)
4008 switch (info->type) {
4009 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4010 devid = get_ioapic_devid(info->ioapic_id);
4012 case X86_IRQ_ALLOC_TYPE_HPET:
4013 devid = get_hpet_devid(info->hpet_id);
4015 case X86_IRQ_ALLOC_TYPE_MSI:
4016 case X86_IRQ_ALLOC_TYPE_MSIX:
4017 devid = get_device_id(&info->msi_dev->dev);
4027 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4029 struct amd_iommu *iommu;
4035 devid = get_devid(info);
4037 iommu = amd_iommu_rlookup_table[devid];
4039 return iommu->ir_domain;
4045 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4047 struct amd_iommu *iommu;
4053 switch (info->type) {
4054 case X86_IRQ_ALLOC_TYPE_MSI:
4055 case X86_IRQ_ALLOC_TYPE_MSIX:
4056 devid = get_device_id(&info->msi_dev->dev);
4060 iommu = amd_iommu_rlookup_table[devid];
4062 return iommu->msi_domain;
4071 struct irq_remap_ops amd_iommu_irq_ops = {
4072 .prepare = amd_iommu_prepare,
4073 .enable = amd_iommu_enable,
4074 .disable = amd_iommu_disable,
4075 .reenable = amd_iommu_reenable,
4076 .enable_faulting = amd_iommu_enable_faulting,
4077 .get_ir_irq_domain = get_ir_irq_domain,
4078 .get_irq_domain = get_irq_domain,
4081 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4082 struct irq_cfg *irq_cfg,
4083 struct irq_alloc_info *info,
4084 int devid, int index, int sub_handle)
4086 struct irq_2_irte *irte_info = &data->irq_2_irte;
4087 struct msi_msg *msg = &data->msi_entry;
4088 struct IO_APIC_route_entry *entry;
4089 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4094 data->irq_2_irte.devid = devid;
4095 data->irq_2_irte.index = index + sub_handle;
4096 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4097 apic->irq_dest_mode, irq_cfg->vector,
4098 irq_cfg->dest_apicid, devid);
4100 switch (info->type) {
4101 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4102 /* Setup IOAPIC entry */
4103 entry = info->ioapic_entry;
4104 info->ioapic_entry = NULL;
4105 memset(entry, 0, sizeof(*entry));
4106 entry->vector = index;
4108 entry->trigger = info->ioapic_trigger;
4109 entry->polarity = info->ioapic_polarity;
4110 /* Mask level triggered irqs. */
4111 if (info->ioapic_trigger)
4115 case X86_IRQ_ALLOC_TYPE_HPET:
4116 case X86_IRQ_ALLOC_TYPE_MSI:
4117 case X86_IRQ_ALLOC_TYPE_MSIX:
4118 msg->address_hi = MSI_ADDR_BASE_HI;
4119 msg->address_lo = MSI_ADDR_BASE_LO;
4120 msg->data = irte_info->index;
4129 struct amd_irte_ops irte_32_ops = {
4130 .prepare = irte_prepare,
4131 .activate = irte_activate,
4132 .deactivate = irte_deactivate,
4133 .set_affinity = irte_set_affinity,
4134 .set_allocated = irte_set_allocated,
4135 .is_allocated = irte_is_allocated,
4136 .clear_allocated = irte_clear_allocated,
4139 struct amd_irte_ops irte_128_ops = {
4140 .prepare = irte_ga_prepare,
4141 .activate = irte_ga_activate,
4142 .deactivate = irte_ga_deactivate,
4143 .set_affinity = irte_ga_set_affinity,
4144 .set_allocated = irte_ga_set_allocated,
4145 .is_allocated = irte_ga_is_allocated,
4146 .clear_allocated = irte_ga_clear_allocated,
4149 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4150 unsigned int nr_irqs, void *arg)
4152 struct irq_alloc_info *info = arg;
4153 struct irq_data *irq_data;
4154 struct amd_ir_data *data = NULL;
4155 struct irq_cfg *cfg;
4161 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4162 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4166 * With IRQ remapping enabled, don't need contiguous CPU vectors
4167 * to support multiple MSI interrupts.
4169 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4170 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4172 devid = get_devid(info);
4176 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4180 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4181 if (get_irq_table(devid, true))
4182 index = info->ioapic_pin;
4186 index = alloc_irq_index(devid, nr_irqs);
4189 pr_warn("Failed to allocate IRTE\n");
4191 goto out_free_parent;
4194 for (i = 0; i < nr_irqs; i++) {
4195 irq_data = irq_domain_get_irq_data(domain, virq + i);
4196 cfg = irqd_cfg(irq_data);
4197 if (!irq_data || !cfg) {
4203 data = kzalloc(sizeof(*data), GFP_KERNEL);
4207 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4208 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4210 data->entry = kzalloc(sizeof(struct irte_ga),
4217 irq_data->hwirq = (devid << 16) + i;
4218 irq_data->chip_data = data;
4219 irq_data->chip = &amd_ir_chip;
4220 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4221 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4227 for (i--; i >= 0; i--) {
4228 irq_data = irq_domain_get_irq_data(domain, virq + i);
4230 kfree(irq_data->chip_data);
4232 for (i = 0; i < nr_irqs; i++)
4233 free_irte(devid, index + i);
4235 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4239 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4240 unsigned int nr_irqs)
4242 struct irq_2_irte *irte_info;
4243 struct irq_data *irq_data;
4244 struct amd_ir_data *data;
4247 for (i = 0; i < nr_irqs; i++) {
4248 irq_data = irq_domain_get_irq_data(domain, virq + i);
4249 if (irq_data && irq_data->chip_data) {
4250 data = irq_data->chip_data;
4251 irte_info = &data->irq_2_irte;
4252 free_irte(irte_info->devid, irte_info->index);
4257 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4260 static void irq_remapping_activate(struct irq_domain *domain,
4261 struct irq_data *irq_data)
4263 struct amd_ir_data *data = irq_data->chip_data;
4264 struct irq_2_irte *irte_info = &data->irq_2_irte;
4265 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4268 iommu->irte_ops->activate(data->entry, irte_info->devid,
4272 static void irq_remapping_deactivate(struct irq_domain *domain,
4273 struct irq_data *irq_data)
4275 struct amd_ir_data *data = irq_data->chip_data;
4276 struct irq_2_irte *irte_info = &data->irq_2_irte;
4277 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4280 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4284 static struct irq_domain_ops amd_ir_domain_ops = {
4285 .alloc = irq_remapping_alloc,
4286 .free = irq_remapping_free,
4287 .activate = irq_remapping_activate,
4288 .deactivate = irq_remapping_deactivate,
4291 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4293 struct amd_iommu *iommu;
4294 struct amd_iommu_pi_data *pi_data = vcpu_info;
4295 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4296 struct amd_ir_data *ir_data = data->chip_data;
4297 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4298 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4299 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4302 * This device has never been set up for guest mode.
4303 * we should not modify the IRTE
4305 if (!dev_data || !dev_data->use_vapic)
4308 pi_data->ir_data = ir_data;
4311 * SVM tries to set up for VAPIC mode, but we are in
4312 * legacy mode. So, we force legacy mode instead.
4314 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4315 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4317 pi_data->is_guest_mode = false;
4320 iommu = amd_iommu_rlookup_table[irte_info->devid];
4324 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4325 if (pi_data->is_guest_mode) {
4327 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4328 irte->hi.fields.vector = vcpu_pi_info->vector;
4329 irte->lo.fields_vapic.guest_mode = 1;
4330 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4332 ir_data->cached_ga_tag = pi_data->ga_tag;
4335 struct irq_cfg *cfg = irqd_cfg(data);
4339 irte->hi.fields.vector = cfg->vector;
4340 irte->lo.fields_remap.guest_mode = 0;
4341 irte->lo.fields_remap.destination = cfg->dest_apicid;
4342 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4343 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4346 * This communicates the ga_tag back to the caller
4347 * so that it can do all the necessary clean up.
4349 ir_data->cached_ga_tag = 0;
4352 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4355 static int amd_ir_set_affinity(struct irq_data *data,
4356 const struct cpumask *mask, bool force)
4358 struct amd_ir_data *ir_data = data->chip_data;
4359 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4360 struct irq_cfg *cfg = irqd_cfg(data);
4361 struct irq_data *parent = data->parent_data;
4362 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4368 ret = parent->chip->irq_set_affinity(parent, mask, force);
4369 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4373 * Atomically updates the IRTE with the new destination, vector
4374 * and flushes the interrupt entry cache.
4376 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4377 irte_info->index, cfg->vector, cfg->dest_apicid);
4380 * After this point, all the interrupts will start arriving
4381 * at the new destination. So, time to cleanup the previous
4382 * vector allocation.
4384 send_cleanup_vector(cfg);
4386 return IRQ_SET_MASK_OK_DONE;
4389 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4391 struct amd_ir_data *ir_data = irq_data->chip_data;
4393 *msg = ir_data->msi_entry;
4396 static struct irq_chip amd_ir_chip = {
4398 .irq_ack = ir_ack_apic_edge,
4399 .irq_set_affinity = amd_ir_set_affinity,
4400 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4401 .irq_compose_msi_msg = ir_compose_msi_msg,
4404 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4406 struct fwnode_handle *fn;
4408 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4411 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4412 irq_domain_free_fwnode(fn);
4413 if (!iommu->ir_domain)
4416 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4417 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4423 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4425 unsigned long flags;
4426 struct amd_iommu *iommu;
4427 struct irq_remap_table *irt;
4428 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4429 int devid = ir_data->irq_2_irte.devid;
4430 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4431 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4433 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4434 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4437 iommu = amd_iommu_rlookup_table[devid];
4441 irt = get_irq_table(devid, false);
4445 spin_lock_irqsave(&irt->lock, flags);
4447 if (ref->lo.fields_vapic.guest_mode) {
4449 ref->lo.fields_vapic.destination = cpu;
4450 ref->lo.fields_vapic.is_run = is_run;
4454 spin_unlock_irqrestore(&irt->lock, flags);
4456 iommu_flush_irt(iommu, devid);
4457 iommu_completion_wait(iommu);
4460 EXPORT_SYMBOL(amd_iommu_update_ga);