2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <linux/kmemleak.h>
32 #include <linux/crash_dump.h>
33 #include <asm/pci-direct.h>
34 #include <asm/iommu.h>
36 #include <asm/x86_init.h>
37 #include <asm/iommu_table.h>
38 #include <asm/io_apic.h>
39 #include <asm/irq_remapping.h>
41 #include "amd_iommu_proto.h"
42 #include "amd_iommu_types.h"
43 #include "irq_remapping.h"
46 * definitions for the ACPI scanning code
48 #define IVRS_HEADER_LENGTH 48
50 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
51 #define ACPI_IVMD_TYPE_ALL 0x20
52 #define ACPI_IVMD_TYPE 0x21
53 #define ACPI_IVMD_TYPE_RANGE 0x22
55 #define IVHD_DEV_ALL 0x01
56 #define IVHD_DEV_SELECT 0x02
57 #define IVHD_DEV_SELECT_RANGE_START 0x03
58 #define IVHD_DEV_RANGE_END 0x04
59 #define IVHD_DEV_ALIAS 0x42
60 #define IVHD_DEV_ALIAS_RANGE 0x43
61 #define IVHD_DEV_EXT_SELECT 0x46
62 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
63 #define IVHD_DEV_SPECIAL 0x48
64 #define IVHD_DEV_ACPI_HID 0xf0
66 #define UID_NOT_PRESENT 0
67 #define UID_IS_INTEGER 1
68 #define UID_IS_CHARACTER 2
70 #define IVHD_SPECIAL_IOAPIC 1
71 #define IVHD_SPECIAL_HPET 2
73 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
74 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
75 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
76 #define IVHD_FLAG_ISOC_EN_MASK 0x08
78 #define IVMD_FLAG_EXCL_RANGE 0x08
79 #define IVMD_FLAG_UNITY_MAP 0x01
81 #define ACPI_DEVFLAG_INITPASS 0x01
82 #define ACPI_DEVFLAG_EXTINT 0x02
83 #define ACPI_DEVFLAG_NMI 0x04
84 #define ACPI_DEVFLAG_SYSMGT1 0x10
85 #define ACPI_DEVFLAG_SYSMGT2 0x20
86 #define ACPI_DEVFLAG_LINT0 0x40
87 #define ACPI_DEVFLAG_LINT1 0x80
88 #define ACPI_DEVFLAG_ATSDIS 0x10000000
90 #define LOOP_TIMEOUT 100000
92 * ACPI table definitions
94 * These data structures are laid over the table to parse the important values
98 extern const struct iommu_ops amd_iommu_ops;
101 * structure describing one IOMMU in the ACPI table. Typically followed by one
102 * or more ivhd_entrys.
115 /* Following only valid on IVHD type 11h and 40h */
116 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
118 } __attribute__((packed));
121 * A device entry describing which devices a specific IOMMU translates and
122 * which requestor ids they use.
134 } __attribute__((packed));
137 * An AMD IOMMU memory definition structure. It defines things like exclusion
138 * ranges for devices and regions that should be unity mapped.
149 } __attribute__((packed));
152 bool amd_iommu_irq_remap __read_mostly;
154 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
156 static bool amd_iommu_detected;
157 static bool __initdata amd_iommu_disabled;
158 static int amd_iommu_target_ivhd_type;
160 u16 amd_iommu_last_bdf; /* largest PCI device id we have
162 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
164 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
166 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
169 /* Array to assign indices to IOMMUs*/
170 struct amd_iommu *amd_iommus[MAX_IOMMUS];
172 /* Number of IOMMUs present in the system */
173 static int amd_iommus_present;
175 /* IOMMUs have a non-present cache? */
176 bool amd_iommu_np_cache __read_mostly;
177 bool amd_iommu_iotlb_sup __read_mostly = true;
179 u32 amd_iommu_max_pasid __read_mostly = ~0;
181 bool amd_iommu_v2_present __read_mostly;
182 static bool amd_iommu_pc_present __read_mostly;
184 bool amd_iommu_force_isolation __read_mostly;
187 * List of protection domains - used during resume
189 LIST_HEAD(amd_iommu_pd_list);
190 spinlock_t amd_iommu_pd_lock;
193 * Pointer to the device table which is shared by all AMD IOMMUs
194 * it is indexed by the PCI device id or the HT unit id and contains
195 * information about the domain the device belongs to as well as the
196 * page table root pointer.
198 struct dev_table_entry *amd_iommu_dev_table;
201 * The alias table is a driver specific data structure which contains the
202 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
203 * More than one device can share the same requestor id.
205 u16 *amd_iommu_alias_table;
208 * The rlookup table is used to find the IOMMU which is responsible
209 * for a specific device. It is also indexed by the PCI device id.
211 struct amd_iommu **amd_iommu_rlookup_table;
214 * This table is used to find the irq remapping table for a given device id
217 struct irq_remap_table **irq_lookup_table;
220 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
221 * to know which ones are already in use.
223 unsigned long *amd_iommu_pd_alloc_bitmap;
225 static u32 dev_table_size; /* size of the device table */
226 static u32 alias_table_size; /* size of the alias table */
227 static u32 rlookup_table_size; /* size if the rlookup table */
229 enum iommu_init_state {
240 IOMMU_CMDLINE_DISABLED,
243 /* Early ioapic and hpet maps from kernel command line */
244 #define EARLY_MAP_SIZE 4
245 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
246 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
247 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
249 static int __initdata early_ioapic_map_size;
250 static int __initdata early_hpet_map_size;
251 static int __initdata early_acpihid_map_size;
253 static bool __initdata cmdline_maps;
255 static enum iommu_init_state init_state = IOMMU_START_STATE;
257 static int amd_iommu_enable_interrupts(void);
258 static int __init iommu_go_to_state(enum iommu_init_state state);
259 static void init_device_table_dma(void);
261 static inline void update_last_devid(u16 devid)
263 if (devid > amd_iommu_last_bdf)
264 amd_iommu_last_bdf = devid;
267 static inline unsigned long tbl_size(int entry_size)
269 unsigned shift = PAGE_SHIFT +
270 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
275 int amd_iommu_get_num_iommus(void)
277 return amd_iommus_present;
280 /* Access to l1 and l2 indexed register spaces */
282 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
286 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
287 pci_read_config_dword(iommu->dev, 0xfc, &val);
291 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
293 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
294 pci_write_config_dword(iommu->dev, 0xfc, val);
295 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
298 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
302 pci_write_config_dword(iommu->dev, 0xf0, address);
303 pci_read_config_dword(iommu->dev, 0xf4, &val);
307 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
309 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
310 pci_write_config_dword(iommu->dev, 0xf4, val);
313 /****************************************************************************
315 * AMD IOMMU MMIO register space handling functions
317 * These functions are used to program the IOMMU device registers in
318 * MMIO space required for that driver.
320 ****************************************************************************/
323 * This function set the exclusion range in the IOMMU. DMA accesses to the
324 * exclusion range are passed through untranslated
326 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
328 u64 start = iommu->exclusion_start & PAGE_MASK;
329 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
332 if (!iommu->exclusion_start)
335 entry = start | MMIO_EXCL_ENABLE_MASK;
336 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
337 &entry, sizeof(entry));
340 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
341 &entry, sizeof(entry));
344 /* Programs the physical address of the device table into the IOMMU hardware */
345 static void iommu_set_device_table(struct amd_iommu *iommu)
349 BUG_ON(iommu->mmio_base == NULL);
351 entry = virt_to_phys(amd_iommu_dev_table);
352 entry |= (dev_table_size >> 12) - 1;
353 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
354 &entry, sizeof(entry));
357 /* Generic functions to enable/disable certain features of the IOMMU. */
358 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
362 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
364 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
367 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
371 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
373 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
376 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
380 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
381 ctrl &= ~CTRL_INV_TO_MASK;
382 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
383 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
386 /* Function to enable the hardware */
387 static void iommu_enable(struct amd_iommu *iommu)
389 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
392 static void iommu_disable(struct amd_iommu *iommu)
394 /* Disable command buffer */
395 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
397 /* Disable event logging and event interrupts */
398 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
399 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
401 /* Disable IOMMU GA_LOG */
402 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
403 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
405 /* Disable IOMMU hardware itself */
406 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
410 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
411 * the system has one.
413 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
415 if (!request_mem_region(address, end, "amd_iommu")) {
416 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
418 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
422 return (u8 __iomem *)ioremap_nocache(address, end);
425 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
427 if (iommu->mmio_base)
428 iounmap(iommu->mmio_base);
429 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
432 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
448 /****************************************************************************
450 * The functions below belong to the first pass of AMD IOMMU ACPI table
451 * parsing. In this pass we try to find out the highest device id this
452 * code has to handle. Upon this information the size of the shared data
453 * structures is determined later.
455 ****************************************************************************/
458 * This function calculates the length of a given IVHD entry
460 static inline int ivhd_entry_length(u8 *ivhd)
462 u32 type = ((struct ivhd_entry *)ivhd)->type;
465 return 0x04 << (*ivhd >> 6);
466 } else if (type == IVHD_DEV_ACPI_HID) {
467 /* For ACPI_HID, offset 21 is uid len */
468 return *((u8 *)ivhd + 21) + 22;
474 * After reading the highest device id from the IOMMU PCI capability header
475 * this function looks if there is a higher device id defined in the ACPI table
477 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
479 u8 *p = (void *)h, *end = (void *)h;
480 struct ivhd_entry *dev;
482 u32 ivhd_size = get_ivhd_header_size(h);
485 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
493 dev = (struct ivhd_entry *)p;
496 /* Use maximum BDF value for DEV_ALL */
497 update_last_devid(0xffff);
499 case IVHD_DEV_SELECT:
500 case IVHD_DEV_RANGE_END:
502 case IVHD_DEV_EXT_SELECT:
503 /* all the above subfield types refer to device ids */
504 update_last_devid(dev->devid);
509 p += ivhd_entry_length(p);
517 static int __init check_ivrs_checksum(struct acpi_table_header *table)
520 u8 checksum = 0, *p = (u8 *)table;
522 for (i = 0; i < table->length; ++i)
525 /* ACPI table corrupt */
526 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
534 * Iterate over all IVHD entries in the ACPI table and find the highest device
535 * id which we need to handle. This is the first of three functions which parse
536 * the ACPI table. So we check the checksum here.
538 static int __init find_last_devid_acpi(struct acpi_table_header *table)
540 u8 *p = (u8 *)table, *end = (u8 *)table;
541 struct ivhd_header *h;
543 p += IVRS_HEADER_LENGTH;
545 end += table->length;
547 h = (struct ivhd_header *)p;
548 if (h->type == amd_iommu_target_ivhd_type) {
549 int ret = find_last_devid_from_ivhd(h);
561 /****************************************************************************
563 * The following functions belong to the code path which parses the ACPI table
564 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
565 * data structures, initialize the device/alias/rlookup table and also
566 * basically initialize the hardware.
568 ****************************************************************************/
571 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
572 * write commands to that buffer later and the IOMMU will execute them
575 static int __init alloc_command_buffer(struct amd_iommu *iommu)
577 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
578 get_order(CMD_BUFFER_SIZE));
580 return iommu->cmd_buf ? 0 : -ENOMEM;
584 * This function resets the command buffer if the IOMMU stopped fetching
587 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
589 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
591 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
592 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
593 iommu->cmd_buf_head = 0;
594 iommu->cmd_buf_tail = 0;
596 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
600 * This function writes the command buffer address to the hardware and
603 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
607 BUG_ON(iommu->cmd_buf == NULL);
609 entry = (u64)virt_to_phys(iommu->cmd_buf);
610 entry |= MMIO_CMD_SIZE_512;
612 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
613 &entry, sizeof(entry));
615 amd_iommu_reset_cmd_buffer(iommu);
618 static void __init free_command_buffer(struct amd_iommu *iommu)
620 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
623 /* allocates the memory where the IOMMU will log its events to */
624 static int __init alloc_event_buffer(struct amd_iommu *iommu)
626 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
627 get_order(EVT_BUFFER_SIZE));
629 return iommu->evt_buf ? 0 : -ENOMEM;
632 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
636 BUG_ON(iommu->evt_buf == NULL);
638 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
640 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
641 &entry, sizeof(entry));
643 /* set head and tail to zero manually */
644 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
645 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
647 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
650 static void __init free_event_buffer(struct amd_iommu *iommu)
652 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
655 /* allocates the memory where the IOMMU will log its events to */
656 static int __init alloc_ppr_log(struct amd_iommu *iommu)
658 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
659 get_order(PPR_LOG_SIZE));
661 return iommu->ppr_log ? 0 : -ENOMEM;
664 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
668 if (iommu->ppr_log == NULL)
671 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
673 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
674 &entry, sizeof(entry));
676 /* set head and tail to zero manually */
677 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
678 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
680 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
681 iommu_feature_enable(iommu, CONTROL_PPR_EN);
684 static void __init free_ppr_log(struct amd_iommu *iommu)
686 if (iommu->ppr_log == NULL)
689 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
692 static void free_ga_log(struct amd_iommu *iommu)
694 #ifdef CONFIG_IRQ_REMAP
696 free_pages((unsigned long)iommu->ga_log,
697 get_order(GA_LOG_SIZE));
698 if (iommu->ga_log_tail)
699 free_pages((unsigned long)iommu->ga_log_tail,
704 static int iommu_ga_log_enable(struct amd_iommu *iommu)
706 #ifdef CONFIG_IRQ_REMAP
712 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
714 /* Check if already running */
715 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
718 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
719 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
721 for (i = 0; i < LOOP_TIMEOUT; ++i) {
722 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
723 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
727 if (i >= LOOP_TIMEOUT)
729 #endif /* CONFIG_IRQ_REMAP */
733 #ifdef CONFIG_IRQ_REMAP
734 static int iommu_init_ga_log(struct amd_iommu *iommu)
738 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
741 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
742 get_order(GA_LOG_SIZE));
746 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
748 if (!iommu->ga_log_tail)
751 entry = (u64)virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
752 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
753 &entry, sizeof(entry));
754 entry = ((u64)virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
755 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
756 &entry, sizeof(entry));
757 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
758 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
765 #endif /* CONFIG_IRQ_REMAP */
767 static int iommu_init_ga(struct amd_iommu *iommu)
771 #ifdef CONFIG_IRQ_REMAP
772 /* Note: We have already checked GASup from IVRS table.
773 * Now, we need to make sure that GAMSup is set.
775 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
776 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
777 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
779 ret = iommu_init_ga_log(iommu);
780 #endif /* CONFIG_IRQ_REMAP */
785 static void iommu_enable_gt(struct amd_iommu *iommu)
787 if (!iommu_feature(iommu, FEATURE_GT))
790 iommu_feature_enable(iommu, CONTROL_GT_EN);
793 /* sets a specific bit in the device table entry. */
794 static void set_dev_entry_bit(u16 devid, u8 bit)
796 int i = (bit >> 6) & 0x03;
797 int _bit = bit & 0x3f;
799 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
802 static int get_dev_entry_bit(u16 devid, u8 bit)
804 int i = (bit >> 6) & 0x03;
805 int _bit = bit & 0x3f;
807 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
811 void amd_iommu_apply_erratum_63(u16 devid)
815 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
816 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
819 set_dev_entry_bit(devid, DEV_ENTRY_IW);
822 /* Writes the specific IOMMU for a device into the rlookup table */
823 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
825 amd_iommu_rlookup_table[devid] = iommu;
829 * This function takes the device specific flags read from the ACPI
830 * table and sets up the device table entry with that information
832 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
833 u16 devid, u32 flags, u32 ext_flags)
835 if (flags & ACPI_DEVFLAG_INITPASS)
836 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
837 if (flags & ACPI_DEVFLAG_EXTINT)
838 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
839 if (flags & ACPI_DEVFLAG_NMI)
840 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
841 if (flags & ACPI_DEVFLAG_SYSMGT1)
842 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
843 if (flags & ACPI_DEVFLAG_SYSMGT2)
844 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
845 if (flags & ACPI_DEVFLAG_LINT0)
846 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
847 if (flags & ACPI_DEVFLAG_LINT1)
848 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
850 amd_iommu_apply_erratum_63(devid);
852 set_iommu_for_device(iommu, devid);
855 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
857 struct devid_map *entry;
858 struct list_head *list;
860 if (type == IVHD_SPECIAL_IOAPIC)
862 else if (type == IVHD_SPECIAL_HPET)
867 list_for_each_entry(entry, list, list) {
868 if (!(entry->id == id && entry->cmd_line))
871 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
872 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
874 *devid = entry->devid;
879 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
884 entry->devid = *devid;
885 entry->cmd_line = cmd_line;
887 list_add_tail(&entry->list, list);
892 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
895 struct acpihid_map_entry *entry;
896 struct list_head *list = &acpihid_map;
898 list_for_each_entry(entry, list, list) {
899 if (strcmp(entry->hid, hid) ||
900 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
904 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
906 *devid = entry->devid;
910 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
914 memcpy(entry->uid, uid, strlen(uid));
915 memcpy(entry->hid, hid, strlen(hid));
916 entry->devid = *devid;
917 entry->cmd_line = cmd_line;
918 entry->root_devid = (entry->devid & (~0x7));
920 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
921 entry->cmd_line ? "cmd" : "ivrs",
922 entry->hid, entry->uid, entry->root_devid);
924 list_add_tail(&entry->list, list);
928 static int __init add_early_maps(void)
932 for (i = 0; i < early_ioapic_map_size; ++i) {
933 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
934 early_ioapic_map[i].id,
935 &early_ioapic_map[i].devid,
936 early_ioapic_map[i].cmd_line);
941 for (i = 0; i < early_hpet_map_size; ++i) {
942 ret = add_special_device(IVHD_SPECIAL_HPET,
943 early_hpet_map[i].id,
944 &early_hpet_map[i].devid,
945 early_hpet_map[i].cmd_line);
950 for (i = 0; i < early_acpihid_map_size; ++i) {
951 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
952 early_acpihid_map[i].uid,
953 &early_acpihid_map[i].devid,
954 early_acpihid_map[i].cmd_line);
963 * Reads the device exclusion range from ACPI and initializes the IOMMU with
966 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
968 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
970 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
975 * We only can configure exclusion ranges per IOMMU, not
976 * per device. But we can enable the exclusion range per
977 * device. This is done here
979 set_dev_entry_bit(devid, DEV_ENTRY_EX);
980 iommu->exclusion_start = m->range_start;
981 iommu->exclusion_length = m->range_length;
986 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
987 * initializes the hardware and our data structures with it.
989 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
990 struct ivhd_header *h)
993 u8 *end = p, flags = 0;
994 u16 devid = 0, devid_start = 0, devid_to = 0;
995 u32 dev_i, ext_flags = 0;
997 struct ivhd_entry *e;
1002 ret = add_early_maps();
1007 * First save the recommended feature enable bits from ACPI
1009 iommu->acpi_flags = h->flags;
1012 * Done. Now parse the device entries
1014 ivhd_size = get_ivhd_header_size(h);
1016 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1026 e = (struct ivhd_entry *)p;
1030 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1032 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1033 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1035 case IVHD_DEV_SELECT:
1037 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1039 PCI_BUS_NUM(e->devid),
1045 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1047 case IVHD_DEV_SELECT_RANGE_START:
1049 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1050 "devid: %02x:%02x.%x flags: %02x\n",
1051 PCI_BUS_NUM(e->devid),
1056 devid_start = e->devid;
1061 case IVHD_DEV_ALIAS:
1063 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1064 "flags: %02x devid_to: %02x:%02x.%x\n",
1065 PCI_BUS_NUM(e->devid),
1069 PCI_BUS_NUM(e->ext >> 8),
1070 PCI_SLOT(e->ext >> 8),
1071 PCI_FUNC(e->ext >> 8));
1074 devid_to = e->ext >> 8;
1075 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1076 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1077 amd_iommu_alias_table[devid] = devid_to;
1079 case IVHD_DEV_ALIAS_RANGE:
1081 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1082 "devid: %02x:%02x.%x flags: %02x "
1083 "devid_to: %02x:%02x.%x\n",
1084 PCI_BUS_NUM(e->devid),
1088 PCI_BUS_NUM(e->ext >> 8),
1089 PCI_SLOT(e->ext >> 8),
1090 PCI_FUNC(e->ext >> 8));
1092 devid_start = e->devid;
1094 devid_to = e->ext >> 8;
1098 case IVHD_DEV_EXT_SELECT:
1100 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1101 "flags: %02x ext: %08x\n",
1102 PCI_BUS_NUM(e->devid),
1108 set_dev_entry_from_acpi(iommu, devid, e->flags,
1111 case IVHD_DEV_EXT_SELECT_RANGE:
1113 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1114 "%02x:%02x.%x flags: %02x ext: %08x\n",
1115 PCI_BUS_NUM(e->devid),
1120 devid_start = e->devid;
1125 case IVHD_DEV_RANGE_END:
1127 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1128 PCI_BUS_NUM(e->devid),
1130 PCI_FUNC(e->devid));
1133 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1135 amd_iommu_alias_table[dev_i] = devid_to;
1136 set_dev_entry_from_acpi(iommu,
1137 devid_to, flags, ext_flags);
1139 set_dev_entry_from_acpi(iommu, dev_i,
1143 case IVHD_DEV_SPECIAL: {
1149 handle = e->ext & 0xff;
1150 devid = (e->ext >> 8) & 0xffff;
1151 type = (e->ext >> 24) & 0xff;
1153 if (type == IVHD_SPECIAL_IOAPIC)
1155 else if (type == IVHD_SPECIAL_HPET)
1160 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1166 ret = add_special_device(type, handle, &devid, false);
1171 * add_special_device might update the devid in case a
1172 * command-line override is present. So call
1173 * set_dev_entry_from_acpi after add_special_device.
1175 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1179 case IVHD_DEV_ACPI_HID: {
1181 u8 hid[ACPIHID_HID_LEN] = {0};
1182 u8 uid[ACPIHID_UID_LEN] = {0};
1185 if (h->type != 0x40) {
1186 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1191 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1192 hid[ACPIHID_HID_LEN - 1] = '\0';
1195 pr_err(FW_BUG "Invalid HID.\n");
1200 case UID_NOT_PRESENT:
1203 pr_warn(FW_BUG "Invalid UID length.\n");
1206 case UID_IS_INTEGER:
1208 sprintf(uid, "%d", e->uid);
1211 case UID_IS_CHARACTER:
1213 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1214 uid[ACPIHID_UID_LEN - 1] = '\0';
1222 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1230 ret = add_acpi_hid_device(hid, uid, &devid, false);
1235 * add_special_device might update the devid in case a
1236 * command-line override is present. So call
1237 * set_dev_entry_from_acpi after add_special_device.
1239 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1247 p += ivhd_entry_length(p);
1253 static void __init free_iommu_one(struct amd_iommu *iommu)
1255 free_command_buffer(iommu);
1256 free_event_buffer(iommu);
1257 free_ppr_log(iommu);
1259 iommu_unmap_mmio_space(iommu);
1262 static void __init free_iommu_all(void)
1264 struct amd_iommu *iommu, *next;
1266 for_each_iommu_safe(iommu, next) {
1267 list_del(&iommu->list);
1268 free_iommu_one(iommu);
1274 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1276 * BIOS should disable L2B micellaneous clock gating by setting
1277 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1279 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1283 if ((boot_cpu_data.x86 != 0x15) ||
1284 (boot_cpu_data.x86_model < 0x10) ||
1285 (boot_cpu_data.x86_model > 0x1f))
1288 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1289 pci_read_config_dword(iommu->dev, 0xf4, &value);
1294 /* Select NB indirect register 0x90 and enable writing */
1295 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1297 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1298 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1299 dev_name(&iommu->dev->dev));
1301 /* Clear the enable writing bit */
1302 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1306 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1308 * BIOS should enable ATS write permission check by setting
1309 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1311 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1315 if ((boot_cpu_data.x86 != 0x15) ||
1316 (boot_cpu_data.x86_model < 0x30) ||
1317 (boot_cpu_data.x86_model > 0x3f))
1320 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1321 value = iommu_read_l2(iommu, 0x47);
1326 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1327 iommu_write_l2(iommu, 0x47, value | BIT(0));
1329 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1330 dev_name(&iommu->dev->dev));
1334 * This function clues the initialization function for one IOMMU
1335 * together and also allocates the command buffer and programs the
1336 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1338 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1342 spin_lock_init(&iommu->lock);
1344 /* Add IOMMU to internal data structures */
1345 list_add_tail(&iommu->list, &amd_iommu_list);
1346 iommu->index = amd_iommus_present++;
1348 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1349 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1353 /* Index is fine - add IOMMU to the array */
1354 amd_iommus[iommu->index] = iommu;
1357 * Copy data from ACPI table entry to the iommu struct
1359 iommu->devid = h->devid;
1360 iommu->cap_ptr = h->cap_ptr;
1361 iommu->pci_seg = h->pci_seg;
1362 iommu->mmio_phys = h->mmio_phys;
1366 /* Check if IVHD EFR contains proper max banks/counters */
1367 if ((h->efr_attr != 0) &&
1368 ((h->efr_attr & (0xF << 13)) != 0) &&
1369 ((h->efr_attr & (0x3F << 17)) != 0))
1370 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1372 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1373 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1374 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1378 if (h->efr_reg & (1 << 9))
1379 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1381 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1382 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1383 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1389 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1390 iommu->mmio_phys_end);
1391 if (!iommu->mmio_base)
1394 if (alloc_command_buffer(iommu))
1397 if (alloc_event_buffer(iommu))
1400 iommu->int_enabled = false;
1402 ret = init_iommu_from_acpi(iommu, h);
1406 ret = amd_iommu_create_irq_domain(iommu);
1411 * Make sure IOMMU is not considered to translate itself. The IVRS
1412 * table tells us so, but this is a lie!
1414 amd_iommu_rlookup_table[iommu->devid] = NULL;
1420 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1421 * @ivrs Pointer to the IVRS header
1423 * This function search through all IVDB of the maximum supported IVHD
1425 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1427 u8 *base = (u8 *)ivrs;
1428 struct ivhd_header *ivhd = (struct ivhd_header *)
1429 (base + IVRS_HEADER_LENGTH);
1430 u8 last_type = ivhd->type;
1431 u16 devid = ivhd->devid;
1433 while (((u8 *)ivhd - base < ivrs->length) &&
1434 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1435 u8 *p = (u8 *) ivhd;
1437 if (ivhd->devid == devid)
1438 last_type = ivhd->type;
1439 ivhd = (struct ivhd_header *)(p + ivhd->length);
1446 * Iterates over all IOMMU entries in the ACPI table, allocates the
1447 * IOMMU structure and initializes it with init_iommu_one()
1449 static int __init init_iommu_all(struct acpi_table_header *table)
1451 u8 *p = (u8 *)table, *end = (u8 *)table;
1452 struct ivhd_header *h;
1453 struct amd_iommu *iommu;
1456 end += table->length;
1457 p += IVRS_HEADER_LENGTH;
1460 h = (struct ivhd_header *)p;
1461 if (*p == amd_iommu_target_ivhd_type) {
1463 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1464 "seg: %d flags: %01x info %04x\n",
1465 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1466 PCI_FUNC(h->devid), h->cap_ptr,
1467 h->pci_seg, h->flags, h->info);
1468 DUMP_printk(" mmio-addr: %016llx\n",
1471 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1475 ret = init_iommu_one(iommu, h);
1487 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1488 u8 fxn, u64 *value, bool is_write);
1490 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1492 u64 val = 0xabcd, val2 = 0;
1494 if (!iommu_feature(iommu, FEATURE_PC))
1497 amd_iommu_pc_present = true;
1499 /* Check if the performance counters can be written to */
1500 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1501 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1503 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1504 amd_iommu_pc_present = false;
1508 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1510 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1511 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1512 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1515 static ssize_t amd_iommu_show_cap(struct device *dev,
1516 struct device_attribute *attr,
1519 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1520 return sprintf(buf, "%x\n", iommu->cap);
1522 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1524 static ssize_t amd_iommu_show_features(struct device *dev,
1525 struct device_attribute *attr,
1528 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1529 return sprintf(buf, "%llx\n", iommu->features);
1531 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1533 static struct attribute *amd_iommu_attrs[] = {
1535 &dev_attr_features.attr,
1539 static struct attribute_group amd_iommu_group = {
1540 .name = "amd-iommu",
1541 .attrs = amd_iommu_attrs,
1544 static const struct attribute_group *amd_iommu_groups[] = {
1549 static int iommu_init_pci(struct amd_iommu *iommu)
1551 int cap_ptr = iommu->cap_ptr;
1552 u32 range, misc, low, high;
1555 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1556 iommu->devid & 0xff);
1560 /* Prevent binding other PCI device drivers to IOMMU devices */
1561 iommu->dev->match_driver = false;
1563 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1565 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1567 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1570 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1571 amd_iommu_iotlb_sup = false;
1573 /* read extended feature bits */
1574 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1575 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1577 iommu->features = ((u64)high << 32) | low;
1579 if (iommu_feature(iommu, FEATURE_GT)) {
1584 pasmax = iommu->features & FEATURE_PASID_MASK;
1585 pasmax >>= FEATURE_PASID_SHIFT;
1586 max_pasid = (1 << (pasmax + 1)) - 1;
1588 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1590 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1592 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1593 glxval >>= FEATURE_GLXVAL_SHIFT;
1595 if (amd_iommu_max_glx_val == -1)
1596 amd_iommu_max_glx_val = glxval;
1598 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1601 if (iommu_feature(iommu, FEATURE_GT) &&
1602 iommu_feature(iommu, FEATURE_PPR)) {
1603 iommu->is_iommu_v2 = true;
1604 amd_iommu_v2_present = true;
1607 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1610 ret = iommu_init_ga(iommu);
1614 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1615 amd_iommu_np_cache = true;
1617 init_iommu_perf_ctr(iommu);
1619 if (is_rd890_iommu(iommu->dev)) {
1622 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1626 * Some rd890 systems may not be fully reconfigured by the
1627 * BIOS, so it's necessary for us to store this information so
1628 * it can be reprogrammed on resume
1630 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1631 &iommu->stored_addr_lo);
1632 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1633 &iommu->stored_addr_hi);
1635 /* Low bit locks writes to configuration space */
1636 iommu->stored_addr_lo &= ~1;
1638 for (i = 0; i < 6; i++)
1639 for (j = 0; j < 0x12; j++)
1640 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1642 for (i = 0; i < 0x83; i++)
1643 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1646 amd_iommu_erratum_746_workaround(iommu);
1647 amd_iommu_ats_write_check_workaround(iommu);
1649 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1650 amd_iommu_groups, "ivhd%d", iommu->index);
1651 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1652 iommu_device_register(&iommu->iommu);
1654 return pci_enable_device(iommu->dev);
1657 static void print_iommu_info(void)
1659 static const char * const feat_str[] = {
1660 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1661 "IA", "GA", "HE", "PC"
1663 struct amd_iommu *iommu;
1665 for_each_iommu(iommu) {
1668 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1669 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1671 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1672 pr_info("AMD-Vi: Extended features (%#llx):\n",
1674 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1675 if (iommu_feature(iommu, (1ULL << i)))
1676 pr_cont(" %s", feat_str[i]);
1679 if (iommu->features & FEATURE_GAM_VAPIC)
1680 pr_cont(" GA_vAPIC");
1685 if (irq_remapping_enabled) {
1686 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1687 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1688 pr_info("AMD-Vi: virtual APIC enabled\n");
1692 static int __init amd_iommu_init_pci(void)
1694 struct amd_iommu *iommu;
1697 for_each_iommu(iommu) {
1698 ret = iommu_init_pci(iommu);
1704 * Order is important here to make sure any unity map requirements are
1705 * fulfilled. The unity mappings are created and written to the device
1706 * table during the amd_iommu_init_api() call.
1708 * After that we call init_device_table_dma() to make sure any
1709 * uninitialized DTE will block DMA, and in the end we flush the caches
1710 * of all IOMMUs to make sure the changes to the device table are
1713 ret = amd_iommu_init_api();
1715 init_device_table_dma();
1717 for_each_iommu(iommu)
1718 iommu_flush_all_caches(iommu);
1726 /****************************************************************************
1728 * The following functions initialize the MSI interrupts for all IOMMUs
1729 * in the system. It's a bit challenging because there could be multiple
1730 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1733 ****************************************************************************/
1735 static int iommu_setup_msi(struct amd_iommu *iommu)
1739 r = pci_enable_msi(iommu->dev);
1743 r = request_threaded_irq(iommu->dev->irq,
1744 amd_iommu_int_handler,
1745 amd_iommu_int_thread,
1750 pci_disable_msi(iommu->dev);
1754 iommu->int_enabled = true;
1759 static int iommu_init_msi(struct amd_iommu *iommu)
1763 if (iommu->int_enabled)
1766 if (iommu->dev->msi_cap)
1767 ret = iommu_setup_msi(iommu);
1775 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1777 if (iommu->ppr_log != NULL)
1778 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1780 iommu_ga_log_enable(iommu);
1785 /****************************************************************************
1787 * The next functions belong to the third pass of parsing the ACPI
1788 * table. In this last pass the memory mapping requirements are
1789 * gathered (like exclusion and unity mapping ranges).
1791 ****************************************************************************/
1793 static void __init free_unity_maps(void)
1795 struct unity_map_entry *entry, *next;
1797 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1798 list_del(&entry->list);
1803 /* called when we find an exclusion range definition in ACPI */
1804 static int __init init_exclusion_range(struct ivmd_header *m)
1809 case ACPI_IVMD_TYPE:
1810 set_device_exclusion_range(m->devid, m);
1812 case ACPI_IVMD_TYPE_ALL:
1813 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1814 set_device_exclusion_range(i, m);
1816 case ACPI_IVMD_TYPE_RANGE:
1817 for (i = m->devid; i <= m->aux; ++i)
1818 set_device_exclusion_range(i, m);
1827 /* called for unity map ACPI definition */
1828 static int __init init_unity_map_range(struct ivmd_header *m)
1830 struct unity_map_entry *e = NULL;
1833 e = kzalloc(sizeof(*e), GFP_KERNEL);
1841 case ACPI_IVMD_TYPE:
1842 s = "IVMD_TYPEi\t\t\t";
1843 e->devid_start = e->devid_end = m->devid;
1845 case ACPI_IVMD_TYPE_ALL:
1846 s = "IVMD_TYPE_ALL\t\t";
1848 e->devid_end = amd_iommu_last_bdf;
1850 case ACPI_IVMD_TYPE_RANGE:
1851 s = "IVMD_TYPE_RANGE\t\t";
1852 e->devid_start = m->devid;
1853 e->devid_end = m->aux;
1856 e->address_start = PAGE_ALIGN(m->range_start);
1857 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1858 e->prot = m->flags >> 1;
1860 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1861 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1862 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1863 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1864 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1865 e->address_start, e->address_end, m->flags);
1867 list_add_tail(&e->list, &amd_iommu_unity_map);
1872 /* iterates over all memory definitions we find in the ACPI table */
1873 static int __init init_memory_definitions(struct acpi_table_header *table)
1875 u8 *p = (u8 *)table, *end = (u8 *)table;
1876 struct ivmd_header *m;
1878 end += table->length;
1879 p += IVRS_HEADER_LENGTH;
1882 m = (struct ivmd_header *)p;
1883 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1884 init_exclusion_range(m);
1885 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1886 init_unity_map_range(m);
1895 * Init the device table to not allow DMA access for devices and
1896 * suppress all page faults
1898 static void init_device_table_dma(void)
1902 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1903 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1904 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1906 * In kdump kernels in-flight DMA from the old kernel might
1907 * cause IO_PAGE_FAULTs. There are no reports that a kdump
1908 * actually failed because of that, so just disable fault
1909 * reporting in the hardware to get rid of the messages
1911 if (is_kdump_kernel())
1912 set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
1916 static void __init uninit_device_table_dma(void)
1920 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1921 amd_iommu_dev_table[devid].data[0] = 0ULL;
1922 amd_iommu_dev_table[devid].data[1] = 0ULL;
1926 static void init_device_table(void)
1930 if (!amd_iommu_irq_remap)
1933 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1934 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1937 static void iommu_init_flags(struct amd_iommu *iommu)
1939 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1940 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1941 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1943 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1944 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1945 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1947 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1948 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1949 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1951 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1952 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1953 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1956 * make IOMMU memory accesses cache coherent
1958 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1960 /* Set IOTLB invalidation timeout to 1s */
1961 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1964 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1967 u32 ioc_feature_control;
1968 struct pci_dev *pdev = iommu->root_pdev;
1970 /* RD890 BIOSes may not have completely reconfigured the iommu */
1971 if (!is_rd890_iommu(iommu->dev) || !pdev)
1975 * First, we need to ensure that the iommu is enabled. This is
1976 * controlled by a register in the northbridge
1979 /* Select Northbridge indirect register 0x75 and enable writing */
1980 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1981 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1983 /* Enable the iommu */
1984 if (!(ioc_feature_control & 0x1))
1985 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1987 /* Restore the iommu BAR */
1988 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1989 iommu->stored_addr_lo);
1990 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1991 iommu->stored_addr_hi);
1993 /* Restore the l1 indirect regs for each of the 6 l1s */
1994 for (i = 0; i < 6; i++)
1995 for (j = 0; j < 0x12; j++)
1996 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1998 /* Restore the l2 indirect regs */
1999 for (i = 0; i < 0x83; i++)
2000 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2002 /* Lock PCI setup registers */
2003 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2004 iommu->stored_addr_lo | 1);
2007 static void iommu_enable_ga(struct amd_iommu *iommu)
2009 #ifdef CONFIG_IRQ_REMAP
2010 switch (amd_iommu_guest_ir) {
2011 case AMD_IOMMU_GUEST_IR_VAPIC:
2012 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2014 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2015 iommu_feature_enable(iommu, CONTROL_GA_EN);
2016 iommu->irte_ops = &irte_128_ops;
2019 iommu->irte_ops = &irte_32_ops;
2026 * This function finally enables all IOMMUs found in the system after
2027 * they have been initialized
2029 static void early_enable_iommus(void)
2031 struct amd_iommu *iommu;
2033 for_each_iommu(iommu) {
2034 iommu_disable(iommu);
2035 iommu_init_flags(iommu);
2036 iommu_set_device_table(iommu);
2037 iommu_enable_command_buffer(iommu);
2038 iommu_enable_event_buffer(iommu);
2039 iommu_set_exclusion_range(iommu);
2040 iommu_enable_ga(iommu);
2041 iommu_enable(iommu);
2042 iommu_flush_all_caches(iommu);
2045 #ifdef CONFIG_IRQ_REMAP
2046 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2047 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2051 static void enable_iommus_v2(void)
2053 struct amd_iommu *iommu;
2055 for_each_iommu(iommu) {
2056 iommu_enable_ppr_log(iommu);
2057 iommu_enable_gt(iommu);
2061 static void enable_iommus(void)
2063 early_enable_iommus();
2068 static void disable_iommus(void)
2070 struct amd_iommu *iommu;
2072 for_each_iommu(iommu)
2073 iommu_disable(iommu);
2075 #ifdef CONFIG_IRQ_REMAP
2076 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2077 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2082 * Suspend/Resume support
2083 * disable suspend until real resume implemented
2086 static void amd_iommu_resume(void)
2088 struct amd_iommu *iommu;
2090 for_each_iommu(iommu)
2091 iommu_apply_resume_quirks(iommu);
2093 /* re-load the hardware */
2096 amd_iommu_enable_interrupts();
2099 static int amd_iommu_suspend(void)
2101 /* disable IOMMUs to go out of the way for BIOS */
2107 static struct syscore_ops amd_iommu_syscore_ops = {
2108 .suspend = amd_iommu_suspend,
2109 .resume = amd_iommu_resume,
2112 static void __init free_iommu_resources(void)
2114 kmemleak_free(irq_lookup_table);
2115 free_pages((unsigned long)irq_lookup_table,
2116 get_order(rlookup_table_size));
2117 irq_lookup_table = NULL;
2119 kmem_cache_destroy(amd_iommu_irq_cache);
2120 amd_iommu_irq_cache = NULL;
2122 free_pages((unsigned long)amd_iommu_rlookup_table,
2123 get_order(rlookup_table_size));
2124 amd_iommu_rlookup_table = NULL;
2126 free_pages((unsigned long)amd_iommu_alias_table,
2127 get_order(alias_table_size));
2128 amd_iommu_alias_table = NULL;
2130 free_pages((unsigned long)amd_iommu_dev_table,
2131 get_order(dev_table_size));
2132 amd_iommu_dev_table = NULL;
2136 #ifdef CONFIG_GART_IOMMU
2138 * We failed to initialize the AMD IOMMU - try fallback to GART
2146 /* SB IOAPIC is always on this device in AMD systems */
2147 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2149 static bool __init check_ioapic_information(void)
2151 const char *fw_bug = FW_BUG;
2152 bool ret, has_sb_ioapic;
2155 has_sb_ioapic = false;
2159 * If we have map overrides on the kernel command line the
2160 * messages in this function might not describe firmware bugs
2161 * anymore - so be careful
2166 for (idx = 0; idx < nr_ioapics; idx++) {
2167 int devid, id = mpc_ioapic_id(idx);
2169 devid = get_ioapic_devid(id);
2171 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2174 } else if (devid == IOAPIC_SB_DEVID) {
2175 has_sb_ioapic = true;
2180 if (!has_sb_ioapic) {
2182 * We expect the SB IOAPIC to be listed in the IVRS
2183 * table. The system timer is connected to the SB IOAPIC
2184 * and if we don't have it in the list the system will
2185 * panic at boot time. This situation usually happens
2186 * when the BIOS is buggy and provides us the wrong
2187 * device id for the IOAPIC in the system.
2189 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2193 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2198 static void __init free_dma_resources(void)
2200 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2201 get_order(MAX_DOMAIN_ID/8));
2202 amd_iommu_pd_alloc_bitmap = NULL;
2208 * This is the hardware init function for AMD IOMMU in the system.
2209 * This function is called either from amd_iommu_init or from the interrupt
2210 * remapping setup code.
2212 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2215 * 1 pass) Discover the most comprehensive IVHD type to use.
2217 * 2 pass) Find the highest PCI device id the driver has to handle.
2218 * Upon this information the size of the data structures is
2219 * determined that needs to be allocated.
2221 * 3 pass) Initialize the data structures just allocated with the
2222 * information in the ACPI table about available AMD IOMMUs
2223 * in the system. It also maps the PCI devices in the
2224 * system to specific IOMMUs
2226 * 4 pass) After the basic data structures are allocated and
2227 * initialized we update them with information about memory
2228 * remapping requirements parsed out of the ACPI table in
2231 * After everything is set up the IOMMUs are enabled and the necessary
2232 * hotplug and suspend notifiers are registered.
2234 static int __init early_amd_iommu_init(void)
2236 struct acpi_table_header *ivrs_base;
2238 int i, remap_cache_sz, ret = 0;
2240 if (!amd_iommu_detected)
2243 status = acpi_get_table("IVRS", 0, &ivrs_base);
2244 if (status == AE_NOT_FOUND)
2246 else if (ACPI_FAILURE(status)) {
2247 const char *err = acpi_format_exception(status);
2248 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2253 * Validate checksum here so we don't need to do it when
2254 * we actually parse the table
2256 ret = check_ivrs_checksum(ivrs_base);
2260 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2261 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2264 * First parse ACPI tables to find the largest Bus/Dev/Func
2265 * we need to handle. Upon this information the shared data
2266 * structures for the IOMMUs in the system will be allocated
2268 ret = find_last_devid_acpi(ivrs_base);
2272 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2273 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2274 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2276 /* Device table - directly used by all IOMMUs */
2278 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
2279 get_order(dev_table_size));
2280 if (amd_iommu_dev_table == NULL)
2284 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2285 * IOMMU see for that device
2287 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2288 get_order(alias_table_size));
2289 if (amd_iommu_alias_table == NULL)
2292 /* IOMMU rlookup table - find the IOMMU for a specific device */
2293 amd_iommu_rlookup_table = (void *)__get_free_pages(
2294 GFP_KERNEL | __GFP_ZERO,
2295 get_order(rlookup_table_size));
2296 if (amd_iommu_rlookup_table == NULL)
2299 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2300 GFP_KERNEL | __GFP_ZERO,
2301 get_order(MAX_DOMAIN_ID/8));
2302 if (amd_iommu_pd_alloc_bitmap == NULL)
2306 * let all alias entries point to itself
2308 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2309 amd_iommu_alias_table[i] = i;
2312 * never allocate domain 0 because its used as the non-allocated and
2313 * error value placeholder
2315 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2317 spin_lock_init(&amd_iommu_pd_lock);
2320 * now the data structures are allocated and basically initialized
2321 * start the real acpi table scan
2323 ret = init_iommu_all(ivrs_base);
2327 /* Disable any previously enabled IOMMUs */
2330 if (amd_iommu_irq_remap)
2331 amd_iommu_irq_remap = check_ioapic_information();
2333 if (amd_iommu_irq_remap) {
2335 * Interrupt remapping enabled, create kmem_cache for the
2339 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2340 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2342 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2343 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2345 IRQ_TABLE_ALIGNMENT,
2347 if (!amd_iommu_irq_cache)
2350 irq_lookup_table = (void *)__get_free_pages(
2351 GFP_KERNEL | __GFP_ZERO,
2352 get_order(rlookup_table_size));
2353 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2355 if (!irq_lookup_table)
2359 ret = init_memory_definitions(ivrs_base);
2363 /* init the device table */
2364 init_device_table();
2367 /* Don't leak any ACPI memory */
2368 acpi_put_table(ivrs_base);
2374 static int amd_iommu_enable_interrupts(void)
2376 struct amd_iommu *iommu;
2379 for_each_iommu(iommu) {
2380 ret = iommu_init_msi(iommu);
2389 static bool detect_ivrs(void)
2391 struct acpi_table_header *ivrs_base;
2394 status = acpi_get_table("IVRS", 0, &ivrs_base);
2395 if (status == AE_NOT_FOUND)
2397 else if (ACPI_FAILURE(status)) {
2398 const char *err = acpi_format_exception(status);
2399 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2403 acpi_put_table(ivrs_base);
2405 /* Make sure ACS will be enabled during PCI probe */
2411 /****************************************************************************
2413 * AMD IOMMU Initialization State Machine
2415 ****************************************************************************/
2417 static int __init state_next(void)
2421 switch (init_state) {
2422 case IOMMU_START_STATE:
2423 if (!detect_ivrs()) {
2424 init_state = IOMMU_NOT_FOUND;
2427 init_state = IOMMU_IVRS_DETECTED;
2430 case IOMMU_IVRS_DETECTED:
2431 ret = early_amd_iommu_init();
2432 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2433 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2434 pr_info("AMD-Vi: AMD IOMMU disabled on kernel command-line\n");
2435 free_dma_resources();
2436 free_iommu_resources();
2437 init_state = IOMMU_CMDLINE_DISABLED;
2441 case IOMMU_ACPI_FINISHED:
2442 early_enable_iommus();
2443 register_syscore_ops(&amd_iommu_syscore_ops);
2444 x86_platform.iommu_shutdown = disable_iommus;
2445 init_state = IOMMU_ENABLED;
2448 ret = amd_iommu_init_pci();
2449 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2452 case IOMMU_PCI_INIT:
2453 ret = amd_iommu_enable_interrupts();
2454 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2456 case IOMMU_INTERRUPTS_EN:
2457 ret = amd_iommu_init_dma_ops();
2458 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2461 init_state = IOMMU_INITIALIZED;
2463 case IOMMU_INITIALIZED:
2466 case IOMMU_NOT_FOUND:
2467 case IOMMU_INIT_ERROR:
2468 case IOMMU_CMDLINE_DISABLED:
2469 /* Error states => do nothing */
2480 static int __init iommu_go_to_state(enum iommu_init_state state)
2484 while (init_state != state) {
2485 if (init_state == IOMMU_NOT_FOUND ||
2486 init_state == IOMMU_INIT_ERROR ||
2487 init_state == IOMMU_CMDLINE_DISABLED)
2495 #ifdef CONFIG_IRQ_REMAP
2496 int __init amd_iommu_prepare(void)
2500 amd_iommu_irq_remap = true;
2502 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2505 return amd_iommu_irq_remap ? 0 : -ENODEV;
2508 int __init amd_iommu_enable(void)
2512 ret = iommu_go_to_state(IOMMU_ENABLED);
2516 irq_remapping_enabled = 1;
2521 void amd_iommu_disable(void)
2523 amd_iommu_suspend();
2526 int amd_iommu_reenable(int mode)
2533 int __init amd_iommu_enable_faulting(void)
2535 /* We enable MSI later when PCI is initialized */
2541 * This is the core init function for AMD IOMMU hardware in the system.
2542 * This function is called from the generic x86 DMA layer initialization
2545 static int __init amd_iommu_init(void)
2549 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2551 free_dma_resources();
2552 if (!irq_remapping_enabled) {
2554 free_iommu_resources();
2556 struct amd_iommu *iommu;
2558 uninit_device_table_dma();
2559 for_each_iommu(iommu)
2560 iommu_flush_all_caches(iommu);
2567 /****************************************************************************
2569 * Early detect code. This code runs at IOMMU detection time in the DMA
2570 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2573 ****************************************************************************/
2574 int __init amd_iommu_detect(void)
2578 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2581 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2585 amd_iommu_detected = true;
2587 x86_init.iommu.iommu_init = amd_iommu_init;
2592 /****************************************************************************
2594 * Parsing functions for the AMD IOMMU specific kernel command line
2597 ****************************************************************************/
2599 static int __init parse_amd_iommu_dump(char *str)
2601 amd_iommu_dump = true;
2606 static int __init parse_amd_iommu_intr(char *str)
2608 for (; *str; ++str) {
2609 if (strncmp(str, "legacy", 6) == 0) {
2610 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2613 if (strncmp(str, "vapic", 5) == 0) {
2614 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2621 static int __init parse_amd_iommu_options(char *str)
2623 for (; *str; ++str) {
2624 if (strncmp(str, "fullflush", 9) == 0)
2625 amd_iommu_unmap_flush = true;
2626 if (strncmp(str, "off", 3) == 0)
2627 amd_iommu_disabled = true;
2628 if (strncmp(str, "force_isolation", 15) == 0)
2629 amd_iommu_force_isolation = true;
2635 static int __init parse_ivrs_ioapic(char *str)
2637 unsigned int bus, dev, fn;
2641 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2644 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2648 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2649 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2654 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2656 cmdline_maps = true;
2657 i = early_ioapic_map_size++;
2658 early_ioapic_map[i].id = id;
2659 early_ioapic_map[i].devid = devid;
2660 early_ioapic_map[i].cmd_line = true;
2665 static int __init parse_ivrs_hpet(char *str)
2667 unsigned int bus, dev, fn;
2671 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2674 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2678 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2679 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2684 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2686 cmdline_maps = true;
2687 i = early_hpet_map_size++;
2688 early_hpet_map[i].id = id;
2689 early_hpet_map[i].devid = devid;
2690 early_hpet_map[i].cmd_line = true;
2695 static int __init parse_ivrs_acpihid(char *str)
2698 char *hid, *uid, *p;
2699 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2702 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2704 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2709 hid = strsep(&p, ":");
2712 if (!hid || !(*hid) || !uid) {
2713 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2717 i = early_acpihid_map_size++;
2718 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2719 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2720 early_acpihid_map[i].devid =
2721 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2722 early_acpihid_map[i].cmd_line = true;
2727 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2728 __setup("amd_iommu=", parse_amd_iommu_options);
2729 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2730 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2731 __setup("ivrs_hpet", parse_ivrs_hpet);
2732 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2734 IOMMU_INIT_FINISH(amd_iommu_detect,
2735 gart_iommu_hole_init,
2739 bool amd_iommu_v2_supported(void)
2741 return amd_iommu_v2_present;
2743 EXPORT_SYMBOL(amd_iommu_v2_supported);
2745 struct amd_iommu *get_amd_iommu(unsigned int idx)
2748 struct amd_iommu *iommu;
2750 for_each_iommu(iommu)
2755 EXPORT_SYMBOL(get_amd_iommu);
2757 /****************************************************************************
2759 * IOMMU EFR Performance Counter support functionality. This code allows
2760 * access to the IOMMU PC functionality.
2762 ****************************************************************************/
2764 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
2766 struct amd_iommu *iommu = get_amd_iommu(idx);
2769 return iommu->max_banks;
2773 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2775 bool amd_iommu_pc_supported(void)
2777 return amd_iommu_pc_present;
2779 EXPORT_SYMBOL(amd_iommu_pc_supported);
2781 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
2783 struct amd_iommu *iommu = get_amd_iommu(idx);
2786 return iommu->max_counters;
2790 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2792 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
2793 u8 fxn, u64 *value, bool is_write)
2798 /* Make sure the IOMMU PC resource is available */
2799 if (!amd_iommu_pc_present)
2802 /* Check for valid iommu and pc register indexing */
2803 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
2806 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
2808 /* Limit the offset to the hw defined mmio region aperture */
2809 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
2810 (iommu->max_counters << 8) | 0x28);
2811 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2812 (offset > max_offset_lim))
2816 u64 val = *value & GENMASK_ULL(47, 0);
2818 writel((u32)val, iommu->mmio_base + offset);
2819 writel((val >> 32), iommu->mmio_base + offset + 4);
2821 *value = readl(iommu->mmio_base + offset + 4);
2823 *value |= readl(iommu->mmio_base + offset);
2824 *value &= GENMASK_ULL(47, 0);
2830 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
2835 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
2837 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
2839 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
2844 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
2846 EXPORT_SYMBOL(amd_iommu_pc_set_reg);