1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/pci.h>
12 #include <linux/acpi.h>
13 #include <linux/list.h>
14 #include <linux/bitmap.h>
15 #include <linux/slab.h>
16 #include <linux/syscore_ops.h>
17 #include <linux/interrupt.h>
18 #include <linux/msi.h>
19 #include <linux/amd-iommu.h>
20 #include <linux/export.h>
21 #include <linux/iommu.h>
22 #include <linux/kmemleak.h>
23 #include <linux/mem_encrypt.h>
24 #include <asm/pci-direct.h>
25 #include <asm/iommu.h>
27 #include <asm/x86_init.h>
28 #include <asm/iommu_table.h>
29 #include <asm/io_apic.h>
30 #include <asm/irq_remapping.h>
32 #include <linux/crash_dump.h>
33 #include "amd_iommu_proto.h"
34 #include "amd_iommu_types.h"
35 #include "irq_remapping.h"
38 * definitions for the ACPI scanning code
40 #define IVRS_HEADER_LENGTH 48
42 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
43 #define ACPI_IVMD_TYPE_ALL 0x20
44 #define ACPI_IVMD_TYPE 0x21
45 #define ACPI_IVMD_TYPE_RANGE 0x22
47 #define IVHD_DEV_ALL 0x01
48 #define IVHD_DEV_SELECT 0x02
49 #define IVHD_DEV_SELECT_RANGE_START 0x03
50 #define IVHD_DEV_RANGE_END 0x04
51 #define IVHD_DEV_ALIAS 0x42
52 #define IVHD_DEV_ALIAS_RANGE 0x43
53 #define IVHD_DEV_EXT_SELECT 0x46
54 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
55 #define IVHD_DEV_SPECIAL 0x48
56 #define IVHD_DEV_ACPI_HID 0xf0
58 #define UID_NOT_PRESENT 0
59 #define UID_IS_INTEGER 1
60 #define UID_IS_CHARACTER 2
62 #define IVHD_SPECIAL_IOAPIC 1
63 #define IVHD_SPECIAL_HPET 2
65 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
66 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
67 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
68 #define IVHD_FLAG_ISOC_EN_MASK 0x08
70 #define IVMD_FLAG_EXCL_RANGE 0x08
71 #define IVMD_FLAG_UNITY_MAP 0x01
73 #define ACPI_DEVFLAG_INITPASS 0x01
74 #define ACPI_DEVFLAG_EXTINT 0x02
75 #define ACPI_DEVFLAG_NMI 0x04
76 #define ACPI_DEVFLAG_SYSMGT1 0x10
77 #define ACPI_DEVFLAG_SYSMGT2 0x20
78 #define ACPI_DEVFLAG_LINT0 0x40
79 #define ACPI_DEVFLAG_LINT1 0x80
80 #define ACPI_DEVFLAG_ATSDIS 0x10000000
82 #define LOOP_TIMEOUT 100000
84 * ACPI table definitions
86 * These data structures are laid over the table to parse the important values
90 extern const struct iommu_ops amd_iommu_ops;
93 * structure describing one IOMMU in the ACPI table. Typically followed by one
94 * or more ivhd_entrys.
107 /* Following only valid on IVHD type 11h and 40h */
108 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
110 } __attribute__((packed));
113 * A device entry describing which devices a specific IOMMU translates and
114 * which requestor ids they use.
126 } __attribute__((packed));
129 * An AMD IOMMU memory definition structure. It defines things like exclusion
130 * ranges for devices and regions that should be unity mapped.
141 } __attribute__((packed));
144 bool amd_iommu_irq_remap __read_mostly;
146 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
147 static int amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
149 static bool amd_iommu_detected;
150 static bool __initdata amd_iommu_disabled;
151 static int amd_iommu_target_ivhd_type;
153 u16 amd_iommu_last_bdf; /* largest PCI device id we have
155 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
157 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
159 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
162 /* Array to assign indices to IOMMUs*/
163 struct amd_iommu *amd_iommus[MAX_IOMMUS];
165 /* Number of IOMMUs present in the system */
166 static int amd_iommus_present;
168 /* IOMMUs have a non-present cache? */
169 bool amd_iommu_np_cache __read_mostly;
170 bool amd_iommu_iotlb_sup __read_mostly = true;
172 u32 amd_iommu_max_pasid __read_mostly = ~0;
174 bool amd_iommu_v2_present __read_mostly;
175 static bool amd_iommu_pc_present __read_mostly;
177 bool amd_iommu_force_isolation __read_mostly;
180 * Pointer to the device table which is shared by all AMD IOMMUs
181 * it is indexed by the PCI device id or the HT unit id and contains
182 * information about the domain the device belongs to as well as the
183 * page table root pointer.
185 struct dev_table_entry *amd_iommu_dev_table;
187 * Pointer to a device table which the content of old device table
188 * will be copied to. It's only be used in kdump kernel.
190 static struct dev_table_entry *old_dev_tbl_cpy;
193 * The alias table is a driver specific data structure which contains the
194 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
195 * More than one device can share the same requestor id.
197 u16 *amd_iommu_alias_table;
200 * The rlookup table is used to find the IOMMU which is responsible
201 * for a specific device. It is also indexed by the PCI device id.
203 struct amd_iommu **amd_iommu_rlookup_table;
204 EXPORT_SYMBOL(amd_iommu_rlookup_table);
207 * This table is used to find the irq remapping table for a given device id
210 struct irq_remap_table **irq_lookup_table;
213 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
214 * to know which ones are already in use.
216 unsigned long *amd_iommu_pd_alloc_bitmap;
218 static u32 dev_table_size; /* size of the device table */
219 static u32 alias_table_size; /* size of the alias table */
220 static u32 rlookup_table_size; /* size if the rlookup table */
222 enum iommu_init_state {
233 IOMMU_CMDLINE_DISABLED,
236 /* Early ioapic and hpet maps from kernel command line */
237 #define EARLY_MAP_SIZE 4
238 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
239 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
240 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
242 static int __initdata early_ioapic_map_size;
243 static int __initdata early_hpet_map_size;
244 static int __initdata early_acpihid_map_size;
246 static bool __initdata cmdline_maps;
248 static enum iommu_init_state init_state = IOMMU_START_STATE;
250 static int amd_iommu_enable_interrupts(void);
251 static int __init iommu_go_to_state(enum iommu_init_state state);
252 static void init_device_table_dma(void);
254 static bool amd_iommu_pre_enabled = true;
256 bool translation_pre_enabled(struct amd_iommu *iommu)
258 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
260 EXPORT_SYMBOL(translation_pre_enabled);
262 static void clear_translation_pre_enabled(struct amd_iommu *iommu)
264 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
267 static void init_translation_status(struct amd_iommu *iommu)
271 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
272 if (ctrl & (1<<CONTROL_IOMMU_EN))
273 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
276 static inline void update_last_devid(u16 devid)
278 if (devid > amd_iommu_last_bdf)
279 amd_iommu_last_bdf = devid;
282 static inline unsigned long tbl_size(int entry_size)
284 unsigned shift = PAGE_SHIFT +
285 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
290 int amd_iommu_get_num_iommus(void)
292 return amd_iommus_present;
295 /* Access to l1 and l2 indexed register spaces */
297 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
301 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
302 pci_read_config_dword(iommu->dev, 0xfc, &val);
306 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
308 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
309 pci_write_config_dword(iommu->dev, 0xfc, val);
310 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
313 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
317 pci_write_config_dword(iommu->dev, 0xf0, address);
318 pci_read_config_dword(iommu->dev, 0xf4, &val);
322 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
324 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
325 pci_write_config_dword(iommu->dev, 0xf4, val);
328 /****************************************************************************
330 * AMD IOMMU MMIO register space handling functions
332 * These functions are used to program the IOMMU device registers in
333 * MMIO space required for that driver.
335 ****************************************************************************/
338 * This function set the exclusion range in the IOMMU. DMA accesses to the
339 * exclusion range are passed through untranslated
341 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
343 u64 start = iommu->exclusion_start & PAGE_MASK;
344 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
347 if (!iommu->exclusion_start)
350 entry = start | MMIO_EXCL_ENABLE_MASK;
351 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
352 &entry, sizeof(entry));
355 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
356 &entry, sizeof(entry));
359 /* Programs the physical address of the device table into the IOMMU hardware */
360 static void iommu_set_device_table(struct amd_iommu *iommu)
364 BUG_ON(iommu->mmio_base == NULL);
366 entry = iommu_virt_to_phys(amd_iommu_dev_table);
367 entry |= (dev_table_size >> 12) - 1;
368 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
369 &entry, sizeof(entry));
372 /* Generic functions to enable/disable certain features of the IOMMU. */
373 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
377 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
378 ctrl |= (1ULL << bit);
379 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
382 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
386 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
387 ctrl &= ~(1ULL << bit);
388 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
391 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
395 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
396 ctrl &= ~CTRL_INV_TO_MASK;
397 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
398 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
401 /* Function to enable the hardware */
402 static void iommu_enable(struct amd_iommu *iommu)
404 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
407 static void iommu_disable(struct amd_iommu *iommu)
409 /* Disable command buffer */
410 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
412 /* Disable event logging and event interrupts */
413 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
414 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
416 /* Disable IOMMU GA_LOG */
417 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
418 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
420 /* Disable IOMMU hardware itself */
421 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
425 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
426 * the system has one.
428 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
430 if (!request_mem_region(address, end, "amd_iommu")) {
431 pr_err("Can not reserve memory region %llx-%llx for mmio\n",
433 pr_err("This is a BIOS bug. Please contact your hardware vendor\n");
437 return (u8 __iomem *)ioremap_nocache(address, end);
440 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
442 if (iommu->mmio_base)
443 iounmap(iommu->mmio_base);
444 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
447 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
463 /****************************************************************************
465 * The functions below belong to the first pass of AMD IOMMU ACPI table
466 * parsing. In this pass we try to find out the highest device id this
467 * code has to handle. Upon this information the size of the shared data
468 * structures is determined later.
470 ****************************************************************************/
473 * This function calculates the length of a given IVHD entry
475 static inline int ivhd_entry_length(u8 *ivhd)
477 u32 type = ((struct ivhd_entry *)ivhd)->type;
480 return 0x04 << (*ivhd >> 6);
481 } else if (type == IVHD_DEV_ACPI_HID) {
482 /* For ACPI_HID, offset 21 is uid len */
483 return *((u8 *)ivhd + 21) + 22;
489 * After reading the highest device id from the IOMMU PCI capability header
490 * this function looks if there is a higher device id defined in the ACPI table
492 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
494 u8 *p = (void *)h, *end = (void *)h;
495 struct ivhd_entry *dev;
497 u32 ivhd_size = get_ivhd_header_size(h);
500 pr_err("Unsupported IVHD type %#x\n", h->type);
508 dev = (struct ivhd_entry *)p;
511 /* Use maximum BDF value for DEV_ALL */
512 update_last_devid(0xffff);
514 case IVHD_DEV_SELECT:
515 case IVHD_DEV_RANGE_END:
517 case IVHD_DEV_EXT_SELECT:
518 /* all the above subfield types refer to device ids */
519 update_last_devid(dev->devid);
524 p += ivhd_entry_length(p);
532 static int __init check_ivrs_checksum(struct acpi_table_header *table)
535 u8 checksum = 0, *p = (u8 *)table;
537 for (i = 0; i < table->length; ++i)
540 /* ACPI table corrupt */
541 pr_err(FW_BUG "IVRS invalid checksum\n");
549 * Iterate over all IVHD entries in the ACPI table and find the highest device
550 * id which we need to handle. This is the first of three functions which parse
551 * the ACPI table. So we check the checksum here.
553 static int __init find_last_devid_acpi(struct acpi_table_header *table)
555 u8 *p = (u8 *)table, *end = (u8 *)table;
556 struct ivhd_header *h;
558 p += IVRS_HEADER_LENGTH;
560 end += table->length;
562 h = (struct ivhd_header *)p;
563 if (h->type == amd_iommu_target_ivhd_type) {
564 int ret = find_last_devid_from_ivhd(h);
576 /****************************************************************************
578 * The following functions belong to the code path which parses the ACPI table
579 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
580 * data structures, initialize the device/alias/rlookup table and also
581 * basically initialize the hardware.
583 ****************************************************************************/
586 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
587 * write commands to that buffer later and the IOMMU will execute them
590 static int __init alloc_command_buffer(struct amd_iommu *iommu)
592 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
593 get_order(CMD_BUFFER_SIZE));
595 return iommu->cmd_buf ? 0 : -ENOMEM;
599 * This function resets the command buffer if the IOMMU stopped fetching
602 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
604 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
606 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
607 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
608 iommu->cmd_buf_head = 0;
609 iommu->cmd_buf_tail = 0;
611 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
615 * This function writes the command buffer address to the hardware and
618 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
622 BUG_ON(iommu->cmd_buf == NULL);
624 entry = iommu_virt_to_phys(iommu->cmd_buf);
625 entry |= MMIO_CMD_SIZE_512;
627 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
628 &entry, sizeof(entry));
630 amd_iommu_reset_cmd_buffer(iommu);
634 * This function disables the command buffer
636 static void iommu_disable_command_buffer(struct amd_iommu *iommu)
638 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
641 static void __init free_command_buffer(struct amd_iommu *iommu)
643 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
646 /* allocates the memory where the IOMMU will log its events to */
647 static int __init alloc_event_buffer(struct amd_iommu *iommu)
649 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
650 get_order(EVT_BUFFER_SIZE));
652 return iommu->evt_buf ? 0 : -ENOMEM;
655 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
659 BUG_ON(iommu->evt_buf == NULL);
661 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
663 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
664 &entry, sizeof(entry));
666 /* set head and tail to zero manually */
667 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
668 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
670 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
674 * This function disables the event log buffer
676 static void iommu_disable_event_buffer(struct amd_iommu *iommu)
678 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
681 static void __init free_event_buffer(struct amd_iommu *iommu)
683 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
686 /* allocates the memory where the IOMMU will log its events to */
687 static int __init alloc_ppr_log(struct amd_iommu *iommu)
689 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
690 get_order(PPR_LOG_SIZE));
692 return iommu->ppr_log ? 0 : -ENOMEM;
695 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
699 if (iommu->ppr_log == NULL)
702 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
704 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
705 &entry, sizeof(entry));
707 /* set head and tail to zero manually */
708 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
709 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
711 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
712 iommu_feature_enable(iommu, CONTROL_PPR_EN);
715 static void __init free_ppr_log(struct amd_iommu *iommu)
717 if (iommu->ppr_log == NULL)
720 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
723 static void free_ga_log(struct amd_iommu *iommu)
725 #ifdef CONFIG_IRQ_REMAP
727 free_pages((unsigned long)iommu->ga_log,
728 get_order(GA_LOG_SIZE));
729 if (iommu->ga_log_tail)
730 free_pages((unsigned long)iommu->ga_log_tail,
735 static int iommu_ga_log_enable(struct amd_iommu *iommu)
737 #ifdef CONFIG_IRQ_REMAP
743 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
745 /* Check if already running */
746 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
749 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
750 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
752 for (i = 0; i < LOOP_TIMEOUT; ++i) {
753 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
754 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
758 if (i >= LOOP_TIMEOUT)
760 #endif /* CONFIG_IRQ_REMAP */
764 #ifdef CONFIG_IRQ_REMAP
765 static int iommu_init_ga_log(struct amd_iommu *iommu)
769 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
772 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
773 get_order(GA_LOG_SIZE));
777 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
779 if (!iommu->ga_log_tail)
782 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
783 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
784 &entry, sizeof(entry));
785 entry = (iommu_virt_to_phys(iommu->ga_log_tail) &
786 (BIT_ULL(52)-1)) & ~7ULL;
787 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
788 &entry, sizeof(entry));
789 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
790 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
797 #endif /* CONFIG_IRQ_REMAP */
799 static int iommu_init_ga(struct amd_iommu *iommu)
803 #ifdef CONFIG_IRQ_REMAP
804 /* Note: We have already checked GASup from IVRS table.
805 * Now, we need to make sure that GAMSup is set.
807 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
808 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
809 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
811 ret = iommu_init_ga_log(iommu);
812 #endif /* CONFIG_IRQ_REMAP */
817 static void iommu_enable_xt(struct amd_iommu *iommu)
819 #ifdef CONFIG_IRQ_REMAP
821 * XT mode (32-bit APIC destination ID) requires
822 * GA mode (128-bit IRTE support) as a prerequisite.
824 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
825 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
826 iommu_feature_enable(iommu, CONTROL_XT_EN);
827 #endif /* CONFIG_IRQ_REMAP */
830 static void iommu_enable_gt(struct amd_iommu *iommu)
832 if (!iommu_feature(iommu, FEATURE_GT))
835 iommu_feature_enable(iommu, CONTROL_GT_EN);
838 /* sets a specific bit in the device table entry. */
839 static void set_dev_entry_bit(u16 devid, u8 bit)
841 int i = (bit >> 6) & 0x03;
842 int _bit = bit & 0x3f;
844 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
847 static int get_dev_entry_bit(u16 devid, u8 bit)
849 int i = (bit >> 6) & 0x03;
850 int _bit = bit & 0x3f;
852 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
856 static bool copy_device_table(void)
858 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
859 struct dev_table_entry *old_devtb = NULL;
860 u32 lo, hi, devid, old_devtb_size;
861 phys_addr_t old_devtb_phys;
862 struct amd_iommu *iommu;
863 u16 dom_id, dte_v, irq_v;
867 if (!amd_iommu_pre_enabled)
870 pr_warn("Translation is already enabled - trying to copy translation structures\n");
871 for_each_iommu(iommu) {
872 /* All IOMMUs should use the same device table with the same size */
873 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
874 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
875 entry = (((u64) hi) << 32) + lo;
876 if (last_entry && last_entry != entry) {
877 pr_err("IOMMU:%d should use the same dev table as others!\n",
883 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
884 if (old_devtb_size != dev_table_size) {
885 pr_err("The device table size of IOMMU:%d is not expected!\n",
892 * When SME is enabled in the first kernel, the entry includes the
893 * memory encryption mask(sme_me_mask), we must remove the memory
894 * encryption mask to obtain the true physical address in kdump kernel.
896 old_devtb_phys = __sme_clr(entry) & PAGE_MASK;
898 if (old_devtb_phys >= 0x100000000ULL) {
899 pr_err("The address of old device table is above 4G, not trustworthy!\n");
902 old_devtb = (sme_active() && is_kdump_kernel())
903 ? (__force void *)ioremap_encrypted(old_devtb_phys,
905 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
910 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
911 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
912 get_order(dev_table_size));
913 if (old_dev_tbl_cpy == NULL) {
914 pr_err("Failed to allocate memory for copying old device table!\n");
918 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
919 old_dev_tbl_cpy[devid] = old_devtb[devid];
920 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
921 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
923 if (dte_v && dom_id) {
924 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
925 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
926 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
927 /* If gcr3 table existed, mask it out */
928 if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
929 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
930 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
931 old_dev_tbl_cpy[devid].data[1] &= ~tmp;
932 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
934 old_dev_tbl_cpy[devid].data[0] &= ~tmp;
938 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
939 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
940 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK;
941 if (irq_v && (int_ctl || int_tab_len)) {
942 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
943 (int_tab_len != DTE_IRQ_TABLE_LEN)) {
944 pr_err("Wrong old irq remapping flag: %#x\n", devid);
948 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
956 void amd_iommu_apply_erratum_63(u16 devid)
960 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
961 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
964 set_dev_entry_bit(devid, DEV_ENTRY_IW);
967 /* Writes the specific IOMMU for a device into the rlookup table */
968 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
970 amd_iommu_rlookup_table[devid] = iommu;
974 * This function takes the device specific flags read from the ACPI
975 * table and sets up the device table entry with that information
977 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
978 u16 devid, u32 flags, u32 ext_flags)
980 if (flags & ACPI_DEVFLAG_INITPASS)
981 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
982 if (flags & ACPI_DEVFLAG_EXTINT)
983 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
984 if (flags & ACPI_DEVFLAG_NMI)
985 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
986 if (flags & ACPI_DEVFLAG_SYSMGT1)
987 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
988 if (flags & ACPI_DEVFLAG_SYSMGT2)
989 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
990 if (flags & ACPI_DEVFLAG_LINT0)
991 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
992 if (flags & ACPI_DEVFLAG_LINT1)
993 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
995 amd_iommu_apply_erratum_63(devid);
997 set_iommu_for_device(iommu, devid);
1000 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
1002 struct devid_map *entry;
1003 struct list_head *list;
1005 if (type == IVHD_SPECIAL_IOAPIC)
1007 else if (type == IVHD_SPECIAL_HPET)
1012 list_for_each_entry(entry, list, list) {
1013 if (!(entry->id == id && entry->cmd_line))
1016 pr_info("Command-line override present for %s id %d - ignoring\n",
1017 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
1019 *devid = entry->devid;
1024 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1029 entry->devid = *devid;
1030 entry->cmd_line = cmd_line;
1032 list_add_tail(&entry->list, list);
1037 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
1040 struct acpihid_map_entry *entry;
1041 struct list_head *list = &acpihid_map;
1043 list_for_each_entry(entry, list, list) {
1044 if (strcmp(entry->hid, hid) ||
1045 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
1049 pr_info("Command-line override for hid:%s uid:%s\n",
1051 *devid = entry->devid;
1055 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1059 memcpy(entry->uid, uid, strlen(uid));
1060 memcpy(entry->hid, hid, strlen(hid));
1061 entry->devid = *devid;
1062 entry->cmd_line = cmd_line;
1063 entry->root_devid = (entry->devid & (~0x7));
1065 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n",
1066 entry->cmd_line ? "cmd" : "ivrs",
1067 entry->hid, entry->uid, entry->root_devid);
1069 list_add_tail(&entry->list, list);
1073 static int __init add_early_maps(void)
1077 for (i = 0; i < early_ioapic_map_size; ++i) {
1078 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
1079 early_ioapic_map[i].id,
1080 &early_ioapic_map[i].devid,
1081 early_ioapic_map[i].cmd_line);
1086 for (i = 0; i < early_hpet_map_size; ++i) {
1087 ret = add_special_device(IVHD_SPECIAL_HPET,
1088 early_hpet_map[i].id,
1089 &early_hpet_map[i].devid,
1090 early_hpet_map[i].cmd_line);
1095 for (i = 0; i < early_acpihid_map_size; ++i) {
1096 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
1097 early_acpihid_map[i].uid,
1098 &early_acpihid_map[i].devid,
1099 early_acpihid_map[i].cmd_line);
1108 * Reads the device exclusion range from ACPI and initializes the IOMMU with
1111 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
1113 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1115 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
1120 * We only can configure exclusion ranges per IOMMU, not
1121 * per device. But we can enable the exclusion range per
1122 * device. This is done here
1124 set_dev_entry_bit(devid, DEV_ENTRY_EX);
1125 iommu->exclusion_start = m->range_start;
1126 iommu->exclusion_length = m->range_length;
1131 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1132 * initializes the hardware and our data structures with it.
1134 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
1135 struct ivhd_header *h)
1138 u8 *end = p, flags = 0;
1139 u16 devid = 0, devid_start = 0, devid_to = 0;
1140 u32 dev_i, ext_flags = 0;
1142 struct ivhd_entry *e;
1147 ret = add_early_maps();
1152 * First save the recommended feature enable bits from ACPI
1154 iommu->acpi_flags = h->flags;
1157 * Done. Now parse the device entries
1159 ivhd_size = get_ivhd_header_size(h);
1161 pr_err("Unsupported IVHD type %#x\n", h->type);
1171 e = (struct ivhd_entry *)p;
1175 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1177 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1178 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1180 case IVHD_DEV_SELECT:
1182 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1184 PCI_BUS_NUM(e->devid),
1190 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1192 case IVHD_DEV_SELECT_RANGE_START:
1194 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1195 "devid: %02x:%02x.%x flags: %02x\n",
1196 PCI_BUS_NUM(e->devid),
1201 devid_start = e->devid;
1206 case IVHD_DEV_ALIAS:
1208 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1209 "flags: %02x devid_to: %02x:%02x.%x\n",
1210 PCI_BUS_NUM(e->devid),
1214 PCI_BUS_NUM(e->ext >> 8),
1215 PCI_SLOT(e->ext >> 8),
1216 PCI_FUNC(e->ext >> 8));
1219 devid_to = e->ext >> 8;
1220 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1221 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1222 amd_iommu_alias_table[devid] = devid_to;
1224 case IVHD_DEV_ALIAS_RANGE:
1226 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1227 "devid: %02x:%02x.%x flags: %02x "
1228 "devid_to: %02x:%02x.%x\n",
1229 PCI_BUS_NUM(e->devid),
1233 PCI_BUS_NUM(e->ext >> 8),
1234 PCI_SLOT(e->ext >> 8),
1235 PCI_FUNC(e->ext >> 8));
1237 devid_start = e->devid;
1239 devid_to = e->ext >> 8;
1243 case IVHD_DEV_EXT_SELECT:
1245 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1246 "flags: %02x ext: %08x\n",
1247 PCI_BUS_NUM(e->devid),
1253 set_dev_entry_from_acpi(iommu, devid, e->flags,
1256 case IVHD_DEV_EXT_SELECT_RANGE:
1258 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1259 "%02x:%02x.%x flags: %02x ext: %08x\n",
1260 PCI_BUS_NUM(e->devid),
1265 devid_start = e->devid;
1270 case IVHD_DEV_RANGE_END:
1272 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1273 PCI_BUS_NUM(e->devid),
1275 PCI_FUNC(e->devid));
1278 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1280 amd_iommu_alias_table[dev_i] = devid_to;
1281 set_dev_entry_from_acpi(iommu,
1282 devid_to, flags, ext_flags);
1284 set_dev_entry_from_acpi(iommu, dev_i,
1288 case IVHD_DEV_SPECIAL: {
1294 handle = e->ext & 0xff;
1295 devid = (e->ext >> 8) & 0xffff;
1296 type = (e->ext >> 24) & 0xff;
1298 if (type == IVHD_SPECIAL_IOAPIC)
1300 else if (type == IVHD_SPECIAL_HPET)
1305 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1311 ret = add_special_device(type, handle, &devid, false);
1316 * add_special_device might update the devid in case a
1317 * command-line override is present. So call
1318 * set_dev_entry_from_acpi after add_special_device.
1320 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1324 case IVHD_DEV_ACPI_HID: {
1326 u8 hid[ACPIHID_HID_LEN] = {0};
1327 u8 uid[ACPIHID_UID_LEN] = {0};
1330 if (h->type != 0x40) {
1331 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1336 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1337 hid[ACPIHID_HID_LEN - 1] = '\0';
1340 pr_err(FW_BUG "Invalid HID.\n");
1345 case UID_NOT_PRESENT:
1348 pr_warn(FW_BUG "Invalid UID length.\n");
1351 case UID_IS_INTEGER:
1353 sprintf(uid, "%d", e->uid);
1356 case UID_IS_CHARACTER:
1358 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1359 uid[ACPIHID_UID_LEN - 1] = '\0';
1367 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1375 ret = add_acpi_hid_device(hid, uid, &devid, false);
1380 * add_special_device might update the devid in case a
1381 * command-line override is present. So call
1382 * set_dev_entry_from_acpi after add_special_device.
1384 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1392 p += ivhd_entry_length(p);
1398 static void __init free_iommu_one(struct amd_iommu *iommu)
1400 free_command_buffer(iommu);
1401 free_event_buffer(iommu);
1402 free_ppr_log(iommu);
1404 iommu_unmap_mmio_space(iommu);
1407 static void __init free_iommu_all(void)
1409 struct amd_iommu *iommu, *next;
1411 for_each_iommu_safe(iommu, next) {
1412 list_del(&iommu->list);
1413 free_iommu_one(iommu);
1419 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1421 * BIOS should disable L2B micellaneous clock gating by setting
1422 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1424 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1428 if ((boot_cpu_data.x86 != 0x15) ||
1429 (boot_cpu_data.x86_model < 0x10) ||
1430 (boot_cpu_data.x86_model > 0x1f))
1433 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1434 pci_read_config_dword(iommu->dev, 0xf4, &value);
1439 /* Select NB indirect register 0x90 and enable writing */
1440 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1442 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1443 pci_info(iommu->dev, "Applying erratum 746 workaround\n");
1445 /* Clear the enable writing bit */
1446 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1450 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1452 * BIOS should enable ATS write permission check by setting
1453 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1455 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1459 if ((boot_cpu_data.x86 != 0x15) ||
1460 (boot_cpu_data.x86_model < 0x30) ||
1461 (boot_cpu_data.x86_model > 0x3f))
1464 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1465 value = iommu_read_l2(iommu, 0x47);
1470 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1471 iommu_write_l2(iommu, 0x47, value | BIT(0));
1473 pci_info(iommu->dev, "Applying ATS write check workaround\n");
1477 * This function clues the initialization function for one IOMMU
1478 * together and also allocates the command buffer and programs the
1479 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1481 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1485 raw_spin_lock_init(&iommu->lock);
1487 /* Add IOMMU to internal data structures */
1488 list_add_tail(&iommu->list, &amd_iommu_list);
1489 iommu->index = amd_iommus_present++;
1491 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1492 WARN(1, "System has more IOMMUs than supported by this driver\n");
1496 /* Index is fine - add IOMMU to the array */
1497 amd_iommus[iommu->index] = iommu;
1500 * Copy data from ACPI table entry to the iommu struct
1502 iommu->devid = h->devid;
1503 iommu->cap_ptr = h->cap_ptr;
1504 iommu->pci_seg = h->pci_seg;
1505 iommu->mmio_phys = h->mmio_phys;
1509 /* Check if IVHD EFR contains proper max banks/counters */
1510 if ((h->efr_attr != 0) &&
1511 ((h->efr_attr & (0xF << 13)) != 0) &&
1512 ((h->efr_attr & (0x3F << 17)) != 0))
1513 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1515 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1516 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1517 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1518 if (((h->efr_attr & (0x1 << IOMMU_FEAT_XTSUP_SHIFT)) == 0))
1519 amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
1523 if (h->efr_reg & (1 << 9))
1524 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1526 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1527 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1528 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1529 if (((h->efr_reg & (0x1 << IOMMU_EFR_XTSUP_SHIFT)) == 0))
1530 amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
1536 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1537 iommu->mmio_phys_end);
1538 if (!iommu->mmio_base)
1541 if (alloc_command_buffer(iommu))
1544 if (alloc_event_buffer(iommu))
1547 iommu->int_enabled = false;
1549 init_translation_status(iommu);
1550 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
1551 iommu_disable(iommu);
1552 clear_translation_pre_enabled(iommu);
1553 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1556 if (amd_iommu_pre_enabled)
1557 amd_iommu_pre_enabled = translation_pre_enabled(iommu);
1559 ret = init_iommu_from_acpi(iommu, h);
1563 ret = amd_iommu_create_irq_domain(iommu);
1568 * Make sure IOMMU is not considered to translate itself. The IVRS
1569 * table tells us so, but this is a lie!
1571 amd_iommu_rlookup_table[iommu->devid] = NULL;
1577 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1578 * @ivrs Pointer to the IVRS header
1580 * This function search through all IVDB of the maximum supported IVHD
1582 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1584 u8 *base = (u8 *)ivrs;
1585 struct ivhd_header *ivhd = (struct ivhd_header *)
1586 (base + IVRS_HEADER_LENGTH);
1587 u8 last_type = ivhd->type;
1588 u16 devid = ivhd->devid;
1590 while (((u8 *)ivhd - base < ivrs->length) &&
1591 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1592 u8 *p = (u8 *) ivhd;
1594 if (ivhd->devid == devid)
1595 last_type = ivhd->type;
1596 ivhd = (struct ivhd_header *)(p + ivhd->length);
1603 * Iterates over all IOMMU entries in the ACPI table, allocates the
1604 * IOMMU structure and initializes it with init_iommu_one()
1606 static int __init init_iommu_all(struct acpi_table_header *table)
1608 u8 *p = (u8 *)table, *end = (u8 *)table;
1609 struct ivhd_header *h;
1610 struct amd_iommu *iommu;
1613 end += table->length;
1614 p += IVRS_HEADER_LENGTH;
1617 h = (struct ivhd_header *)p;
1618 if (*p == amd_iommu_target_ivhd_type) {
1620 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1621 "seg: %d flags: %01x info %04x\n",
1622 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1623 PCI_FUNC(h->devid), h->cap_ptr,
1624 h->pci_seg, h->flags, h->info);
1625 DUMP_printk(" mmio-addr: %016llx\n",
1628 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1632 ret = init_iommu_one(iommu, h);
1644 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1645 u8 fxn, u64 *value, bool is_write);
1647 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1649 struct pci_dev *pdev = iommu->dev;
1650 u64 val = 0xabcd, val2 = 0;
1652 if (!iommu_feature(iommu, FEATURE_PC))
1655 amd_iommu_pc_present = true;
1657 /* Check if the performance counters can be written to */
1658 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1659 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1661 pci_err(pdev, "Unable to write to IOMMU perf counter.\n");
1662 amd_iommu_pc_present = false;
1666 pci_info(pdev, "IOMMU performance counters supported\n");
1668 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1669 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1670 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1673 static ssize_t amd_iommu_show_cap(struct device *dev,
1674 struct device_attribute *attr,
1677 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1678 return sprintf(buf, "%x\n", iommu->cap);
1680 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1682 static ssize_t amd_iommu_show_features(struct device *dev,
1683 struct device_attribute *attr,
1686 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1687 return sprintf(buf, "%llx\n", iommu->features);
1689 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1691 static struct attribute *amd_iommu_attrs[] = {
1693 &dev_attr_features.attr,
1697 static struct attribute_group amd_iommu_group = {
1698 .name = "amd-iommu",
1699 .attrs = amd_iommu_attrs,
1702 static const struct attribute_group *amd_iommu_groups[] = {
1707 static int __init iommu_init_pci(struct amd_iommu *iommu)
1709 int cap_ptr = iommu->cap_ptr;
1710 u32 range, misc, low, high;
1713 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
1714 iommu->devid & 0xff);
1718 /* Prevent binding other PCI device drivers to IOMMU devices */
1719 iommu->dev->match_driver = false;
1721 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1723 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1725 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1728 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1729 amd_iommu_iotlb_sup = false;
1731 /* read extended feature bits */
1732 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1733 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1735 iommu->features = ((u64)high << 32) | low;
1737 if (iommu_feature(iommu, FEATURE_GT)) {
1742 pasmax = iommu->features & FEATURE_PASID_MASK;
1743 pasmax >>= FEATURE_PASID_SHIFT;
1744 max_pasid = (1 << (pasmax + 1)) - 1;
1746 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1748 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1750 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1751 glxval >>= FEATURE_GLXVAL_SHIFT;
1753 if (amd_iommu_max_glx_val == -1)
1754 amd_iommu_max_glx_val = glxval;
1756 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1759 if (iommu_feature(iommu, FEATURE_GT) &&
1760 iommu_feature(iommu, FEATURE_PPR)) {
1761 iommu->is_iommu_v2 = true;
1762 amd_iommu_v2_present = true;
1765 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1768 ret = iommu_init_ga(iommu);
1772 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1773 amd_iommu_np_cache = true;
1775 init_iommu_perf_ctr(iommu);
1777 if (is_rd890_iommu(iommu->dev)) {
1781 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
1785 * Some rd890 systems may not be fully reconfigured by the
1786 * BIOS, so it's necessary for us to store this information so
1787 * it can be reprogrammed on resume
1789 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1790 &iommu->stored_addr_lo);
1791 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1792 &iommu->stored_addr_hi);
1794 /* Low bit locks writes to configuration space */
1795 iommu->stored_addr_lo &= ~1;
1797 for (i = 0; i < 6; i++)
1798 for (j = 0; j < 0x12; j++)
1799 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1801 for (i = 0; i < 0x83; i++)
1802 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1805 amd_iommu_erratum_746_workaround(iommu);
1806 amd_iommu_ats_write_check_workaround(iommu);
1808 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1809 amd_iommu_groups, "ivhd%d", iommu->index);
1810 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1811 iommu_device_register(&iommu->iommu);
1813 return pci_enable_device(iommu->dev);
1816 static void print_iommu_info(void)
1818 static const char * const feat_str[] = {
1819 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1820 "IA", "GA", "HE", "PC"
1822 struct amd_iommu *iommu;
1824 for_each_iommu(iommu) {
1825 struct pci_dev *pdev = iommu->dev;
1828 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr);
1830 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1831 pci_info(pdev, "Extended features (%#llx):\n",
1833 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1834 if (iommu_feature(iommu, (1ULL << i)))
1835 pr_cont(" %s", feat_str[i]);
1838 if (iommu->features & FEATURE_GAM_VAPIC)
1839 pr_cont(" GA_vAPIC");
1844 if (irq_remapping_enabled) {
1845 pr_info("Interrupt remapping enabled\n");
1846 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1847 pr_info("Virtual APIC enabled\n");
1848 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
1849 pr_info("X2APIC enabled\n");
1853 static int __init amd_iommu_init_pci(void)
1855 struct amd_iommu *iommu;
1858 for_each_iommu(iommu) {
1859 ret = iommu_init_pci(iommu);
1865 * Order is important here to make sure any unity map requirements are
1866 * fulfilled. The unity mappings are created and written to the device
1867 * table during the amd_iommu_init_api() call.
1869 * After that we call init_device_table_dma() to make sure any
1870 * uninitialized DTE will block DMA, and in the end we flush the caches
1871 * of all IOMMUs to make sure the changes to the device table are
1874 ret = amd_iommu_init_api();
1876 init_device_table_dma();
1878 for_each_iommu(iommu)
1879 iommu_flush_all_caches(iommu);
1887 /****************************************************************************
1889 * The following functions initialize the MSI interrupts for all IOMMUs
1890 * in the system. It's a bit challenging because there could be multiple
1891 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1894 ****************************************************************************/
1896 static int iommu_setup_msi(struct amd_iommu *iommu)
1900 r = pci_enable_msi(iommu->dev);
1904 r = request_threaded_irq(iommu->dev->irq,
1905 amd_iommu_int_handler,
1906 amd_iommu_int_thread,
1911 pci_disable_msi(iommu->dev);
1915 iommu->int_enabled = true;
1920 static int iommu_init_msi(struct amd_iommu *iommu)
1924 if (iommu->int_enabled)
1927 if (iommu->dev->msi_cap)
1928 ret = iommu_setup_msi(iommu);
1936 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1938 if (iommu->ppr_log != NULL)
1939 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1941 iommu_ga_log_enable(iommu);
1946 /****************************************************************************
1948 * The next functions belong to the third pass of parsing the ACPI
1949 * table. In this last pass the memory mapping requirements are
1950 * gathered (like exclusion and unity mapping ranges).
1952 ****************************************************************************/
1954 static void __init free_unity_maps(void)
1956 struct unity_map_entry *entry, *next;
1958 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1959 list_del(&entry->list);
1964 /* called when we find an exclusion range definition in ACPI */
1965 static int __init init_exclusion_range(struct ivmd_header *m)
1970 case ACPI_IVMD_TYPE:
1971 set_device_exclusion_range(m->devid, m);
1973 case ACPI_IVMD_TYPE_ALL:
1974 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1975 set_device_exclusion_range(i, m);
1977 case ACPI_IVMD_TYPE_RANGE:
1978 for (i = m->devid; i <= m->aux; ++i)
1979 set_device_exclusion_range(i, m);
1988 /* called for unity map ACPI definition */
1989 static int __init init_unity_map_range(struct ivmd_header *m)
1991 struct unity_map_entry *e = NULL;
1994 e = kzalloc(sizeof(*e), GFP_KERNEL);
1998 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1999 init_exclusion_range(m);
2005 case ACPI_IVMD_TYPE:
2006 s = "IVMD_TYPEi\t\t\t";
2007 e->devid_start = e->devid_end = m->devid;
2009 case ACPI_IVMD_TYPE_ALL:
2010 s = "IVMD_TYPE_ALL\t\t";
2012 e->devid_end = amd_iommu_last_bdf;
2014 case ACPI_IVMD_TYPE_RANGE:
2015 s = "IVMD_TYPE_RANGE\t\t";
2016 e->devid_start = m->devid;
2017 e->devid_end = m->aux;
2020 e->address_start = PAGE_ALIGN(m->range_start);
2021 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
2022 e->prot = m->flags >> 1;
2024 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2025 " range_start: %016llx range_end: %016llx flags: %x\n", s,
2026 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
2027 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
2028 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
2029 e->address_start, e->address_end, m->flags);
2031 list_add_tail(&e->list, &amd_iommu_unity_map);
2036 /* iterates over all memory definitions we find in the ACPI table */
2037 static int __init init_memory_definitions(struct acpi_table_header *table)
2039 u8 *p = (u8 *)table, *end = (u8 *)table;
2040 struct ivmd_header *m;
2042 end += table->length;
2043 p += IVRS_HEADER_LENGTH;
2046 m = (struct ivmd_header *)p;
2047 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE))
2048 init_unity_map_range(m);
2057 * Init the device table to not allow DMA access for devices
2059 static void init_device_table_dma(void)
2063 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2064 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2065 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2069 static void __init uninit_device_table_dma(void)
2073 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2074 amd_iommu_dev_table[devid].data[0] = 0ULL;
2075 amd_iommu_dev_table[devid].data[1] = 0ULL;
2079 static void init_device_table(void)
2083 if (!amd_iommu_irq_remap)
2086 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2087 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
2090 static void iommu_init_flags(struct amd_iommu *iommu)
2092 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
2093 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
2094 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
2096 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
2097 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
2098 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
2100 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
2101 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
2102 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
2104 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
2105 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
2106 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
2109 * make IOMMU memory accesses cache coherent
2111 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
2113 /* Set IOTLB invalidation timeout to 1s */
2114 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
2117 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
2120 u32 ioc_feature_control;
2121 struct pci_dev *pdev = iommu->root_pdev;
2123 /* RD890 BIOSes may not have completely reconfigured the iommu */
2124 if (!is_rd890_iommu(iommu->dev) || !pdev)
2128 * First, we need to ensure that the iommu is enabled. This is
2129 * controlled by a register in the northbridge
2132 /* Select Northbridge indirect register 0x75 and enable writing */
2133 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
2134 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
2136 /* Enable the iommu */
2137 if (!(ioc_feature_control & 0x1))
2138 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
2140 /* Restore the iommu BAR */
2141 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2142 iommu->stored_addr_lo);
2143 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
2144 iommu->stored_addr_hi);
2146 /* Restore the l1 indirect regs for each of the 6 l1s */
2147 for (i = 0; i < 6; i++)
2148 for (j = 0; j < 0x12; j++)
2149 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
2151 /* Restore the l2 indirect regs */
2152 for (i = 0; i < 0x83; i++)
2153 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2155 /* Lock PCI setup registers */
2156 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2157 iommu->stored_addr_lo | 1);
2160 static void iommu_enable_ga(struct amd_iommu *iommu)
2162 #ifdef CONFIG_IRQ_REMAP
2163 switch (amd_iommu_guest_ir) {
2164 case AMD_IOMMU_GUEST_IR_VAPIC:
2165 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2167 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2168 iommu_feature_enable(iommu, CONTROL_GA_EN);
2169 iommu->irte_ops = &irte_128_ops;
2172 iommu->irte_ops = &irte_32_ops;
2178 static void early_enable_iommu(struct amd_iommu *iommu)
2180 iommu_disable(iommu);
2181 iommu_init_flags(iommu);
2182 iommu_set_device_table(iommu);
2183 iommu_enable_command_buffer(iommu);
2184 iommu_enable_event_buffer(iommu);
2185 iommu_set_exclusion_range(iommu);
2186 iommu_enable_ga(iommu);
2187 iommu_enable_xt(iommu);
2188 iommu_enable(iommu);
2189 iommu_flush_all_caches(iommu);
2193 * This function finally enables all IOMMUs found in the system after
2194 * they have been initialized.
2196 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2197 * the old content of device table entries. Not this case or copy failed,
2198 * just continue as normal kernel does.
2200 static void early_enable_iommus(void)
2202 struct amd_iommu *iommu;
2205 if (!copy_device_table()) {
2207 * If come here because of failure in copying device table from old
2208 * kernel with all IOMMUs enabled, print error message and try to
2209 * free allocated old_dev_tbl_cpy.
2211 if (amd_iommu_pre_enabled)
2212 pr_err("Failed to copy DEV table from previous kernel.\n");
2213 if (old_dev_tbl_cpy != NULL)
2214 free_pages((unsigned long)old_dev_tbl_cpy,
2215 get_order(dev_table_size));
2217 for_each_iommu(iommu) {
2218 clear_translation_pre_enabled(iommu);
2219 early_enable_iommu(iommu);
2222 pr_info("Copied DEV table from previous kernel.\n");
2223 free_pages((unsigned long)amd_iommu_dev_table,
2224 get_order(dev_table_size));
2225 amd_iommu_dev_table = old_dev_tbl_cpy;
2226 for_each_iommu(iommu) {
2227 iommu_disable_command_buffer(iommu);
2228 iommu_disable_event_buffer(iommu);
2229 iommu_enable_command_buffer(iommu);
2230 iommu_enable_event_buffer(iommu);
2231 iommu_enable_ga(iommu);
2232 iommu_enable_xt(iommu);
2233 iommu_set_device_table(iommu);
2234 iommu_flush_all_caches(iommu);
2238 #ifdef CONFIG_IRQ_REMAP
2239 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2240 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2244 static void enable_iommus_v2(void)
2246 struct amd_iommu *iommu;
2248 for_each_iommu(iommu) {
2249 iommu_enable_ppr_log(iommu);
2250 iommu_enable_gt(iommu);
2254 static void enable_iommus(void)
2256 early_enable_iommus();
2261 static void disable_iommus(void)
2263 struct amd_iommu *iommu;
2265 for_each_iommu(iommu)
2266 iommu_disable(iommu);
2268 #ifdef CONFIG_IRQ_REMAP
2269 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2270 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2275 * Suspend/Resume support
2276 * disable suspend until real resume implemented
2279 static void amd_iommu_resume(void)
2281 struct amd_iommu *iommu;
2283 for_each_iommu(iommu)
2284 iommu_apply_resume_quirks(iommu);
2286 /* re-load the hardware */
2289 amd_iommu_enable_interrupts();
2292 static int amd_iommu_suspend(void)
2294 /* disable IOMMUs to go out of the way for BIOS */
2300 static struct syscore_ops amd_iommu_syscore_ops = {
2301 .suspend = amd_iommu_suspend,
2302 .resume = amd_iommu_resume,
2305 static void __init free_iommu_resources(void)
2307 kmemleak_free(irq_lookup_table);
2308 free_pages((unsigned long)irq_lookup_table,
2309 get_order(rlookup_table_size));
2310 irq_lookup_table = NULL;
2312 kmem_cache_destroy(amd_iommu_irq_cache);
2313 amd_iommu_irq_cache = NULL;
2315 free_pages((unsigned long)amd_iommu_rlookup_table,
2316 get_order(rlookup_table_size));
2317 amd_iommu_rlookup_table = NULL;
2319 free_pages((unsigned long)amd_iommu_alias_table,
2320 get_order(alias_table_size));
2321 amd_iommu_alias_table = NULL;
2323 free_pages((unsigned long)amd_iommu_dev_table,
2324 get_order(dev_table_size));
2325 amd_iommu_dev_table = NULL;
2329 #ifdef CONFIG_GART_IOMMU
2331 * We failed to initialize the AMD IOMMU - try fallback to GART
2339 /* SB IOAPIC is always on this device in AMD systems */
2340 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2342 static bool __init check_ioapic_information(void)
2344 const char *fw_bug = FW_BUG;
2345 bool ret, has_sb_ioapic;
2348 has_sb_ioapic = false;
2352 * If we have map overrides on the kernel command line the
2353 * messages in this function might not describe firmware bugs
2354 * anymore - so be careful
2359 for (idx = 0; idx < nr_ioapics; idx++) {
2360 int devid, id = mpc_ioapic_id(idx);
2362 devid = get_ioapic_devid(id);
2364 pr_err("%s: IOAPIC[%d] not in IVRS table\n",
2367 } else if (devid == IOAPIC_SB_DEVID) {
2368 has_sb_ioapic = true;
2373 if (!has_sb_ioapic) {
2375 * We expect the SB IOAPIC to be listed in the IVRS
2376 * table. The system timer is connected to the SB IOAPIC
2377 * and if we don't have it in the list the system will
2378 * panic at boot time. This situation usually happens
2379 * when the BIOS is buggy and provides us the wrong
2380 * device id for the IOAPIC in the system.
2382 pr_err("%s: No southbridge IOAPIC found\n", fw_bug);
2386 pr_err("Disabling interrupt remapping\n");
2391 static void __init free_dma_resources(void)
2393 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2394 get_order(MAX_DOMAIN_ID/8));
2395 amd_iommu_pd_alloc_bitmap = NULL;
2401 * This is the hardware init function for AMD IOMMU in the system.
2402 * This function is called either from amd_iommu_init or from the interrupt
2403 * remapping setup code.
2405 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2408 * 1 pass) Discover the most comprehensive IVHD type to use.
2410 * 2 pass) Find the highest PCI device id the driver has to handle.
2411 * Upon this information the size of the data structures is
2412 * determined that needs to be allocated.
2414 * 3 pass) Initialize the data structures just allocated with the
2415 * information in the ACPI table about available AMD IOMMUs
2416 * in the system. It also maps the PCI devices in the
2417 * system to specific IOMMUs
2419 * 4 pass) After the basic data structures are allocated and
2420 * initialized we update them with information about memory
2421 * remapping requirements parsed out of the ACPI table in
2424 * After everything is set up the IOMMUs are enabled and the necessary
2425 * hotplug and suspend notifiers are registered.
2427 static int __init early_amd_iommu_init(void)
2429 struct acpi_table_header *ivrs_base;
2431 int i, remap_cache_sz, ret = 0;
2433 if (!amd_iommu_detected)
2436 status = acpi_get_table("IVRS", 0, &ivrs_base);
2437 if (status == AE_NOT_FOUND)
2439 else if (ACPI_FAILURE(status)) {
2440 const char *err = acpi_format_exception(status);
2441 pr_err("IVRS table error: %s\n", err);
2446 * Validate checksum here so we don't need to do it when
2447 * we actually parse the table
2449 ret = check_ivrs_checksum(ivrs_base);
2453 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2454 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2457 * First parse ACPI tables to find the largest Bus/Dev/Func
2458 * we need to handle. Upon this information the shared data
2459 * structures for the IOMMUs in the system will be allocated
2461 ret = find_last_devid_acpi(ivrs_base);
2465 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2466 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2467 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2469 /* Device table - directly used by all IOMMUs */
2471 amd_iommu_dev_table = (void *)__get_free_pages(
2472 GFP_KERNEL | __GFP_ZERO | GFP_DMA32,
2473 get_order(dev_table_size));
2474 if (amd_iommu_dev_table == NULL)
2478 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2479 * IOMMU see for that device
2481 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2482 get_order(alias_table_size));
2483 if (amd_iommu_alias_table == NULL)
2486 /* IOMMU rlookup table - find the IOMMU for a specific device */
2487 amd_iommu_rlookup_table = (void *)__get_free_pages(
2488 GFP_KERNEL | __GFP_ZERO,
2489 get_order(rlookup_table_size));
2490 if (amd_iommu_rlookup_table == NULL)
2493 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2494 GFP_KERNEL | __GFP_ZERO,
2495 get_order(MAX_DOMAIN_ID/8));
2496 if (amd_iommu_pd_alloc_bitmap == NULL)
2500 * let all alias entries point to itself
2502 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2503 amd_iommu_alias_table[i] = i;
2506 * never allocate domain 0 because its used as the non-allocated and
2507 * error value placeholder
2509 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2512 * now the data structures are allocated and basically initialized
2513 * start the real acpi table scan
2515 ret = init_iommu_all(ivrs_base);
2519 /* Disable any previously enabled IOMMUs */
2520 if (!is_kdump_kernel() || amd_iommu_disabled)
2523 if (amd_iommu_irq_remap)
2524 amd_iommu_irq_remap = check_ioapic_information();
2526 if (amd_iommu_irq_remap) {
2528 * Interrupt remapping enabled, create kmem_cache for the
2532 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2533 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2535 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2536 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2538 IRQ_TABLE_ALIGNMENT,
2540 if (!amd_iommu_irq_cache)
2543 irq_lookup_table = (void *)__get_free_pages(
2544 GFP_KERNEL | __GFP_ZERO,
2545 get_order(rlookup_table_size));
2546 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2548 if (!irq_lookup_table)
2552 ret = init_memory_definitions(ivrs_base);
2556 /* init the device table */
2557 init_device_table();
2560 /* Don't leak any ACPI memory */
2561 acpi_put_table(ivrs_base);
2567 static int amd_iommu_enable_interrupts(void)
2569 struct amd_iommu *iommu;
2572 for_each_iommu(iommu) {
2573 ret = iommu_init_msi(iommu);
2582 static bool detect_ivrs(void)
2584 struct acpi_table_header *ivrs_base;
2587 status = acpi_get_table("IVRS", 0, &ivrs_base);
2588 if (status == AE_NOT_FOUND)
2590 else if (ACPI_FAILURE(status)) {
2591 const char *err = acpi_format_exception(status);
2592 pr_err("IVRS table error: %s\n", err);
2596 acpi_put_table(ivrs_base);
2598 /* Make sure ACS will be enabled during PCI probe */
2604 /****************************************************************************
2606 * AMD IOMMU Initialization State Machine
2608 ****************************************************************************/
2610 static int __init state_next(void)
2614 switch (init_state) {
2615 case IOMMU_START_STATE:
2616 if (!detect_ivrs()) {
2617 init_state = IOMMU_NOT_FOUND;
2620 init_state = IOMMU_IVRS_DETECTED;
2623 case IOMMU_IVRS_DETECTED:
2624 ret = early_amd_iommu_init();
2625 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2626 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2627 pr_info("AMD IOMMU disabled on kernel command-line\n");
2628 free_dma_resources();
2629 free_iommu_resources();
2630 init_state = IOMMU_CMDLINE_DISABLED;
2634 case IOMMU_ACPI_FINISHED:
2635 early_enable_iommus();
2636 x86_platform.iommu_shutdown = disable_iommus;
2637 init_state = IOMMU_ENABLED;
2640 register_syscore_ops(&amd_iommu_syscore_ops);
2641 ret = amd_iommu_init_pci();
2642 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2645 case IOMMU_PCI_INIT:
2646 ret = amd_iommu_enable_interrupts();
2647 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2649 case IOMMU_INTERRUPTS_EN:
2650 ret = amd_iommu_init_dma_ops();
2651 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2654 init_state = IOMMU_INITIALIZED;
2656 case IOMMU_INITIALIZED:
2659 case IOMMU_NOT_FOUND:
2660 case IOMMU_INIT_ERROR:
2661 case IOMMU_CMDLINE_DISABLED:
2662 /* Error states => do nothing */
2673 static int __init iommu_go_to_state(enum iommu_init_state state)
2677 while (init_state != state) {
2678 if (init_state == IOMMU_NOT_FOUND ||
2679 init_state == IOMMU_INIT_ERROR ||
2680 init_state == IOMMU_CMDLINE_DISABLED)
2688 #ifdef CONFIG_IRQ_REMAP
2689 int __init amd_iommu_prepare(void)
2693 amd_iommu_irq_remap = true;
2695 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2698 return amd_iommu_irq_remap ? 0 : -ENODEV;
2701 int __init amd_iommu_enable(void)
2705 ret = iommu_go_to_state(IOMMU_ENABLED);
2709 irq_remapping_enabled = 1;
2710 return amd_iommu_xt_mode;
2713 void amd_iommu_disable(void)
2715 amd_iommu_suspend();
2718 int amd_iommu_reenable(int mode)
2725 int __init amd_iommu_enable_faulting(void)
2727 /* We enable MSI later when PCI is initialized */
2733 * This is the core init function for AMD IOMMU hardware in the system.
2734 * This function is called from the generic x86 DMA layer initialization
2737 static int __init amd_iommu_init(void)
2739 struct amd_iommu *iommu;
2742 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2744 free_dma_resources();
2745 if (!irq_remapping_enabled) {
2747 free_iommu_resources();
2749 uninit_device_table_dma();
2750 for_each_iommu(iommu)
2751 iommu_flush_all_caches(iommu);
2755 for_each_iommu(iommu)
2756 amd_iommu_debugfs_setup(iommu);
2761 static bool amd_iommu_sme_check(void)
2763 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
2766 /* For Fam17h, a specific level of support is required */
2767 if (boot_cpu_data.microcode >= 0x08001205)
2770 if ((boot_cpu_data.microcode >= 0x08001126) &&
2771 (boot_cpu_data.microcode <= 0x080011ff))
2774 pr_notice("IOMMU not currently supported when SME is active\n");
2779 /****************************************************************************
2781 * Early detect code. This code runs at IOMMU detection time in the DMA
2782 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2785 ****************************************************************************/
2786 int __init amd_iommu_detect(void)
2790 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2793 if (!amd_iommu_sme_check())
2796 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2800 amd_iommu_detected = true;
2802 x86_init.iommu.iommu_init = amd_iommu_init;
2807 /****************************************************************************
2809 * Parsing functions for the AMD IOMMU specific kernel command line
2812 ****************************************************************************/
2814 static int __init parse_amd_iommu_dump(char *str)
2816 amd_iommu_dump = true;
2821 static int __init parse_amd_iommu_intr(char *str)
2823 for (; *str; ++str) {
2824 if (strncmp(str, "legacy", 6) == 0) {
2825 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2828 if (strncmp(str, "vapic", 5) == 0) {
2829 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2836 static int __init parse_amd_iommu_options(char *str)
2838 for (; *str; ++str) {
2839 if (strncmp(str, "fullflush", 9) == 0)
2840 amd_iommu_unmap_flush = true;
2841 if (strncmp(str, "off", 3) == 0)
2842 amd_iommu_disabled = true;
2843 if (strncmp(str, "force_isolation", 15) == 0)
2844 amd_iommu_force_isolation = true;
2850 static int __init parse_ivrs_ioapic(char *str)
2852 unsigned int bus, dev, fn;
2856 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2859 pr_err("Invalid command line: ivrs_ioapic%s\n", str);
2863 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2864 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2869 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2871 cmdline_maps = true;
2872 i = early_ioapic_map_size++;
2873 early_ioapic_map[i].id = id;
2874 early_ioapic_map[i].devid = devid;
2875 early_ioapic_map[i].cmd_line = true;
2880 static int __init parse_ivrs_hpet(char *str)
2882 unsigned int bus, dev, fn;
2886 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2889 pr_err("Invalid command line: ivrs_hpet%s\n", str);
2893 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2894 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n",
2899 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2901 cmdline_maps = true;
2902 i = early_hpet_map_size++;
2903 early_hpet_map[i].id = id;
2904 early_hpet_map[i].devid = devid;
2905 early_hpet_map[i].cmd_line = true;
2910 static int __init parse_ivrs_acpihid(char *str)
2913 char *hid, *uid, *p;
2914 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2917 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2919 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str);
2924 hid = strsep(&p, ":");
2927 if (!hid || !(*hid) || !uid) {
2928 pr_err("Invalid command line: hid or uid\n");
2932 i = early_acpihid_map_size++;
2933 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2934 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2935 early_acpihid_map[i].devid =
2936 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2937 early_acpihid_map[i].cmd_line = true;
2942 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2943 __setup("amd_iommu=", parse_amd_iommu_options);
2944 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2945 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2946 __setup("ivrs_hpet", parse_ivrs_hpet);
2947 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2949 IOMMU_INIT_FINISH(amd_iommu_detect,
2950 gart_iommu_hole_init,
2954 bool amd_iommu_v2_supported(void)
2956 return amd_iommu_v2_present;
2958 EXPORT_SYMBOL(amd_iommu_v2_supported);
2960 struct amd_iommu *get_amd_iommu(unsigned int idx)
2963 struct amd_iommu *iommu;
2965 for_each_iommu(iommu)
2970 EXPORT_SYMBOL(get_amd_iommu);
2972 /****************************************************************************
2974 * IOMMU EFR Performance Counter support functionality. This code allows
2975 * access to the IOMMU PC functionality.
2977 ****************************************************************************/
2979 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
2981 struct amd_iommu *iommu = get_amd_iommu(idx);
2984 return iommu->max_banks;
2988 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2990 bool amd_iommu_pc_supported(void)
2992 return amd_iommu_pc_present;
2994 EXPORT_SYMBOL(amd_iommu_pc_supported);
2996 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
2998 struct amd_iommu *iommu = get_amd_iommu(idx);
3001 return iommu->max_counters;
3005 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
3007 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
3008 u8 fxn, u64 *value, bool is_write)
3013 /* Make sure the IOMMU PC resource is available */
3014 if (!amd_iommu_pc_present)
3017 /* Check for valid iommu and pc register indexing */
3018 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
3021 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3023 /* Limit the offset to the hw defined mmio region aperture */
3024 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
3025 (iommu->max_counters << 8) | 0x28);
3026 if ((offset < MMIO_CNTR_REG_OFFSET) ||
3027 (offset > max_offset_lim))
3031 u64 val = *value & GENMASK_ULL(47, 0);
3033 writel((u32)val, iommu->mmio_base + offset);
3034 writel((val >> 32), iommu->mmio_base + offset + 4);
3036 *value = readl(iommu->mmio_base + offset + 4);
3038 *value |= readl(iommu->mmio_base + offset);
3039 *value &= GENMASK_ULL(47, 0);
3045 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3050 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3052 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
3054 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3059 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
3061 EXPORT_SYMBOL(amd_iommu_pc_set_reg);