1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
9 #define _ASM_X86_AMD_IOMMU_TYPES_H
11 #include <linux/types.h>
12 #include <linux/mutex.h>
13 #include <linux/msi.h>
14 #include <linux/list.h>
15 #include <linux/spinlock.h>
16 #include <linux/pci.h>
17 #include <linux/irqreturn.h>
20 * Maximum number of IOMMUs supported
25 * some size calculation constants
27 #define DEV_TABLE_ENTRY_SIZE 32
28 #define ALIAS_TABLE_ENTRY_SIZE 2
29 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
31 /* Capability offsets used by the driver */
32 #define MMIO_CAP_HDR_OFFSET 0x00
33 #define MMIO_RANGE_OFFSET 0x0c
34 #define MMIO_MISC_OFFSET 0x10
36 /* Masks, shifts and macros to parse the device range capability */
37 #define MMIO_RANGE_LD_MASK 0xff000000
38 #define MMIO_RANGE_FD_MASK 0x00ff0000
39 #define MMIO_RANGE_BUS_MASK 0x0000ff00
40 #define MMIO_RANGE_LD_SHIFT 24
41 #define MMIO_RANGE_FD_SHIFT 16
42 #define MMIO_RANGE_BUS_SHIFT 8
43 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
44 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
45 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
46 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
48 /* Flag masks for the AMD IOMMU exclusion range */
49 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
50 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
52 /* Used offsets into the MMIO space */
53 #define MMIO_DEV_TABLE_OFFSET 0x0000
54 #define MMIO_CMD_BUF_OFFSET 0x0008
55 #define MMIO_EVT_BUF_OFFSET 0x0010
56 #define MMIO_CONTROL_OFFSET 0x0018
57 #define MMIO_EXCL_BASE_OFFSET 0x0020
58 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
59 #define MMIO_EXT_FEATURES 0x0030
60 #define MMIO_PPR_LOG_OFFSET 0x0038
61 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
62 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
63 #define MMIO_CMD_HEAD_OFFSET 0x2000
64 #define MMIO_CMD_TAIL_OFFSET 0x2008
65 #define MMIO_EVT_HEAD_OFFSET 0x2010
66 #define MMIO_EVT_TAIL_OFFSET 0x2018
67 #define MMIO_STATUS_OFFSET 0x2020
68 #define MMIO_PPR_HEAD_OFFSET 0x2030
69 #define MMIO_PPR_TAIL_OFFSET 0x2038
70 #define MMIO_GA_HEAD_OFFSET 0x2040
71 #define MMIO_GA_TAIL_OFFSET 0x2048
72 #define MMIO_CNTR_CONF_OFFSET 0x4000
73 #define MMIO_CNTR_REG_OFFSET 0x40000
74 #define MMIO_REG_END_OFFSET 0x80000
78 /* Extended Feature Bits */
79 #define FEATURE_PREFETCH (1ULL<<0)
80 #define FEATURE_PPR (1ULL<<1)
81 #define FEATURE_X2APIC (1ULL<<2)
82 #define FEATURE_NX (1ULL<<3)
83 #define FEATURE_GT (1ULL<<4)
84 #define FEATURE_IA (1ULL<<6)
85 #define FEATURE_GA (1ULL<<7)
86 #define FEATURE_HE (1ULL<<8)
87 #define FEATURE_PC (1ULL<<9)
88 #define FEATURE_GAM_VAPIC (1ULL<<21)
89 #define FEATURE_EPHSUP (1ULL<<50)
91 #define FEATURE_PASID_SHIFT 32
92 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
94 #define FEATURE_GLXVAL_SHIFT 14
95 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
98 * The current driver only support 16-bit PASID.
99 * Currently, hardware only implement upto 16-bit PASID
100 * even though the spec says it could have upto 20 bits.
102 #define PASID_MASK 0x0000ffff
104 /* MMIO status bits */
105 #define MMIO_STATUS_EVT_INT_MASK (1 << 1)
106 #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
107 #define MMIO_STATUS_PPR_INT_MASK (1 << 6)
108 #define MMIO_STATUS_GALOG_RUN_MASK (1 << 8)
109 #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
110 #define MMIO_STATUS_GALOG_INT_MASK (1 << 10)
112 /* event logging constants */
113 #define EVENT_ENTRY_SIZE 0x10
114 #define EVENT_TYPE_SHIFT 28
115 #define EVENT_TYPE_MASK 0xf
116 #define EVENT_TYPE_ILL_DEV 0x1
117 #define EVENT_TYPE_IO_FAULT 0x2
118 #define EVENT_TYPE_DEV_TAB_ERR 0x3
119 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
120 #define EVENT_TYPE_ILL_CMD 0x5
121 #define EVENT_TYPE_CMD_HARD_ERR 0x6
122 #define EVENT_TYPE_IOTLB_INV_TO 0x7
123 #define EVENT_TYPE_INV_DEV_REQ 0x8
124 #define EVENT_TYPE_INV_PPR_REQ 0x9
125 #define EVENT_DEVID_MASK 0xffff
126 #define EVENT_DEVID_SHIFT 0
127 #define EVENT_DOMID_MASK 0xffff
128 #define EVENT_DOMID_SHIFT 0
129 #define EVENT_FLAGS_MASK 0xfff
130 #define EVENT_FLAGS_SHIFT 0x10
132 /* feature control bits */
133 #define CONTROL_IOMMU_EN 0x00ULL
134 #define CONTROL_HT_TUN_EN 0x01ULL
135 #define CONTROL_EVT_LOG_EN 0x02ULL
136 #define CONTROL_EVT_INT_EN 0x03ULL
137 #define CONTROL_COMWAIT_EN 0x04ULL
138 #define CONTROL_INV_TIMEOUT 0x05ULL
139 #define CONTROL_PASSPW_EN 0x08ULL
140 #define CONTROL_RESPASSPW_EN 0x09ULL
141 #define CONTROL_COHERENT_EN 0x0aULL
142 #define CONTROL_ISOC_EN 0x0bULL
143 #define CONTROL_CMDBUF_EN 0x0cULL
144 #define CONTROL_PPFLOG_EN 0x0dULL
145 #define CONTROL_PPFINT_EN 0x0eULL
146 #define CONTROL_PPR_EN 0x0fULL
147 #define CONTROL_GT_EN 0x10ULL
148 #define CONTROL_GA_EN 0x11ULL
149 #define CONTROL_GAM_EN 0x19ULL
150 #define CONTROL_GALOG_EN 0x1CULL
151 #define CONTROL_GAINT_EN 0x1DULL
152 #define CONTROL_XT_EN 0x32ULL
154 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
155 #define CTRL_INV_TO_NONE 0
156 #define CTRL_INV_TO_1MS 1
157 #define CTRL_INV_TO_10MS 2
158 #define CTRL_INV_TO_100MS 3
159 #define CTRL_INV_TO_1S 4
160 #define CTRL_INV_TO_10S 5
161 #define CTRL_INV_TO_100S 6
163 /* command specific defines */
164 #define CMD_COMPL_WAIT 0x01
165 #define CMD_INV_DEV_ENTRY 0x02
166 #define CMD_INV_IOMMU_PAGES 0x03
167 #define CMD_INV_IOTLB_PAGES 0x04
168 #define CMD_INV_IRT 0x05
169 #define CMD_COMPLETE_PPR 0x07
170 #define CMD_INV_ALL 0x08
172 #define CMD_COMPL_WAIT_STORE_MASK 0x01
173 #define CMD_COMPL_WAIT_INT_MASK 0x02
174 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
175 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
176 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
178 #define PPR_STATUS_MASK 0xf
179 #define PPR_STATUS_SHIFT 12
181 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
183 /* macros and definitions for device table entries */
184 #define DEV_ENTRY_VALID 0x00
185 #define DEV_ENTRY_TRANSLATION 0x01
186 #define DEV_ENTRY_PPR 0x34
187 #define DEV_ENTRY_IR 0x3d
188 #define DEV_ENTRY_IW 0x3e
189 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
190 #define DEV_ENTRY_EX 0x67
191 #define DEV_ENTRY_SYSMGT1 0x68
192 #define DEV_ENTRY_SYSMGT2 0x69
193 #define DEV_ENTRY_IRQ_TBL_EN 0x80
194 #define DEV_ENTRY_INIT_PASS 0xb8
195 #define DEV_ENTRY_EINT_PASS 0xb9
196 #define DEV_ENTRY_NMI_PASS 0xba
197 #define DEV_ENTRY_LINT0_PASS 0xbe
198 #define DEV_ENTRY_LINT1_PASS 0xbf
199 #define DEV_ENTRY_MODE_MASK 0x07
200 #define DEV_ENTRY_MODE_SHIFT 0x09
202 #define MAX_DEV_TABLE_ENTRIES 0xffff
204 /* constants to configure the command buffer */
205 #define CMD_BUFFER_SIZE 8192
206 #define CMD_BUFFER_UNINITIALIZED 1
207 #define CMD_BUFFER_ENTRIES 512
208 #define MMIO_CMD_SIZE_SHIFT 56
209 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
211 /* constants for event buffer handling */
212 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
213 #define EVT_LEN_MASK (0x9ULL << 56)
215 /* Constants for PPR Log handling */
216 #define PPR_LOG_ENTRIES 512
217 #define PPR_LOG_SIZE_SHIFT 56
218 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
219 #define PPR_ENTRY_SIZE 16
220 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
222 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
223 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
224 #define PPR_DEVID(x) ((x) & 0xffffULL)
225 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
226 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
227 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
228 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
230 #define PPR_REQ_FAULT 0x01
232 /* Constants for GA Log handling */
233 #define GA_LOG_ENTRIES 512
234 #define GA_LOG_SIZE_SHIFT 56
235 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
236 #define GA_ENTRY_SIZE 8
237 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
239 #define GA_TAG(x) (u32)(x & 0xffffffffULL)
240 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
241 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
243 #define GA_GUEST_NR 0x1
245 /* Bit value definition for dte irq remapping fields*/
246 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
247 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
248 #define DTE_IRQ_TABLE_LEN_MASK (0xfULL << 1)
249 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
250 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
251 #define DTE_IRQ_REMAP_ENABLE 1ULL
253 #define PAGE_MODE_NONE 0x00
254 #define PAGE_MODE_1_LEVEL 0x01
255 #define PAGE_MODE_2_LEVEL 0x02
256 #define PAGE_MODE_3_LEVEL 0x03
257 #define PAGE_MODE_4_LEVEL 0x04
258 #define PAGE_MODE_5_LEVEL 0x05
259 #define PAGE_MODE_6_LEVEL 0x06
260 #define PAGE_MODE_7_LEVEL 0x07
262 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
263 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
264 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
265 (0xffffffffffffffffULL))
266 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
267 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
268 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
269 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
270 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
273 #define PM_ADDR_MASK 0x000ffffffffff000ULL
274 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
275 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
276 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
279 * Returns the page table level to use for a given page size
280 * Pagesize is expected to be a power-of-two
282 #define PAGE_SIZE_LEVEL(pagesize) \
283 ((__ffs(pagesize) - 12) / 9)
285 * Returns the number of ptes to use for a given page size
286 * Pagesize is expected to be a power-of-two
288 #define PAGE_SIZE_PTE_COUNT(pagesize) \
289 (1ULL << ((__ffs(pagesize) - 12) % 9))
292 * Aligns a given io-virtual address to a given page size
293 * Pagesize is expected to be a power-of-two
295 #define PAGE_SIZE_ALIGN(address, pagesize) \
296 ((address) & ~((pagesize) - 1))
298 * Creates an IOMMU PTE for an address and a given pagesize
299 * The PTE has no permission bits set
300 * Pagesize is expected to be a power-of-two larger than 4096
302 #define PAGE_SIZE_PTE(address, pagesize) \
303 (((address) | ((pagesize) - 1)) & \
304 (~(pagesize >> 1)) & PM_ADDR_MASK)
307 * Takes a PTE value with mode=0x07 and returns the page size it maps
309 #define PTE_PAGE_SIZE(pte) \
310 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
313 * Takes a page-table level and returns the default page-size for this level
315 #define PTE_LEVEL_PAGE_SIZE(level) \
316 (1ULL << (12 + (9 * (level))))
319 * Bit value definition for I/O PTE fields
321 #define IOMMU_PTE_PR (1ULL << 0)
322 #define IOMMU_PTE_U (1ULL << 59)
323 #define IOMMU_PTE_FC (1ULL << 60)
324 #define IOMMU_PTE_IR (1ULL << 61)
325 #define IOMMU_PTE_IW (1ULL << 62)
328 * Bit value definition for DTE fields
330 #define DTE_FLAG_V (1ULL << 0)
331 #define DTE_FLAG_TV (1ULL << 1)
332 #define DTE_FLAG_IR (1ULL << 61)
333 #define DTE_FLAG_IW (1ULL << 62)
335 #define DTE_FLAG_IOTLB (1ULL << 32)
336 #define DTE_FLAG_GV (1ULL << 55)
337 #define DTE_FLAG_MASK (0x3ffULL << 32)
338 #define DTE_GLX_SHIFT (56)
339 #define DTE_GLX_MASK (3)
340 #define DEV_DOMID_MASK 0xffffULL
342 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
343 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
344 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL)
346 #define DTE_GCR3_INDEX_A 0
347 #define DTE_GCR3_INDEX_B 1
348 #define DTE_GCR3_INDEX_C 1
350 #define DTE_GCR3_SHIFT_A 58
351 #define DTE_GCR3_SHIFT_B 16
352 #define DTE_GCR3_SHIFT_C 43
354 #define GCR3_VALID 0x01ULL
356 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
357 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR)
358 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK))
359 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
361 #define IOMMU_PROT_MASK 0x03
362 #define IOMMU_PROT_IR 0x01
363 #define IOMMU_PROT_IW 0x02
365 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
367 /* IOMMU capabilities */
368 #define IOMMU_CAP_IOTLB 24
369 #define IOMMU_CAP_NPCACHE 26
370 #define IOMMU_CAP_EFR 27
372 /* IOMMU Feature Reporting Field (for IVHD type 10h */
373 #define IOMMU_FEAT_XTSUP_SHIFT 0
374 #define IOMMU_FEAT_GASUP_SHIFT 6
376 /* IOMMU Extended Feature Register (EFR) */
377 #define IOMMU_EFR_XTSUP_SHIFT 2
378 #define IOMMU_EFR_GASUP_SHIFT 7
380 #define MAX_DOMAIN_ID 65536
382 /* Protection domain flags */
383 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
384 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
385 domain for an IOMMU */
386 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
388 #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */
390 extern bool amd_iommu_dump;
391 #define DUMP_printk(format, arg...) \
393 if (amd_iommu_dump) \
394 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
397 /* global flag if IOMMUs cache non-present entries */
398 extern bool amd_iommu_np_cache;
399 /* Only true if all IOMMUs support device IOTLBs */
400 extern bool amd_iommu_iotlb_sup;
402 #define MAX_IRQS_PER_TABLE 256
403 #define IRQ_TABLE_ALIGNMENT 128
405 struct irq_remap_table {
411 extern struct irq_remap_table **irq_lookup_table;
413 /* Interrupt remapping feature used? */
414 extern bool amd_iommu_irq_remap;
416 /* kmem_cache to get tables with 128 byte alignement */
417 extern struct kmem_cache *amd_iommu_irq_cache;
420 * Make iterating over all IOMMUs easier
422 #define for_each_iommu(iommu) \
423 list_for_each_entry((iommu), &amd_iommu_list, list)
424 #define for_each_iommu_safe(iommu, next) \
425 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
427 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
428 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
429 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
430 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
431 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
432 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
435 * This struct is used to pass information about
436 * incoming PPR faults around.
438 struct amd_iommu_fault {
439 u64 address; /* IO virtual address of the fault*/
440 u32 pasid; /* Address space identifier */
441 u16 device_id; /* Originating PCI device id */
442 u16 tag; /* PPR tag */
443 u16 flags; /* Fault flags */
452 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
455 * This structure contains generic data for IOMMU protection domains
456 * independent of their use.
458 struct protection_domain {
459 struct list_head list; /* for list of all protection domains */
460 struct list_head dev_list; /* List of all devices in this domain */
461 struct iommu_domain domain; /* generic domain handle used by
463 spinlock_t lock; /* mostly used to lock the page table*/
464 struct mutex api_lock; /* protect page tables in the iommu-api path */
465 u16 id; /* the domain id written to the device table */
466 int mode; /* paging mode (0-6 levels) */
467 u64 *pt_root; /* page table root pointer */
468 int glx; /* Number of levels for GCR3 table */
469 u64 *gcr3_tbl; /* Guest CR3 table */
470 unsigned long flags; /* flags to find out type of domain */
471 bool updated; /* complete domain flush required */
472 unsigned dev_cnt; /* devices assigned to this domain */
473 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
477 * Structure where we save information about one hardware AMD IOMMU in the
481 struct list_head list;
483 /* Index within the IOMMU array */
486 /* locks the accesses to the hardware */
489 /* Pointer to PCI device of this IOMMU */
492 /* Cache pdev to root device for resume quirks */
493 struct pci_dev *root_pdev;
495 /* physical address of MMIO space */
498 /* physical end address of MMIO space */
501 /* virtual address of MMIO space */
502 u8 __iomem *mmio_base;
504 /* capabilities of that IOMMU read from ACPI */
507 /* flags read from acpi table */
510 /* Extended features */
516 /* PCI device id of the IOMMU device */
520 * Capability pointer. There could be more than one IOMMU per PCI
521 * device function if there are more than one AMD IOMMU capability
526 /* pci domain of this IOMMU */
529 /* start of exclusion range of that IOMMU */
531 /* length of exclusion range of that IOMMU */
532 u64 exclusion_length;
534 /* command buffer virtual address */
539 /* event buffer virtual address */
542 /* Base of the PPR log, if present */
545 /* Base of the GA log, if present */
548 /* Tail of the GA log, if present */
551 /* true if interrupts for this IOMMU are already enabled */
554 /* if one, we need to send a completion wait command */
557 /* Handle for IOMMU core code */
558 struct iommu_device iommu;
561 * We can't rely on the BIOS to restore all values on reinit, so we
570 * Each iommu has 6 l1s, each of which is documented as having 0x12
573 u32 stored_l1[6][0x12];
575 /* The l2 indirect registers */
578 /* The maximum PC banks and counters/bank (PCSup=1) */
581 #ifdef CONFIG_IRQ_REMAP
582 struct irq_domain *ir_domain;
583 struct irq_domain *msi_domain;
585 struct amd_irte_ops *irte_ops;
589 volatile u64 __aligned(8) cmd_sem;
591 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
593 struct dentry *debugfs;
597 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
599 struct iommu_device *iommu = dev_to_iommu_device(dev);
601 return container_of(iommu, struct amd_iommu, iommu);
604 #define ACPIHID_UID_LEN 256
605 #define ACPIHID_HID_LEN 9
607 struct acpihid_map_entry {
608 struct list_head list;
609 u8 uid[ACPIHID_UID_LEN];
610 u8 hid[ACPIHID_HID_LEN];
614 struct iommu_group *group;
618 struct list_head list;
625 * This struct contains device specific data for the IOMMU
627 struct iommu_dev_data {
628 struct list_head list; /* For domain->dev_list */
629 struct llist_node dev_data_list; /* For global dev_data_list */
630 struct protection_domain *domain; /* Domain the device is bound to */
631 u16 devid; /* PCI Device ID */
632 u16 alias; /* Alias Device ID */
633 bool iommu_v2; /* Device can make use of IOMMUv2 */
634 bool passthrough; /* Device is identity mapped */
638 } ats; /* ATS state */
639 bool pri_tlp; /* PASID TLB required for
641 u32 errata; /* Bitmap for errata to apply */
642 bool use_vapic; /* Enable device to use vapic mode */
645 struct ratelimit_state rs; /* Ratelimit IOPF messages */
648 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
649 extern struct list_head ioapic_map;
650 extern struct list_head hpet_map;
651 extern struct list_head acpihid_map;
654 * List with all IOMMUs in the system. This list is not locked because it is
655 * only written and read at driver initialization or suspend time
657 extern struct list_head amd_iommu_list;
660 * Array with pointers to each IOMMU struct
661 * The indices are referenced in the protection domains
663 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
666 * Structure defining one entry in the device table
668 struct dev_table_entry {
673 * One entry for unity mappings parsed out of the ACPI table.
675 struct unity_map_entry {
676 struct list_head list;
678 /* starting device id this entry is used for (including) */
680 /* end device id this entry is used for (including) */
683 /* start address to unity map (including) */
685 /* end address to unity map (including) */
688 /* required protection */
693 * List of all unity mappings. It is not locked because as runtime it is only
694 * read. It is created at ACPI table parsing time.
696 extern struct list_head amd_iommu_unity_map;
699 * Data structures for device handling
703 * Device table used by hardware. Read and write accesses by software are
704 * locked with the amd_iommu_pd_table lock.
706 extern struct dev_table_entry *amd_iommu_dev_table;
709 * Alias table to find requestor ids to device ids. Not locked because only
712 extern u16 *amd_iommu_alias_table;
715 * Reverse lookup table to find the IOMMU which translates a specific device.
717 extern struct amd_iommu **amd_iommu_rlookup_table;
719 /* size of the dma_ops aperture as power of 2 */
720 extern unsigned amd_iommu_aperture_order;
722 /* largest PCI device id we expect translation requests for */
723 extern u16 amd_iommu_last_bdf;
725 /* allocation bitmap for domain ids */
726 extern unsigned long *amd_iommu_pd_alloc_bitmap;
729 * If true, the addresses will be flushed on unmap time, not when
732 extern bool amd_iommu_unmap_flush;
734 /* Smallest max PASID supported by any IOMMU in the system */
735 extern u32 amd_iommu_max_pasid;
737 extern bool amd_iommu_v2_present;
739 extern bool amd_iommu_force_isolation;
741 /* Max levels of glxval supported */
742 extern int amd_iommu_max_glx_val;
745 * This function flushes all internal caches of
746 * the IOMMU used by this driver.
748 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
750 static inline int get_ioapic_devid(int id)
752 struct devid_map *entry;
754 list_for_each_entry(entry, &ioapic_map, list) {
762 static inline int get_hpet_devid(int id)
764 struct devid_map *entry;
766 list_for_each_entry(entry, &hpet_map, list) {
774 enum amd_iommu_intr_mode_type {
775 AMD_IOMMU_GUEST_IR_LEGACY,
777 /* This mode is not visible to users. It is used when
778 * we cannot fully enable vAPIC and fallback to only support
779 * legacy interrupt remapping via 128-bit IRTE.
781 AMD_IOMMU_GUEST_IR_LEGACY_GA,
782 AMD_IOMMU_GUEST_IR_VAPIC,
785 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
786 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
788 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
805 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff)
806 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff)
811 /* For int remapping */
825 /* For guest vAPIC */
857 u16 devid; /* Device ID for IRTE table */
858 u16 index; /* Index into IRTE table*/
863 struct irq_2_irte irq_2_irte;
864 struct msi_msg msi_entry;
865 void *entry; /* Pointer to union irte or struct irte_ga */
866 void *ref; /* Pointer to the actual irte */
869 struct amd_irte_ops {
870 void (*prepare)(void *, u32, u32, u8, u32, int);
871 void (*activate)(void *, u16, u16);
872 void (*deactivate)(void *, u16, u16);
873 void (*set_affinity)(void *, u16, u16, u8, u32);
874 void *(*get)(struct irq_remap_table *, int);
875 void (*set_allocated)(struct irq_remap_table *, int);
876 bool (*is_allocated)(struct irq_remap_table *, int);
877 void (*clear_allocated)(struct irq_remap_table *, int);
880 #ifdef CONFIG_IRQ_REMAP
881 extern struct amd_irte_ops irte_32_ops;
882 extern struct amd_irte_ops irte_128_ops;
885 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */