1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * IOMMU API for ARM architected SMMU implementations.
5 * Copyright (C) 2013 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
10 #ifndef _ARM_SMMU_REGS_H
11 #define _ARM_SMMU_REGS_H
13 /* Configuration registers */
14 #define ARM_SMMU_GR0_sCR0 0x0
15 #define sCR0_CLIENTPD (1 << 0)
16 #define sCR0_GFRE (1 << 1)
17 #define sCR0_GFIE (1 << 2)
18 #define sCR0_EXIDENABLE (1 << 3)
19 #define sCR0_GCFGFRE (1 << 4)
20 #define sCR0_GCFGFIE (1 << 5)
21 #define sCR0_USFCFG (1 << 10)
22 #define sCR0_VMIDPNE (1 << 11)
23 #define sCR0_PTM (1 << 12)
24 #define sCR0_FB (1 << 13)
25 #define sCR0_VMID16EN (1 << 31)
26 #define sCR0_BSU_SHIFT 14
27 #define sCR0_BSU_MASK 0x3
29 /* Auxiliary Configuration register */
30 #define ARM_SMMU_GR0_sACR 0x10
32 /* Identification registers */
33 #define ARM_SMMU_GR0_ID0 0x20
34 #define ARM_SMMU_GR0_ID1 0x24
35 #define ARM_SMMU_GR0_ID2 0x28
36 #define ARM_SMMU_GR0_ID3 0x2c
37 #define ARM_SMMU_GR0_ID4 0x30
38 #define ARM_SMMU_GR0_ID5 0x34
39 #define ARM_SMMU_GR0_ID6 0x38
40 #define ARM_SMMU_GR0_ID7 0x3c
41 #define ARM_SMMU_GR0_sGFSR 0x48
42 #define ARM_SMMU_GR0_sGFSYNR0 0x50
43 #define ARM_SMMU_GR0_sGFSYNR1 0x54
44 #define ARM_SMMU_GR0_sGFSYNR2 0x58
46 #define ID0_S1TS (1 << 30)
47 #define ID0_S2TS (1 << 29)
48 #define ID0_NTS (1 << 28)
49 #define ID0_SMS (1 << 27)
50 #define ID0_ATOSNS (1 << 26)
51 #define ID0_PTFS_NO_AARCH32 (1 << 25)
52 #define ID0_PTFS_NO_AARCH32S (1 << 24)
53 #define ID0_CTTW (1 << 14)
54 #define ID0_NUMIRPT_SHIFT 16
55 #define ID0_NUMIRPT_MASK 0xff
56 #define ID0_NUMSIDB_SHIFT 9
57 #define ID0_NUMSIDB_MASK 0xf
58 #define ID0_EXIDS (1 << 8)
59 #define ID0_NUMSMRG_SHIFT 0
60 #define ID0_NUMSMRG_MASK 0xff
62 #define ID1_PAGESIZE (1 << 31)
63 #define ID1_NUMPAGENDXB_SHIFT 28
64 #define ID1_NUMPAGENDXB_MASK 7
65 #define ID1_NUMS2CB_SHIFT 16
66 #define ID1_NUMS2CB_MASK 0xff
67 #define ID1_NUMCB_SHIFT 0
68 #define ID1_NUMCB_MASK 0xff
70 #define ID2_OAS_SHIFT 4
71 #define ID2_OAS_MASK 0xf
72 #define ID2_IAS_SHIFT 0
73 #define ID2_IAS_MASK 0xf
74 #define ID2_UBS_SHIFT 8
75 #define ID2_UBS_MASK 0xf
76 #define ID2_PTFS_4K (1 << 12)
77 #define ID2_PTFS_16K (1 << 13)
78 #define ID2_PTFS_64K (1 << 14)
79 #define ID2_VMID16 (1 << 15)
81 #define ID7_MAJOR_SHIFT 4
82 #define ID7_MAJOR_MASK 0xf
84 /* Global TLB invalidation */
85 #define ARM_SMMU_GR0_TLBIVMID 0x64
86 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
87 #define ARM_SMMU_GR0_TLBIALLH 0x6c
88 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
89 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
90 #define sTLBGSTATUS_GSACTIVE (1 << 0)
92 /* Stream mapping registers */
93 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
94 #define SMR_VALID (1 << 31)
95 #define SMR_MASK_SHIFT 16
96 #define SMR_ID_SHIFT 0
98 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
99 #define S2CR_CBNDX_SHIFT 0
100 #define S2CR_CBNDX_MASK 0xff
101 #define S2CR_EXIDVALID (1 << 10)
102 #define S2CR_TYPE_SHIFT 16
103 #define S2CR_TYPE_MASK 0x3
104 enum arm_smmu_s2cr_type {
110 #define S2CR_PRIVCFG_SHIFT 24
111 #define S2CR_PRIVCFG_MASK 0x3
112 enum arm_smmu_s2cr_privcfg {
113 S2CR_PRIVCFG_DEFAULT,
119 /* Context bank attribute registers */
120 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
121 #define CBAR_VMID_SHIFT 0
122 #define CBAR_VMID_MASK 0xff
123 #define CBAR_S1_BPSHCFG_SHIFT 8
124 #define CBAR_S1_BPSHCFG_MASK 3
125 #define CBAR_S1_BPSHCFG_NSH 3
126 #define CBAR_S1_MEMATTR_SHIFT 12
127 #define CBAR_S1_MEMATTR_MASK 0xf
128 #define CBAR_S1_MEMATTR_WB 0xf
129 #define CBAR_TYPE_SHIFT 16
130 #define CBAR_TYPE_MASK 0x3
131 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
132 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
133 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
134 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
135 #define CBAR_IRPTNDX_SHIFT 24
136 #define CBAR_IRPTNDX_MASK 0xff
138 #define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2))
140 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
141 #define CBA2R_RW64_32BIT (0 << 0)
142 #define CBA2R_RW64_64BIT (1 << 0)
143 #define CBA2R_VMID_SHIFT 16
144 #define CBA2R_VMID_MASK 0xffff
146 #define ARM_SMMU_CB_SCTLR 0x0
147 #define ARM_SMMU_CB_ACTLR 0x4
148 #define ARM_SMMU_CB_RESUME 0x8
149 #define ARM_SMMU_CB_TTBCR2 0x10
150 #define ARM_SMMU_CB_TTBR0 0x20
151 #define ARM_SMMU_CB_TTBR1 0x28
152 #define ARM_SMMU_CB_TTBCR 0x30
153 #define ARM_SMMU_CB_CONTEXTIDR 0x34
154 #define ARM_SMMU_CB_S1_MAIR0 0x38
155 #define ARM_SMMU_CB_S1_MAIR1 0x3c
156 #define ARM_SMMU_CB_PAR 0x50
157 #define ARM_SMMU_CB_FSR 0x58
158 #define ARM_SMMU_CB_FAR 0x60
159 #define ARM_SMMU_CB_FSYNR0 0x68
160 #define ARM_SMMU_CB_S1_TLBIVA 0x600
161 #define ARM_SMMU_CB_S1_TLBIASID 0x610
162 #define ARM_SMMU_CB_S1_TLBIVAL 0x620
163 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
164 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
165 #define ARM_SMMU_CB_TLBSYNC 0x7f0
166 #define ARM_SMMU_CB_TLBSTATUS 0x7f4
167 #define ARM_SMMU_CB_ATS1PR 0x800
168 #define ARM_SMMU_CB_ATSR 0x8f0
170 #define SCTLR_S1_ASIDPNE (1 << 12)
171 #define SCTLR_CFCFG (1 << 7)
172 #define SCTLR_CFIE (1 << 6)
173 #define SCTLR_CFRE (1 << 5)
174 #define SCTLR_E (1 << 4)
175 #define SCTLR_AFE (1 << 2)
176 #define SCTLR_TRE (1 << 1)
177 #define SCTLR_M (1 << 0)
179 #define CB_PAR_F (1 << 0)
181 #define ATSR_ACTIVE (1 << 0)
183 #define RESUME_RETRY (0 << 0)
184 #define RESUME_TERMINATE (1 << 0)
186 #define TTBCR2_SEP_SHIFT 15
187 #define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
188 #define TTBCR2_AS (1 << 4)
190 #define TTBRn_ASID_SHIFT 48
192 #define FSR_MULTI (1 << 31)
193 #define FSR_SS (1 << 30)
194 #define FSR_UUT (1 << 8)
195 #define FSR_ASF (1 << 7)
196 #define FSR_TLBLKF (1 << 6)
197 #define FSR_TLBMCF (1 << 5)
198 #define FSR_EF (1 << 4)
199 #define FSR_PF (1 << 3)
200 #define FSR_AFF (1 << 2)
201 #define FSR_TF (1 << 1)
203 #define FSR_IGN (FSR_AFF | FSR_ASF | \
204 FSR_TLBMCF | FSR_TLBLKF)
205 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
206 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
208 #define FSYNR0_WNR (1 << 4)
210 #endif /* _ARM_SMMU_REGS_H */