drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - Context fault reporting
  27  */
  28
  29 #define pr_fmt(fmt) "arm-smmu: " fmt
  30
  31 #include <linux/acpi.h>
  32 #include <linux/acpi_iort.h>
  33 #include <linux/atomic.h>
  34 #include <linux/delay.h>
  35 #include <linux/dma-iommu.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/err.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/io.h>
  40 #include <linux/io-64-nonatomic-hi-lo.h>
  41 #include <linux/iommu.h>
  42 #include <linux/iopoll.h>
  43 #include <linux/module.h>
  44 #include <linux/of.h>
  45 #include <linux/of_address.h>
  46 #include <linux/of_device.h>
  47 #include <linux/of_iommu.h>
  48 #include <linux/pci.h>
  49 #include <linux/platform_device.h>
  50 #include <linux/slab.h>
  51 #include <linux/spinlock.h>
  52
  53 #include <linux/amba/bus.h>
  54
  55 #include "io-pgtable.h"
  56
  57 /* Maximum number of context banks per SMMU */
  58 #define ARM_SMMU_MAX_CBS                128
  59
  60 /* SMMU global address space */
  61 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  62 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (1 << (smmu)->pgshift))
  63
  64 /*
  65  * SMMU global address space with conditional offset to access secure
  66  * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
  67  * nsGFSYNR0: 0x450)
  68  */
  69 #define ARM_SMMU_GR0_NS(smmu)                                           \
  70         ((smmu)->base +                                                 \
  71                 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
  72                         ? 0x400 : 0))
  73
  74 /*
  75  * Some 64-bit registers only make sense to write atomically, but in such
  76  * cases all the data relevant to AArch32 formats lies within the lower word,
  77  * therefore this actually makes more sense than it might first appear.
  78  */
  79 #ifdef CONFIG_64BIT
  80 #define smmu_write_atomic_lq            writeq_relaxed
  81 #else
  82 #define smmu_write_atomic_lq            writel_relaxed
  83 #endif
  84
  85 /* Configuration registers */
  86 #define ARM_SMMU_GR0_sCR0               0x0
  87 #define sCR0_CLIENTPD                   (1 << 0)
  88 #define sCR0_GFRE                       (1 << 1)
  89 #define sCR0_GFIE                       (1 << 2)
  90 #define sCR0_GCFGFRE                    (1 << 4)
  91 #define sCR0_GCFGFIE                    (1 << 5)
  92 #define sCR0_USFCFG                     (1 << 10)
  93 #define sCR0_VMIDPNE                    (1 << 11)
  94 #define sCR0_PTM                        (1 << 12)
  95 #define sCR0_FB                         (1 << 13)
  96 #define sCR0_VMID16EN                   (1 << 31)
  97 #define sCR0_BSU_SHIFT                  14
  98 #define sCR0_BSU_MASK                   0x3
  99
 100 /* Auxiliary Configuration register */
 101 #define ARM_SMMU_GR0_sACR               0x10
 102
 103 /* Identification registers */
 104 #define ARM_SMMU_GR0_ID0                0x20
 105 #define ARM_SMMU_GR0_ID1                0x24
 106 #define ARM_SMMU_GR0_ID2                0x28
 107 #define ARM_SMMU_GR0_ID3                0x2c
 108 #define ARM_SMMU_GR0_ID4                0x30
 109 #define ARM_SMMU_GR0_ID5                0x34
 110 #define ARM_SMMU_GR0_ID6                0x38
 111 #define ARM_SMMU_GR0_ID7                0x3c
 112 #define ARM_SMMU_GR0_sGFSR              0x48
 113 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 114 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 115 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 116
 117 #define ID0_S1TS                        (1 << 30)
 118 #define ID0_S2TS                        (1 << 29)
 119 #define ID0_NTS                         (1 << 28)
 120 #define ID0_SMS                         (1 << 27)
 121 #define ID0_ATOSNS                      (1 << 26)
 122 #define ID0_PTFS_NO_AARCH32             (1 << 25)
 123 #define ID0_PTFS_NO_AARCH32S            (1 << 24)
 124 #define ID0_CTTW                        (1 << 14)
 125 #define ID0_NUMIRPT_SHIFT               16
 126 #define ID0_NUMIRPT_MASK                0xff
 127 #define ID0_NUMSIDB_SHIFT               9
 128 #define ID0_NUMSIDB_MASK                0xf
 129 #define ID0_NUMSMRG_SHIFT               0
 130 #define ID0_NUMSMRG_MASK                0xff
 131
 132 #define ID1_PAGESIZE                    (1 << 31)
 133 #define ID1_NUMPAGENDXB_SHIFT           28
 134 #define ID1_NUMPAGENDXB_MASK            7
 135 #define ID1_NUMS2CB_SHIFT               16
 136 #define ID1_NUMS2CB_MASK                0xff
 137 #define ID1_NUMCB_SHIFT                 0
 138 #define ID1_NUMCB_MASK                  0xff
 139
 140 #define ID2_OAS_SHIFT                   4
 141 #define ID2_OAS_MASK                    0xf
 142 #define ID2_IAS_SHIFT                   0
 143 #define ID2_IAS_MASK                    0xf
 144 #define ID2_UBS_SHIFT                   8
 145 #define ID2_UBS_MASK                    0xf
 146 #define ID2_PTFS_4K                     (1 << 12)
 147 #define ID2_PTFS_16K                    (1 << 13)
 148 #define ID2_PTFS_64K                    (1 << 14)
 149 #define ID2_VMID16                      (1 << 15)
 150
 151 #define ID7_MAJOR_SHIFT                 4
 152 #define ID7_MAJOR_MASK                  0xf
 153
 154 /* Global TLB invalidation */
 155 #define ARM_SMMU_GR0_TLBIVMID           0x64
 156 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 157 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 158 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 159 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 160 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 161 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 162
 163 /* Stream mapping registers */
 164 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 165 #define SMR_VALID                       (1 << 31)
 166 #define SMR_MASK_SHIFT                  16
 167 #define SMR_ID_SHIFT                    0
 168
 169 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 170 #define S2CR_CBNDX_SHIFT                0
 171 #define S2CR_CBNDX_MASK                 0xff
 172 #define S2CR_TYPE_SHIFT                 16
 173 #define S2CR_TYPE_MASK                  0x3
 174 enum arm_smmu_s2cr_type {
 175         S2CR_TYPE_TRANS,
 176         S2CR_TYPE_BYPASS,
 177         S2CR_TYPE_FAULT,
 178 };
 179
 180 #define S2CR_PRIVCFG_SHIFT              24
 181 #define S2CR_PRIVCFG_MASK               0x3
 182 enum arm_smmu_s2cr_privcfg {
 183         S2CR_PRIVCFG_DEFAULT,
 184         S2CR_PRIVCFG_DIPAN,
 185         S2CR_PRIVCFG_UNPRIV,
 186         S2CR_PRIVCFG_PRIV,
 187 };
 188
 189 /* Context bank attribute registers */
 190 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 191 #define CBAR_VMID_SHIFT                 0
 192 #define CBAR_VMID_MASK                  0xff
 193 #define CBAR_S1_BPSHCFG_SHIFT           8
 194 #define CBAR_S1_BPSHCFG_MASK            3
 195 #define CBAR_S1_BPSHCFG_NSH             3
 196 #define CBAR_S1_MEMATTR_SHIFT           12
 197 #define CBAR_S1_MEMATTR_MASK            0xf
 198 #define CBAR_S1_MEMATTR_WB              0xf
 199 #define CBAR_TYPE_SHIFT                 16
 200 #define CBAR_TYPE_MASK                  0x3
 201 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 202 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 203 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 204 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 205 #define CBAR_IRPTNDX_SHIFT              24
 206 #define CBAR_IRPTNDX_MASK               0xff
 207
 208 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 209 #define CBA2R_RW64_32BIT                (0 << 0)
 210 #define CBA2R_RW64_64BIT                (1 << 0)
 211 #define CBA2R_VMID_SHIFT                16
 212 #define CBA2R_VMID_MASK                 0xffff
 213
 214 /* Translation context bank */
 215 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 216 #define ARM_SMMU_CB(smmu, n)            ((n) * (1 << (smmu)->pgshift))
 217
 218 #define ARM_SMMU_CB_SCTLR               0x0
 219 #define ARM_SMMU_CB_ACTLR               0x4
 220 #define ARM_SMMU_CB_RESUME              0x8
 221 #define ARM_SMMU_CB_TTBCR2              0x10
 222 #define ARM_SMMU_CB_TTBR0               0x20
 223 #define ARM_SMMU_CB_TTBR1               0x28
 224 #define ARM_SMMU_CB_TTBCR               0x30
 225 #define ARM_SMMU_CB_CONTEXTIDR          0x34
 226 #define ARM_SMMU_CB_S1_MAIR0            0x38
 227 #define ARM_SMMU_CB_S1_MAIR1            0x3c
 228 #define ARM_SMMU_CB_PAR                 0x50
 229 #define ARM_SMMU_CB_FSR                 0x58
 230 #define ARM_SMMU_CB_FAR                 0x60
 231 #define ARM_SMMU_CB_FSYNR0              0x68
 232 #define ARM_SMMU_CB_S1_TLBIVA           0x600
 233 #define ARM_SMMU_CB_S1_TLBIASID         0x610
 234 #define ARM_SMMU_CB_S1_TLBIVAL          0x620
 235 #define ARM_SMMU_CB_S2_TLBIIPAS2        0x630
 236 #define ARM_SMMU_CB_S2_TLBIIPAS2L       0x638
 237 #define ARM_SMMU_CB_ATS1PR              0x800
 238 #define ARM_SMMU_CB_ATSR                0x8f0
 239
 240 #define SCTLR_S1_ASIDPNE                (1 << 12)
 241 #define SCTLR_CFCFG                     (1 << 7)
 242 #define SCTLR_CFIE                      (1 << 6)
 243 #define SCTLR_CFRE                      (1 << 5)
 244 #define SCTLR_E                         (1 << 4)
 245 #define SCTLR_AFE                       (1 << 2)
 246 #define SCTLR_TRE                       (1 << 1)
 247 #define SCTLR_M                         (1 << 0)
 248
 249 #define ARM_MMU500_ACTLR_CPRE           (1 << 1)
 250
 251 #define ARM_MMU500_ACR_CACHE_LOCK       (1 << 26)
 252 #define ARM_MMU500_ACR_SMTNMB_TLBEN     (1 << 8)
 253
 254 #define CB_PAR_F                        (1 << 0)
 255
 256 #define ATSR_ACTIVE                     (1 << 0)
 257
 258 #define RESUME_RETRY                    (0 << 0)
 259 #define RESUME_TERMINATE                (1 << 0)
 260
 261 #define TTBCR2_SEP_SHIFT                15
 262 #define TTBCR2_SEP_UPSTREAM             (0x7 << TTBCR2_SEP_SHIFT)
 263
 264 #define TTBRn_ASID_SHIFT                48
 265
 266 #define FSR_MULTI                       (1 << 31)
 267 #define FSR_SS                          (1 << 30)
 268 #define FSR_UUT                         (1 << 8)
 269 #define FSR_ASF                         (1 << 7)
 270 #define FSR_TLBLKF                      (1 << 6)
 271 #define FSR_TLBMCF                      (1 << 5)
 272 #define FSR_EF                          (1 << 4)
 273 #define FSR_PF                          (1 << 3)
 274 #define FSR_AFF                         (1 << 2)
 275 #define FSR_TF                          (1 << 1)
 276
 277 #define FSR_IGN                         (FSR_AFF | FSR_ASF | \
 278                                          FSR_TLBMCF | FSR_TLBLKF)
 279 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT | \
 280                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
 281
 282 #define FSYNR0_WNR                      (1 << 4)
 283
 284 #define MSI_IOVA_BASE                   0x8000000
 285 #define MSI_IOVA_LENGTH                 0x100000
 286
 287 static int force_stage;
 288 module_param(force_stage, int, S_IRUGO);
 289 MODULE_PARM_DESC(force_stage,
 290         "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
 291 static bool disable_bypass;
 292 module_param(disable_bypass, bool, S_IRUGO);
 293 MODULE_PARM_DESC(disable_bypass,
 294         "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
 295
 296 enum arm_smmu_arch_version {
 297         ARM_SMMU_V1,
 298         ARM_SMMU_V1_64K,
 299         ARM_SMMU_V2,
 300 };
 301
 302 enum arm_smmu_implementation {
 303         GENERIC_SMMU,
 304         ARM_MMU500,
 305         CAVIUM_SMMUV2,
 306 };
 307
 308 struct arm_smmu_s2cr {
 309         struct iommu_group              *group;
 310         int                             count;
 311         enum arm_smmu_s2cr_type         type;
 312         enum arm_smmu_s2cr_privcfg      privcfg;
 313         u8                              cbndx;
 314 };
 315
 316 #define s2cr_init_val (struct arm_smmu_s2cr){                           \
 317         .type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS,    \
 318 }
 319
 320 struct arm_smmu_smr {
 321         u16                             mask;
 322         u16                             id;
 323         bool                            valid;
 324 };
 325
 326 struct arm_smmu_master_cfg {
 327         struct arm_smmu_device          *smmu;
 328         s16                             smendx[];
 329 };
 330 #define INVALID_SMENDX                  -1
 331 #define __fwspec_cfg(fw) ((struct arm_smmu_master_cfg *)fw->iommu_priv)
 332 #define fwspec_smmu(fw)  (__fwspec_cfg(fw)->smmu)
 333 #define fwspec_smendx(fw, i) \
 334         (i >= fw->num_ids ? INVALID_SMENDX : __fwspec_cfg(fw)->smendx[i])
 335 #define for_each_cfg_sme(fw, i, idx) \
 336         for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i)
 337
 338 struct arm_smmu_device {
 339         struct device                   *dev;
 340
 341         void __iomem                    *base;
 342         unsigned long                   size;
 343         unsigned long                   pgshift;
 344
 345 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 346 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 347 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 348 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 349 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 350 #define ARM_SMMU_FEAT_TRANS_OPS         (1 << 5)
 351 #define ARM_SMMU_FEAT_VMID16            (1 << 6)
 352 #define ARM_SMMU_FEAT_FMT_AARCH64_4K    (1 << 7)
 353 #define ARM_SMMU_FEAT_FMT_AARCH64_16K   (1 << 8)
 354 #define ARM_SMMU_FEAT_FMT_AARCH64_64K   (1 << 9)
 355 #define ARM_SMMU_FEAT_FMT_AARCH32_L     (1 << 10)
 356 #define ARM_SMMU_FEAT_FMT_AARCH32_S     (1 << 11)
 357         u32                             features;
 358
 359 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
 360         u32                             options;
 361         enum arm_smmu_arch_version      version;
 362         enum arm_smmu_implementation    model;
 363
 364         u32                             num_context_banks;
 365         u32                             num_s2_context_banks;
 366         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 367         atomic_t                        irptndx;
 368
 369         u32                             num_mapping_groups;
 370         u16                             streamid_mask;
 371         u16                             smr_mask_mask;
 372         struct arm_smmu_smr             *smrs;
 373         struct arm_smmu_s2cr            *s2crs;
 374         struct mutex                    stream_map_mutex;
 375
 376         unsigned long                   va_size;
 377         unsigned long                   ipa_size;
 378         unsigned long                   pa_size;
 379         unsigned long                   pgsize_bitmap;
 380
 381         u32                             num_global_irqs;
 382         u32                             num_context_irqs;
 383         unsigned int                    *irqs;
 384
 385         u32                             cavium_id_base; /* Specific to Cavium */
 386 };
 387
 388 enum arm_smmu_context_fmt {
 389         ARM_SMMU_CTX_FMT_NONE,
 390         ARM_SMMU_CTX_FMT_AARCH64,
 391         ARM_SMMU_CTX_FMT_AARCH32_L,
 392         ARM_SMMU_CTX_FMT_AARCH32_S,
 393 };
 394
 395 struct arm_smmu_cfg {
 396         u8                              cbndx;
 397         u8                              irptndx;
 398         u32                             cbar;
 399         enum arm_smmu_context_fmt       fmt;
 400 };
 401 #define INVALID_IRPTNDX                 0xff
 402
 403 #define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
 404 #define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
 405
 406 enum arm_smmu_domain_stage {
 407         ARM_SMMU_DOMAIN_S1 = 0,
 408         ARM_SMMU_DOMAIN_S2,
 409         ARM_SMMU_DOMAIN_NESTED,
 410 };
 411
 412 struct arm_smmu_domain {
 413         struct arm_smmu_device          *smmu;
 414         struct io_pgtable_ops           *pgtbl_ops;
 415         spinlock_t                      pgtbl_lock;
 416         struct arm_smmu_cfg             cfg;
 417         enum arm_smmu_domain_stage      stage;
 418         struct mutex                    init_mutex; /* Protects smmu pointer */
 419         struct iommu_domain             domain;
 420 };
 421
 422 struct arm_smmu_option_prop {
 423         u32 opt;
 424         const char *prop;
 425 };
 426
 427 static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);
 428
 429 static bool using_legacy_binding, using_generic_binding;
 430
 431 static struct arm_smmu_option_prop arm_smmu_options[] = {
 432         { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
 433         { 0, NULL},
 434 };
 435
 436 static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
 437 {
 438         return container_of(dom, struct arm_smmu_domain, domain);
 439 }
 440
 441 static void parse_driver_options(struct arm_smmu_device *smmu)
 442 {
 443         int i = 0;
 444
 445         do {
 446                 if (of_property_read_bool(smmu->dev->of_node,
 447                                                 arm_smmu_options[i].prop)) {
 448                         smmu->options |= arm_smmu_options[i].opt;
 449                         dev_notice(smmu->dev, "option %s\n",
 450                                 arm_smmu_options[i].prop);
 451                 }
 452         } while (arm_smmu_options[++i].opt);
 453 }
 454
 455 static struct device_node *dev_get_dev_node(struct device *dev)
 456 {
 457         if (dev_is_pci(dev)) {
 458                 struct pci_bus *bus = to_pci_dev(dev)->bus;
 459
 460                 while (!pci_is_root_bus(bus))
 461                         bus = bus->parent;
 462                 return of_node_get(bus->bridge->parent->of_node);
 463         }
 464
 465         return of_node_get(dev->of_node);
 466 }
 467
 468 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
 469 {
 470         *((__be32 *)data) = cpu_to_be32(alias);
 471         return 0; /* Continue walking */
 472 }
 473
 474 static int __find_legacy_master_phandle(struct device *dev, void *data)
 475 {
 476         struct of_phandle_iterator *it = *(void **)data;
 477         struct device_node *np = it->node;
 478         int err;
 479
 480         of_for_each_phandle(it, err, dev->of_node, "mmu-masters",
 481                             "#stream-id-cells", 0)
 482                 if (it->node == np) {
 483                         *(void **)data = dev;
 484                         return 1;
 485                 }
 486         it->node = np;
 487         return err == -ENOENT ? 0 : err;
 488 }
 489
 490 static struct platform_driver arm_smmu_driver;
 491 static struct iommu_ops arm_smmu_ops;
 492
 493 static int arm_smmu_register_legacy_master(struct device *dev,
 494                                            struct arm_smmu_device **smmu)
 495 {
 496         struct device *smmu_dev;
 497         struct device_node *np;
 498         struct of_phandle_iterator it;
 499         void *data = &it;
 500         u32 *sids;
 501         __be32 pci_sid;
 502         int err;
 503
 504         np = dev_get_dev_node(dev);
 505         if (!np || !of_find_property(np, "#stream-id-cells", NULL)) {
 506                 of_node_put(np);
 507                 return -ENODEV;
 508         }
 509
 510         it.node = np;
 511         err = driver_for_each_device(&arm_smmu_driver.driver, NULL, &data,
 512                                      __find_legacy_master_phandle);
 513         smmu_dev = data;
 514         of_node_put(np);
 515         if (err == 0)
 516                 return -ENODEV;
 517         if (err < 0)
 518                 return err;
 519
 520         if (dev_is_pci(dev)) {
 521                 /* "mmu-masters" assumes Stream ID == Requester ID */
 522                 pci_for_each_dma_alias(to_pci_dev(dev), __arm_smmu_get_pci_sid,
 523                                        &pci_sid);
 524                 it.cur = &pci_sid;
 525                 it.cur_count = 1;
 526         }
 527
 528         err = iommu_fwspec_init(dev, &smmu_dev->of_node->fwnode,
 529                                 &arm_smmu_ops);
 530         if (err)
 531                 return err;
 532
 533         sids = kcalloc(it.cur_count, sizeof(*sids), GFP_KERNEL);
 534         if (!sids)
 535                 return -ENOMEM;
 536
 537         *smmu = dev_get_drvdata(smmu_dev);
 538         of_phandle_iterator_args(&it, sids, it.cur_count);
 539         err = iommu_fwspec_add_ids(dev, sids, it.cur_count);
 540         kfree(sids);
 541         return err;
 542 }
 543
 544 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 545 {
 546         int idx;
 547
 548         do {
 549                 idx = find_next_zero_bit(map, end, start);
 550                 if (idx == end)
 551                         return -ENOSPC;
 552         } while (test_and_set_bit(idx, map));
 553
 554         return idx;
 555 }
 556
 557 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 558 {
 559         clear_bit(idx, map);
 560 }
 561
 562 /* Wait for any pending TLB invalidations to complete */
 563 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 564 {
 565         int count = 0;
 566         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 567
 568         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 569         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 570                & sTLBGSTATUS_GSACTIVE) {
 571                 cpu_relax();
 572                 if (++count == TLB_LOOP_TIMEOUT) {
 573                         dev_err_ratelimited(smmu->dev,
 574                         "TLB sync timed out -- SMMU may be deadlocked\n");
 575                         return;
 576                 }
 577                 udelay(1);
 578         }
 579 }
 580
 581 static void arm_smmu_tlb_sync(void *cookie)
 582 {
 583         struct arm_smmu_domain *smmu_domain = cookie;
 584         __arm_smmu_tlb_sync(smmu_domain->smmu);
 585 }
 586
 587 static void arm_smmu_tlb_inv_context(void *cookie)
 588 {
 589         struct arm_smmu_domain *smmu_domain = cookie;
 590         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 591         struct arm_smmu_device *smmu = smmu_domain->smmu;
 592         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 593         void __iomem *base;
 594
 595         if (stage1) {
 596                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 597                 writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg),
 598                                base + ARM_SMMU_CB_S1_TLBIASID);
 599         } else {
 600                 base = ARM_SMMU_GR0(smmu);
 601                 writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg),
 602                                base + ARM_SMMU_GR0_TLBIVMID);
 603         }
 604
 605         __arm_smmu_tlb_sync(smmu);
 606 }
 607
 608 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
 609                                           size_t granule, bool leaf, void *cookie)
 610 {
 611         struct arm_smmu_domain *smmu_domain = cookie;
 612         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 613         struct arm_smmu_device *smmu = smmu_domain->smmu;
 614         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 615         void __iomem *reg;
 616
 617         if (stage1) {
 618                 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 619                 reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
 620
 621                 if (cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) {
 622                         iova &= ~12UL;
 623                         iova |= ARM_SMMU_CB_ASID(smmu, cfg);
 624                         do {
 625                                 writel_relaxed(iova, reg);
 626                                 iova += granule;
 627                         } while (size -= granule);
 628                 } else {
 629                         iova >>= 12;
 630                         iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48;
 631                         do {
 632                                 writeq_relaxed(iova, reg);
 633                                 iova += granule >> 12;
 634                         } while (size -= granule);
 635                 }
 636         } else if (smmu->version == ARM_SMMU_V2) {
 637                 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 638                 reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
 639                               ARM_SMMU_CB_S2_TLBIIPAS2;
 640                 iova >>= 12;
 641                 do {
 642                         smmu_write_atomic_lq(iova, reg);
 643                         iova += granule >> 12;
 644                 } while (size -= granule);
 645         } else {
 646                 reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
 647                 writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg);
 648         }
 649 }
 650
 651 static const struct iommu_gather_ops arm_smmu_gather_ops = {
 652         .tlb_flush_all  = arm_smmu_tlb_inv_context,
 653         .tlb_add_flush  = arm_smmu_tlb_inv_range_nosync,
 654         .tlb_sync       = arm_smmu_tlb_sync,
 655 };
 656
 657 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 658 {
 659         u32 fsr, fsynr;
 660         unsigned long iova;
 661         struct iommu_domain *domain = dev;
 662         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 663         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 664         struct arm_smmu_device *smmu = smmu_domain->smmu;
 665         void __iomem *cb_base;
 666
 667         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 668         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 669
 670         if (!(fsr & FSR_FAULT))
 671                 return IRQ_NONE;
 672
 673         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 674         iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
 675
 676         dev_err_ratelimited(smmu->dev,
 677         "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
 678                             fsr, iova, fsynr, cfg->cbndx);
 679
 680         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 681         return IRQ_HANDLED;
 682 }
 683
 684 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 685 {
 686         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 687         struct arm_smmu_device *smmu = dev;
 688         void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
 689
 690         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 691         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 692         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 693         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 694
 695         if (!gfsr)
 696                 return IRQ_NONE;
 697
 698         dev_err_ratelimited(smmu->dev,
 699                 "Unexpected global fault, this could be serious\n");
 700         dev_err_ratelimited(smmu->dev,
 701                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 702                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 703
 704         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 705         return IRQ_HANDLED;
 706 }
 707
 708 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 709                                        struct io_pgtable_cfg *pgtbl_cfg)
 710 {
 711         u32 reg, reg2;
 712         u64 reg64;
 713         bool stage1;
 714         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 715         struct arm_smmu_device *smmu = smmu_domain->smmu;
 716         void __iomem *cb_base, *gr1_base;
 717
 718         gr1_base = ARM_SMMU_GR1(smmu);
 719         stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
 720         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 721
 722         if (smmu->version > ARM_SMMU_V1) {
 723                 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
 724                         reg = CBA2R_RW64_64BIT;
 725                 else
 726                         reg = CBA2R_RW64_32BIT;
 727                 /* 16-bit VMIDs live in CBA2R */
 728                 if (smmu->features & ARM_SMMU_FEAT_VMID16)
 729                         reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT;
 730
 731                 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
 732         }
 733
 734         /* CBAR */
 735         reg = cfg->cbar;
 736         if (smmu->version < ARM_SMMU_V2)
 737                 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 738
 739         /*
 740          * Use the weakest shareability/memory types, so they are
 741          * overridden by the ttbcr/pte.
 742          */
 743         if (stage1) {
 744                 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
 745                         (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 746         } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
 747                 /* 8-bit VMIDs live in CBAR */
 748                 reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT;
 749         }
 750         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
 751
 752         /* TTBRs */
 753         if (stage1) {
 754                 u16 asid = ARM_SMMU_CB_ASID(smmu, cfg);
 755
 756                 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
 757                         reg = pgtbl_cfg->arm_v7s_cfg.ttbr[0];
 758                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0);
 759                         reg = pgtbl_cfg->arm_v7s_cfg.ttbr[1];
 760                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1);
 761                         writel_relaxed(asid, cb_base + ARM_SMMU_CB_CONTEXTIDR);
 762                 } else {
 763                         reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
 764                         reg64 |= (u64)asid << TTBRn_ASID_SHIFT;
 765                         writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0);
 766                         reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
 767                         reg64 |= (u64)asid << TTBRn_ASID_SHIFT;
 768                         writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR1);
 769                 }
 770         } else {
 771                 reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
 772                 writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0);
 773         }
 774
 775         /* TTBCR */
 776         if (stage1) {
 777                 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
 778                         reg = pgtbl_cfg->arm_v7s_cfg.tcr;
 779                         reg2 = 0;
 780                 } else {
 781                         reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
 782                         reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
 783                         reg2 |= TTBCR2_SEP_UPSTREAM;
 784                 }
 785                 if (smmu->version > ARM_SMMU_V1)
 786                         writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
 787         } else {
 788                 reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
 789         }
 790         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 791
 792         /* MAIRs (stage-1 only) */
 793         if (stage1) {
 794                 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
 795                         reg = pgtbl_cfg->arm_v7s_cfg.prrr;
 796                         reg2 = pgtbl_cfg->arm_v7s_cfg.nmrr;
 797                 } else {
 798                         reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
 799                         reg2 = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
 800                 }
 801                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 802                 writel_relaxed(reg2, cb_base + ARM_SMMU_CB_S1_MAIR1);
 803         }
 804
 805         /* SCTLR */
 806         reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | SCTLR_M;
 807         if (stage1)
 808                 reg |= SCTLR_S1_ASIDPNE;
 809 #ifdef __BIG_ENDIAN
 810         reg |= SCTLR_E;
 811 #endif
 812         writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
 813 }
 814
 815 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 816                                         struct arm_smmu_device *smmu)
 817 {
 818         int irq, start, ret = 0;
 819         unsigned long ias, oas;
 820         struct io_pgtable_ops *pgtbl_ops;
 821         struct io_pgtable_cfg pgtbl_cfg;
 822         enum io_pgtable_fmt fmt;
 823         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 824         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 825
 826         mutex_lock(&smmu_domain->init_mutex);
 827         if (smmu_domain->smmu)
 828                 goto out_unlock;
 829
 830         /*
 831          * Mapping the requested stage onto what we support is surprisingly
 832          * complicated, mainly because the spec allows S1+S2 SMMUs without
 833          * support for nested translation. That means we end up with the
 834          * following table:
 835          *
 836          * Requested        Supported        Actual
 837          *     S1               N              S1
 838          *     S1             S1+S2            S1
 839          *     S1               S2             S2
 840          *     S1               S1             S1
 841          *     N                N              N
 842          *     N              S1+S2            S2
 843          *     N                S2             S2
 844          *     N                S1             S1
 845          *
 846          * Note that you can't actually request stage-2 mappings.
 847          */
 848         if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
 849                 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
 850         if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
 851                 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
 852
 853         /*
 854          * Choosing a suitable context format is even more fiddly. Until we
 855          * grow some way for the caller to express a preference, and/or move
 856          * the decision into the io-pgtable code where it arguably belongs,
 857          * just aim for the closest thing to the rest of the system, and hope
 858          * that the hardware isn't esoteric enough that we can't assume AArch64
 859          * support to be a superset of AArch32 support...
 860          */
 861         if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L)
 862                 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L;
 863         if (IS_ENABLED(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) &&
 864             !IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_ARM_LPAE) &&
 865             (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) &&
 866             (smmu_domain->stage == ARM_SMMU_DOMAIN_S1))
 867                 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_S;
 868         if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) &&
 869             (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K |
 870                                ARM_SMMU_FEAT_FMT_AARCH64_16K |
 871                                ARM_SMMU_FEAT_FMT_AARCH64_4K)))
 872                 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64;
 873
 874         if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) {
 875                 ret = -EINVAL;
 876                 goto out_unlock;
 877         }
 878
 879         switch (smmu_domain->stage) {
 880         case ARM_SMMU_DOMAIN_S1:
 881                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 882                 start = smmu->num_s2_context_banks;
 883                 ias = smmu->va_size;
 884                 oas = smmu->ipa_size;
 885                 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
 886                         fmt = ARM_64_LPAE_S1;
 887                 } else if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_L) {
 888                         fmt = ARM_32_LPAE_S1;
 889                         ias = min(ias, 32UL);
 890                         oas = min(oas, 40UL);
 891                 } else {
 892                         fmt = ARM_V7S;
 893                         ias = min(ias, 32UL);
 894                         oas = min(oas, 32UL);
 895                 }
 896                 break;
 897         case ARM_SMMU_DOMAIN_NESTED:
 898                 /*
 899                  * We will likely want to change this if/when KVM gets
 900                  * involved.
 901                  */
 902         case ARM_SMMU_DOMAIN_S2:
 903                 cfg->cbar = CBAR_TYPE_S2_TRANS;
 904                 start = 0;
 905                 ias = smmu->ipa_size;
 906                 oas = smmu->pa_size;
 907                 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
 908                         fmt = ARM_64_LPAE_S2;
 909                 } else {
 910                         fmt = ARM_32_LPAE_S2;
 911                         ias = min(ias, 40UL);
 912                         oas = min(oas, 40UL);
 913                 }
 914                 break;
 915         default:
 916                 ret = -EINVAL;
 917                 goto out_unlock;
 918         }
 919
 920         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 921                                       smmu->num_context_banks);
 922         if (ret < 0)
 923                 goto out_unlock;
 924
 925         cfg->cbndx = ret;
 926         if (smmu->version < ARM_SMMU_V2) {
 927                 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 928                 cfg->irptndx %= smmu->num_context_irqs;
 929         } else {
 930                 cfg->irptndx = cfg->cbndx;
 931         }
 932
 933         pgtbl_cfg = (struct io_pgtable_cfg) {
 934                 .pgsize_bitmap  = smmu->pgsize_bitmap,
 935                 .ias            = ias,
 936                 .oas            = oas,
 937                 .tlb            = &arm_smmu_gather_ops,
 938                 .iommu_dev      = smmu->dev,
 939         };
 940
 941         smmu_domain->smmu = smmu;
 942         pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
 943         if (!pgtbl_ops) {
 944                 ret = -ENOMEM;
 945                 goto out_clear_smmu;
 946         }
 947
 948         /* Update the domain's page sizes to reflect the page table format */
 949         domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
 950         domain->geometry.aperture_end = (1UL << ias) - 1;
 951         domain->geometry.force_aperture = true;
 952
 953         /* Initialise the context bank with our page table cfg */
 954         arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);
 955
 956         /*
 957          * Request context fault interrupt. Do this last to avoid the
 958          * handler seeing a half-initialised domain state.
 959          */
 960         irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
 961         ret = devm_request_irq(smmu->dev, irq, arm_smmu_context_fault,
 962                                IRQF_SHARED, "arm-smmu-context-fault", domain);
 963         if (ret < 0) {
 964                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 965                         cfg->irptndx, irq);
 966                 cfg->irptndx = INVALID_IRPTNDX;
 967         }
 968
 969         mutex_unlock(&smmu_domain->init_mutex);
 970
 971         /* Publish page table ops for map/unmap */
 972         smmu_domain->pgtbl_ops = pgtbl_ops;
 973         return 0;
 974
 975 out_clear_smmu:
 976         smmu_domain->smmu = NULL;
 977 out_unlock:
 978         mutex_unlock(&smmu_domain->init_mutex);
 979         return ret;
 980 }
 981
 982 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 983 {
 984         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 985         struct arm_smmu_device *smmu = smmu_domain->smmu;
 986         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 987         void __iomem *cb_base;
 988         int irq;
 989
 990         if (!smmu)
 991                 return;
 992
 993         /*
 994          * Disable the context bank and free the page tables before freeing
 995          * it.
 996          */
 997         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
 998         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
 999
1000         if (cfg->irptndx != INVALID_IRPTNDX) {
1001                 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
1002                 devm_free_irq(smmu->dev, irq, domain);
1003         }
1004
1005         free_io_pgtable_ops(smmu_domain->pgtbl_ops);
1006         __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
1007 }
1008
1009 static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
1010 {
1011         struct arm_smmu_domain *smmu_domain;
1012
1013         if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
1014                 return NULL;
1015         /*
1016          * Allocate the domain and initialise some of its data structures.
1017          * We can't really do anything meaningful until we've added a
1018          * master.
1019          */
1020         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
1021         if (!smmu_domain)
1022                 return NULL;
1023
1024         if (type == IOMMU_DOMAIN_DMA && (using_legacy_binding ||
1025             iommu_get_dma_cookie(&smmu_domain->domain))) {
1026                 kfree(smmu_domain);
1027                 return NULL;
1028         }
1029
1030         mutex_init(&smmu_domain->init_mutex);
1031         spin_lock_init(&smmu_domain->pgtbl_lock);
1032
1033         return &smmu_domain->domain;
1034 }
1035
1036 static void arm_smmu_domain_free(struct iommu_domain *domain)
1037 {
1038         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1039
1040         /*
1041          * Free the domain resources. We assume that all devices have
1042          * already been detached.
1043          */
1044         iommu_put_dma_cookie(domain);
1045         arm_smmu_destroy_domain_context(domain);
1046         kfree(smmu_domain);
1047 }
1048
1049 static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx)
1050 {
1051         struct arm_smmu_smr *smr = smmu->smrs + idx;
1052         u32 reg = smr->id << SMR_ID_SHIFT | smr->mask << SMR_MASK_SHIFT;
1053
1054         if (smr->valid)
1055                 reg |= SMR_VALID;
1056         writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx));
1057 }
1058
1059 static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
1060 {
1061         struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
1062         u32 reg = (s2cr->type & S2CR_TYPE_MASK) << S2CR_TYPE_SHIFT |
1063                   (s2cr->cbndx & S2CR_CBNDX_MASK) << S2CR_CBNDX_SHIFT |
1064                   (s2cr->privcfg & S2CR_PRIVCFG_MASK) << S2CR_PRIVCFG_SHIFT;
1065
1066         writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_S2CR(idx));
1067 }
1068
1069 static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx)
1070 {
1071         arm_smmu_write_s2cr(smmu, idx);
1072         if (smmu->smrs)
1073                 arm_smmu_write_smr(smmu, idx);
1074 }
1075
1076 static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
1077 {
1078         struct arm_smmu_smr *smrs = smmu->smrs;
1079         int i, free_idx = -ENOSPC;
1080
1081         /* Stream indexing is blissfully easy */
1082         if (!smrs)
1083                 return id;
1084
1085         /* Validating SMRs is... less so */
1086         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1087                 if (!smrs[i].valid) {
1088                         /*
1089                          * Note the first free entry we come across, which
1090                          * we'll claim in the end if nothing else matches.
1091                          */
1092                         if (free_idx < 0)
1093                                 free_idx = i;
1094                         continue;
1095                 }
1096                 /*
1097                  * If the new entry is _entirely_ matched by an existing entry,
1098                  * then reuse that, with the guarantee that there also cannot
1099                  * be any subsequent conflicting entries. In normal use we'd
1100                  * expect simply identical entries for this case, but there's
1101                  * no harm in accommodating the generalisation.
1102                  */
1103                 if ((mask & smrs[i].mask) == mask &&
1104                     !((id ^ smrs[i].id) & ~smrs[i].mask))
1105                         return i;
1106                 /*
1107                  * If the new entry has any other overlap with an existing one,
1108                  * though, then there always exists at least one stream ID
1109                  * which would cause a conflict, and we can't allow that risk.
1110                  */
1111                 if (!((id ^ smrs[i].id) & ~(smrs[i].mask | mask)))
1112                         return -EINVAL;
1113         }
1114
1115         return free_idx;
1116 }
1117
1118 static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx)
1119 {
1120         if (--smmu->s2crs[idx].count)
1121                 return false;
1122
1123         smmu->s2crs[idx] = s2cr_init_val;
1124         if (smmu->smrs)
1125                 smmu->smrs[idx].valid = false;
1126
1127         return true;
1128 }
1129
1130 static int arm_smmu_master_alloc_smes(struct device *dev)
1131 {
1132         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1133         struct arm_smmu_master_cfg *cfg = fwspec->iommu_priv;
1134         struct arm_smmu_device *smmu = cfg->smmu;
1135         struct arm_smmu_smr *smrs = smmu->smrs;
1136         struct iommu_group *group;
1137         int i, idx, ret;
1138
1139         mutex_lock(&smmu->stream_map_mutex);
1140         /* Figure out a viable stream map entry allocation */
1141         for_each_cfg_sme(fwspec, i, idx) {
1142                 u16 sid = fwspec->ids[i];
1143                 u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;
1144
1145                 if (idx != INVALID_SMENDX) {
1146                         ret = -EEXIST;
1147                         goto out_err;
1148                 }
1149
1150                 ret = arm_smmu_find_sme(smmu, sid, mask);
1151                 if (ret < 0)
1152                         goto out_err;
1153
1154                 idx = ret;
1155                 if (smrs && smmu->s2crs[idx].count == 0) {
1156                         smrs[idx].id = sid;
1157                         smrs[idx].mask = mask;
1158                         smrs[idx].valid = true;
1159                 }
1160                 smmu->s2crs[idx].count++;
1161                 cfg->smendx[i] = (s16)idx;
1162         }
1163
1164         group = iommu_group_get_for_dev(dev);
1165         if (!group)
1166                 group = ERR_PTR(-ENOMEM);
1167         if (IS_ERR(group)) {
1168                 ret = PTR_ERR(group);
1169                 goto out_err;
1170         }
1171         iommu_group_put(group);
1172
1173         /* It worked! Now, poke the actual hardware */
1174         for_each_cfg_sme(fwspec, i, idx) {
1175                 arm_smmu_write_sme(smmu, idx);
1176                 smmu->s2crs[idx].group = group;
1177         }
1178
1179         mutex_unlock(&smmu->stream_map_mutex);
1180         return 0;
1181
1182 out_err:
1183         while (i--) {
1184                 arm_smmu_free_sme(smmu, cfg->smendx[i]);
1185                 cfg->smendx[i] = INVALID_SMENDX;
1186         }
1187         mutex_unlock(&smmu->stream_map_mutex);
1188         return ret;
1189 }
1190
1191 static void arm_smmu_master_free_smes(struct iommu_fwspec *fwspec)
1192 {
1193         struct arm_smmu_device *smmu = fwspec_smmu(fwspec);
1194         struct arm_smmu_master_cfg *cfg = fwspec->iommu_priv;
1195         int i, idx;
1196
1197         mutex_lock(&smmu->stream_map_mutex);
1198         for_each_cfg_sme(fwspec, i, idx) {
1199                 if (arm_smmu_free_sme(smmu, idx))
1200                         arm_smmu_write_sme(smmu, idx);
1201                 cfg->smendx[i] = INVALID_SMENDX;
1202         }
1203         mutex_unlock(&smmu->stream_map_mutex);
1204 }
1205
1206 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1207                                       struct iommu_fwspec *fwspec)
1208 {
1209         struct arm_smmu_device *smmu = smmu_domain->smmu;
1210         struct arm_smmu_s2cr *s2cr = smmu->s2crs;
1211         enum arm_smmu_s2cr_type type = S2CR_TYPE_TRANS;
1212         u8 cbndx = smmu_domain->cfg.cbndx;
1213         int i, idx;
1214
1215         for_each_cfg_sme(fwspec, i, idx) {
1216                 if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)
1217                         continue;
1218
1219                 s2cr[idx].type = type;
1220                 s2cr[idx].privcfg = S2CR_PRIVCFG_UNPRIV;
1221                 s2cr[idx].cbndx = cbndx;
1222                 arm_smmu_write_s2cr(smmu, idx);
1223         }
1224         return 0;
1225 }
1226
1227 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1228 {
1229         int ret;
1230         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1231         struct arm_smmu_device *smmu;
1232         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1233
1234         if (!fwspec || fwspec->ops != &arm_smmu_ops) {
1235                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1236                 return -ENXIO;
1237         }
1238
1239         /*
1240          * FIXME: The arch/arm DMA API code tries to attach devices to its own
1241          * domains between of_xlate() and add_device() - we have no way to cope
1242          * with that, so until ARM gets converted to rely on groups and default
1243          * domains, just say no (but more politely than by dereferencing NULL).
1244          * This should be at least a WARN_ON once that's sorted.
1245          */
1246         if (!fwspec->iommu_priv)
1247                 return -ENODEV;
1248
1249         smmu = fwspec_smmu(fwspec);
1250         /* Ensure that the domain is finalised */
1251         ret = arm_smmu_init_domain_context(domain, smmu);
1252         if (ret < 0)
1253                 return ret;
1254
1255         /*
1256          * Sanity check the domain. We don't support domains across
1257          * different SMMUs.
1258          */
1259         if (smmu_domain->smmu != smmu) {
1260                 dev_err(dev,
1261                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1262                         dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1263                 return -EINVAL;
1264         }
1265
1266         /* Looks ok, so add the device to the domain */
1267         return arm_smmu_domain_add_master(smmu_domain, fwspec);
1268 }
1269
1270 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1271                         phys_addr_t paddr, size_t size, int prot)
1272 {
1273         int ret;
1274         unsigned long flags;
1275         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1276         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1277
1278         if (!ops)
1279                 return -ENODEV;
1280
1281         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1282         ret = ops->map(ops, iova, paddr, size, prot);
1283         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1284         return ret;
1285 }
1286
1287 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1288                              size_t size)
1289 {
1290         size_t ret;
1291         unsigned long flags;
1292         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1293         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1294
1295         if (!ops)
1296                 return 0;
1297
1298         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1299         ret = ops->unmap(ops, iova, size);
1300         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1301         return ret;
1302 }
1303
1304 static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
1305                                               dma_addr_t iova)
1306 {
1307         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1308         struct arm_smmu_device *smmu = smmu_domain->smmu;
1309         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1310         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1311         struct device *dev = smmu->dev;
1312         void __iomem *cb_base;
1313         u32 tmp;
1314         u64 phys;
1315         unsigned long va;
1316
1317         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
1318
1319         /* ATS1 registers can only be written atomically */
1320         va = iova & ~0xfffUL;
1321         if (smmu->version == ARM_SMMU_V2)
1322                 smmu_write_atomic_lq(va, cb_base + ARM_SMMU_CB_ATS1PR);
1323         else /* Register is only 32-bit in v1 */
1324                 writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
1325
1326         if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
1327                                       !(tmp & ATSR_ACTIVE), 5, 50)) {
1328                 dev_err(dev,
1329                         "iova to phys timed out on %pad. Falling back to software table walk.\n",
1330                         &iova);
1331                 return ops->iova_to_phys(ops, iova);
1332         }
1333
1334         phys = readq_relaxed(cb_base + ARM_SMMU_CB_PAR);
1335         if (phys & CB_PAR_F) {
1336                 dev_err(dev, "translation fault!\n");
1337                 dev_err(dev, "PAR = 0x%llx\n", phys);
1338                 return 0;
1339         }
1340
1341         return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
1342 }
1343
1344 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1345                                         dma_addr_t iova)
1346 {
1347         phys_addr_t ret;
1348         unsigned long flags;
1349         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1350         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1351
1352         if (!ops)
1353                 return 0;
1354
1355         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1356         if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
1357                         smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1358                 ret = arm_smmu_iova_to_phys_hard(domain, iova);
1359         } else {
1360                 ret = ops->iova_to_phys(ops, iova);
1361         }
1362
1363         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1364
1365         return ret;
1366 }
1367
1368 static bool arm_smmu_capable(enum iommu_cap cap)
1369 {
1370         switch (cap) {
1371         case IOMMU_CAP_CACHE_COHERENCY:
1372                 /*
1373                  * Return true here as the SMMU can always send out coherent
1374                  * requests.
1375                  */
1376                 return true;
1377         case IOMMU_CAP_NOEXEC:
1378                 return true;
1379         default:
1380                 return false;
1381         }
1382 }
1383
1384 static int arm_smmu_match_node(struct device *dev, void *data)
1385 {
1386         return dev->fwnode == data;
1387 }
1388
1389 static
1390 struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
1391 {
1392         struct device *dev = driver_find_device(&arm_smmu_driver.driver, NULL,
1393                                                 fwnode, arm_smmu_match_node);
1394         put_device(dev);
1395         return dev ? dev_get_drvdata(dev) : NULL;
1396 }
1397
1398 static int arm_smmu_add_device(struct device *dev)
1399 {
1400         struct arm_smmu_device *smmu;
1401         struct arm_smmu_master_cfg *cfg;
1402         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1403         int i, ret;
1404
1405         if (using_legacy_binding) {
1406                 ret = arm_smmu_register_legacy_master(dev, &smmu);
1407                 fwspec = dev->iommu_fwspec;
1408                 if (ret)
1409                         goto out_free;
1410         } else if (fwspec && fwspec->ops == &arm_smmu_ops) {
1411                 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode);
1412         } else {
1413                 return -ENODEV;
1414         }
1415
1416         ret = -EINVAL;
1417         for (i = 0; i < fwspec->num_ids; i++) {
1418                 u16 sid = fwspec->ids[i];
1419                 u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;
1420
1421                 if (sid & ~smmu->streamid_mask) {
1422                         dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n",
1423                                 sid, smmu->streamid_mask);
1424                         goto out_free;
1425                 }
1426                 if (mask & ~smmu->smr_mask_mask) {
1427                         dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n",
1428                                 sid, smmu->smr_mask_mask);
1429                         goto out_free;
1430                 }
1431         }
1432
1433         ret = -ENOMEM;
1434         cfg = kzalloc(offsetof(struct arm_smmu_master_cfg, smendx[i]),
1435                       GFP_KERNEL);
1436         if (!cfg)
1437                 goto out_free;
1438
1439         cfg->smmu = smmu;
1440         fwspec->iommu_priv = cfg;
1441         while (i--)
1442                 cfg->smendx[i] = INVALID_SMENDX;
1443
1444         ret = arm_smmu_master_alloc_smes(dev);
1445         if (ret)
1446                 goto out_free;
1447
1448         return 0;
1449
1450 out_free:
1451         if (fwspec)
1452                 kfree(fwspec->iommu_priv);
1453         iommu_fwspec_free(dev);
1454         return ret;
1455 }
1456
1457 static void arm_smmu_remove_device(struct device *dev)
1458 {
1459         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1460
1461         if (!fwspec || fwspec->ops != &arm_smmu_ops)
1462                 return;
1463
1464         arm_smmu_master_free_smes(fwspec);
1465         iommu_group_remove_device(dev);
1466         kfree(fwspec->iommu_priv);
1467         iommu_fwspec_free(dev);
1468 }
1469
1470 static struct iommu_group *arm_smmu_device_group(struct device *dev)
1471 {
1472         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1473         struct arm_smmu_device *smmu = fwspec_smmu(fwspec);
1474         struct iommu_group *group = NULL;
1475         int i, idx;
1476
1477         for_each_cfg_sme(fwspec, i, idx) {
1478                 if (group && smmu->s2crs[idx].group &&
1479                     group != smmu->s2crs[idx].group)
1480                         return ERR_PTR(-EINVAL);
1481
1482                 group = smmu->s2crs[idx].group;
1483         }
1484
1485         if (group)
1486                 return iommu_group_ref_get(group);
1487
1488         if (dev_is_pci(dev))
1489                 group = pci_device_group(dev);
1490         else
1491                 group = generic_device_group(dev);
1492
1493         return group;
1494 }
1495
1496 static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1497                                     enum iommu_attr attr, void *data)
1498 {
1499         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1500
1501         switch (attr) {
1502         case DOMAIN_ATTR_NESTING:
1503                 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1504                 return 0;
1505         default:
1506                 return -ENODEV;
1507         }
1508 }
1509
1510 static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1511                                     enum iommu_attr attr, void *data)
1512 {
1513         int ret = 0;
1514         struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1515
1516         mutex_lock(&smmu_domain->init_mutex);
1517
1518         switch (attr) {
1519         case DOMAIN_ATTR_NESTING:
1520                 if (smmu_domain->smmu) {
1521                         ret = -EPERM;
1522                         goto out_unlock;
1523                 }
1524
1525                 if (*(int *)data)
1526                         smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1527                 else
1528                         smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1529
1530                 break;
1531         default:
1532                 ret = -ENODEV;
1533         }
1534
1535 out_unlock:
1536         mutex_unlock(&smmu_domain->init_mutex);
1537         return ret;
1538 }
1539
1540 static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
1541 {
1542         u32 fwid = 0;
1543
1544         if (args->args_count > 0)
1545                 fwid |= (u16)args->args[0];
1546
1547         if (args->args_count > 1)
1548                 fwid |= (u16)args->args[1] << SMR_MASK_SHIFT;
1549
1550         return iommu_fwspec_add_ids(dev, &fwid, 1);
1551 }
1552
1553 static void arm_smmu_get_resv_regions(struct device *dev,
1554                                       struct list_head *head)
1555 {
1556         struct iommu_resv_region *region;
1557         int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
1558
1559         region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH,
1560                                          prot, IOMMU_RESV_MSI);
1561         if (!region)
1562                 return;
1563
1564         list_add_tail(&region->list, head);
1565 }
1566
1567 static void arm_smmu_put_resv_regions(struct device *dev,
1568                                       struct list_head *head)
1569 {
1570         struct iommu_resv_region *entry, *next;
1571
1572         list_for_each_entry_safe(entry, next, head, list)
1573                 kfree(entry);
1574 }
1575
1576 static struct iommu_ops arm_smmu_ops = {
1577         .capable                = arm_smmu_capable,
1578         .domain_alloc           = arm_smmu_domain_alloc,
1579         .domain_free            = arm_smmu_domain_free,
1580         .attach_dev             = arm_smmu_attach_dev,
1581         .map                    = arm_smmu_map,
1582         .unmap                  = arm_smmu_unmap,
1583         .map_sg                 = default_iommu_map_sg,
1584         .iova_to_phys           = arm_smmu_iova_to_phys,
1585         .add_device             = arm_smmu_add_device,
1586         .remove_device          = arm_smmu_remove_device,
1587         .device_group           = arm_smmu_device_group,
1588         .domain_get_attr        = arm_smmu_domain_get_attr,
1589         .domain_set_attr        = arm_smmu_domain_set_attr,
1590         .of_xlate               = arm_smmu_of_xlate,
1591         .get_resv_regions       = arm_smmu_get_resv_regions,
1592         .put_resv_regions       = arm_smmu_put_resv_regions,
1593         .pgsize_bitmap          = -1UL, /* Restricted during device attach */
1594 };
1595
1596 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1597 {
1598         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1599         void __iomem *cb_base;
1600         int i;
1601         u32 reg, major;
1602
1603         /* clear global FSR */
1604         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1605         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1606
1607         /*
1608          * Reset stream mapping groups: Initial values mark all SMRn as
1609          * invalid and all S2CRn as bypass unless overridden.
1610          */
1611         for (i = 0; i < smmu->num_mapping_groups; ++i)
1612                 arm_smmu_write_sme(smmu, i);
1613
1614         if (smmu->model == ARM_MMU500) {
1615                 /*
1616                  * Before clearing ARM_MMU500_ACTLR_CPRE, need to
1617                  * clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
1618                  * bit is only present in MMU-500r2 onwards.
1619                  */
1620                 reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
1621                 major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
1622                 reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
1623                 if (major >= 2)
1624                         reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
1625                 /*
1626                  * Allow unmatched Stream IDs to allocate bypass
1627                  * TLB entries for reduced latency.
1628                  */
1629                 reg |= ARM_MMU500_ACR_SMTNMB_TLBEN;
1630                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
1631         }
1632
1633         /* Make sure all context banks are disabled and clear CB_FSR  */
1634         for (i = 0; i < smmu->num_context_banks; ++i) {
1635                 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1636                 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1637                 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1638                 /*
1639                  * Disable MMU-500's not-particularly-beneficial next-page
1640                  * prefetcher for the sake of errata #841119 and #826419.
1641                  */
1642                 if (smmu->model == ARM_MMU500) {
1643                         reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR);
1644                         reg &= ~ARM_MMU500_ACTLR_CPRE;
1645                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR);
1646                 }
1647         }
1648
1649         /* Invalidate the TLB, just in case */
1650         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1651         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1652
1653         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1654
1655         /* Enable fault reporting */
1656         reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1657
1658         /* Disable TLB broadcasting. */
1659         reg |= (sCR0_VMIDPNE | sCR0_PTM);
1660
1661         /* Enable client access, handling unmatched streams as appropriate */
1662         reg &= ~sCR0_CLIENTPD;
1663         if (disable_bypass)
1664                 reg |= sCR0_USFCFG;
1665         else
1666                 reg &= ~sCR0_USFCFG;
1667
1668         /* Disable forced broadcasting */
1669         reg &= ~sCR0_FB;
1670
1671         /* Don't upgrade barriers */
1672         reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1673
1674         if (smmu->features & ARM_SMMU_FEAT_VMID16)
1675                 reg |= sCR0_VMID16EN;
1676
1677         /* Push the button */
1678         __arm_smmu_tlb_sync(smmu);
1679         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1680 }
1681
1682 static int arm_smmu_id_size_to_bits(int size)
1683 {
1684         switch (size) {
1685         case 0:
1686                 return 32;
1687         case 1:
1688                 return 36;
1689         case 2:
1690                 return 40;
1691         case 3:
1692                 return 42;
1693         case 4:
1694                 return 44;
1695         case 5:
1696         default:
1697                 return 48;
1698         }
1699 }
1700
1701 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1702 {
1703         unsigned long size;
1704         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1705         u32 id;
1706         bool cttw_reg, cttw_fw = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK;
1707         int i;
1708
1709         dev_notice(smmu->dev, "probing hardware configuration...\n");
1710         dev_notice(smmu->dev, "SMMUv%d with:\n",
1711                         smmu->version == ARM_SMMU_V2 ? 2 : 1);
1712
1713         /* ID0 */
1714         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1715
1716         /* Restrict available stages based on module parameter */
1717         if (force_stage == 1)
1718                 id &= ~(ID0_S2TS | ID0_NTS);
1719         else if (force_stage == 2)
1720                 id &= ~(ID0_S1TS | ID0_NTS);
1721
1722         if (id & ID0_S1TS) {
1723                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1724                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1725         }
1726
1727         if (id & ID0_S2TS) {
1728                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1729                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1730         }
1731
1732         if (id & ID0_NTS) {
1733                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1734                 dev_notice(smmu->dev, "\tnested translation\n");
1735         }
1736
1737         if (!(smmu->features &
1738                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1739                 dev_err(smmu->dev, "\tno translation support!\n");
1740                 return -ENODEV;
1741         }
1742
1743         if ((id & ID0_S1TS) &&
1744                 ((smmu->version < ARM_SMMU_V2) || !(id & ID0_ATOSNS))) {
1745                 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
1746                 dev_notice(smmu->dev, "\taddress translation ops\n");
1747         }
1748
1749         /*
1750          * In order for DMA API calls to work properly, we must defer to what
1751          * the FW says about coherency, regardless of what the hardware claims.
1752          * Fortunately, this also opens up a workaround for systems where the
1753          * ID register value has ended up configured incorrectly.
1754          */
1755         cttw_reg = !!(id & ID0_CTTW);
1756         if (cttw_fw || cttw_reg)
1757                 dev_notice(smmu->dev, "\t%scoherent table walk\n",
1758                            cttw_fw ? "" : "non-");
1759         if (cttw_fw != cttw_reg)
1760                 dev_notice(smmu->dev,
1761                            "\t(IDR0.CTTW overridden by FW configuration)\n");
1762
1763         /* Max. number of entries we have for stream matching/indexing */
1764         size = 1 << ((id >> ID0_NUMSIDB_SHIFT) & ID0_NUMSIDB_MASK);
1765         smmu->streamid_mask = size - 1;
1766         if (id & ID0_SMS) {
1767                 u32 smr;
1768
1769                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1770                 size = (id >> ID0_NUMSMRG_SHIFT) & ID0_NUMSMRG_MASK;
1771                 if (size == 0) {
1772                         dev_err(smmu->dev,
1773                                 "stream-matching supported, but no SMRs present!\n");
1774                         return -ENODEV;
1775                 }
1776
1777                 /*
1778                  * SMR.ID bits may not be preserved if the corresponding MASK
1779                  * bits are set, so check each one separately. We can reject
1780                  * masters later if they try to claim IDs outside these masks.
1781                  */
1782                 smr = smmu->streamid_mask << SMR_ID_SHIFT;
1783                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1784                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1785                 smmu->streamid_mask = smr >> SMR_ID_SHIFT;
1786
1787                 smr = smmu->streamid_mask << SMR_MASK_SHIFT;
1788                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1789                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1790                 smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT;
1791
1792                 /* Zero-initialised to mark as invalid */
1793                 smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs),
1794                                           GFP_KERNEL);
1795                 if (!smmu->smrs)
1796                         return -ENOMEM;
1797
1798                 dev_notice(smmu->dev,
1799                            "\tstream matching with %lu register groups, mask 0x%x",
1800                            size, smmu->smr_mask_mask);
1801         }
1802         /* s2cr->type == 0 means translation, so initialise explicitly */
1803         smmu->s2crs = devm_kmalloc_array(smmu->dev, size, sizeof(*smmu->s2crs),
1804                                          GFP_KERNEL);
1805         if (!smmu->s2crs)
1806                 return -ENOMEM;
1807         for (i = 0; i < size; i++)
1808                 smmu->s2crs[i] = s2cr_init_val;
1809
1810         smmu->num_mapping_groups = size;
1811         mutex_init(&smmu->stream_map_mutex);
1812
1813         if (smmu->version < ARM_SMMU_V2 || !(id & ID0_PTFS_NO_AARCH32)) {
1814                 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L;
1815                 if (!(id & ID0_PTFS_NO_AARCH32S))
1816                         smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S;
1817         }
1818
1819         /* ID1 */
1820         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1821         smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1822
1823         /* Check for size mismatch of SMMU address space from mapped region */
1824         size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1825         size *= 2 << smmu->pgshift;
1826         if (smmu->size != size)
1827                 dev_warn(smmu->dev,
1828                         "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1829                         size, smmu->size);
1830
1831         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
1832         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1833         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1834                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1835                 return -ENODEV;
1836         }
1837         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1838                    smmu->num_context_banks, smmu->num_s2_context_banks);
1839         /*
1840          * Cavium CN88xx erratum #27704.
1841          * Ensure ASID and VMID allocation is unique across all SMMUs in
1842          * the system.
1843          */
1844         if (smmu->model == CAVIUM_SMMUV2) {
1845                 smmu->cavium_id_base =
1846                         atomic_add_return(smmu->num_context_banks,
1847                                           &cavium_smmu_context_count);
1848                 smmu->cavium_id_base -= smmu->num_context_banks;
1849         }
1850
1851         /* ID2 */
1852         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1853         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1854         smmu->ipa_size = size;
1855
1856         /* The output mask is also applied for bypass */
1857         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1858         smmu->pa_size = size;
1859
1860         if (id & ID2_VMID16)
1861                 smmu->features |= ARM_SMMU_FEAT_VMID16;
1862
1863         /*
1864          * What the page table walker can address actually depends on which
1865          * descriptor format is in use, but since a) we don't know that yet,
1866          * and b) it can vary per context bank, this will have to do...
1867          */
1868         if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size)))
1869                 dev_warn(smmu->dev,
1870                          "failed to set DMA mask for table walker\n");
1871
1872         if (smmu->version < ARM_SMMU_V2) {
1873                 smmu->va_size = smmu->ipa_size;
1874                 if (smmu->version == ARM_SMMU_V1_64K)
1875                         smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K;
1876         } else {
1877                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1878                 smmu->va_size = arm_smmu_id_size_to_bits(size);
1879                 if (id & ID2_PTFS_4K)
1880                         smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K;
1881                 if (id & ID2_PTFS_16K)
1882                         smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K;
1883                 if (id & ID2_PTFS_64K)
1884                         smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K;
1885         }
1886
1887         /* Now we've corralled the various formats, what'll it do? */
1888         if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S)
1889                 smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
1890         if (smmu->features &
1891             (ARM_SMMU_FEAT_FMT_AARCH32_L | ARM_SMMU_FEAT_FMT_AARCH64_4K))
1892                 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
1893         if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K)
1894                 smmu->pgsize_bitmap |= SZ_16K | SZ_32M;
1895         if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K)
1896                 smmu->pgsize_bitmap |= SZ_64K | SZ_512M;
1897
1898         if (arm_smmu_ops.pgsize_bitmap == -1UL)
1899                 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
1900         else
1901                 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
1902         dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n",
1903                    smmu->pgsize_bitmap);
1904
1905
1906         if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
1907                 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1908                            smmu->va_size, smmu->ipa_size);
1909
1910         if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
1911                 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1912                            smmu->ipa_size, smmu->pa_size);
1913
1914         return 0;
1915 }
1916
1917 struct arm_smmu_match_data {
1918         enum arm_smmu_arch_version version;
1919         enum arm_smmu_implementation model;
1920 };
1921
1922 #define ARM_SMMU_MATCH_DATA(name, ver, imp)     \
1923 static struct arm_smmu_match_data name = { .version = ver, .model = imp }
1924
1925 ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
1926 ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
1927 ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
1928 ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
1929 ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
1930
1931 static const struct of_device_id arm_smmu_of_match[] = {
1932         { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
1933         { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
1934         { .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
1935         { .compatible = "arm,mmu-401", .data = &arm_mmu401 },
1936         { .compatible = "arm,mmu-500", .data = &arm_mmu500 },
1937         { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
1938         { },
1939 };
1940 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1941
1942 #ifdef CONFIG_ACPI
1943 static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu)
1944 {
1945         int ret = 0;
1946
1947         switch (model) {
1948         case ACPI_IORT_SMMU_V1:
1949         case ACPI_IORT_SMMU_CORELINK_MMU400:
1950                 smmu->version = ARM_SMMU_V1;
1951                 smmu->model = GENERIC_SMMU;
1952                 break;
1953         case ACPI_IORT_SMMU_V2:
1954                 smmu->version = ARM_SMMU_V2;
1955                 smmu->model = GENERIC_SMMU;
1956                 break;
1957         case ACPI_IORT_SMMU_CORELINK_MMU500:
1958                 smmu->version = ARM_SMMU_V2;
1959                 smmu->model = ARM_MMU500;
1960                 break;
1961         default:
1962                 ret = -ENODEV;
1963         }
1964
1965         return ret;
1966 }
1967
1968 static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
1969                                       struct arm_smmu_device *smmu)
1970 {
1971         struct device *dev = smmu->dev;
1972         struct acpi_iort_node *node =
1973                 *(struct acpi_iort_node **)dev_get_platdata(dev);
1974         struct acpi_iort_smmu *iort_smmu;
1975         int ret;
1976
1977         /* Retrieve SMMU1/2 specific data */
1978         iort_smmu = (struct acpi_iort_smmu *)node->node_data;
1979
1980         ret = acpi_smmu_get_data(iort_smmu->model, smmu);
1981         if (ret < 0)
1982                 return ret;
1983
1984         /* Ignore the configuration access interrupt */
1985         smmu->num_global_irqs = 1;
1986
1987         if (iort_smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK)
1988                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1989
1990         return 0;
1991 }
1992 #else
1993 static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
1994                                              struct arm_smmu_device *smmu)
1995 {
1996         return -ENODEV;
1997 }
1998 #endif
1999
2000 static int arm_smmu_device_dt_probe(struct platform_device *pdev,
2001                                     struct arm_smmu_device *smmu)
2002 {
2003         const struct arm_smmu_match_data *data;
2004         struct device *dev = &pdev->dev;
2005         bool legacy_binding;
2006
2007         if (of_property_read_u32(dev->of_node, "#global-interrupts",
2008                                  &smmu->num_global_irqs)) {
2009                 dev_err(dev, "missing #global-interrupts property\n");
2010                 return -ENODEV;
2011         }
2012
2013         data = of_device_get_match_data(dev);
2014         smmu->version = data->version;
2015         smmu->model = data->model;
2016
2017         parse_driver_options(smmu);
2018
2019         legacy_binding = of_find_property(dev->of_node, "mmu-masters", NULL);
2020         if (legacy_binding && !using_generic_binding) {
2021                 if (!using_legacy_binding)
2022                         pr_notice("deprecated \"mmu-masters\" DT property in use; DMA API support unavailable\n");
2023                 using_legacy_binding = true;
2024         } else if (!legacy_binding && !using_legacy_binding) {
2025                 using_generic_binding = true;
2026         } else {
2027                 dev_err(dev, "not probing due to mismatched DT properties\n");
2028                 return -ENODEV;
2029         }
2030
2031         if (of_dma_is_coherent(dev->of_node))
2032                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
2033
2034         return 0;
2035 }
2036
2037 static int arm_smmu_device_probe(struct platform_device *pdev)
2038 {
2039         struct resource *res;
2040         struct arm_smmu_device *smmu;
2041         struct device *dev = &pdev->dev;
2042         int num_irqs, i, err;
2043
2044         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
2045         if (!smmu) {
2046                 dev_err(dev, "failed to allocate arm_smmu_device\n");
2047                 return -ENOMEM;
2048         }
2049         smmu->dev = dev;
2050
2051         if (dev->of_node)
2052                 err = arm_smmu_device_dt_probe(pdev, smmu);
2053         else
2054                 err = arm_smmu_device_acpi_probe(pdev, smmu);
2055
2056         if (err)
2057                 return err;
2058
2059         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2060         smmu->base = devm_ioremap_resource(dev, res);
2061         if (IS_ERR(smmu->base))
2062                 return PTR_ERR(smmu->base);
2063         smmu->size = resource_size(res);
2064
2065         num_irqs = 0;
2066         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
2067                 num_irqs++;
2068                 if (num_irqs > smmu->num_global_irqs)
2069                         smmu->num_context_irqs++;
2070         }
2071
2072         if (!smmu->num_context_irqs) {
2073                 dev_err(dev, "found %d interrupts but expected at least %d\n",
2074                         num_irqs, smmu->num_global_irqs + 1);
2075                 return -ENODEV;
2076         }
2077
2078         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
2079                                   GFP_KERNEL);
2080         if (!smmu->irqs) {
2081                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
2082                 return -ENOMEM;
2083         }
2084
2085         for (i = 0; i < num_irqs; ++i) {
2086                 int irq = platform_get_irq(pdev, i);
2087
2088                 if (irq < 0) {
2089                         dev_err(dev, "failed to get irq index %d\n", i);
2090                         return -ENODEV;
2091                 }
2092                 smmu->irqs[i] = irq;
2093         }
2094
2095         err = arm_smmu_device_cfg_probe(smmu);
2096         if (err)
2097                 return err;
2098
2099         if (smmu->version == ARM_SMMU_V2 &&
2100             smmu->num_context_banks != smmu->num_context_irqs) {
2101                 dev_err(dev,
2102                         "found only %d context interrupt(s) but %d required\n",
2103                         smmu->num_context_irqs, smmu->num_context_banks);
2104                 return -ENODEV;
2105         }
2106
2107         for (i = 0; i < smmu->num_global_irqs; ++i) {
2108                 err = devm_request_irq(smmu->dev, smmu->irqs[i],
2109                                        arm_smmu_global_fault,
2110                                        IRQF_SHARED,
2111                                        "arm-smmu global fault",
2112                                        smmu);
2113                 if (err) {
2114                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
2115                                 i, smmu->irqs[i]);
2116                         return err;
2117                 }
2118         }
2119
2120         iommu_register_instance(dev->fwnode, &arm_smmu_ops);
2121         platform_set_drvdata(pdev, smmu);
2122         arm_smmu_device_reset(smmu);
2123
2124         /* Oh, for a proper bus abstraction */
2125         if (!iommu_present(&platform_bus_type))
2126                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2127 #ifdef CONFIG_ARM_AMBA
2128         if (!iommu_present(&amba_bustype))
2129                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2130 #endif
2131 #ifdef CONFIG_PCI
2132         if (!iommu_present(&pci_bus_type)) {
2133                 pci_request_acs();
2134                 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2135         }
2136 #endif
2137         return 0;
2138 }
2139
2140 static int arm_smmu_device_remove(struct platform_device *pdev)
2141 {
2142         struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
2143
2144         if (!smmu)
2145                 return -ENODEV;
2146
2147         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
2148                 dev_err(&pdev->dev, "removing device with active domains!\n");
2149
2150         /* Turn the thing off */
2151         writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2152         return 0;
2153 }
2154
2155 static struct platform_driver arm_smmu_driver = {
2156         .driver = {
2157                 .name           = "arm-smmu",
2158                 .of_match_table = of_match_ptr(arm_smmu_of_match),
2159         },
2160         .probe  = arm_smmu_device_probe,
2161         .remove = arm_smmu_device_remove,
2162 };
2163
2164 static int __init arm_smmu_init(void)
2165 {
2166         static bool registered;
2167         int ret = 0;
2168
2169         if (!registered) {
2170                 ret = platform_driver_register(&arm_smmu_driver);
2171                 registered = !ret;
2172         }
2173         return ret;
2174 }
2175
2176 static void __exit arm_smmu_exit(void)
2177 {
2178         return platform_driver_unregister(&arm_smmu_driver);
2179 }
2180
2181 subsys_initcall(arm_smmu_init);
2182 module_exit(arm_smmu_exit);
2183
2184 static int __init arm_smmu_of_init(struct device_node *np)
2185 {
2186         int ret = arm_smmu_init();
2187
2188         if (ret)
2189                 return ret;
2190
2191         if (!of_platform_device_create(np, NULL, platform_bus_type.dev_root))
2192                 return -ENODEV;
2193
2194         return 0;
2195 }
2196 IOMMU_OF_DECLARE(arm_smmuv1, "arm,smmu-v1", arm_smmu_of_init);
2197 IOMMU_OF_DECLARE(arm_smmuv2, "arm,smmu-v2", arm_smmu_of_init);
2198 IOMMU_OF_DECLARE(arm_mmu400, "arm,mmu-400", arm_smmu_of_init);
2199 IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401", arm_smmu_of_init);
2200 IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500", arm_smmu_of_init);
2201 IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2", arm_smmu_of_init);
2202
2203 #ifdef CONFIG_ACPI
2204 static int __init arm_smmu_acpi_init(struct acpi_table_header *table)
2205 {
2206         if (iort_node_match(ACPI_IORT_NODE_SMMU))
2207                 return arm_smmu_init();
2208
2209         return 0;
2210 }
2211 IORT_ACPI_DECLARE(arm_smmu, ACPI_SIG_IORT, arm_smmu_acpi_init);
2212 #endif
2213
2214 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2215 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2216 MODULE_LICENSE("GPL v2");