2 * A fairly generic DMA-API to IOMMU-API glue layer.
4 * Copyright (C) 2014-2015 ARM Ltd.
6 * based in part on arch/arm/mm/dma-mapping.c:
7 * Copyright (C) 2000-2004 Russell King
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/device.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/gfp.h>
25 #include <linux/huge_mm.h>
26 #include <linux/iommu.h>
27 #include <linux/iova.h>
28 #include <linux/irq.h>
30 #include <linux/pci.h>
31 #include <linux/scatterlist.h>
32 #include <linux/vmalloc.h>
34 struct iommu_dma_msi_page {
35 struct list_head list;
40 enum iommu_dma_cookie_type {
41 IOMMU_DMA_IOVA_COOKIE,
45 struct iommu_dma_cookie {
46 enum iommu_dma_cookie_type type;
48 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */
49 struct iova_domain iovad;
50 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
53 struct list_head msi_page_list;
57 static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
59 if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
60 return cookie->iovad.granule;
64 static inline struct iova_domain *cookie_iovad(struct iommu_domain *domain)
66 struct iommu_dma_cookie *cookie = domain->iova_cookie;
68 if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
69 return &cookie->iovad;
73 static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
75 struct iommu_dma_cookie *cookie;
77 cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
79 spin_lock_init(&cookie->msi_lock);
80 INIT_LIST_HEAD(&cookie->msi_page_list);
86 int iommu_dma_init(void)
88 return iova_cache_get();
92 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
93 * @domain: IOMMU domain to prepare for DMA-API usage
95 * IOMMU drivers should normally call this from their domain_alloc
96 * callback when domain->type == IOMMU_DOMAIN_DMA.
98 int iommu_get_dma_cookie(struct iommu_domain *domain)
100 if (domain->iova_cookie)
103 domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
104 if (!domain->iova_cookie)
109 EXPORT_SYMBOL(iommu_get_dma_cookie);
112 * iommu_get_msi_cookie - Acquire just MSI remapping resources
113 * @domain: IOMMU domain to prepare
114 * @base: Start address of IOVA region for MSI mappings
116 * Users who manage their own IOVA allocation and do not want DMA API support,
117 * but would still like to take advantage of automatic MSI remapping, can use
118 * this to initialise their own domain appropriately. Users should reserve a
119 * contiguous IOVA region, starting at @base, large enough to accommodate the
120 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
121 * used by the devices attached to @domain.
123 int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
125 struct iommu_dma_cookie *cookie;
127 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
130 if (domain->iova_cookie)
133 cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
137 cookie->msi_iova = base;
138 domain->iova_cookie = cookie;
141 EXPORT_SYMBOL(iommu_get_msi_cookie);
144 * iommu_put_dma_cookie - Release a domain's DMA mapping resources
145 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
146 * iommu_get_msi_cookie()
148 * IOMMU drivers should normally call this from their domain_free callback.
150 void iommu_put_dma_cookie(struct iommu_domain *domain)
152 struct iommu_dma_cookie *cookie = domain->iova_cookie;
153 struct iommu_dma_msi_page *msi, *tmp;
158 if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule)
159 put_iova_domain(&cookie->iovad);
161 list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
162 list_del(&msi->list);
166 domain->iova_cookie = NULL;
168 EXPORT_SYMBOL(iommu_put_dma_cookie);
170 static void iova_reserve_pci_windows(struct pci_dev *dev,
171 struct iova_domain *iovad)
173 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
174 struct resource_entry *window;
175 unsigned long lo, hi;
177 resource_list_for_each_entry(window, &bridge->windows) {
178 if (resource_type(window->res) != IORESOURCE_MEM &&
179 resource_type(window->res) != IORESOURCE_IO)
182 lo = iova_pfn(iovad, window->res->start - window->offset);
183 hi = iova_pfn(iovad, window->res->end - window->offset);
184 reserve_iova(iovad, lo, hi);
189 * iommu_dma_init_domain - Initialise a DMA mapping domain
190 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
191 * @base: IOVA at which the mappable address space starts
192 * @size: Size of IOVA space
193 * @dev: Device the domain is being initialised for
195 * @base and @size should be exact multiples of IOMMU page granularity to
196 * avoid rounding surprises. If necessary, we reserve the page at address 0
197 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
198 * any change which could make prior IOVAs invalid will fail.
200 int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
201 u64 size, struct device *dev)
203 struct iommu_dma_cookie *cookie = domain->iova_cookie;
204 struct iova_domain *iovad = &cookie->iovad;
205 unsigned long order, base_pfn, end_pfn;
207 if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
210 /* Use the smallest supported page size for IOVA granularity */
211 order = __ffs(domain->pgsize_bitmap);
212 base_pfn = max_t(unsigned long, 1, base >> order);
213 end_pfn = (base + size - 1) >> order;
215 /* Check the domain allows at least some access to the device... */
216 if (domain->geometry.force_aperture) {
217 if (base > domain->geometry.aperture_end ||
218 base + size <= domain->geometry.aperture_start) {
219 pr_warn("specified DMA range outside IOMMU capability\n");
222 /* ...then finally give it a kicking to make sure it fits */
223 base_pfn = max_t(unsigned long, base_pfn,
224 domain->geometry.aperture_start >> order);
225 end_pfn = min_t(unsigned long, end_pfn,
226 domain->geometry.aperture_end >> order);
229 /* All we can safely do with an existing domain is enlarge it */
230 if (iovad->start_pfn) {
231 if (1UL << order != iovad->granule ||
232 base_pfn != iovad->start_pfn ||
233 end_pfn < iovad->dma_32bit_pfn) {
234 pr_warn("Incompatible range for DMA domain\n");
237 iovad->dma_32bit_pfn = end_pfn;
239 init_iova_domain(iovad, 1UL << order, base_pfn, end_pfn);
240 if (dev && dev_is_pci(dev))
241 iova_reserve_pci_windows(to_pci_dev(dev), iovad);
245 EXPORT_SYMBOL(iommu_dma_init_domain);
248 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
250 * @dir: Direction of DMA transfer
251 * @coherent: Is the DMA master cache-coherent?
252 * @attrs: DMA attributes for the mapping
254 * Return: corresponding IOMMU API page protection flags
256 int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
259 int prot = coherent ? IOMMU_CACHE : 0;
261 if (attrs & DMA_ATTR_PRIVILEGED)
265 case DMA_BIDIRECTIONAL:
266 return prot | IOMMU_READ | IOMMU_WRITE;
268 return prot | IOMMU_READ;
269 case DMA_FROM_DEVICE:
270 return prot | IOMMU_WRITE;
276 static struct iova *__alloc_iova(struct iommu_domain *domain, size_t size,
277 dma_addr_t dma_limit)
279 struct iova_domain *iovad = cookie_iovad(domain);
280 unsigned long shift = iova_shift(iovad);
281 unsigned long length = iova_align(iovad, size) >> shift;
283 if (domain->geometry.force_aperture)
284 dma_limit = min(dma_limit, domain->geometry.aperture_end);
286 * Enforce size-alignment to be safe - there could perhaps be an
287 * attribute to control this per-device, or at least per-domain...
289 return alloc_iova(iovad, length, dma_limit >> shift, true);
292 /* The IOVA allocator knows what we mapped, so just unmap whatever that was */
293 static void __iommu_dma_unmap(struct iommu_domain *domain, dma_addr_t dma_addr)
295 struct iova_domain *iovad = cookie_iovad(domain);
296 unsigned long shift = iova_shift(iovad);
297 unsigned long pfn = dma_addr >> shift;
298 struct iova *iova = find_iova(iovad, pfn);
304 size = iova_size(iova) << shift;
305 size -= iommu_unmap(domain, pfn << shift, size);
306 /* ...and if we can't, then something is horribly, horribly wrong */
308 __free_iova(iovad, iova);
311 static void __iommu_dma_free_pages(struct page **pages, int count)
314 __free_page(pages[count]);
318 static struct page **__iommu_dma_alloc_pages(unsigned int count,
319 unsigned long order_mask, gfp_t gfp)
322 unsigned int i = 0, array_size = count * sizeof(*pages);
324 order_mask &= (2U << MAX_ORDER) - 1;
328 if (array_size <= PAGE_SIZE)
329 pages = kzalloc(array_size, GFP_KERNEL);
331 pages = vzalloc(array_size);
335 /* IOMMU can map any pages, so himem can also be used here */
336 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
339 struct page *page = NULL;
340 unsigned int order_size;
343 * Higher-order allocations are a convenience rather
344 * than a necessity, hence using __GFP_NORETRY until
345 * falling back to minimum-order allocations.
347 for (order_mask &= (2U << __fls(count)) - 1;
348 order_mask; order_mask &= ~order_size) {
349 unsigned int order = __fls(order_mask);
351 order_size = 1U << order;
352 page = alloc_pages((order_mask - order_size) ?
353 gfp | __GFP_NORETRY : gfp, order);
358 if (!PageCompound(page)) {
359 split_page(page, order);
361 } else if (!split_huge_page(page)) {
364 __free_pages(page, order);
367 __iommu_dma_free_pages(pages, i);
378 * iommu_dma_free - Free a buffer allocated by iommu_dma_alloc()
379 * @dev: Device which owns this buffer
380 * @pages: Array of buffer pages as returned by iommu_dma_alloc()
381 * @size: Size of buffer in bytes
382 * @handle: DMA address of buffer
384 * Frees both the pages associated with the buffer, and the array
387 void iommu_dma_free(struct device *dev, struct page **pages, size_t size,
390 __iommu_dma_unmap(iommu_get_domain_for_dev(dev), *handle);
391 __iommu_dma_free_pages(pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
392 *handle = DMA_ERROR_CODE;
396 * iommu_dma_alloc - Allocate and map a buffer contiguous in IOVA space
397 * @dev: Device to allocate memory for. Must be a real device
398 * attached to an iommu_dma_domain
399 * @size: Size of buffer in bytes
400 * @gfp: Allocation flags
401 * @attrs: DMA attributes for this allocation
402 * @prot: IOMMU mapping flags
403 * @handle: Out argument for allocated DMA handle
404 * @flush_page: Arch callback which must ensure PAGE_SIZE bytes from the
405 * given VA/PA are visible to the given non-coherent device.
407 * If @size is less than PAGE_SIZE, then a full CPU page will be allocated,
408 * but an IOMMU which supports smaller pages might not map the whole thing.
410 * Return: Array of struct page pointers describing the buffer,
411 * or NULL on failure.
413 struct page **iommu_dma_alloc(struct device *dev, size_t size, gfp_t gfp,
414 unsigned long attrs, int prot, dma_addr_t *handle,
415 void (*flush_page)(struct device *, const void *, phys_addr_t))
417 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
418 struct iova_domain *iovad = cookie_iovad(domain);
423 unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
425 *handle = DMA_ERROR_CODE;
427 min_size = alloc_sizes & -alloc_sizes;
428 if (min_size < PAGE_SIZE) {
429 min_size = PAGE_SIZE;
430 alloc_sizes |= PAGE_SIZE;
432 size = ALIGN(size, min_size);
434 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
435 alloc_sizes = min_size;
437 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
438 pages = __iommu_dma_alloc_pages(count, alloc_sizes >> PAGE_SHIFT, gfp);
442 iova = __alloc_iova(domain, size, dev->coherent_dma_mask);
446 size = iova_align(iovad, size);
447 if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL))
450 if (!(prot & IOMMU_CACHE)) {
451 struct sg_mapping_iter miter;
453 * The CPU-centric flushing implied by SG_MITER_TO_SG isn't
454 * sufficient here, so skip it by using the "wrong" direction.
456 sg_miter_start(&miter, sgt.sgl, sgt.orig_nents, SG_MITER_FROM_SG);
457 while (sg_miter_next(&miter))
458 flush_page(dev, miter.addr, page_to_phys(miter.page));
459 sg_miter_stop(&miter);
462 dma_addr = iova_dma_addr(iovad, iova);
463 if (iommu_map_sg(domain, dma_addr, sgt.sgl, sgt.orig_nents, prot)
474 __free_iova(iovad, iova);
476 __iommu_dma_free_pages(pages, count);
481 * iommu_dma_mmap - Map a buffer into provided user VMA
482 * @pages: Array representing buffer from iommu_dma_alloc()
483 * @size: Size of buffer in bytes
484 * @vma: VMA describing requested userspace mapping
486 * Maps the pages of the buffer in @pages into @vma. The caller is responsible
487 * for verifying the correct size and protection of @vma beforehand.
490 int iommu_dma_mmap(struct page **pages, size_t size, struct vm_area_struct *vma)
492 unsigned long uaddr = vma->vm_start;
493 unsigned int i, count = PAGE_ALIGN(size) >> PAGE_SHIFT;
496 for (i = vma->vm_pgoff; i < count && uaddr < vma->vm_end; i++) {
497 ret = vm_insert_page(vma, uaddr, pages[i]);
505 static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
506 size_t size, int prot)
509 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
510 struct iova_domain *iovad = cookie_iovad(domain);
511 size_t iova_off = iova_offset(iovad, phys);
512 size_t len = iova_align(iovad, size + iova_off);
513 struct iova *iova = __alloc_iova(domain, len, dma_get_mask(dev));
516 return DMA_ERROR_CODE;
518 dma_addr = iova_dma_addr(iovad, iova);
519 if (iommu_map(domain, dma_addr, phys - iova_off, len, prot)) {
520 __free_iova(iovad, iova);
521 return DMA_ERROR_CODE;
523 return dma_addr + iova_off;
526 dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
527 unsigned long offset, size_t size, int prot)
529 return __iommu_dma_map(dev, page_to_phys(page) + offset, size, prot);
532 void iommu_dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
533 enum dma_data_direction dir, unsigned long attrs)
535 __iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle);
539 * Prepare a successfully-mapped scatterlist to give back to the caller.
541 * At this point the segments are already laid out by iommu_dma_map_sg() to
542 * avoid individually crossing any boundaries, so we merely need to check a
543 * segment's start address to avoid concatenating across one.
545 static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents,
548 struct scatterlist *s, *cur = sg;
549 unsigned long seg_mask = dma_get_seg_boundary(dev);
550 unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
553 for_each_sg(sg, s, nents, i) {
554 /* Restore this segment's original unaligned fields first */
555 unsigned int s_iova_off = sg_dma_address(s);
556 unsigned int s_length = sg_dma_len(s);
557 unsigned int s_iova_len = s->length;
559 s->offset += s_iova_off;
560 s->length = s_length;
561 sg_dma_address(s) = DMA_ERROR_CODE;
565 * Now fill in the real DMA data. If...
566 * - there is a valid output segment to append to
567 * - and this segment starts on an IOVA page boundary
568 * - but doesn't fall at a segment boundary
569 * - and wouldn't make the resulting output segment too long
571 if (cur_len && !s_iova_off && (dma_addr & seg_mask) &&
572 (cur_len + s_length <= max_len)) {
573 /* ...then concatenate it with the previous one */
576 /* Otherwise start the next output segment */
582 sg_dma_address(cur) = dma_addr + s_iova_off;
585 sg_dma_len(cur) = cur_len;
586 dma_addr += s_iova_len;
588 if (s_length + s_iova_off < s_iova_len)
595 * If mapping failed, then just restore the original list,
596 * but making sure the DMA fields are invalidated.
598 static void __invalidate_sg(struct scatterlist *sg, int nents)
600 struct scatterlist *s;
603 for_each_sg(sg, s, nents, i) {
604 if (sg_dma_address(s) != DMA_ERROR_CODE)
605 s->offset += sg_dma_address(s);
607 s->length = sg_dma_len(s);
608 sg_dma_address(s) = DMA_ERROR_CODE;
614 * The DMA API client is passing in a scatterlist which could describe
615 * any old buffer layout, but the IOMMU API requires everything to be
616 * aligned to IOMMU pages. Hence the need for this complicated bit of
617 * impedance-matching, to be able to hand off a suitably-aligned list,
618 * but still preserve the original offsets and sizes for the caller.
620 int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg,
623 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
624 struct iova_domain *iovad = cookie_iovad(domain);
626 struct scatterlist *s, *prev = NULL;
629 unsigned long mask = dma_get_seg_boundary(dev);
633 * Work out how much IOVA space we need, and align the segments to
634 * IOVA granules for the IOMMU driver to handle. With some clever
635 * trickery we can modify the list in-place, but reversibly, by
636 * stashing the unaligned parts in the as-yet-unused DMA fields.
638 for_each_sg(sg, s, nents, i) {
639 size_t s_iova_off = iova_offset(iovad, s->offset);
640 size_t s_length = s->length;
641 size_t pad_len = (mask - iova_len + 1) & mask;
643 sg_dma_address(s) = s_iova_off;
644 sg_dma_len(s) = s_length;
645 s->offset -= s_iova_off;
646 s_length = iova_align(iovad, s_length + s_iova_off);
647 s->length = s_length;
650 * Due to the alignment of our single IOVA allocation, we can
651 * depend on these assumptions about the segment boundary mask:
652 * - If mask size >= IOVA size, then the IOVA range cannot
653 * possibly fall across a boundary, so we don't care.
654 * - If mask size < IOVA size, then the IOVA range must start
655 * exactly on a boundary, therefore we can lay things out
656 * based purely on segment lengths without needing to know
657 * the actual addresses beforehand.
658 * - The mask must be a power of 2, so pad_len == 0 if
659 * iova_len == 0, thus we cannot dereference prev the first
660 * time through here (i.e. before it has a meaningful value).
662 if (pad_len && pad_len < s_length - 1) {
663 prev->length += pad_len;
667 iova_len += s_length;
671 iova = __alloc_iova(domain, iova_len, dma_get_mask(dev));
676 * We'll leave any physical concatenation to the IOMMU driver's
677 * implementation - it knows better than we do.
679 dma_addr = iova_dma_addr(iovad, iova);
680 if (iommu_map_sg(domain, dma_addr, sg, nents, prot) < iova_len)
683 return __finalise_sg(dev, sg, nents, dma_addr);
686 __free_iova(iovad, iova);
688 __invalidate_sg(sg, nents);
692 void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
693 enum dma_data_direction dir, unsigned long attrs)
696 * The scatterlist segments are mapped into a single
697 * contiguous IOVA allocation, so this is incredibly easy.
699 __iommu_dma_unmap(iommu_get_domain_for_dev(dev), sg_dma_address(sg));
702 dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
703 size_t size, enum dma_data_direction dir, unsigned long attrs)
705 return __iommu_dma_map(dev, phys, size,
706 dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO);
709 void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
710 size_t size, enum dma_data_direction dir, unsigned long attrs)
712 __iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle);
715 int iommu_dma_supported(struct device *dev, u64 mask)
718 * 'Special' IOMMUs which don't have the same addressing capability
719 * as the CPU will have to wait until we have some way to query that
720 * before they'll be able to use this framework.
725 int iommu_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
727 return dma_addr == DMA_ERROR_CODE;
730 static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
731 phys_addr_t msi_addr, struct iommu_domain *domain)
733 struct iommu_dma_cookie *cookie = domain->iova_cookie;
734 struct iommu_dma_msi_page *msi_page;
735 struct iova_domain *iovad = cookie_iovad(domain);
737 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
738 size_t size = cookie_msi_granule(cookie);
740 msi_addr &= ~(phys_addr_t)(size - 1);
741 list_for_each_entry(msi_page, &cookie->msi_page_list, list)
742 if (msi_page->phys == msi_addr)
745 msi_page = kzalloc(sizeof(*msi_page), GFP_ATOMIC);
749 msi_page->phys = msi_addr;
751 iova = __alloc_iova(domain, size, dma_get_mask(dev));
754 msi_page->iova = iova_dma_addr(iovad, iova);
756 msi_page->iova = cookie->msi_iova;
757 cookie->msi_iova += size;
760 if (iommu_map(domain, msi_page->iova, msi_addr, size, prot))
763 INIT_LIST_HEAD(&msi_page->list);
764 list_add(&msi_page->list, &cookie->msi_page_list);
769 __free_iova(iovad, iova);
771 cookie->msi_iova -= size;
777 void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg)
779 struct device *dev = msi_desc_to_dev(irq_get_msi_desc(irq));
780 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
781 struct iommu_dma_cookie *cookie;
782 struct iommu_dma_msi_page *msi_page;
783 phys_addr_t msi_addr = (u64)msg->address_hi << 32 | msg->address_lo;
786 if (!domain || !domain->iova_cookie)
789 cookie = domain->iova_cookie;
792 * We disable IRQs to rule out a possible inversion against
793 * irq_desc_lock if, say, someone tries to retarget the affinity
794 * of an MSI from within an IPI handler.
796 spin_lock_irqsave(&cookie->msi_lock, flags);
797 msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
798 spin_unlock_irqrestore(&cookie->msi_lock, flags);
800 if (WARN_ON(!msi_page)) {
802 * We're called from a void callback, so the best we can do is
803 * 'fail' by filling the message with obviously bogus values.
804 * Since we got this far due to an IOMMU being present, it's
805 * not like the existing address would have worked anyway...
807 msg->address_hi = ~0U;
808 msg->address_lo = ~0U;
811 msg->address_hi = upper_32_bits(msi_page->iova);
812 msg->address_lo &= cookie_msi_granule(cookie) - 1;
813 msg->address_lo += lower_32_bits(msi_page->iova);