1 // SPDX-License-Identifier: GPL-2.0-only
3 * A fairly generic DMA-API to IOMMU-API glue layer.
5 * Copyright (C) 2014-2015 ARM Ltd.
7 * based in part on arch/arm/mm/dma-mapping.c:
8 * Copyright (C) 2000-2004 Russell King
11 #include <linux/acpi_iort.h>
12 #include <linux/device.h>
13 #include <linux/dma-contiguous.h>
14 #include <linux/dma-iommu.h>
15 #include <linux/dma-noncoherent.h>
16 #include <linux/gfp.h>
17 #include <linux/huge_mm.h>
18 #include <linux/iommu.h>
19 #include <linux/iova.h>
20 #include <linux/irq.h>
22 #include <linux/pci.h>
23 #include <linux/scatterlist.h>
24 #include <linux/vmalloc.h>
26 struct iommu_dma_msi_page {
27 struct list_head list;
32 enum iommu_dma_cookie_type {
33 IOMMU_DMA_IOVA_COOKIE,
37 struct iommu_dma_cookie {
38 enum iommu_dma_cookie_type type;
40 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */
41 struct iova_domain iovad;
42 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
45 struct list_head msi_page_list;
48 /* Domain for flush queue callback; NULL if flush queue not in use */
49 struct iommu_domain *fq_domain;
52 static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
54 if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
55 return cookie->iovad.granule;
59 static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
61 struct iommu_dma_cookie *cookie;
63 cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
65 spin_lock_init(&cookie->msi_lock);
66 INIT_LIST_HEAD(&cookie->msi_page_list);
73 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
74 * @domain: IOMMU domain to prepare for DMA-API usage
76 * IOMMU drivers should normally call this from their domain_alloc
77 * callback when domain->type == IOMMU_DOMAIN_DMA.
79 int iommu_get_dma_cookie(struct iommu_domain *domain)
81 if (domain->iova_cookie)
84 domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
85 if (!domain->iova_cookie)
90 EXPORT_SYMBOL(iommu_get_dma_cookie);
93 * iommu_get_msi_cookie - Acquire just MSI remapping resources
94 * @domain: IOMMU domain to prepare
95 * @base: Start address of IOVA region for MSI mappings
97 * Users who manage their own IOVA allocation and do not want DMA API support,
98 * but would still like to take advantage of automatic MSI remapping, can use
99 * this to initialise their own domain appropriately. Users should reserve a
100 * contiguous IOVA region, starting at @base, large enough to accommodate the
101 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
102 * used by the devices attached to @domain.
104 int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
106 struct iommu_dma_cookie *cookie;
108 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
111 if (domain->iova_cookie)
114 cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
118 cookie->msi_iova = base;
119 domain->iova_cookie = cookie;
122 EXPORT_SYMBOL(iommu_get_msi_cookie);
125 * iommu_put_dma_cookie - Release a domain's DMA mapping resources
126 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
127 * iommu_get_msi_cookie()
129 * IOMMU drivers should normally call this from their domain_free callback.
131 void iommu_put_dma_cookie(struct iommu_domain *domain)
133 struct iommu_dma_cookie *cookie = domain->iova_cookie;
134 struct iommu_dma_msi_page *msi, *tmp;
139 if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule)
140 put_iova_domain(&cookie->iovad);
142 list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
143 list_del(&msi->list);
147 domain->iova_cookie = NULL;
149 EXPORT_SYMBOL(iommu_put_dma_cookie);
152 * iommu_dma_get_resv_regions - Reserved region driver helper
153 * @dev: Device from iommu_get_resv_regions()
154 * @list: Reserved region list from iommu_get_resv_regions()
156 * IOMMU drivers can use this to implement their .get_resv_regions callback
157 * for general non-IOMMU-specific reservations. Currently, this covers GICv3
158 * ITS region reservation on ACPI based ARM platforms that may require HW MSI
161 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
164 if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode))
165 iort_iommu_msi_get_resv_regions(dev, list);
168 EXPORT_SYMBOL(iommu_dma_get_resv_regions);
170 static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie,
171 phys_addr_t start, phys_addr_t end)
173 struct iova_domain *iovad = &cookie->iovad;
174 struct iommu_dma_msi_page *msi_page;
177 start -= iova_offset(iovad, start);
178 num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
180 msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL);
184 for (i = 0; i < num_pages; i++) {
185 msi_page[i].phys = start;
186 msi_page[i].iova = start;
187 INIT_LIST_HEAD(&msi_page[i].list);
188 list_add(&msi_page[i].list, &cookie->msi_page_list);
189 start += iovad->granule;
195 static int iova_reserve_pci_windows(struct pci_dev *dev,
196 struct iova_domain *iovad)
198 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
199 struct resource_entry *window;
200 unsigned long lo, hi;
201 phys_addr_t start = 0, end;
203 resource_list_for_each_entry(window, &bridge->windows) {
204 if (resource_type(window->res) != IORESOURCE_MEM)
207 lo = iova_pfn(iovad, window->res->start - window->offset);
208 hi = iova_pfn(iovad, window->res->end - window->offset);
209 reserve_iova(iovad, lo, hi);
212 /* Get reserved DMA windows from host bridge */
213 resource_list_for_each_entry(window, &bridge->dma_ranges) {
214 end = window->res->start - window->offset;
217 lo = iova_pfn(iovad, start);
218 hi = iova_pfn(iovad, end);
219 reserve_iova(iovad, lo, hi);
221 /* dma_ranges list should be sorted */
222 dev_err(&dev->dev, "Failed to reserve IOVA\n");
226 start = window->res->end - window->offset + 1;
227 /* If window is last entry */
228 if (window->node.next == &bridge->dma_ranges &&
229 end != ~(phys_addr_t)0) {
230 end = ~(phys_addr_t)0;
238 static int iova_reserve_iommu_regions(struct device *dev,
239 struct iommu_domain *domain)
241 struct iommu_dma_cookie *cookie = domain->iova_cookie;
242 struct iova_domain *iovad = &cookie->iovad;
243 struct iommu_resv_region *region;
244 LIST_HEAD(resv_regions);
247 if (dev_is_pci(dev)) {
248 ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad);
253 iommu_get_resv_regions(dev, &resv_regions);
254 list_for_each_entry(region, &resv_regions, list) {
255 unsigned long lo, hi;
257 /* We ARE the software that manages these! */
258 if (region->type == IOMMU_RESV_SW_MSI)
261 lo = iova_pfn(iovad, region->start);
262 hi = iova_pfn(iovad, region->start + region->length - 1);
263 reserve_iova(iovad, lo, hi);
265 if (region->type == IOMMU_RESV_MSI)
266 ret = cookie_init_hw_msi_region(cookie, region->start,
267 region->start + region->length);
271 iommu_put_resv_regions(dev, &resv_regions);
276 static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad)
278 struct iommu_dma_cookie *cookie;
279 struct iommu_domain *domain;
281 cookie = container_of(iovad, struct iommu_dma_cookie, iovad);
282 domain = cookie->fq_domain;
284 * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE
285 * implies that ops->flush_iotlb_all must be non-NULL.
287 domain->ops->flush_iotlb_all(domain);
291 * iommu_dma_init_domain - Initialise a DMA mapping domain
292 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
293 * @base: IOVA at which the mappable address space starts
294 * @size: Size of IOVA space
295 * @dev: Device the domain is being initialised for
297 * @base and @size should be exact multiples of IOMMU page granularity to
298 * avoid rounding surprises. If necessary, we reserve the page at address 0
299 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
300 * any change which could make prior IOVAs invalid will fail.
302 static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
303 u64 size, struct device *dev)
305 struct iommu_dma_cookie *cookie = domain->iova_cookie;
306 struct iova_domain *iovad = &cookie->iovad;
307 unsigned long order, base_pfn;
310 if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
313 /* Use the smallest supported page size for IOVA granularity */
314 order = __ffs(domain->pgsize_bitmap);
315 base_pfn = max_t(unsigned long, 1, base >> order);
317 /* Check the domain allows at least some access to the device... */
318 if (domain->geometry.force_aperture) {
319 if (base > domain->geometry.aperture_end ||
320 base + size <= domain->geometry.aperture_start) {
321 pr_warn("specified DMA range outside IOMMU capability\n");
324 /* ...then finally give it a kicking to make sure it fits */
325 base_pfn = max_t(unsigned long, base_pfn,
326 domain->geometry.aperture_start >> order);
329 /* start_pfn is always nonzero for an already-initialised domain */
330 if (iovad->start_pfn) {
331 if (1UL << order != iovad->granule ||
332 base_pfn != iovad->start_pfn) {
333 pr_warn("Incompatible range for DMA domain\n");
340 init_iova_domain(iovad, 1UL << order, base_pfn);
342 if (!cookie->fq_domain && !iommu_domain_get_attr(domain,
343 DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && attr) {
344 cookie->fq_domain = domain;
345 init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, NULL);
351 return iova_reserve_iommu_regions(dev, domain);
355 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
357 * @dir: Direction of DMA transfer
358 * @coherent: Is the DMA master cache-coherent?
359 * @attrs: DMA attributes for the mapping
361 * Return: corresponding IOMMU API page protection flags
363 static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
366 int prot = coherent ? IOMMU_CACHE : 0;
368 if (attrs & DMA_ATTR_PRIVILEGED)
372 case DMA_BIDIRECTIONAL:
373 return prot | IOMMU_READ | IOMMU_WRITE;
375 return prot | IOMMU_READ;
376 case DMA_FROM_DEVICE:
377 return prot | IOMMU_WRITE;
383 static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
384 size_t size, dma_addr_t dma_limit, struct device *dev)
386 struct iommu_dma_cookie *cookie = domain->iova_cookie;
387 struct iova_domain *iovad = &cookie->iovad;
388 unsigned long shift, iova_len, iova = 0;
390 if (cookie->type == IOMMU_DMA_MSI_COOKIE) {
391 cookie->msi_iova += size;
392 return cookie->msi_iova - size;
395 shift = iova_shift(iovad);
396 iova_len = size >> shift;
398 * Freeing non-power-of-two-sized allocations back into the IOVA caches
399 * will come back to bite us badly, so we have to waste a bit of space
400 * rounding up anything cacheable to make sure that can't happen. The
401 * order of the unadjusted size will still match upon freeing.
403 if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1)))
404 iova_len = roundup_pow_of_two(iova_len);
406 if (dev->bus_dma_mask)
407 dma_limit &= dev->bus_dma_mask;
409 if (domain->geometry.force_aperture)
410 dma_limit = min(dma_limit, domain->geometry.aperture_end);
412 /* Try to get PCI devices a SAC address */
413 if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev))
414 iova = alloc_iova_fast(iovad, iova_len,
415 DMA_BIT_MASK(32) >> shift, false);
418 iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift,
421 return (dma_addr_t)iova << shift;
424 static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie,
425 dma_addr_t iova, size_t size)
427 struct iova_domain *iovad = &cookie->iovad;
429 /* The MSI case is only ever cleaning up its most recent allocation */
430 if (cookie->type == IOMMU_DMA_MSI_COOKIE)
431 cookie->msi_iova -= size;
432 else if (cookie->fq_domain) /* non-strict mode */
433 queue_iova(iovad, iova_pfn(iovad, iova),
434 size >> iova_shift(iovad), 0);
436 free_iova_fast(iovad, iova_pfn(iovad, iova),
437 size >> iova_shift(iovad));
440 static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr,
443 struct iommu_domain *domain = iommu_get_dma_domain(dev);
444 struct iommu_dma_cookie *cookie = domain->iova_cookie;
445 struct iova_domain *iovad = &cookie->iovad;
446 size_t iova_off = iova_offset(iovad, dma_addr);
448 dma_addr -= iova_off;
449 size = iova_align(iovad, size + iova_off);
451 WARN_ON(iommu_unmap_fast(domain, dma_addr, size) != size);
452 if (!cookie->fq_domain)
453 iommu_tlb_sync(domain);
454 iommu_dma_free_iova(cookie, dma_addr, size);
457 static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
458 size_t size, int prot)
460 struct iommu_domain *domain = iommu_get_dma_domain(dev);
461 struct iommu_dma_cookie *cookie = domain->iova_cookie;
462 struct iova_domain *iovad = &cookie->iovad;
463 size_t iova_off = iova_offset(iovad, phys);
466 size = iova_align(iovad, size + iova_off);
468 iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
470 return DMA_MAPPING_ERROR;
472 if (iommu_map(domain, iova, phys - iova_off, size, prot)) {
473 iommu_dma_free_iova(cookie, iova, size);
474 return DMA_MAPPING_ERROR;
476 return iova + iova_off;
479 static void __iommu_dma_free_pages(struct page **pages, int count)
482 __free_page(pages[count]);
486 static struct page **__iommu_dma_alloc_pages(struct device *dev,
487 unsigned int count, unsigned long order_mask, gfp_t gfp)
490 unsigned int i = 0, nid = dev_to_node(dev);
492 order_mask &= (2U << MAX_ORDER) - 1;
496 pages = kvzalloc(count * sizeof(*pages), GFP_KERNEL);
500 /* IOMMU can map any pages, so himem can also be used here */
501 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
504 struct page *page = NULL;
505 unsigned int order_size;
508 * Higher-order allocations are a convenience rather
509 * than a necessity, hence using __GFP_NORETRY until
510 * falling back to minimum-order allocations.
512 for (order_mask &= (2U << __fls(count)) - 1;
513 order_mask; order_mask &= ~order_size) {
514 unsigned int order = __fls(order_mask);
515 gfp_t alloc_flags = gfp;
517 order_size = 1U << order;
518 if (order_mask > order_size)
519 alloc_flags |= __GFP_NORETRY;
520 page = alloc_pages_node(nid, alloc_flags, order);
525 if (!PageCompound(page)) {
526 split_page(page, order);
528 } else if (!split_huge_page(page)) {
531 __free_pages(page, order);
534 __iommu_dma_free_pages(pages, i);
544 static struct page **__iommu_dma_get_pages(void *cpu_addr)
546 struct vm_struct *area = find_vm_area(cpu_addr);
548 if (!area || !area->pages)
554 * iommu_dma_alloc_remap - Allocate and map a buffer contiguous in IOVA space
555 * @dev: Device to allocate memory for. Must be a real device
556 * attached to an iommu_dma_domain
557 * @size: Size of buffer in bytes
558 * @dma_handle: Out argument for allocated DMA handle
559 * @gfp: Allocation flags
560 * @attrs: DMA attributes for this allocation
562 * If @size is less than PAGE_SIZE, then a full CPU page will be allocated,
563 * but an IOMMU which supports smaller pages might not map the whole thing.
565 * Return: Mapped virtual address, or NULL on failure.
567 static void *iommu_dma_alloc_remap(struct device *dev, size_t size,
568 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
570 struct iommu_domain *domain = iommu_get_dma_domain(dev);
571 struct iommu_dma_cookie *cookie = domain->iova_cookie;
572 struct iova_domain *iovad = &cookie->iovad;
573 bool coherent = dev_is_dma_coherent(dev);
574 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
575 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
576 unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
582 *dma_handle = DMA_MAPPING_ERROR;
584 min_size = alloc_sizes & -alloc_sizes;
585 if (min_size < PAGE_SIZE) {
586 min_size = PAGE_SIZE;
587 alloc_sizes |= PAGE_SIZE;
589 size = ALIGN(size, min_size);
591 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
592 alloc_sizes = min_size;
594 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
595 pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT,
600 size = iova_align(iovad, size);
601 iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev);
605 if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL))
608 if (!(ioprot & IOMMU_CACHE)) {
609 struct scatterlist *sg;
612 for_each_sg(sgt.sgl, sg, sgt.orig_nents, i)
613 arch_dma_prep_coherent(sg_page(sg), sg->length);
616 if (iommu_map_sg(domain, iova, sgt.sgl, sgt.orig_nents, ioprot)
620 vaddr = dma_common_pages_remap(pages, size, VM_USERMAP, prot,
621 __builtin_return_address(0));
630 __iommu_dma_unmap(dev, iova, size);
634 iommu_dma_free_iova(cookie, iova, size);
636 __iommu_dma_free_pages(pages, count);
641 * __iommu_dma_mmap - Map a buffer into provided user VMA
642 * @pages: Array representing buffer from __iommu_dma_alloc()
643 * @size: Size of buffer in bytes
644 * @vma: VMA describing requested userspace mapping
646 * Maps the pages of the buffer in @pages into @vma. The caller is responsible
647 * for verifying the correct size and protection of @vma beforehand.
649 static int __iommu_dma_mmap(struct page **pages, size_t size,
650 struct vm_area_struct *vma)
652 return vm_map_pages(vma, pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
655 static void iommu_dma_sync_single_for_cpu(struct device *dev,
656 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
660 if (dev_is_dma_coherent(dev))
663 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
664 arch_sync_dma_for_cpu(dev, phys, size, dir);
667 static void iommu_dma_sync_single_for_device(struct device *dev,
668 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
672 if (dev_is_dma_coherent(dev))
675 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
676 arch_sync_dma_for_device(dev, phys, size, dir);
679 static void iommu_dma_sync_sg_for_cpu(struct device *dev,
680 struct scatterlist *sgl, int nelems,
681 enum dma_data_direction dir)
683 struct scatterlist *sg;
686 if (dev_is_dma_coherent(dev))
689 for_each_sg(sgl, sg, nelems, i)
690 arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir);
693 static void iommu_dma_sync_sg_for_device(struct device *dev,
694 struct scatterlist *sgl, int nelems,
695 enum dma_data_direction dir)
697 struct scatterlist *sg;
700 if (dev_is_dma_coherent(dev))
703 for_each_sg(sgl, sg, nelems, i)
704 arch_sync_dma_for_device(dev, sg_phys(sg), sg->length, dir);
707 static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
708 unsigned long offset, size_t size, enum dma_data_direction dir,
711 phys_addr_t phys = page_to_phys(page) + offset;
712 bool coherent = dev_is_dma_coherent(dev);
713 int prot = dma_info_to_prot(dir, coherent, attrs);
714 dma_addr_t dma_handle;
716 dma_handle =__iommu_dma_map(dev, phys, size, prot);
717 if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
718 dma_handle != DMA_MAPPING_ERROR)
719 arch_sync_dma_for_device(dev, phys, size, dir);
723 static void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
724 size_t size, enum dma_data_direction dir, unsigned long attrs)
726 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
727 iommu_dma_sync_single_for_cpu(dev, dma_handle, size, dir);
728 __iommu_dma_unmap(dev, dma_handle, size);
732 * Prepare a successfully-mapped scatterlist to give back to the caller.
734 * At this point the segments are already laid out by iommu_dma_map_sg() to
735 * avoid individually crossing any boundaries, so we merely need to check a
736 * segment's start address to avoid concatenating across one.
738 static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents,
741 struct scatterlist *s, *cur = sg;
742 unsigned long seg_mask = dma_get_seg_boundary(dev);
743 unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
746 for_each_sg(sg, s, nents, i) {
747 /* Restore this segment's original unaligned fields first */
748 unsigned int s_iova_off = sg_dma_address(s);
749 unsigned int s_length = sg_dma_len(s);
750 unsigned int s_iova_len = s->length;
752 s->offset += s_iova_off;
753 s->length = s_length;
754 sg_dma_address(s) = DMA_MAPPING_ERROR;
758 * Now fill in the real DMA data. If...
759 * - there is a valid output segment to append to
760 * - and this segment starts on an IOVA page boundary
761 * - but doesn't fall at a segment boundary
762 * - and wouldn't make the resulting output segment too long
764 if (cur_len && !s_iova_off && (dma_addr & seg_mask) &&
765 (max_len - cur_len >= s_length)) {
766 /* ...then concatenate it with the previous one */
769 /* Otherwise start the next output segment */
775 sg_dma_address(cur) = dma_addr + s_iova_off;
778 sg_dma_len(cur) = cur_len;
779 dma_addr += s_iova_len;
781 if (s_length + s_iova_off < s_iova_len)
788 * If mapping failed, then just restore the original list,
789 * but making sure the DMA fields are invalidated.
791 static void __invalidate_sg(struct scatterlist *sg, int nents)
793 struct scatterlist *s;
796 for_each_sg(sg, s, nents, i) {
797 if (sg_dma_address(s) != DMA_MAPPING_ERROR)
798 s->offset += sg_dma_address(s);
800 s->length = sg_dma_len(s);
801 sg_dma_address(s) = DMA_MAPPING_ERROR;
807 * The DMA API client is passing in a scatterlist which could describe
808 * any old buffer layout, but the IOMMU API requires everything to be
809 * aligned to IOMMU pages. Hence the need for this complicated bit of
810 * impedance-matching, to be able to hand off a suitably-aligned list,
811 * but still preserve the original offsets and sizes for the caller.
813 static int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg,
814 int nents, enum dma_data_direction dir, unsigned long attrs)
816 struct iommu_domain *domain = iommu_get_dma_domain(dev);
817 struct iommu_dma_cookie *cookie = domain->iova_cookie;
818 struct iova_domain *iovad = &cookie->iovad;
819 struct scatterlist *s, *prev = NULL;
820 int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs);
823 unsigned long mask = dma_get_seg_boundary(dev);
826 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
827 iommu_dma_sync_sg_for_device(dev, sg, nents, dir);
830 * Work out how much IOVA space we need, and align the segments to
831 * IOVA granules for the IOMMU driver to handle. With some clever
832 * trickery we can modify the list in-place, but reversibly, by
833 * stashing the unaligned parts in the as-yet-unused DMA fields.
835 for_each_sg(sg, s, nents, i) {
836 size_t s_iova_off = iova_offset(iovad, s->offset);
837 size_t s_length = s->length;
838 size_t pad_len = (mask - iova_len + 1) & mask;
840 sg_dma_address(s) = s_iova_off;
841 sg_dma_len(s) = s_length;
842 s->offset -= s_iova_off;
843 s_length = iova_align(iovad, s_length + s_iova_off);
844 s->length = s_length;
847 * Due to the alignment of our single IOVA allocation, we can
848 * depend on these assumptions about the segment boundary mask:
849 * - If mask size >= IOVA size, then the IOVA range cannot
850 * possibly fall across a boundary, so we don't care.
851 * - If mask size < IOVA size, then the IOVA range must start
852 * exactly on a boundary, therefore we can lay things out
853 * based purely on segment lengths without needing to know
854 * the actual addresses beforehand.
855 * - The mask must be a power of 2, so pad_len == 0 if
856 * iova_len == 0, thus we cannot dereference prev the first
857 * time through here (i.e. before it has a meaningful value).
859 if (pad_len && pad_len < s_length - 1) {
860 prev->length += pad_len;
864 iova_len += s_length;
868 iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev);
873 * We'll leave any physical concatenation to the IOMMU driver's
874 * implementation - it knows better than we do.
876 if (iommu_map_sg(domain, iova, sg, nents, prot) < iova_len)
879 return __finalise_sg(dev, sg, nents, iova);
882 iommu_dma_free_iova(cookie, iova, iova_len);
884 __invalidate_sg(sg, nents);
888 static void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
889 int nents, enum dma_data_direction dir, unsigned long attrs)
891 dma_addr_t start, end;
892 struct scatterlist *tmp;
895 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
896 iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir);
899 * The scatterlist segments are mapped into a single
900 * contiguous IOVA allocation, so this is incredibly easy.
902 start = sg_dma_address(sg);
903 for_each_sg(sg_next(sg), tmp, nents - 1, i) {
904 if (sg_dma_len(tmp) == 0)
908 end = sg_dma_address(sg) + sg_dma_len(sg);
909 __iommu_dma_unmap(dev, start, end - start);
912 static dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
913 size_t size, enum dma_data_direction dir, unsigned long attrs)
915 return __iommu_dma_map(dev, phys, size,
916 dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO);
919 static void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
920 size_t size, enum dma_data_direction dir, unsigned long attrs)
922 __iommu_dma_unmap(dev, handle, size);
925 static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
927 size_t alloc_size = PAGE_ALIGN(size);
928 int count = alloc_size >> PAGE_SHIFT;
929 struct page *page = NULL, **pages = NULL;
931 /* Non-coherent atomic allocation? Easy */
932 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
933 dma_free_from_pool(cpu_addr, alloc_size))
936 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
938 * If it the address is remapped, then it's either non-coherent
939 * or highmem CMA, or an iommu_dma_alloc_remap() construction.
941 pages = __iommu_dma_get_pages(cpu_addr);
943 page = vmalloc_to_page(cpu_addr);
944 dma_common_free_remap(cpu_addr, alloc_size, VM_USERMAP);
946 /* Lowmem means a coherent atomic or CMA allocation */
947 page = virt_to_page(cpu_addr);
951 __iommu_dma_free_pages(pages, count);
953 dma_free_contiguous(dev, page, alloc_size);
956 static void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
957 dma_addr_t handle, unsigned long attrs)
959 __iommu_dma_unmap(dev, handle, size);
960 __iommu_dma_free(dev, size, cpu_addr);
963 static void *iommu_dma_alloc_pages(struct device *dev, size_t size,
964 struct page **pagep, gfp_t gfp, unsigned long attrs)
966 bool coherent = dev_is_dma_coherent(dev);
967 size_t alloc_size = PAGE_ALIGN(size);
968 struct page *page = NULL;
971 page = dma_alloc_contiguous(dev, alloc_size, gfp);
975 if (IS_ENABLED(CONFIG_DMA_REMAP) && (!coherent || PageHighMem(page))) {
976 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
978 cpu_addr = dma_common_contiguous_remap(page, alloc_size,
979 VM_USERMAP, prot, __builtin_return_address(0));
984 arch_dma_prep_coherent(page, size);
986 cpu_addr = page_address(page);
990 memset(cpu_addr, 0, alloc_size);
993 dma_free_contiguous(dev, page, alloc_size);
997 static void *iommu_dma_alloc(struct device *dev, size_t size,
998 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1000 bool coherent = dev_is_dma_coherent(dev);
1001 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
1002 struct page *page = NULL;
1007 if (IS_ENABLED(CONFIG_DMA_REMAP) && gfpflags_allow_blocking(gfp) &&
1008 !(attrs & DMA_ATTR_FORCE_CONTIGUOUS))
1009 return iommu_dma_alloc_remap(dev, size, handle, gfp, attrs);
1011 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1012 !gfpflags_allow_blocking(gfp) && !coherent)
1013 cpu_addr = dma_alloc_from_pool(PAGE_ALIGN(size), &page, gfp);
1015 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs);
1019 *handle = __iommu_dma_map(dev, page_to_phys(page), size, ioprot);
1020 if (*handle == DMA_MAPPING_ERROR) {
1021 __iommu_dma_free(dev, size, cpu_addr);
1028 static int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
1029 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1030 unsigned long attrs)
1032 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1033 unsigned long pfn, off = vma->vm_pgoff;
1036 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
1038 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
1041 if (off >= nr_pages || vma_pages(vma) > nr_pages - off)
1044 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1045 struct page **pages = __iommu_dma_get_pages(cpu_addr);
1048 return __iommu_dma_mmap(pages, size, vma);
1049 pfn = vmalloc_to_pfn(cpu_addr);
1051 pfn = page_to_pfn(virt_to_page(cpu_addr));
1054 return remap_pfn_range(vma, vma->vm_start, pfn + off,
1055 vma->vm_end - vma->vm_start,
1059 static int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
1060 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1061 unsigned long attrs)
1066 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1067 struct page **pages = __iommu_dma_get_pages(cpu_addr);
1070 return sg_alloc_table_from_pages(sgt, pages,
1071 PAGE_ALIGN(size) >> PAGE_SHIFT,
1072 0, size, GFP_KERNEL);
1075 page = vmalloc_to_page(cpu_addr);
1077 page = virt_to_page(cpu_addr);
1080 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
1082 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
1086 static const struct dma_map_ops iommu_dma_ops = {
1087 .alloc = iommu_dma_alloc,
1088 .free = iommu_dma_free,
1089 .mmap = iommu_dma_mmap,
1090 .get_sgtable = iommu_dma_get_sgtable,
1091 .map_page = iommu_dma_map_page,
1092 .unmap_page = iommu_dma_unmap_page,
1093 .map_sg = iommu_dma_map_sg,
1094 .unmap_sg = iommu_dma_unmap_sg,
1095 .sync_single_for_cpu = iommu_dma_sync_single_for_cpu,
1096 .sync_single_for_device = iommu_dma_sync_single_for_device,
1097 .sync_sg_for_cpu = iommu_dma_sync_sg_for_cpu,
1098 .sync_sg_for_device = iommu_dma_sync_sg_for_device,
1099 .map_resource = iommu_dma_map_resource,
1100 .unmap_resource = iommu_dma_unmap_resource,
1104 * The IOMMU core code allocates the default DMA domain, which the underlying
1105 * IOMMU driver needs to support via the dma-iommu layer.
1107 void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size)
1109 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1115 * The IOMMU core code allocates the default DMA domain, which the
1116 * underlying IOMMU driver needs to support via the dma-iommu layer.
1118 if (domain->type == IOMMU_DOMAIN_DMA) {
1119 if (iommu_dma_init_domain(domain, dma_base, size, dev))
1121 dev->dma_ops = &iommu_dma_ops;
1126 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
1130 static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
1131 phys_addr_t msi_addr, struct iommu_domain *domain)
1133 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1134 struct iommu_dma_msi_page *msi_page;
1136 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
1137 size_t size = cookie_msi_granule(cookie);
1139 msi_addr &= ~(phys_addr_t)(size - 1);
1140 list_for_each_entry(msi_page, &cookie->msi_page_list, list)
1141 if (msi_page->phys == msi_addr)
1144 msi_page = kzalloc(sizeof(*msi_page), GFP_ATOMIC);
1148 iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
1152 if (iommu_map(domain, iova, msi_addr, size, prot))
1155 INIT_LIST_HEAD(&msi_page->list);
1156 msi_page->phys = msi_addr;
1157 msi_page->iova = iova;
1158 list_add(&msi_page->list, &cookie->msi_page_list);
1162 iommu_dma_free_iova(cookie, iova, size);
1168 int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
1170 struct device *dev = msi_desc_to_dev(desc);
1171 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1172 struct iommu_dma_cookie *cookie;
1173 struct iommu_dma_msi_page *msi_page;
1174 unsigned long flags;
1176 if (!domain || !domain->iova_cookie) {
1177 desc->iommu_cookie = NULL;
1181 cookie = domain->iova_cookie;
1184 * We disable IRQs to rule out a possible inversion against
1185 * irq_desc_lock if, say, someone tries to retarget the affinity
1186 * of an MSI from within an IPI handler.
1188 spin_lock_irqsave(&cookie->msi_lock, flags);
1189 msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
1190 spin_unlock_irqrestore(&cookie->msi_lock, flags);
1192 msi_desc_set_iommu_cookie(desc, msi_page);
1199 void iommu_dma_compose_msi_msg(struct msi_desc *desc,
1200 struct msi_msg *msg)
1202 struct device *dev = msi_desc_to_dev(desc);
1203 const struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1204 const struct iommu_dma_msi_page *msi_page;
1206 msi_page = msi_desc_get_iommu_cookie(desc);
1208 if (!domain || !domain->iova_cookie || WARN_ON(!msi_page))
1211 msg->address_hi = upper_32_bits(msi_page->iova);
1212 msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1;
1213 msg->address_lo += lower_32_bits(msi_page->iova);
1216 static int iommu_dma_init(void)
1218 return iova_cache_get();
1220 arch_initcall(iommu_dma_init);