drivers/iommu/dmar.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2006, Intel Corporation.
   4  *
   5  * Copyright (C) 2006-2008 Intel Corporation
   6  * Author: Ashok Raj <ashok.raj@intel.com>
   7  * Author: Shaohua Li <shaohua.li@intel.com>
   8  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
   9  *
  10  * This file implements early detection/parsing of Remapping Devices
  11  * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
  12  * tables.
  13  *
  14  * These routines are used by both DMA-remapping and Interrupt-remapping
  15  */
  16
  17 #define pr_fmt(fmt)     "DMAR: " fmt
  18
  19 #include <linux/pci.h>
  20 #include <linux/dmar.h>
  21 #include <linux/iova.h>
  22 #include <linux/intel-iommu.h>
  23 #include <linux/timer.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/tboot.h>
  27 #include <linux/dmi.h>
  28 #include <linux/slab.h>
  29 #include <linux/iommu.h>
  30 #include <linux/numa.h>
  31 #include <asm/irq_remapping.h>
  32 #include <asm/iommu_table.h>
  33
  34 #include "irq_remapping.h"
  35
  36 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
  37 struct dmar_res_callback {
  38         dmar_res_handler_t      cb[ACPI_DMAR_TYPE_RESERVED];
  39         void                    *arg[ACPI_DMAR_TYPE_RESERVED];
  40         bool                    ignore_unhandled;
  41         bool                    print_entry;
  42 };
  43
  44 /*
  45  * Assumptions:
  46  * 1) The hotplug framework guarentees that DMAR unit will be hot-added
  47  *    before IO devices managed by that unit.
  48  * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
  49  *    after IO devices managed by that unit.
  50  * 3) Hotplug events are rare.
  51  *
  52  * Locking rules for DMA and interrupt remapping related global data structures:
  53  * 1) Use dmar_global_lock in process context
  54  * 2) Use RCU in interrupt context
  55  */
  56 DECLARE_RWSEM(dmar_global_lock);
  57 LIST_HEAD(dmar_drhd_units);
  58
  59 struct acpi_table_header * __initdata dmar_tbl;
  60 static int dmar_dev_scope_status = 1;
  61 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
  62
  63 static int alloc_iommu(struct dmar_drhd_unit *drhd);
  64 static void free_iommu(struct intel_iommu *iommu);
  65
  66 extern const struct iommu_ops intel_iommu_ops;
  67
  68 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
  69 {
  70         /*
  71          * add INCLUDE_ALL at the tail, so scan the list will find it at
  72          * the very end.
  73          */
  74         if (drhd->include_all)
  75                 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
  76         else
  77                 list_add_rcu(&drhd->list, &dmar_drhd_units);
  78 }
  79
  80 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
  81 {
  82         struct acpi_dmar_device_scope *scope;
  83
  84         *cnt = 0;
  85         while (start < end) {
  86                 scope = start;
  87                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
  88                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
  89                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
  90                         (*cnt)++;
  91                 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
  92                         scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
  93                         pr_warn("Unsupported device scope\n");
  94                 }
  95                 start += scope->length;
  96         }
  97         if (*cnt == 0)
  98                 return NULL;
  99
 100         return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
 101 }
 102
 103 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
 104 {
 105         int i;
 106         struct device *tmp_dev;
 107
 108         if (*devices && *cnt) {
 109                 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
 110                         put_device(tmp_dev);
 111                 kfree(*devices);
 112         }
 113
 114         *devices = NULL;
 115         *cnt = 0;
 116 }
 117
 118 /* Optimize out kzalloc()/kfree() for normal cases */
 119 static char dmar_pci_notify_info_buf[64];
 120
 121 static struct dmar_pci_notify_info *
 122 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
 123 {
 124         int level = 0;
 125         size_t size;
 126         struct pci_dev *tmp;
 127         struct dmar_pci_notify_info *info;
 128
 129         BUG_ON(dev->is_virtfn);
 130
 131         /* Only generate path[] for device addition event */
 132         if (event == BUS_NOTIFY_ADD_DEVICE)
 133                 for (tmp = dev; tmp; tmp = tmp->bus->self)
 134                         level++;
 135
 136         size = struct_size(info, path, level);
 137         if (size <= sizeof(dmar_pci_notify_info_buf)) {
 138                 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
 139         } else {
 140                 info = kzalloc(size, GFP_KERNEL);
 141                 if (!info) {
 142                         pr_warn("Out of memory when allocating notify_info "
 143                                 "for %s.\n", pci_name(dev));
 144                         if (dmar_dev_scope_status == 0)
 145                                 dmar_dev_scope_status = -ENOMEM;
 146                         return NULL;
 147                 }
 148         }
 149
 150         info->event = event;
 151         info->dev = dev;
 152         info->seg = pci_domain_nr(dev->bus);
 153         info->level = level;
 154         if (event == BUS_NOTIFY_ADD_DEVICE) {
 155                 for (tmp = dev; tmp; tmp = tmp->bus->self) {
 156                         level--;
 157                         info->path[level].bus = tmp->bus->number;
 158                         info->path[level].device = PCI_SLOT(tmp->devfn);
 159                         info->path[level].function = PCI_FUNC(tmp->devfn);
 160                         if (pci_is_root_bus(tmp->bus))
 161                                 info->bus = tmp->bus->number;
 162                 }
 163         }
 164
 165         return info;
 166 }
 167
 168 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
 169 {
 170         if ((void *)info != dmar_pci_notify_info_buf)
 171                 kfree(info);
 172 }
 173
 174 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
 175                                 struct acpi_dmar_pci_path *path, int count)
 176 {
 177         int i;
 178
 179         if (info->bus != bus)
 180                 goto fallback;
 181         if (info->level != count)
 182                 goto fallback;
 183
 184         for (i = 0; i < count; i++) {
 185                 if (path[i].device != info->path[i].device ||
 186                     path[i].function != info->path[i].function)
 187                         goto fallback;
 188         }
 189
 190         return true;
 191
 192 fallback:
 193
 194         if (count != 1)
 195                 return false;
 196
 197         i = info->level - 1;
 198         if (bus              == info->path[i].bus &&
 199             path[0].device   == info->path[i].device &&
 200             path[0].function == info->path[i].function) {
 201                 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
 202                         bus, path[0].device, path[0].function);
 203                 return true;
 204         }
 205
 206         return false;
 207 }
 208
 209 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
 210 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
 211                           void *start, void*end, u16 segment,
 212                           struct dmar_dev_scope *devices,
 213                           int devices_cnt)
 214 {
 215         int i, level;
 216         struct device *tmp, *dev = &info->dev->dev;
 217         struct acpi_dmar_device_scope *scope;
 218         struct acpi_dmar_pci_path *path;
 219
 220         if (segment != info->seg)
 221                 return 0;
 222
 223         for (; start < end; start += scope->length) {
 224                 scope = start;
 225                 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 226                     scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 227                         continue;
 228
 229                 path = (struct acpi_dmar_pci_path *)(scope + 1);
 230                 level = (scope->length - sizeof(*scope)) / sizeof(*path);
 231                 if (!dmar_match_pci_path(info, scope->bus, path, level))
 232                         continue;
 233
 234                 /*
 235                  * We expect devices with endpoint scope to have normal PCI
 236                  * headers, and devices with bridge scope to have bridge PCI
 237                  * headers.  However PCI NTB devices may be listed in the
 238                  * DMAR table with bridge scope, even though they have a
 239                  * normal PCI header.  NTB devices are identified by class
 240                  * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
 241                  * for this special case.
 242                  */
 243                 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 244                      info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
 245                     (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
 246                      (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
 247                       info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) {
 248                         pr_warn("Device scope type does not match for %s\n",
 249                                 pci_name(info->dev));
 250                         return -EINVAL;
 251                 }
 252
 253                 for_each_dev_scope(devices, devices_cnt, i, tmp)
 254                         if (tmp == NULL) {
 255                                 devices[i].bus = info->dev->bus->number;
 256                                 devices[i].devfn = info->dev->devfn;
 257                                 rcu_assign_pointer(devices[i].dev,
 258                                                    get_device(dev));
 259                                 return 1;
 260                         }
 261                 BUG_ON(i >= devices_cnt);
 262         }
 263
 264         return 0;
 265 }
 266
 267 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
 268                           struct dmar_dev_scope *devices, int count)
 269 {
 270         int index;
 271         struct device *tmp;
 272
 273         if (info->seg != segment)
 274                 return 0;
 275
 276         for_each_active_dev_scope(devices, count, index, tmp)
 277                 if (tmp == &info->dev->dev) {
 278                         RCU_INIT_POINTER(devices[index].dev, NULL);
 279                         synchronize_rcu();
 280                         put_device(tmp);
 281                         return 1;
 282                 }
 283
 284         return 0;
 285 }
 286
 287 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
 288 {
 289         int ret = 0;
 290         struct dmar_drhd_unit *dmaru;
 291         struct acpi_dmar_hardware_unit *drhd;
 292
 293         for_each_drhd_unit(dmaru) {
 294                 if (dmaru->include_all)
 295                         continue;
 296
 297                 drhd = container_of(dmaru->hdr,
 298                                     struct acpi_dmar_hardware_unit, header);
 299                 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
 300                                 ((void *)drhd) + drhd->header.length,
 301                                 dmaru->segment,
 302                                 dmaru->devices, dmaru->devices_cnt);
 303                 if (ret)
 304                         break;
 305         }
 306         if (ret >= 0)
 307                 ret = dmar_iommu_notify_scope_dev(info);
 308         if (ret < 0 && dmar_dev_scope_status == 0)
 309                 dmar_dev_scope_status = ret;
 310
 311         return ret;
 312 }
 313
 314 static void  dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
 315 {
 316         struct dmar_drhd_unit *dmaru;
 317
 318         for_each_drhd_unit(dmaru)
 319                 if (dmar_remove_dev_scope(info, dmaru->segment,
 320                         dmaru->devices, dmaru->devices_cnt))
 321                         break;
 322         dmar_iommu_notify_scope_dev(info);
 323 }
 324
 325 static int dmar_pci_bus_notifier(struct notifier_block *nb,
 326                                  unsigned long action, void *data)
 327 {
 328         struct pci_dev *pdev = to_pci_dev(data);
 329         struct dmar_pci_notify_info *info;
 330
 331         /* Only care about add/remove events for physical functions.
 332          * For VFs we actually do the lookup based on the corresponding
 333          * PF in device_to_iommu() anyway. */
 334         if (pdev->is_virtfn)
 335                 return NOTIFY_DONE;
 336         if (action != BUS_NOTIFY_ADD_DEVICE &&
 337             action != BUS_NOTIFY_REMOVED_DEVICE)
 338                 return NOTIFY_DONE;
 339
 340         info = dmar_alloc_pci_notify_info(pdev, action);
 341         if (!info)
 342                 return NOTIFY_DONE;
 343
 344         down_write(&dmar_global_lock);
 345         if (action == BUS_NOTIFY_ADD_DEVICE)
 346                 dmar_pci_bus_add_dev(info);
 347         else if (action == BUS_NOTIFY_REMOVED_DEVICE)
 348                 dmar_pci_bus_del_dev(info);
 349         up_write(&dmar_global_lock);
 350
 351         dmar_free_pci_notify_info(info);
 352
 353         return NOTIFY_OK;
 354 }
 355
 356 static struct notifier_block dmar_pci_bus_nb = {
 357         .notifier_call = dmar_pci_bus_notifier,
 358         .priority = INT_MIN,
 359 };
 360
 361 static struct dmar_drhd_unit *
 362 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
 363 {
 364         struct dmar_drhd_unit *dmaru;
 365
 366         list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list,
 367                                 dmar_rcu_check())
 368                 if (dmaru->segment == drhd->segment &&
 369                     dmaru->reg_base_addr == drhd->address)
 370                         return dmaru;
 371
 372         return NULL;
 373 }
 374
 375 /**
 376  * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
 377  * structure which uniquely represent one DMA remapping hardware unit
 378  * present in the platform
 379  */
 380 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
 381 {
 382         struct acpi_dmar_hardware_unit *drhd;
 383         struct dmar_drhd_unit *dmaru;
 384         int ret;
 385
 386         drhd = (struct acpi_dmar_hardware_unit *)header;
 387         dmaru = dmar_find_dmaru(drhd);
 388         if (dmaru)
 389                 goto out;
 390
 391         dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
 392         if (!dmaru)
 393                 return -ENOMEM;
 394
 395         /*
 396          * If header is allocated from slab by ACPI _DSM method, we need to
 397          * copy the content because the memory buffer will be freed on return.
 398          */
 399         dmaru->hdr = (void *)(dmaru + 1);
 400         memcpy(dmaru->hdr, header, header->length);
 401         dmaru->reg_base_addr = drhd->address;
 402         dmaru->segment = drhd->segment;
 403         dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
 404         dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
 405                                               ((void *)drhd) + drhd->header.length,
 406                                               &dmaru->devices_cnt);
 407         if (dmaru->devices_cnt && dmaru->devices == NULL) {
 408                 kfree(dmaru);
 409                 return -ENOMEM;
 410         }
 411
 412         ret = alloc_iommu(dmaru);
 413         if (ret) {
 414                 dmar_free_dev_scope(&dmaru->devices,
 415                                     &dmaru->devices_cnt);
 416                 kfree(dmaru);
 417                 return ret;
 418         }
 419         dmar_register_drhd_unit(dmaru);
 420
 421 out:
 422         if (arg)
 423                 (*(int *)arg)++;
 424
 425         return 0;
 426 }
 427
 428 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
 429 {
 430         if (dmaru->devices && dmaru->devices_cnt)
 431                 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
 432         if (dmaru->iommu)
 433                 free_iommu(dmaru->iommu);
 434         kfree(dmaru);
 435 }
 436
 437 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
 438                                       void *arg)
 439 {
 440         struct acpi_dmar_andd *andd = (void *)header;
 441
 442         /* Check for NUL termination within the designated length */
 443         if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
 444                 pr_warn(FW_BUG
 445                            "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
 446                            "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 447                            dmi_get_system_info(DMI_BIOS_VENDOR),
 448                            dmi_get_system_info(DMI_BIOS_VERSION),
 449                            dmi_get_system_info(DMI_PRODUCT_VERSION));
 450                 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 451                 return -EINVAL;
 452         }
 453         pr_info("ANDD device: %x name: %s\n", andd->device_number,
 454                 andd->device_name);
 455
 456         return 0;
 457 }
 458
 459 #ifdef CONFIG_ACPI_NUMA
 460 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
 461 {
 462         struct acpi_dmar_rhsa *rhsa;
 463         struct dmar_drhd_unit *drhd;
 464
 465         rhsa = (struct acpi_dmar_rhsa *)header;
 466         for_each_drhd_unit(drhd) {
 467                 if (drhd->reg_base_addr == rhsa->base_address) {
 468                         int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
 469
 470                         if (!node_online(node))
 471                                 node = NUMA_NO_NODE;
 472                         drhd->iommu->node = node;
 473                         return 0;
 474                 }
 475         }
 476         pr_warn(FW_BUG
 477                 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
 478                 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 479                 drhd->reg_base_addr,
 480                 dmi_get_system_info(DMI_BIOS_VENDOR),
 481                 dmi_get_system_info(DMI_BIOS_VERSION),
 482                 dmi_get_system_info(DMI_PRODUCT_VERSION));
 483         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 484
 485         return 0;
 486 }
 487 #else
 488 #define dmar_parse_one_rhsa             dmar_res_noop
 489 #endif
 490
 491 static void
 492 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
 493 {
 494         struct acpi_dmar_hardware_unit *drhd;
 495         struct acpi_dmar_reserved_memory *rmrr;
 496         struct acpi_dmar_atsr *atsr;
 497         struct acpi_dmar_rhsa *rhsa;
 498
 499         switch (header->type) {
 500         case ACPI_DMAR_TYPE_HARDWARE_UNIT:
 501                 drhd = container_of(header, struct acpi_dmar_hardware_unit,
 502                                     header);
 503                 pr_info("DRHD base: %#016Lx flags: %#x\n",
 504                         (unsigned long long)drhd->address, drhd->flags);
 505                 break;
 506         case ACPI_DMAR_TYPE_RESERVED_MEMORY:
 507                 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
 508                                     header);
 509                 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
 510                         (unsigned long long)rmrr->base_address,
 511                         (unsigned long long)rmrr->end_address);
 512                 break;
 513         case ACPI_DMAR_TYPE_ROOT_ATS:
 514                 atsr = container_of(header, struct acpi_dmar_atsr, header);
 515                 pr_info("ATSR flags: %#x\n", atsr->flags);
 516                 break;
 517         case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
 518                 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
 519                 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
 520                        (unsigned long long)rhsa->base_address,
 521                        rhsa->proximity_domain);
 522                 break;
 523         case ACPI_DMAR_TYPE_NAMESPACE:
 524                 /* We don't print this here because we need to sanity-check
 525                    it first. So print it in dmar_parse_one_andd() instead. */
 526                 break;
 527         }
 528 }
 529
 530 /**
 531  * dmar_table_detect - checks to see if the platform supports DMAR devices
 532  */
 533 static int __init dmar_table_detect(void)
 534 {
 535         acpi_status status = AE_OK;
 536
 537         /* if we could find DMAR table, then there are DMAR devices */
 538         status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
 539
 540         if (ACPI_SUCCESS(status) && !dmar_tbl) {
 541                 pr_warn("Unable to map DMAR\n");
 542                 status = AE_NOT_FOUND;
 543         }
 544
 545         return ACPI_SUCCESS(status) ? 0 : -ENOENT;
 546 }
 547
 548 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
 549                                        size_t len, struct dmar_res_callback *cb)
 550 {
 551         struct acpi_dmar_header *iter, *next;
 552         struct acpi_dmar_header *end = ((void *)start) + len;
 553
 554         for (iter = start; iter < end; iter = next) {
 555                 next = (void *)iter + iter->length;
 556                 if (iter->length == 0) {
 557                         /* Avoid looping forever on bad ACPI tables */
 558                         pr_debug(FW_BUG "Invalid 0-length structure\n");
 559                         break;
 560                 } else if (next > end) {
 561                         /* Avoid passing table end */
 562                         pr_warn(FW_BUG "Record passes table end\n");
 563                         return -EINVAL;
 564                 }
 565
 566                 if (cb->print_entry)
 567                         dmar_table_print_dmar_entry(iter);
 568
 569                 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
 570                         /* continue for forward compatibility */
 571                         pr_debug("Unknown DMAR structure type %d\n",
 572                                  iter->type);
 573                 } else if (cb->cb[iter->type]) {
 574                         int ret;
 575
 576                         ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
 577                         if (ret)
 578                                 return ret;
 579                 } else if (!cb->ignore_unhandled) {
 580                         pr_warn("No handler for DMAR structure type %d\n",
 581                                 iter->type);
 582                         return -EINVAL;
 583                 }
 584         }
 585
 586         return 0;
 587 }
 588
 589 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
 590                                        struct dmar_res_callback *cb)
 591 {
 592         return dmar_walk_remapping_entries((void *)(dmar + 1),
 593                         dmar->header.length - sizeof(*dmar), cb);
 594 }
 595
 596 /**
 597  * parse_dmar_table - parses the DMA reporting table
 598  */
 599 static int __init
 600 parse_dmar_table(void)
 601 {
 602         struct acpi_table_dmar *dmar;
 603         int drhd_count = 0;
 604         int ret;
 605         struct dmar_res_callback cb = {
 606                 .print_entry = true,
 607                 .ignore_unhandled = true,
 608                 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
 609                 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
 610                 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
 611                 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
 612                 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
 613                 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
 614         };
 615
 616         /*
 617          * Do it again, earlier dmar_tbl mapping could be mapped with
 618          * fixed map.
 619          */
 620         dmar_table_detect();
 621
 622         /*
 623          * ACPI tables may not be DMA protected by tboot, so use DMAR copy
 624          * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
 625          */
 626         dmar_tbl = tboot_get_dmar_table(dmar_tbl);
 627
 628         dmar = (struct acpi_table_dmar *)dmar_tbl;
 629         if (!dmar)
 630                 return -ENODEV;
 631
 632         if (dmar->width < PAGE_SHIFT - 1) {
 633                 pr_warn("Invalid DMAR haw\n");
 634                 return -EINVAL;
 635         }
 636
 637         pr_info("Host address width %d\n", dmar->width + 1);
 638         ret = dmar_walk_dmar_table(dmar, &cb);
 639         if (ret == 0 && drhd_count == 0)
 640                 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
 641
 642         return ret;
 643 }
 644
 645 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
 646                                  int cnt, struct pci_dev *dev)
 647 {
 648         int index;
 649         struct device *tmp;
 650
 651         while (dev) {
 652                 for_each_active_dev_scope(devices, cnt, index, tmp)
 653                         if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
 654                                 return 1;
 655
 656                 /* Check our parent */
 657                 dev = dev->bus->self;
 658         }
 659
 660         return 0;
 661 }
 662
 663 struct dmar_drhd_unit *
 664 dmar_find_matched_drhd_unit(struct pci_dev *dev)
 665 {
 666         struct dmar_drhd_unit *dmaru;
 667         struct acpi_dmar_hardware_unit *drhd;
 668
 669         dev = pci_physfn(dev);
 670
 671         rcu_read_lock();
 672         for_each_drhd_unit(dmaru) {
 673                 drhd = container_of(dmaru->hdr,
 674                                     struct acpi_dmar_hardware_unit,
 675                                     header);
 676
 677                 if (dmaru->include_all &&
 678                     drhd->segment == pci_domain_nr(dev->bus))
 679                         goto out;
 680
 681                 if (dmar_pci_device_match(dmaru->devices,
 682                                           dmaru->devices_cnt, dev))
 683                         goto out;
 684         }
 685         dmaru = NULL;
 686 out:
 687         rcu_read_unlock();
 688
 689         return dmaru;
 690 }
 691
 692 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
 693                                               struct acpi_device *adev)
 694 {
 695         struct dmar_drhd_unit *dmaru;
 696         struct acpi_dmar_hardware_unit *drhd;
 697         struct acpi_dmar_device_scope *scope;
 698         struct device *tmp;
 699         int i;
 700         struct acpi_dmar_pci_path *path;
 701
 702         for_each_drhd_unit(dmaru) {
 703                 drhd = container_of(dmaru->hdr,
 704                                     struct acpi_dmar_hardware_unit,
 705                                     header);
 706
 707                 for (scope = (void *)(drhd + 1);
 708                      (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
 709                      scope = ((void *)scope) + scope->length) {
 710                         if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
 711                                 continue;
 712                         if (scope->enumeration_id != device_number)
 713                                 continue;
 714
 715                         path = (void *)(scope + 1);
 716                         pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
 717                                 dev_name(&adev->dev), dmaru->reg_base_addr,
 718                                 scope->bus, path->device, path->function);
 719                         for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
 720                                 if (tmp == NULL) {
 721                                         dmaru->devices[i].bus = scope->bus;
 722                                         dmaru->devices[i].devfn = PCI_DEVFN(path->device,
 723                                                                             path->function);
 724                                         rcu_assign_pointer(dmaru->devices[i].dev,
 725                                                            get_device(&adev->dev));
 726                                         return;
 727                                 }
 728                         BUG_ON(i >= dmaru->devices_cnt);
 729                 }
 730         }
 731         pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
 732                 device_number, dev_name(&adev->dev));
 733 }
 734
 735 static int __init dmar_acpi_dev_scope_init(void)
 736 {
 737         struct acpi_dmar_andd *andd;
 738
 739         if (dmar_tbl == NULL)
 740                 return -ENODEV;
 741
 742         for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
 743              ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
 744              andd = ((void *)andd) + andd->header.length) {
 745                 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
 746                         acpi_handle h;
 747                         struct acpi_device *adev;
 748
 749                         if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
 750                                                           andd->device_name,
 751                                                           &h))) {
 752                                 pr_err("Failed to find handle for ACPI object %s\n",
 753                                        andd->device_name);
 754                                 continue;
 755                         }
 756                         if (acpi_bus_get_device(h, &adev)) {
 757                                 pr_err("Failed to get device for ACPI object %s\n",
 758                                        andd->device_name);
 759                                 continue;
 760                         }
 761                         dmar_acpi_insert_dev_scope(andd->device_number, adev);
 762                 }
 763         }
 764         return 0;
 765 }
 766
 767 int __init dmar_dev_scope_init(void)
 768 {
 769         struct pci_dev *dev = NULL;
 770         struct dmar_pci_notify_info *info;
 771
 772         if (dmar_dev_scope_status != 1)
 773                 return dmar_dev_scope_status;
 774
 775         if (list_empty(&dmar_drhd_units)) {
 776                 dmar_dev_scope_status = -ENODEV;
 777         } else {
 778                 dmar_dev_scope_status = 0;
 779
 780                 dmar_acpi_dev_scope_init();
 781
 782                 for_each_pci_dev(dev) {
 783                         if (dev->is_virtfn)
 784                                 continue;
 785
 786                         info = dmar_alloc_pci_notify_info(dev,
 787                                         BUS_NOTIFY_ADD_DEVICE);
 788                         if (!info) {
 789                                 return dmar_dev_scope_status;
 790                         } else {
 791                                 dmar_pci_bus_add_dev(info);
 792                                 dmar_free_pci_notify_info(info);
 793                         }
 794                 }
 795         }
 796
 797         return dmar_dev_scope_status;
 798 }
 799
 800 void __init dmar_register_bus_notifier(void)
 801 {
 802         bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
 803 }
 804
 805
 806 int __init dmar_table_init(void)
 807 {
 808         static int dmar_table_initialized;
 809         int ret;
 810
 811         if (dmar_table_initialized == 0) {
 812                 ret = parse_dmar_table();
 813                 if (ret < 0) {
 814                         if (ret != -ENODEV)
 815                                 pr_info("Parse DMAR table failure.\n");
 816                 } else  if (list_empty(&dmar_drhd_units)) {
 817                         pr_info("No DMAR devices found\n");
 818                         ret = -ENODEV;
 819                 }
 820
 821                 if (ret < 0)
 822                         dmar_table_initialized = ret;
 823                 else
 824                         dmar_table_initialized = 1;
 825         }
 826
 827         return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
 828 }
 829
 830 static void warn_invalid_dmar(u64 addr, const char *message)
 831 {
 832         pr_warn_once(FW_BUG
 833                 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
 834                 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 835                 addr, message,
 836                 dmi_get_system_info(DMI_BIOS_VENDOR),
 837                 dmi_get_system_info(DMI_BIOS_VERSION),
 838                 dmi_get_system_info(DMI_PRODUCT_VERSION));
 839         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 840 }
 841
 842 static int __ref
 843 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
 844 {
 845         struct acpi_dmar_hardware_unit *drhd;
 846         void __iomem *addr;
 847         u64 cap, ecap;
 848
 849         drhd = (void *)entry;
 850         if (!drhd->address) {
 851                 warn_invalid_dmar(0, "");
 852                 return -EINVAL;
 853         }
 854
 855         if (arg)
 856                 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
 857         else
 858                 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
 859         if (!addr) {
 860                 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
 861                 return -EINVAL;
 862         }
 863
 864         cap = dmar_readq(addr + DMAR_CAP_REG);
 865         ecap = dmar_readq(addr + DMAR_ECAP_REG);
 866
 867         if (arg)
 868                 iounmap(addr);
 869         else
 870                 early_iounmap(addr, VTD_PAGE_SIZE);
 871
 872         if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
 873                 warn_invalid_dmar(drhd->address, " returns all ones");
 874                 return -EINVAL;
 875         }
 876
 877         return 0;
 878 }
 879
 880 int __init detect_intel_iommu(void)
 881 {
 882         int ret;
 883         struct dmar_res_callback validate_drhd_cb = {
 884                 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
 885                 .ignore_unhandled = true,
 886         };
 887
 888         down_write(&dmar_global_lock);
 889         ret = dmar_table_detect();
 890         if (!ret)
 891                 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
 892                                            &validate_drhd_cb);
 893         if (!ret && !no_iommu && !iommu_detected && !dmar_disabled) {
 894                 iommu_detected = 1;
 895                 /* Make sure ACS will be enabled */
 896                 pci_request_acs();
 897         }
 898
 899 #ifdef CONFIG_X86
 900         if (!ret) {
 901                 x86_init.iommu.iommu_init = intel_iommu_init;
 902                 x86_platform.iommu_shutdown = intel_iommu_shutdown;
 903         }
 904
 905 #endif
 906
 907         if (dmar_tbl) {
 908                 acpi_put_table(dmar_tbl);
 909                 dmar_tbl = NULL;
 910         }
 911         up_write(&dmar_global_lock);
 912
 913         return ret ? ret : 1;
 914 }
 915
 916 static void unmap_iommu(struct intel_iommu *iommu)
 917 {
 918         iounmap(iommu->reg);
 919         release_mem_region(iommu->reg_phys, iommu->reg_size);
 920 }
 921
 922 /**
 923  * map_iommu: map the iommu's registers
 924  * @iommu: the iommu to map
 925  * @phys_addr: the physical address of the base resgister
 926  *
 927  * Memory map the iommu's registers.  Start w/ a single page, and
 928  * possibly expand if that turns out to be insufficent.
 929  */
 930 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
 931 {
 932         int map_size, err=0;
 933
 934         iommu->reg_phys = phys_addr;
 935         iommu->reg_size = VTD_PAGE_SIZE;
 936
 937         if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
 938                 pr_err("Can't reserve memory\n");
 939                 err = -EBUSY;
 940                 goto out;
 941         }
 942
 943         iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
 944         if (!iommu->reg) {
 945                 pr_err("Can't map the region\n");
 946                 err = -ENOMEM;
 947                 goto release;
 948         }
 949
 950         iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
 951         iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
 952
 953         if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
 954                 err = -EINVAL;
 955                 warn_invalid_dmar(phys_addr, " returns all ones");
 956                 goto unmap;
 957         }
 958
 959         /* the registers might be more than one page */
 960         map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
 961                          cap_max_fault_reg_offset(iommu->cap));
 962         map_size = VTD_PAGE_ALIGN(map_size);
 963         if (map_size > iommu->reg_size) {
 964                 iounmap(iommu->reg);
 965                 release_mem_region(iommu->reg_phys, iommu->reg_size);
 966                 iommu->reg_size = map_size;
 967                 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
 968                                         iommu->name)) {
 969                         pr_err("Can't reserve memory\n");
 970                         err = -EBUSY;
 971                         goto out;
 972                 }
 973                 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
 974                 if (!iommu->reg) {
 975                         pr_err("Can't map the region\n");
 976                         err = -ENOMEM;
 977                         goto release;
 978                 }
 979         }
 980         err = 0;
 981         goto out;
 982
 983 unmap:
 984         iounmap(iommu->reg);
 985 release:
 986         release_mem_region(iommu->reg_phys, iommu->reg_size);
 987 out:
 988         return err;
 989 }
 990
 991 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
 992 {
 993         iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
 994                                             DMAR_UNITS_SUPPORTED);
 995         if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
 996                 iommu->seq_id = -1;
 997         } else {
 998                 set_bit(iommu->seq_id, dmar_seq_ids);
 999                 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1000         }
1001
1002         return iommu->seq_id;
1003 }
1004
1005 static void dmar_free_seq_id(struct intel_iommu *iommu)
1006 {
1007         if (iommu->seq_id >= 0) {
1008                 clear_bit(iommu->seq_id, dmar_seq_ids);
1009                 iommu->seq_id = -1;
1010         }
1011 }
1012
1013 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1014 {
1015         struct intel_iommu *iommu;
1016         u32 ver, sts;
1017         int agaw = 0;
1018         int msagaw = 0;
1019         int err;
1020
1021         if (!drhd->reg_base_addr) {
1022                 warn_invalid_dmar(0, "");
1023                 return -EINVAL;
1024         }
1025
1026         iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1027         if (!iommu)
1028                 return -ENOMEM;
1029
1030         if (dmar_alloc_seq_id(iommu) < 0) {
1031                 pr_err("Failed to allocate seq_id\n");
1032                 err = -ENOSPC;
1033                 goto error;
1034         }
1035
1036         err = map_iommu(iommu, drhd->reg_base_addr);
1037         if (err) {
1038                 pr_err("Failed to map %s\n", iommu->name);
1039                 goto error_free_seq_id;
1040         }
1041
1042         err = -EINVAL;
1043         agaw = iommu_calculate_agaw(iommu);
1044         if (agaw < 0) {
1045                 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1046                         iommu->seq_id);
1047                 goto err_unmap;
1048         }
1049         msagaw = iommu_calculate_max_sagaw(iommu);
1050         if (msagaw < 0) {
1051                 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1052                         iommu->seq_id);
1053                 goto err_unmap;
1054         }
1055         iommu->agaw = agaw;
1056         iommu->msagaw = msagaw;
1057         iommu->segment = drhd->segment;
1058
1059         iommu->node = NUMA_NO_NODE;
1060
1061         ver = readl(iommu->reg + DMAR_VER_REG);
1062         pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1063                 iommu->name,
1064                 (unsigned long long)drhd->reg_base_addr,
1065                 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1066                 (unsigned long long)iommu->cap,
1067                 (unsigned long long)iommu->ecap);
1068
1069         /* Reflect status in gcmd */
1070         sts = readl(iommu->reg + DMAR_GSTS_REG);
1071         if (sts & DMA_GSTS_IRES)
1072                 iommu->gcmd |= DMA_GCMD_IRE;
1073         if (sts & DMA_GSTS_TES)
1074                 iommu->gcmd |= DMA_GCMD_TE;
1075         if (sts & DMA_GSTS_QIES)
1076                 iommu->gcmd |= DMA_GCMD_QIE;
1077
1078         raw_spin_lock_init(&iommu->register_lock);
1079
1080         if (intel_iommu_enabled) {
1081                 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1082                                              intel_iommu_groups,
1083                                              "%s", iommu->name);
1084                 if (err)
1085                         goto err_unmap;
1086
1087                 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
1088
1089                 err = iommu_device_register(&iommu->iommu);
1090                 if (err)
1091                         goto err_unmap;
1092         }
1093
1094         drhd->iommu = iommu;
1095
1096         return 0;
1097
1098 err_unmap:
1099         unmap_iommu(iommu);
1100 error_free_seq_id:
1101         dmar_free_seq_id(iommu);
1102 error:
1103         kfree(iommu);
1104         return err;
1105 }
1106
1107 static void free_iommu(struct intel_iommu *iommu)
1108 {
1109         if (intel_iommu_enabled) {
1110                 iommu_device_unregister(&iommu->iommu);
1111                 iommu_device_sysfs_remove(&iommu->iommu);
1112         }
1113
1114         if (iommu->irq) {
1115                 if (iommu->pr_irq) {
1116                         free_irq(iommu->pr_irq, iommu);
1117                         dmar_free_hwirq(iommu->pr_irq);
1118                         iommu->pr_irq = 0;
1119                 }
1120                 free_irq(iommu->irq, iommu);
1121                 dmar_free_hwirq(iommu->irq);
1122                 iommu->irq = 0;
1123         }
1124
1125         if (iommu->qi) {
1126                 free_page((unsigned long)iommu->qi->desc);
1127                 kfree(iommu->qi->desc_status);
1128                 kfree(iommu->qi);
1129         }
1130
1131         if (iommu->reg)
1132                 unmap_iommu(iommu);
1133
1134         dmar_free_seq_id(iommu);
1135         kfree(iommu);
1136 }
1137
1138 /*
1139  * Reclaim all the submitted descriptors which have completed its work.
1140  */
1141 static inline void reclaim_free_desc(struct q_inval *qi)
1142 {
1143         while (qi->desc_status[qi->free_tail] == QI_DONE ||
1144                qi->desc_status[qi->free_tail] == QI_ABORT) {
1145                 qi->desc_status[qi->free_tail] = QI_FREE;
1146                 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1147                 qi->free_cnt++;
1148         }
1149 }
1150
1151 static int qi_check_fault(struct intel_iommu *iommu, int index)
1152 {
1153         u32 fault;
1154         int head, tail;
1155         struct q_inval *qi = iommu->qi;
1156         int wait_index = (index + 1) % QI_LENGTH;
1157         int shift = qi_shift(iommu);
1158
1159         if (qi->desc_status[wait_index] == QI_ABORT)
1160                 return -EAGAIN;
1161
1162         fault = readl(iommu->reg + DMAR_FSTS_REG);
1163
1164         /*
1165          * If IQE happens, the head points to the descriptor associated
1166          * with the error. No new descriptors are fetched until the IQE
1167          * is cleared.
1168          */
1169         if (fault & DMA_FSTS_IQE) {
1170                 head = readl(iommu->reg + DMAR_IQH_REG);
1171                 if ((head >> shift) == index) {
1172                         struct qi_desc *desc = qi->desc + head;
1173
1174                         /*
1175                          * desc->qw2 and desc->qw3 are either reserved or
1176                          * used by software as private data. We won't print
1177                          * out these two qw's for security consideration.
1178                          */
1179                         pr_err("VT-d detected invalid descriptor: qw0 = %llx, qw1 = %llx\n",
1180                                (unsigned long long)desc->qw0,
1181                                (unsigned long long)desc->qw1);
1182                         memcpy(desc, qi->desc + (wait_index << shift),
1183                                1 << shift);
1184                         writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1185                         return -EINVAL;
1186                 }
1187         }
1188
1189         /*
1190          * If ITE happens, all pending wait_desc commands are aborted.
1191          * No new descriptors are fetched until the ITE is cleared.
1192          */
1193         if (fault & DMA_FSTS_ITE) {
1194                 head = readl(iommu->reg + DMAR_IQH_REG);
1195                 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1196                 head |= 1;
1197                 tail = readl(iommu->reg + DMAR_IQT_REG);
1198                 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1199
1200                 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1201
1202                 do {
1203                         if (qi->desc_status[head] == QI_IN_USE)
1204                                 qi->desc_status[head] = QI_ABORT;
1205                         head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1206                 } while (head != tail);
1207
1208                 if (qi->desc_status[wait_index] == QI_ABORT)
1209                         return -EAGAIN;
1210         }
1211
1212         if (fault & DMA_FSTS_ICE)
1213                 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1214
1215         return 0;
1216 }
1217
1218 /*
1219  * Submit the queued invalidation descriptor to the remapping
1220  * hardware unit and wait for its completion.
1221  */
1222 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
1223 {
1224         int rc;
1225         struct q_inval *qi = iommu->qi;
1226         int offset, shift, length;
1227         struct qi_desc wait_desc;
1228         int wait_index, index;
1229         unsigned long flags;
1230
1231         if (!qi)
1232                 return 0;
1233
1234 restart:
1235         rc = 0;
1236
1237         raw_spin_lock_irqsave(&qi->q_lock, flags);
1238         while (qi->free_cnt < 3) {
1239                 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1240                 cpu_relax();
1241                 raw_spin_lock_irqsave(&qi->q_lock, flags);
1242         }
1243
1244         index = qi->free_head;
1245         wait_index = (index + 1) % QI_LENGTH;
1246         shift = qi_shift(iommu);
1247         length = 1 << shift;
1248
1249         qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1250
1251         offset = index << shift;
1252         memcpy(qi->desc + offset, desc, length);
1253         wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
1254                         QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1255         wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]);
1256         wait_desc.qw2 = 0;
1257         wait_desc.qw3 = 0;
1258
1259         offset = wait_index << shift;
1260         memcpy(qi->desc + offset, &wait_desc, length);
1261
1262         qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1263         qi->free_cnt -= 2;
1264
1265         /*
1266          * update the HW tail register indicating the presence of
1267          * new descriptors.
1268          */
1269         writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);
1270
1271         while (qi->desc_status[wait_index] != QI_DONE) {
1272                 /*
1273                  * We will leave the interrupts disabled, to prevent interrupt
1274                  * context to queue another cmd while a cmd is already submitted
1275                  * and waiting for completion on this cpu. This is to avoid
1276                  * a deadlock where the interrupt context can wait indefinitely
1277                  * for free slots in the queue.
1278                  */
1279                 rc = qi_check_fault(iommu, index);
1280                 if (rc)
1281                         break;
1282
1283                 raw_spin_unlock(&qi->q_lock);
1284                 cpu_relax();
1285                 raw_spin_lock(&qi->q_lock);
1286         }
1287
1288         qi->desc_status[index] = QI_DONE;
1289
1290         reclaim_free_desc(qi);
1291         raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1292
1293         if (rc == -EAGAIN)
1294                 goto restart;
1295
1296         return rc;
1297 }
1298
1299 /*
1300  * Flush the global interrupt entry cache.
1301  */
1302 void qi_global_iec(struct intel_iommu *iommu)
1303 {
1304         struct qi_desc desc;
1305
1306         desc.qw0 = QI_IEC_TYPE;
1307         desc.qw1 = 0;
1308         desc.qw2 = 0;
1309         desc.qw3 = 0;
1310
1311         /* should never fail */
1312         qi_submit_sync(&desc, iommu);
1313 }
1314
1315 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1316                       u64 type)
1317 {
1318         struct qi_desc desc;
1319
1320         desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1321                         | QI_CC_GRAN(type) | QI_CC_TYPE;
1322         desc.qw1 = 0;
1323         desc.qw2 = 0;
1324         desc.qw3 = 0;
1325
1326         qi_submit_sync(&desc, iommu);
1327 }
1328
1329 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1330                     unsigned int size_order, u64 type)
1331 {
1332         u8 dw = 0, dr = 0;
1333
1334         struct qi_desc desc;
1335         int ih = 0;
1336
1337         if (cap_write_drain(iommu->cap))
1338                 dw = 1;
1339
1340         if (cap_read_drain(iommu->cap))
1341                 dr = 1;
1342
1343         desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1344                 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1345         desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1346                 | QI_IOTLB_AM(size_order);
1347         desc.qw2 = 0;
1348         desc.qw3 = 0;
1349
1350         qi_submit_sync(&desc, iommu);
1351 }
1352
1353 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1354                         u16 qdep, u64 addr, unsigned mask)
1355 {
1356         struct qi_desc desc;
1357
1358         if (mask) {
1359                 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1360                 desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1361         } else
1362                 desc.qw1 = QI_DEV_IOTLB_ADDR(addr);
1363
1364         if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1365                 qdep = 0;
1366
1367         desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1368                    QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1369         desc.qw2 = 0;
1370         desc.qw3 = 0;
1371
1372         qi_submit_sync(&desc, iommu);
1373 }
1374
1375 /* PASID-based IOTLB invalidation */
1376 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
1377                      unsigned long npages, bool ih)
1378 {
1379         struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
1380
1381         /*
1382          * npages == -1 means a PASID-selective invalidation, otherwise,
1383          * a positive value for Page-selective-within-PASID invalidation.
1384          * 0 is not a valid input.
1385          */
1386         if (WARN_ON(!npages)) {
1387                 pr_err("Invalid input npages = %ld\n", npages);
1388                 return;
1389         }
1390
1391         if (npages == -1) {
1392                 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1393                                 QI_EIOTLB_DID(did) |
1394                                 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
1395                                 QI_EIOTLB_TYPE;
1396                 desc.qw1 = 0;
1397         } else {
1398                 int mask = ilog2(__roundup_pow_of_two(npages));
1399                 unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
1400
1401                 if (WARN_ON_ONCE(!ALIGN(addr, align)))
1402                         addr &= ~(align - 1);
1403
1404                 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1405                                 QI_EIOTLB_DID(did) |
1406                                 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
1407                                 QI_EIOTLB_TYPE;
1408                 desc.qw1 = QI_EIOTLB_ADDR(addr) |
1409                                 QI_EIOTLB_IH(ih) |
1410                                 QI_EIOTLB_AM(mask);
1411         }
1412
1413         qi_submit_sync(&desc, iommu);
1414 }
1415
1416 /*
1417  * Disable Queued Invalidation interface.
1418  */
1419 void dmar_disable_qi(struct intel_iommu *iommu)
1420 {
1421         unsigned long flags;
1422         u32 sts;
1423         cycles_t start_time = get_cycles();
1424
1425         if (!ecap_qis(iommu->ecap))
1426                 return;
1427
1428         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1429
1430         sts =  readl(iommu->reg + DMAR_GSTS_REG);
1431         if (!(sts & DMA_GSTS_QIES))
1432                 goto end;
1433
1434         /*
1435          * Give a chance to HW to complete the pending invalidation requests.
1436          */
1437         while ((readl(iommu->reg + DMAR_IQT_REG) !=
1438                 readl(iommu->reg + DMAR_IQH_REG)) &&
1439                 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1440                 cpu_relax();
1441
1442         iommu->gcmd &= ~DMA_GCMD_QIE;
1443         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1444
1445         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1446                       !(sts & DMA_GSTS_QIES), sts);
1447 end:
1448         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1449 }
1450
1451 /*
1452  * Enable queued invalidation.
1453  */
1454 static void __dmar_enable_qi(struct intel_iommu *iommu)
1455 {
1456         u32 sts;
1457         unsigned long flags;
1458         struct q_inval *qi = iommu->qi;
1459         u64 val = virt_to_phys(qi->desc);
1460
1461         qi->free_head = qi->free_tail = 0;
1462         qi->free_cnt = QI_LENGTH;
1463
1464         /*
1465          * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability
1466          * is present.
1467          */
1468         if (ecap_smts(iommu->ecap))
1469                 val |= (1 << 11) | 1;
1470
1471         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1472
1473         /* write zero to the tail reg */
1474         writel(0, iommu->reg + DMAR_IQT_REG);
1475
1476         dmar_writeq(iommu->reg + DMAR_IQA_REG, val);
1477
1478         iommu->gcmd |= DMA_GCMD_QIE;
1479         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1480
1481         /* Make sure hardware complete it */
1482         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1483
1484         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1485 }
1486
1487 /*
1488  * Enable Queued Invalidation interface. This is a must to support
1489  * interrupt-remapping. Also used by DMA-remapping, which replaces
1490  * register based IOTLB invalidation.
1491  */
1492 int dmar_enable_qi(struct intel_iommu *iommu)
1493 {
1494         struct q_inval *qi;
1495         struct page *desc_page;
1496
1497         if (!ecap_qis(iommu->ecap))
1498                 return -ENOENT;
1499
1500         /*
1501          * queued invalidation is already setup and enabled.
1502          */
1503         if (iommu->qi)
1504                 return 0;
1505
1506         iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1507         if (!iommu->qi)
1508                 return -ENOMEM;
1509
1510         qi = iommu->qi;
1511
1512         /*
1513          * Need two pages to accommodate 256 descriptors of 256 bits each
1514          * if the remapping hardware supports scalable mode translation.
1515          */
1516         desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
1517                                      !!ecap_smts(iommu->ecap));
1518         if (!desc_page) {
1519                 kfree(qi);
1520                 iommu->qi = NULL;
1521                 return -ENOMEM;
1522         }
1523
1524         qi->desc = page_address(desc_page);
1525
1526         qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC);
1527         if (!qi->desc_status) {
1528                 free_page((unsigned long) qi->desc);
1529                 kfree(qi);
1530                 iommu->qi = NULL;
1531                 return -ENOMEM;
1532         }
1533
1534         raw_spin_lock_init(&qi->q_lock);
1535
1536         __dmar_enable_qi(iommu);
1537
1538         return 0;
1539 }
1540
1541 /* iommu interrupt handling. Most stuff are MSI-like. */
1542
1543 enum faulttype {
1544         DMA_REMAP,
1545         INTR_REMAP,
1546         UNKNOWN,
1547 };
1548
1549 static const char *dma_remap_fault_reasons[] =
1550 {
1551         "Software",
1552         "Present bit in root entry is clear",
1553         "Present bit in context entry is clear",
1554         "Invalid context entry",
1555         "Access beyond MGAW",
1556         "PTE Write access is not set",
1557         "PTE Read access is not set",
1558         "Next page table ptr is invalid",
1559         "Root table address invalid",
1560         "Context table ptr is invalid",
1561         "non-zero reserved fields in RTP",
1562         "non-zero reserved fields in CTP",
1563         "non-zero reserved fields in PTE",
1564         "PCE for translation request specifies blocking",
1565 };
1566
1567 static const char * const dma_remap_sm_fault_reasons[] = {
1568         "SM: Invalid Root Table Address",
1569         "SM: TTM 0 for request with PASID",
1570         "SM: TTM 0 for page group request",
1571         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1572         "SM: Error attempting to access Root Entry",
1573         "SM: Present bit in Root Entry is clear",
1574         "SM: Non-zero reserved field set in Root Entry",
1575         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1576         "SM: Error attempting to access Context Entry",
1577         "SM: Present bit in Context Entry is clear",
1578         "SM: Non-zero reserved field set in the Context Entry",
1579         "SM: Invalid Context Entry",
1580         "SM: DTE field in Context Entry is clear",
1581         "SM: PASID Enable field in Context Entry is clear",
1582         "SM: PASID is larger than the max in Context Entry",
1583         "SM: PRE field in Context-Entry is clear",
1584         "SM: RID_PASID field error in Context-Entry",
1585         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1586         "SM: Error attempting to access the PASID Directory Entry",
1587         "SM: Present bit in Directory Entry is clear",
1588         "SM: Non-zero reserved field set in PASID Directory Entry",
1589         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1590         "SM: Error attempting to access PASID Table Entry",
1591         "SM: Present bit in PASID Table Entry is clear",
1592         "SM: Non-zero reserved field set in PASID Table Entry",
1593         "SM: Invalid Scalable-Mode PASID Table Entry",
1594         "SM: ERE field is clear in PASID Table Entry",
1595         "SM: SRE field is clear in PASID Table Entry",
1596         "Unknown", "Unknown",/* 0x5E-0x5F */
1597         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */
1598         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */
1599         "SM: Error attempting to access first-level paging entry",
1600         "SM: Present bit in first-level paging entry is clear",
1601         "SM: Non-zero reserved field set in first-level paging entry",
1602         "SM: Error attempting to access FL-PML4 entry",
1603         "SM: First-level entry address beyond MGAW in Nested translation",
1604         "SM: Read permission error in FL-PML4 entry in Nested translation",
1605         "SM: Read permission error in first-level paging entry in Nested translation",
1606         "SM: Write permission error in first-level paging entry in Nested translation",
1607         "SM: Error attempting to access second-level paging entry",
1608         "SM: Read/Write permission error in second-level paging entry",
1609         "SM: Non-zero reserved field set in second-level paging entry",
1610         "SM: Invalid second-level page table pointer",
1611         "SM: A/D bit update needed in second-level entry when set up in no snoop",
1612         "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1613         "SM: Address in first-level translation is not canonical",
1614         "SM: U/S set 0 for first-level translation with user privilege",
1615         "SM: No execute permission for request with PASID and ER=1",
1616         "SM: Address beyond the DMA hardware max",
1617         "SM: Second-level entry address beyond the max",
1618         "SM: No write permission for Write/AtomicOp request",
1619         "SM: No read permission for Read/AtomicOp request",
1620         "SM: Invalid address-interrupt address",
1621         "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */
1622         "SM: A/D bit update needed in first-level entry when set up in no snoop",
1623 };
1624
1625 static const char *irq_remap_fault_reasons[] =
1626 {
1627         "Detected reserved fields in the decoded interrupt-remapped request",
1628         "Interrupt index exceeded the interrupt-remapping table size",
1629         "Present field in the IRTE entry is clear",
1630         "Error accessing interrupt-remapping table pointed by IRTA_REG",
1631         "Detected reserved fields in the IRTE entry",
1632         "Blocked a compatibility format interrupt request",
1633         "Blocked an interrupt request due to source-id verification failure",
1634 };
1635
1636 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1637 {
1638         if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1639                                         ARRAY_SIZE(irq_remap_fault_reasons))) {
1640                 *fault_type = INTR_REMAP;
1641                 return irq_remap_fault_reasons[fault_reason - 0x20];
1642         } else if (fault_reason >= 0x30 && (fault_reason - 0x30 <
1643                         ARRAY_SIZE(dma_remap_sm_fault_reasons))) {
1644                 *fault_type = DMA_REMAP;
1645                 return dma_remap_sm_fault_reasons[fault_reason - 0x30];
1646         } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1647                 *fault_type = DMA_REMAP;
1648                 return dma_remap_fault_reasons[fault_reason];
1649         } else {
1650                 *fault_type = UNKNOWN;
1651                 return "Unknown";
1652         }
1653 }
1654
1655
1656 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1657 {
1658         if (iommu->irq == irq)
1659                 return DMAR_FECTL_REG;
1660         else if (iommu->pr_irq == irq)
1661                 return DMAR_PECTL_REG;
1662         else
1663                 BUG();
1664 }
1665
1666 void dmar_msi_unmask(struct irq_data *data)
1667 {
1668         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1669         int reg = dmar_msi_reg(iommu, data->irq);
1670         unsigned long flag;
1671
1672         /* unmask it */
1673         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1674         writel(0, iommu->reg + reg);
1675         /* Read a reg to force flush the post write */
1676         readl(iommu->reg + reg);
1677         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1678 }
1679
1680 void dmar_msi_mask(struct irq_data *data)
1681 {
1682         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1683         int reg = dmar_msi_reg(iommu, data->irq);
1684         unsigned long flag;
1685
1686         /* mask it */
1687         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1688         writel(DMA_FECTL_IM, iommu->reg + reg);
1689         /* Read a reg to force flush the post write */
1690         readl(iommu->reg + reg);
1691         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1692 }
1693
1694 void dmar_msi_write(int irq, struct msi_msg *msg)
1695 {
1696         struct intel_iommu *iommu = irq_get_handler_data(irq);
1697         int reg = dmar_msi_reg(iommu, irq);
1698         unsigned long flag;
1699
1700         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1701         writel(msg->data, iommu->reg + reg + 4);
1702         writel(msg->address_lo, iommu->reg + reg + 8);
1703         writel(msg->address_hi, iommu->reg + reg + 12);
1704         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1705 }
1706
1707 void dmar_msi_read(int irq, struct msi_msg *msg)
1708 {
1709         struct intel_iommu *iommu = irq_get_handler_data(irq);
1710         int reg = dmar_msi_reg(iommu, irq);
1711         unsigned long flag;
1712
1713         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1714         msg->data = readl(iommu->reg + reg + 4);
1715         msg->address_lo = readl(iommu->reg + reg + 8);
1716         msg->address_hi = readl(iommu->reg + reg + 12);
1717         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1718 }
1719
1720 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1721                 u8 fault_reason, int pasid, u16 source_id,
1722                 unsigned long long addr)
1723 {
1724         const char *reason;
1725         int fault_type;
1726
1727         reason = dmar_get_fault_reason(fault_reason, &fault_type);
1728
1729         if (fault_type == INTR_REMAP)
1730                 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n",
1731                         source_id >> 8, PCI_SLOT(source_id & 0xFF),
1732                         PCI_FUNC(source_id & 0xFF), addr >> 48,
1733                         fault_reason, reason);
1734         else
1735                 pr_err("[%s] Request device [%02x:%02x.%d] PASID %x fault addr %llx [fault reason %02d] %s\n",
1736                        type ? "DMA Read" : "DMA Write",
1737                        source_id >> 8, PCI_SLOT(source_id & 0xFF),
1738                        PCI_FUNC(source_id & 0xFF), pasid, addr,
1739                        fault_reason, reason);
1740         return 0;
1741 }
1742
1743 #define PRIMARY_FAULT_REG_LEN (16)
1744 irqreturn_t dmar_fault(int irq, void *dev_id)
1745 {
1746         struct intel_iommu *iommu = dev_id;
1747         int reg, fault_index;
1748         u32 fault_status;
1749         unsigned long flag;
1750         static DEFINE_RATELIMIT_STATE(rs,
1751                                       DEFAULT_RATELIMIT_INTERVAL,
1752                                       DEFAULT_RATELIMIT_BURST);
1753
1754         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1755         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1756         if (fault_status && __ratelimit(&rs))
1757                 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1758
1759         /* TBD: ignore advanced fault log currently */
1760         if (!(fault_status & DMA_FSTS_PPF))
1761                 goto unlock_exit;
1762
1763         fault_index = dma_fsts_fault_record_index(fault_status);
1764         reg = cap_fault_reg_offset(iommu->cap);
1765         while (1) {
1766                 /* Disable printing, simply clear the fault when ratelimited */
1767                 bool ratelimited = !__ratelimit(&rs);
1768                 u8 fault_reason;
1769                 u16 source_id;
1770                 u64 guest_addr;
1771                 int type, pasid;
1772                 u32 data;
1773                 bool pasid_present;
1774
1775                 /* highest 32 bits */
1776                 data = readl(iommu->reg + reg +
1777                                 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1778                 if (!(data & DMA_FRCD_F))
1779                         break;
1780
1781                 if (!ratelimited) {
1782                         fault_reason = dma_frcd_fault_reason(data);
1783                         type = dma_frcd_type(data);
1784
1785                         pasid = dma_frcd_pasid_value(data);
1786                         data = readl(iommu->reg + reg +
1787                                      fault_index * PRIMARY_FAULT_REG_LEN + 8);
1788                         source_id = dma_frcd_source_id(data);
1789
1790                         pasid_present = dma_frcd_pasid_present(data);
1791                         guest_addr = dmar_readq(iommu->reg + reg +
1792                                         fault_index * PRIMARY_FAULT_REG_LEN);
1793                         guest_addr = dma_frcd_page_addr(guest_addr);
1794                 }
1795
1796                 /* clear the fault */
1797                 writel(DMA_FRCD_F, iommu->reg + reg +
1798                         fault_index * PRIMARY_FAULT_REG_LEN + 12);
1799
1800                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1801
1802                 if (!ratelimited)
1803                         /* Using pasid -1 if pasid is not present */
1804                         dmar_fault_do_one(iommu, type, fault_reason,
1805                                           pasid_present ? pasid : -1,
1806                                           source_id, guest_addr);
1807
1808                 fault_index++;
1809                 if (fault_index >= cap_num_fault_regs(iommu->cap))
1810                         fault_index = 0;
1811                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1812         }
1813
1814         writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO,
1815                iommu->reg + DMAR_FSTS_REG);
1816
1817 unlock_exit:
1818         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1819         return IRQ_HANDLED;
1820 }
1821
1822 int dmar_set_interrupt(struct intel_iommu *iommu)
1823 {
1824         int irq, ret;
1825
1826         /*
1827          * Check if the fault interrupt is already initialized.
1828          */
1829         if (iommu->irq)
1830                 return 0;
1831
1832         irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
1833         if (irq > 0) {
1834                 iommu->irq = irq;
1835         } else {
1836                 pr_err("No free IRQ vectors\n");
1837                 return -EINVAL;
1838         }
1839
1840         ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
1841         if (ret)
1842                 pr_err("Can't request irq\n");
1843         return ret;
1844 }
1845
1846 int __init enable_drhd_fault_handling(void)
1847 {
1848         struct dmar_drhd_unit *drhd;
1849         struct intel_iommu *iommu;
1850
1851         /*
1852          * Enable fault control interrupt.
1853          */
1854         for_each_iommu(iommu, drhd) {
1855                 u32 fault_status;
1856                 int ret = dmar_set_interrupt(iommu);
1857
1858                 if (ret) {
1859                         pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
1860                                (unsigned long long)drhd->reg_base_addr, ret);
1861                         return -1;
1862                 }
1863
1864                 /*
1865                  * Clear any previous faults.
1866                  */
1867                 dmar_fault(iommu->irq, iommu);
1868                 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1869                 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1870         }
1871
1872         return 0;
1873 }
1874
1875 /*
1876  * Re-enable Queued Invalidation interface.
1877  */
1878 int dmar_reenable_qi(struct intel_iommu *iommu)
1879 {
1880         if (!ecap_qis(iommu->ecap))
1881                 return -ENOENT;
1882
1883         if (!iommu->qi)
1884                 return -ENOENT;
1885
1886         /*
1887          * First disable queued invalidation.
1888          */
1889         dmar_disable_qi(iommu);
1890         /*
1891          * Then enable queued invalidation again. Since there is no pending
1892          * invalidation requests now, it's safe to re-enable queued
1893          * invalidation.
1894          */
1895         __dmar_enable_qi(iommu);
1896
1897         return 0;
1898 }
1899
1900 /*
1901  * Check interrupt remapping support in DMAR table description.
1902  */
1903 int __init dmar_ir_support(void)
1904 {
1905         struct acpi_table_dmar *dmar;
1906         dmar = (struct acpi_table_dmar *)dmar_tbl;
1907         if (!dmar)
1908                 return 0;
1909         return dmar->flags & 0x1;
1910 }
1911
1912 /* Check whether DMAR units are in use */
1913 static inline bool dmar_in_use(void)
1914 {
1915         return irq_remapping_enabled || intel_iommu_enabled;
1916 }
1917
1918 static int __init dmar_free_unused_resources(void)
1919 {
1920         struct dmar_drhd_unit *dmaru, *dmaru_n;
1921
1922         if (dmar_in_use())
1923                 return 0;
1924
1925         if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1926                 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
1927
1928         down_write(&dmar_global_lock);
1929         list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1930                 list_del(&dmaru->list);
1931                 dmar_free_drhd(dmaru);
1932         }
1933         up_write(&dmar_global_lock);
1934
1935         return 0;
1936 }
1937
1938 late_initcall(dmar_free_unused_resources);
1939 IOMMU_INIT_POST(detect_intel_iommu);
1940
1941 /*
1942  * DMAR Hotplug Support
1943  * For more details, please refer to Intel(R) Virtualization Technology
1944  * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
1945  * "Remapping Hardware Unit Hot Plug".
1946  */
1947 static guid_t dmar_hp_guid =
1948         GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B,
1949                   0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF);
1950
1951 /*
1952  * Currently there's only one revision and BIOS will not check the revision id,
1953  * so use 0 for safety.
1954  */
1955 #define DMAR_DSM_REV_ID                 0
1956 #define DMAR_DSM_FUNC_DRHD              1
1957 #define DMAR_DSM_FUNC_ATSR              2
1958 #define DMAR_DSM_FUNC_RHSA              3
1959
1960 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
1961 {
1962         return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func);
1963 }
1964
1965 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
1966                                   dmar_res_handler_t handler, void *arg)
1967 {
1968         int ret = -ENODEV;
1969         union acpi_object *obj;
1970         struct acpi_dmar_header *start;
1971         struct dmar_res_callback callback;
1972         static int res_type[] = {
1973                 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
1974                 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
1975                 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
1976         };
1977
1978         if (!dmar_detect_dsm(handle, func))
1979                 return 0;
1980
1981         obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID,
1982                                       func, NULL, ACPI_TYPE_BUFFER);
1983         if (!obj)
1984                 return -ENODEV;
1985
1986         memset(&callback, 0, sizeof(callback));
1987         callback.cb[res_type[func]] = handler;
1988         callback.arg[res_type[func]] = arg;
1989         start = (struct acpi_dmar_header *)obj->buffer.pointer;
1990         ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
1991
1992         ACPI_FREE(obj);
1993
1994         return ret;
1995 }
1996
1997 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
1998 {
1999         int ret;
2000         struct dmar_drhd_unit *dmaru;
2001
2002         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2003         if (!dmaru)
2004                 return -ENODEV;
2005
2006         ret = dmar_ir_hotplug(dmaru, true);
2007         if (ret == 0)
2008                 ret = dmar_iommu_hotplug(dmaru, true);
2009
2010         return ret;
2011 }
2012
2013 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
2014 {
2015         int i, ret;
2016         struct device *dev;
2017         struct dmar_drhd_unit *dmaru;
2018
2019         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2020         if (!dmaru)
2021                 return 0;
2022
2023         /*
2024          * All PCI devices managed by this unit should have been destroyed.
2025          */
2026         if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
2027                 for_each_active_dev_scope(dmaru->devices,
2028                                           dmaru->devices_cnt, i, dev)
2029                         return -EBUSY;
2030         }
2031
2032         ret = dmar_ir_hotplug(dmaru, false);
2033         if (ret == 0)
2034                 ret = dmar_iommu_hotplug(dmaru, false);
2035
2036         return ret;
2037 }
2038
2039 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
2040 {
2041         struct dmar_drhd_unit *dmaru;
2042
2043         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2044         if (dmaru) {
2045                 list_del_rcu(&dmaru->list);
2046                 synchronize_rcu();
2047                 dmar_free_drhd(dmaru);
2048         }
2049
2050         return 0;
2051 }
2052
2053 static int dmar_hotplug_insert(acpi_handle handle)
2054 {
2055         int ret;
2056         int drhd_count = 0;
2057
2058         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2059                                      &dmar_validate_one_drhd, (void *)1);
2060         if (ret)
2061                 goto out;
2062
2063         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2064                                      &dmar_parse_one_drhd, (void *)&drhd_count);
2065         if (ret == 0 && drhd_count == 0) {
2066                 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
2067                 goto out;
2068         } else if (ret) {
2069                 goto release_drhd;
2070         }
2071
2072         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
2073                                      &dmar_parse_one_rhsa, NULL);
2074         if (ret)
2075                 goto release_drhd;
2076
2077         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2078                                      &dmar_parse_one_atsr, NULL);
2079         if (ret)
2080                 goto release_atsr;
2081
2082         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2083                                      &dmar_hp_add_drhd, NULL);
2084         if (!ret)
2085                 return 0;
2086
2087         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2088                                &dmar_hp_remove_drhd, NULL);
2089 release_atsr:
2090         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2091                                &dmar_release_one_atsr, NULL);
2092 release_drhd:
2093         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2094                                &dmar_hp_release_drhd, NULL);
2095 out:
2096         return ret;
2097 }
2098
2099 static int dmar_hotplug_remove(acpi_handle handle)
2100 {
2101         int ret;
2102
2103         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2104                                      &dmar_check_one_atsr, NULL);
2105         if (ret)
2106                 return ret;
2107
2108         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2109                                      &dmar_hp_remove_drhd, NULL);
2110         if (ret == 0) {
2111                 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2112                                                &dmar_release_one_atsr, NULL));
2113                 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2114                                                &dmar_hp_release_drhd, NULL));
2115         } else {
2116                 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2117                                        &dmar_hp_add_drhd, NULL);
2118         }
2119
2120         return ret;
2121 }
2122
2123 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
2124                                        void *context, void **retval)
2125 {
2126         acpi_handle *phdl = retval;
2127
2128         if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2129                 *phdl = handle;
2130                 return AE_CTRL_TERMINATE;
2131         }
2132
2133         return AE_OK;
2134 }
2135
2136 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2137 {
2138         int ret;
2139         acpi_handle tmp = NULL;
2140         acpi_status status;
2141
2142         if (!dmar_in_use())
2143                 return 0;
2144
2145         if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2146                 tmp = handle;
2147         } else {
2148                 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2149                                              ACPI_UINT32_MAX,
2150                                              dmar_get_dsm_handle,
2151                                              NULL, NULL, &tmp);
2152                 if (ACPI_FAILURE(status)) {
2153                         pr_warn("Failed to locate _DSM method.\n");
2154                         return -ENXIO;
2155                 }
2156         }
2157         if (tmp == NULL)
2158                 return 0;
2159
2160         down_write(&dmar_global_lock);
2161         if (insert)
2162                 ret = dmar_hotplug_insert(tmp);
2163         else
2164                 ret = dmar_hotplug_remove(tmp);
2165         up_write(&dmar_global_lock);
2166
2167         return ret;
2168 }
2169
2170 int dmar_device_add(acpi_handle handle)
2171 {
2172         return dmar_device_hotplug(handle, true);
2173 }
2174
2175 int dmar_device_remove(acpi_handle handle)
2176 {
2177         return dmar_device_hotplug(handle, false);
2178 }
2179
2180 /*
2181  * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2182  *
2183  * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in
2184  * the ACPI DMAR table. This means that the platform boot firmware has made
2185  * sure no device can issue DMA outside of RMRR regions.
2186  */
2187 bool dmar_platform_optin(void)
2188 {
2189         struct acpi_table_dmar *dmar;
2190         acpi_status status;
2191         bool ret;
2192
2193         status = acpi_get_table(ACPI_SIG_DMAR, 0,
2194                                 (struct acpi_table_header **)&dmar);
2195         if (ACPI_FAILURE(status))
2196                 return false;
2197
2198         ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN);
2199         acpi_put_table((struct acpi_table_header *)dmar);
2200
2201         return ret;
2202 }
2203 EXPORT_SYMBOL_GPL(dmar_platform_optin);