drivers/iommu/dmar.c

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) 2006-2008 Intel Corporation
  18  * Author: Ashok Raj <ashok.raj@intel.com>
  19  * Author: Shaohua Li <shaohua.li@intel.com>
  20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  21  *
  22  * This file implements early detection/parsing of Remapping Devices
  23  * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
  24  * tables.
  25  *
  26  * These routines are used by both DMA-remapping and Interrupt-remapping
  27  */
  28
  29 #define pr_fmt(fmt)     "DMAR: " fmt
  30
  31 #include <linux/pci.h>
  32 #include <linux/dmar.h>
  33 #include <linux/iova.h>
  34 #include <linux/intel-iommu.h>
  35 #include <linux/timer.h>
  36 #include <linux/irq.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/tboot.h>
  39 #include <linux/dmi.h>
  40 #include <linux/slab.h>
  41 #include <linux/iommu.h>
  42 #include <asm/irq_remapping.h>
  43 #include <asm/iommu_table.h>
  44
  45 #include "irq_remapping.h"
  46
  47 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
  48 struct dmar_res_callback {
  49         dmar_res_handler_t      cb[ACPI_DMAR_TYPE_RESERVED];
  50         void                    *arg[ACPI_DMAR_TYPE_RESERVED];
  51         bool                    ignore_unhandled;
  52         bool                    print_entry;
  53 };
  54
  55 /*
  56  * Assumptions:
  57  * 1) The hotplug framework guarentees that DMAR unit will be hot-added
  58  *    before IO devices managed by that unit.
  59  * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
  60  *    after IO devices managed by that unit.
  61  * 3) Hotplug events are rare.
  62  *
  63  * Locking rules for DMA and interrupt remapping related global data structures:
  64  * 1) Use dmar_global_lock in process context
  65  * 2) Use RCU in interrupt context
  66  */
  67 DECLARE_RWSEM(dmar_global_lock);
  68 LIST_HEAD(dmar_drhd_units);
  69
  70 struct acpi_table_header * __initdata dmar_tbl;
  71 static int dmar_dev_scope_status = 1;
  72 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
  73
  74 static int alloc_iommu(struct dmar_drhd_unit *drhd);
  75 static void free_iommu(struct intel_iommu *iommu);
  76
  77 extern const struct iommu_ops intel_iommu_ops;
  78
  79 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
  80 {
  81         /*
  82          * add INCLUDE_ALL at the tail, so scan the list will find it at
  83          * the very end.
  84          */
  85         if (drhd->include_all)
  86                 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
  87         else
  88                 list_add_rcu(&drhd->list, &dmar_drhd_units);
  89 }
  90
  91 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
  92 {
  93         struct acpi_dmar_device_scope *scope;
  94
  95         *cnt = 0;
  96         while (start < end) {
  97                 scope = start;
  98                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
  99                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
 100                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 101                         (*cnt)++;
 102                 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
 103                         scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
 104                         pr_warn("Unsupported device scope\n");
 105                 }
 106                 start += scope->length;
 107         }
 108         if (*cnt == 0)
 109                 return NULL;
 110
 111         return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
 112 }
 113
 114 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
 115 {
 116         int i;
 117         struct device *tmp_dev;
 118
 119         if (*devices && *cnt) {
 120                 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
 121                         put_device(tmp_dev);
 122                 kfree(*devices);
 123         }
 124
 125         *devices = NULL;
 126         *cnt = 0;
 127 }
 128
 129 /* Optimize out kzalloc()/kfree() for normal cases */
 130 static char dmar_pci_notify_info_buf[64];
 131
 132 static struct dmar_pci_notify_info *
 133 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
 134 {
 135         int level = 0;
 136         size_t size;
 137         struct pci_dev *tmp;
 138         struct dmar_pci_notify_info *info;
 139
 140         BUG_ON(dev->is_virtfn);
 141
 142         /* Only generate path[] for device addition event */
 143         if (event == BUS_NOTIFY_ADD_DEVICE)
 144                 for (tmp = dev; tmp; tmp = tmp->bus->self)
 145                         level++;
 146
 147         size = sizeof(*info) + level * sizeof(struct acpi_dmar_pci_path);
 148         if (size <= sizeof(dmar_pci_notify_info_buf)) {
 149                 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
 150         } else {
 151                 info = kzalloc(size, GFP_KERNEL);
 152                 if (!info) {
 153                         pr_warn("Out of memory when allocating notify_info "
 154                                 "for %s.\n", pci_name(dev));
 155                         if (dmar_dev_scope_status == 0)
 156                                 dmar_dev_scope_status = -ENOMEM;
 157                         return NULL;
 158                 }
 159         }
 160
 161         info->event = event;
 162         info->dev = dev;
 163         info->seg = pci_domain_nr(dev->bus);
 164         info->level = level;
 165         if (event == BUS_NOTIFY_ADD_DEVICE) {
 166                 for (tmp = dev; tmp; tmp = tmp->bus->self) {
 167                         level--;
 168                         info->path[level].bus = tmp->bus->number;
 169                         info->path[level].device = PCI_SLOT(tmp->devfn);
 170                         info->path[level].function = PCI_FUNC(tmp->devfn);
 171                         if (pci_is_root_bus(tmp->bus))
 172                                 info->bus = tmp->bus->number;
 173                 }
 174         }
 175
 176         return info;
 177 }
 178
 179 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
 180 {
 181         if ((void *)info != dmar_pci_notify_info_buf)
 182                 kfree(info);
 183 }
 184
 185 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
 186                                 struct acpi_dmar_pci_path *path, int count)
 187 {
 188         int i;
 189
 190         if (info->bus != bus)
 191                 goto fallback;
 192         if (info->level != count)
 193                 goto fallback;
 194
 195         for (i = 0; i < count; i++) {
 196                 if (path[i].device != info->path[i].device ||
 197                     path[i].function != info->path[i].function)
 198                         goto fallback;
 199         }
 200
 201         return true;
 202
 203 fallback:
 204
 205         if (count != 1)
 206                 return false;
 207
 208         i = info->level - 1;
 209         if (bus              == info->path[i].bus &&
 210             path[0].device   == info->path[i].device &&
 211             path[0].function == info->path[i].function) {
 212                 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
 213                         bus, path[0].device, path[0].function);
 214                 return true;
 215         }
 216
 217         return false;
 218 }
 219
 220 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
 221 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
 222                           void *start, void*end, u16 segment,
 223                           struct dmar_dev_scope *devices,
 224                           int devices_cnt)
 225 {
 226         int i, level;
 227         struct device *tmp, *dev = &info->dev->dev;
 228         struct acpi_dmar_device_scope *scope;
 229         struct acpi_dmar_pci_path *path;
 230
 231         if (segment != info->seg)
 232                 return 0;
 233
 234         for (; start < end; start += scope->length) {
 235                 scope = start;
 236                 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 237                     scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 238                         continue;
 239
 240                 path = (struct acpi_dmar_pci_path *)(scope + 1);
 241                 level = (scope->length - sizeof(*scope)) / sizeof(*path);
 242                 if (!dmar_match_pci_path(info, scope->bus, path, level))
 243                         continue;
 244
 245                 /*
 246                  * We expect devices with endpoint scope to have normal PCI
 247                  * headers, and devices with bridge scope to have bridge PCI
 248                  * headers.  However PCI NTB devices may be listed in the
 249                  * DMAR table with bridge scope, even though they have a
 250                  * normal PCI header.  NTB devices are identified by class
 251                  * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
 252                  * for this special case.
 253                  */
 254                 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 255                      info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
 256                     (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
 257                      (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
 258                       info->dev->class >> 8 != PCI_CLASS_BRIDGE_OTHER))) {
 259                         pr_warn("Device scope type does not match for %s\n",
 260                                 pci_name(info->dev));
 261                         return -EINVAL;
 262                 }
 263
 264                 for_each_dev_scope(devices, devices_cnt, i, tmp)
 265                         if (tmp == NULL) {
 266                                 devices[i].bus = info->dev->bus->number;
 267                                 devices[i].devfn = info->dev->devfn;
 268                                 rcu_assign_pointer(devices[i].dev,
 269                                                    get_device(dev));
 270                                 return 1;
 271                         }
 272                 BUG_ON(i >= devices_cnt);
 273         }
 274
 275         return 0;
 276 }
 277
 278 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
 279                           struct dmar_dev_scope *devices, int count)
 280 {
 281         int index;
 282         struct device *tmp;
 283
 284         if (info->seg != segment)
 285                 return 0;
 286
 287         for_each_active_dev_scope(devices, count, index, tmp)
 288                 if (tmp == &info->dev->dev) {
 289                         RCU_INIT_POINTER(devices[index].dev, NULL);
 290                         synchronize_rcu();
 291                         put_device(tmp);
 292                         return 1;
 293                 }
 294
 295         return 0;
 296 }
 297
 298 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
 299 {
 300         int ret = 0;
 301         struct dmar_drhd_unit *dmaru;
 302         struct acpi_dmar_hardware_unit *drhd;
 303
 304         for_each_drhd_unit(dmaru) {
 305                 if (dmaru->include_all)
 306                         continue;
 307
 308                 drhd = container_of(dmaru->hdr,
 309                                     struct acpi_dmar_hardware_unit, header);
 310                 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
 311                                 ((void *)drhd) + drhd->header.length,
 312                                 dmaru->segment,
 313                                 dmaru->devices, dmaru->devices_cnt);
 314                 if (ret != 0)
 315                         break;
 316         }
 317         if (ret >= 0)
 318                 ret = dmar_iommu_notify_scope_dev(info);
 319         if (ret < 0 && dmar_dev_scope_status == 0)
 320                 dmar_dev_scope_status = ret;
 321
 322         return ret;
 323 }
 324
 325 static void  dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
 326 {
 327         struct dmar_drhd_unit *dmaru;
 328
 329         for_each_drhd_unit(dmaru)
 330                 if (dmar_remove_dev_scope(info, dmaru->segment,
 331                         dmaru->devices, dmaru->devices_cnt))
 332                         break;
 333         dmar_iommu_notify_scope_dev(info);
 334 }
 335
 336 static int dmar_pci_bus_notifier(struct notifier_block *nb,
 337                                  unsigned long action, void *data)
 338 {
 339         struct pci_dev *pdev = to_pci_dev(data);
 340         struct dmar_pci_notify_info *info;
 341
 342         /* Only care about add/remove events for physical functions.
 343          * For VFs we actually do the lookup based on the corresponding
 344          * PF in device_to_iommu() anyway. */
 345         if (pdev->is_virtfn)
 346                 return NOTIFY_DONE;
 347         if (action != BUS_NOTIFY_ADD_DEVICE &&
 348             action != BUS_NOTIFY_REMOVED_DEVICE)
 349                 return NOTIFY_DONE;
 350
 351         info = dmar_alloc_pci_notify_info(pdev, action);
 352         if (!info)
 353                 return NOTIFY_DONE;
 354
 355         down_write(&dmar_global_lock);
 356         if (action == BUS_NOTIFY_ADD_DEVICE)
 357                 dmar_pci_bus_add_dev(info);
 358         else if (action == BUS_NOTIFY_REMOVED_DEVICE)
 359                 dmar_pci_bus_del_dev(info);
 360         up_write(&dmar_global_lock);
 361
 362         dmar_free_pci_notify_info(info);
 363
 364         return NOTIFY_OK;
 365 }
 366
 367 static struct notifier_block dmar_pci_bus_nb = {
 368         .notifier_call = dmar_pci_bus_notifier,
 369         .priority = INT_MIN,
 370 };
 371
 372 static struct dmar_drhd_unit *
 373 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
 374 {
 375         struct dmar_drhd_unit *dmaru;
 376
 377         list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list)
 378                 if (dmaru->segment == drhd->segment &&
 379                     dmaru->reg_base_addr == drhd->address)
 380                         return dmaru;
 381
 382         return NULL;
 383 }
 384
 385 /**
 386  * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
 387  * structure which uniquely represent one DMA remapping hardware unit
 388  * present in the platform
 389  */
 390 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
 391 {
 392         struct acpi_dmar_hardware_unit *drhd;
 393         struct dmar_drhd_unit *dmaru;
 394         int ret = 0;
 395
 396         drhd = (struct acpi_dmar_hardware_unit *)header;
 397         dmaru = dmar_find_dmaru(drhd);
 398         if (dmaru)
 399                 goto out;
 400
 401         dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
 402         if (!dmaru)
 403                 return -ENOMEM;
 404
 405         /*
 406          * If header is allocated from slab by ACPI _DSM method, we need to
 407          * copy the content because the memory buffer will be freed on return.
 408          */
 409         dmaru->hdr = (void *)(dmaru + 1);
 410         memcpy(dmaru->hdr, header, header->length);
 411         dmaru->reg_base_addr = drhd->address;
 412         dmaru->segment = drhd->segment;
 413         dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
 414         dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
 415                                               ((void *)drhd) + drhd->header.length,
 416                                               &dmaru->devices_cnt);
 417         if (dmaru->devices_cnt && dmaru->devices == NULL) {
 418                 kfree(dmaru);
 419                 return -ENOMEM;
 420         }
 421
 422         ret = alloc_iommu(dmaru);
 423         if (ret) {
 424                 dmar_free_dev_scope(&dmaru->devices,
 425                                     &dmaru->devices_cnt);
 426                 kfree(dmaru);
 427                 return ret;
 428         }
 429         dmar_register_drhd_unit(dmaru);
 430
 431 out:
 432         if (arg)
 433                 (*(int *)arg)++;
 434
 435         return 0;
 436 }
 437
 438 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
 439 {
 440         if (dmaru->devices && dmaru->devices_cnt)
 441                 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
 442         if (dmaru->iommu)
 443                 free_iommu(dmaru->iommu);
 444         kfree(dmaru);
 445 }
 446
 447 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
 448                                       void *arg)
 449 {
 450         struct acpi_dmar_andd *andd = (void *)header;
 451
 452         /* Check for NUL termination within the designated length */
 453         if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
 454                 WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND,
 455                            "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
 456                            "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 457                            dmi_get_system_info(DMI_BIOS_VENDOR),
 458                            dmi_get_system_info(DMI_BIOS_VERSION),
 459                            dmi_get_system_info(DMI_PRODUCT_VERSION));
 460                 return -EINVAL;
 461         }
 462         pr_info("ANDD device: %x name: %s\n", andd->device_number,
 463                 andd->device_name);
 464
 465         return 0;
 466 }
 467
 468 #ifdef CONFIG_ACPI_NUMA
 469 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
 470 {
 471         struct acpi_dmar_rhsa *rhsa;
 472         struct dmar_drhd_unit *drhd;
 473
 474         rhsa = (struct acpi_dmar_rhsa *)header;
 475         for_each_drhd_unit(drhd) {
 476                 if (drhd->reg_base_addr == rhsa->base_address) {
 477                         int node = acpi_map_pxm_to_node(rhsa->proximity_domain);
 478
 479                         if (!node_online(node))
 480                                 node = -1;
 481                         drhd->iommu->node = node;
 482                         return 0;
 483                 }
 484         }
 485         WARN_TAINT(
 486                 1, TAINT_FIRMWARE_WORKAROUND,
 487                 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
 488                 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 489                 drhd->reg_base_addr,
 490                 dmi_get_system_info(DMI_BIOS_VENDOR),
 491                 dmi_get_system_info(DMI_BIOS_VERSION),
 492                 dmi_get_system_info(DMI_PRODUCT_VERSION));
 493
 494         return 0;
 495 }
 496 #else
 497 #define dmar_parse_one_rhsa             dmar_res_noop
 498 #endif
 499
 500 static void __init
 501 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
 502 {
 503         struct acpi_dmar_hardware_unit *drhd;
 504         struct acpi_dmar_reserved_memory *rmrr;
 505         struct acpi_dmar_atsr *atsr;
 506         struct acpi_dmar_rhsa *rhsa;
 507
 508         switch (header->type) {
 509         case ACPI_DMAR_TYPE_HARDWARE_UNIT:
 510                 drhd = container_of(header, struct acpi_dmar_hardware_unit,
 511                                     header);
 512                 pr_info("DRHD base: %#016Lx flags: %#x\n",
 513                         (unsigned long long)drhd->address, drhd->flags);
 514                 break;
 515         case ACPI_DMAR_TYPE_RESERVED_MEMORY:
 516                 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
 517                                     header);
 518                 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
 519                         (unsigned long long)rmrr->base_address,
 520                         (unsigned long long)rmrr->end_address);
 521                 break;
 522         case ACPI_DMAR_TYPE_ROOT_ATS:
 523                 atsr = container_of(header, struct acpi_dmar_atsr, header);
 524                 pr_info("ATSR flags: %#x\n", atsr->flags);
 525                 break;
 526         case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
 527                 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
 528                 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
 529                        (unsigned long long)rhsa->base_address,
 530                        rhsa->proximity_domain);
 531                 break;
 532         case ACPI_DMAR_TYPE_NAMESPACE:
 533                 /* We don't print this here because we need to sanity-check
 534                    it first. So print it in dmar_parse_one_andd() instead. */
 535                 break;
 536         }
 537 }
 538
 539 /**
 540  * dmar_table_detect - checks to see if the platform supports DMAR devices
 541  */
 542 static int __init dmar_table_detect(void)
 543 {
 544         acpi_status status = AE_OK;
 545
 546         /* if we could find DMAR table, then there are DMAR devices */
 547         status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
 548
 549         if (ACPI_SUCCESS(status) && !dmar_tbl) {
 550                 pr_warn("Unable to map DMAR\n");
 551                 status = AE_NOT_FOUND;
 552         }
 553
 554         return (ACPI_SUCCESS(status) ? 1 : 0);
 555 }
 556
 557 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
 558                                        size_t len, struct dmar_res_callback *cb)
 559 {
 560         int ret = 0;
 561         struct acpi_dmar_header *iter, *next;
 562         struct acpi_dmar_header *end = ((void *)start) + len;
 563
 564         for (iter = start; iter < end && ret == 0; iter = next) {
 565                 next = (void *)iter + iter->length;
 566                 if (iter->length == 0) {
 567                         /* Avoid looping forever on bad ACPI tables */
 568                         pr_debug(FW_BUG "Invalid 0-length structure\n");
 569                         break;
 570                 } else if (next > end) {
 571                         /* Avoid passing table end */
 572                         pr_warn(FW_BUG "Record passes table end\n");
 573                         ret = -EINVAL;
 574                         break;
 575                 }
 576
 577                 if (cb->print_entry)
 578                         dmar_table_print_dmar_entry(iter);
 579
 580                 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
 581                         /* continue for forward compatibility */
 582                         pr_debug("Unknown DMAR structure type %d\n",
 583                                  iter->type);
 584                 } else if (cb->cb[iter->type]) {
 585                         ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
 586                 } else if (!cb->ignore_unhandled) {
 587                         pr_warn("No handler for DMAR structure type %d\n",
 588                                 iter->type);
 589                         ret = -EINVAL;
 590                 }
 591         }
 592
 593         return ret;
 594 }
 595
 596 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
 597                                        struct dmar_res_callback *cb)
 598 {
 599         return dmar_walk_remapping_entries((void *)(dmar + 1),
 600                         dmar->header.length - sizeof(*dmar), cb);
 601 }
 602
 603 /**
 604  * parse_dmar_table - parses the DMA reporting table
 605  */
 606 static int __init
 607 parse_dmar_table(void)
 608 {
 609         struct acpi_table_dmar *dmar;
 610         int ret = 0;
 611         int drhd_count = 0;
 612         struct dmar_res_callback cb = {
 613                 .print_entry = true,
 614                 .ignore_unhandled = true,
 615                 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
 616                 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
 617                 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
 618                 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
 619                 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
 620                 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
 621         };
 622
 623         /*
 624          * Do it again, earlier dmar_tbl mapping could be mapped with
 625          * fixed map.
 626          */
 627         dmar_table_detect();
 628
 629         /*
 630          * ACPI tables may not be DMA protected by tboot, so use DMAR copy
 631          * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
 632          */
 633         dmar_tbl = tboot_get_dmar_table(dmar_tbl);
 634
 635         dmar = (struct acpi_table_dmar *)dmar_tbl;
 636         if (!dmar)
 637                 return -ENODEV;
 638
 639         if (dmar->width < PAGE_SHIFT - 1) {
 640                 pr_warn("Invalid DMAR haw\n");
 641                 return -EINVAL;
 642         }
 643
 644         pr_info("Host address width %d\n", dmar->width + 1);
 645         ret = dmar_walk_dmar_table(dmar, &cb);
 646         if (ret == 0 && drhd_count == 0)
 647                 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
 648
 649         return ret;
 650 }
 651
 652 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
 653                                  int cnt, struct pci_dev *dev)
 654 {
 655         int index;
 656         struct device *tmp;
 657
 658         while (dev) {
 659                 for_each_active_dev_scope(devices, cnt, index, tmp)
 660                         if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
 661                                 return 1;
 662
 663                 /* Check our parent */
 664                 dev = dev->bus->self;
 665         }
 666
 667         return 0;
 668 }
 669
 670 struct dmar_drhd_unit *
 671 dmar_find_matched_drhd_unit(struct pci_dev *dev)
 672 {
 673         struct dmar_drhd_unit *dmaru;
 674         struct acpi_dmar_hardware_unit *drhd;
 675
 676         dev = pci_physfn(dev);
 677
 678         rcu_read_lock();
 679         for_each_drhd_unit(dmaru) {
 680                 drhd = container_of(dmaru->hdr,
 681                                     struct acpi_dmar_hardware_unit,
 682                                     header);
 683
 684                 if (dmaru->include_all &&
 685                     drhd->segment == pci_domain_nr(dev->bus))
 686                         goto out;
 687
 688                 if (dmar_pci_device_match(dmaru->devices,
 689                                           dmaru->devices_cnt, dev))
 690                         goto out;
 691         }
 692         dmaru = NULL;
 693 out:
 694         rcu_read_unlock();
 695
 696         return dmaru;
 697 }
 698
 699 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
 700                                               struct acpi_device *adev)
 701 {
 702         struct dmar_drhd_unit *dmaru;
 703         struct acpi_dmar_hardware_unit *drhd;
 704         struct acpi_dmar_device_scope *scope;
 705         struct device *tmp;
 706         int i;
 707         struct acpi_dmar_pci_path *path;
 708
 709         for_each_drhd_unit(dmaru) {
 710                 drhd = container_of(dmaru->hdr,
 711                                     struct acpi_dmar_hardware_unit,
 712                                     header);
 713
 714                 for (scope = (void *)(drhd + 1);
 715                      (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
 716                      scope = ((void *)scope) + scope->length) {
 717                         if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
 718                                 continue;
 719                         if (scope->enumeration_id != device_number)
 720                                 continue;
 721
 722                         path = (void *)(scope + 1);
 723                         pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
 724                                 dev_name(&adev->dev), dmaru->reg_base_addr,
 725                                 scope->bus, path->device, path->function);
 726                         for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
 727                                 if (tmp == NULL) {
 728                                         dmaru->devices[i].bus = scope->bus;
 729                                         dmaru->devices[i].devfn = PCI_DEVFN(path->device,
 730                                                                             path->function);
 731                                         rcu_assign_pointer(dmaru->devices[i].dev,
 732                                                            get_device(&adev->dev));
 733                                         return;
 734                                 }
 735                         BUG_ON(i >= dmaru->devices_cnt);
 736                 }
 737         }
 738         pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
 739                 device_number, dev_name(&adev->dev));
 740 }
 741
 742 static int __init dmar_acpi_dev_scope_init(void)
 743 {
 744         struct acpi_dmar_andd *andd;
 745
 746         if (dmar_tbl == NULL)
 747                 return -ENODEV;
 748
 749         for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
 750              ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
 751              andd = ((void *)andd) + andd->header.length) {
 752                 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
 753                         acpi_handle h;
 754                         struct acpi_device *adev;
 755
 756                         if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
 757                                                           andd->device_name,
 758                                                           &h))) {
 759                                 pr_err("Failed to find handle for ACPI object %s\n",
 760                                        andd->device_name);
 761                                 continue;
 762                         }
 763                         if (acpi_bus_get_device(h, &adev)) {
 764                                 pr_err("Failed to get device for ACPI object %s\n",
 765                                        andd->device_name);
 766                                 continue;
 767                         }
 768                         dmar_acpi_insert_dev_scope(andd->device_number, adev);
 769                 }
 770         }
 771         return 0;
 772 }
 773
 774 int __init dmar_dev_scope_init(void)
 775 {
 776         struct pci_dev *dev = NULL;
 777         struct dmar_pci_notify_info *info;
 778
 779         if (dmar_dev_scope_status != 1)
 780                 return dmar_dev_scope_status;
 781
 782         if (list_empty(&dmar_drhd_units)) {
 783                 dmar_dev_scope_status = -ENODEV;
 784         } else {
 785                 dmar_dev_scope_status = 0;
 786
 787                 dmar_acpi_dev_scope_init();
 788
 789                 for_each_pci_dev(dev) {
 790                         if (dev->is_virtfn)
 791                                 continue;
 792
 793                         info = dmar_alloc_pci_notify_info(dev,
 794                                         BUS_NOTIFY_ADD_DEVICE);
 795                         if (!info) {
 796                                 return dmar_dev_scope_status;
 797                         } else {
 798                                 dmar_pci_bus_add_dev(info);
 799                                 dmar_free_pci_notify_info(info);
 800                         }
 801                 }
 802
 803                 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
 804         }
 805
 806         return dmar_dev_scope_status;
 807 }
 808
 809
 810 int __init dmar_table_init(void)
 811 {
 812         static int dmar_table_initialized;
 813         int ret;
 814
 815         if (dmar_table_initialized == 0) {
 816                 ret = parse_dmar_table();
 817                 if (ret < 0) {
 818                         if (ret != -ENODEV)
 819                                 pr_info("Parse DMAR table failure.\n");
 820                 } else  if (list_empty(&dmar_drhd_units)) {
 821                         pr_info("No DMAR devices found\n");
 822                         ret = -ENODEV;
 823                 }
 824
 825                 if (ret < 0)
 826                         dmar_table_initialized = ret;
 827                 else
 828                         dmar_table_initialized = 1;
 829         }
 830
 831         return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
 832 }
 833
 834 static void warn_invalid_dmar(u64 addr, const char *message)
 835 {
 836         WARN_TAINT_ONCE(
 837                 1, TAINT_FIRMWARE_WORKAROUND,
 838                 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
 839                 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
 840                 addr, message,
 841                 dmi_get_system_info(DMI_BIOS_VENDOR),
 842                 dmi_get_system_info(DMI_BIOS_VERSION),
 843                 dmi_get_system_info(DMI_PRODUCT_VERSION));
 844 }
 845
 846 static int __ref
 847 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
 848 {
 849         struct acpi_dmar_hardware_unit *drhd;
 850         void __iomem *addr;
 851         u64 cap, ecap;
 852
 853         drhd = (void *)entry;
 854         if (!drhd->address) {
 855                 warn_invalid_dmar(0, "");
 856                 return -EINVAL;
 857         }
 858
 859         if (arg)
 860                 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
 861         else
 862                 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
 863         if (!addr) {
 864                 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
 865                 return -EINVAL;
 866         }
 867
 868         cap = dmar_readq(addr + DMAR_CAP_REG);
 869         ecap = dmar_readq(addr + DMAR_ECAP_REG);
 870
 871         if (arg)
 872                 iounmap(addr);
 873         else
 874                 early_iounmap(addr, VTD_PAGE_SIZE);
 875
 876         if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
 877                 warn_invalid_dmar(drhd->address, " returns all ones");
 878                 return -EINVAL;
 879         }
 880
 881         return 0;
 882 }
 883
 884 int __init detect_intel_iommu(void)
 885 {
 886         int ret;
 887         struct dmar_res_callback validate_drhd_cb = {
 888                 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
 889                 .ignore_unhandled = true,
 890         };
 891
 892         down_write(&dmar_global_lock);
 893         ret = dmar_table_detect();
 894         if (ret)
 895                 ret = !dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
 896                                             &validate_drhd_cb);
 897         if (ret && !no_iommu && !iommu_detected && !dmar_disabled) {
 898                 iommu_detected = 1;
 899                 /* Make sure ACS will be enabled */
 900                 pci_request_acs();
 901         }
 902
 903 #ifdef CONFIG_X86
 904         if (ret)
 905                 x86_init.iommu.iommu_init = intel_iommu_init;
 906 #endif
 907
 908         acpi_put_table(dmar_tbl);
 909         dmar_tbl = NULL;
 910         up_write(&dmar_global_lock);
 911
 912         return ret ? 1 : -ENODEV;
 913 }
 914
 915
 916 static void unmap_iommu(struct intel_iommu *iommu)
 917 {
 918         iounmap(iommu->reg);
 919         release_mem_region(iommu->reg_phys, iommu->reg_size);
 920 }
 921
 922 /**
 923  * map_iommu: map the iommu's registers
 924  * @iommu: the iommu to map
 925  * @phys_addr: the physical address of the base resgister
 926  *
 927  * Memory map the iommu's registers.  Start w/ a single page, and
 928  * possibly expand if that turns out to be insufficent.
 929  */
 930 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
 931 {
 932         int map_size, err=0;
 933
 934         iommu->reg_phys = phys_addr;
 935         iommu->reg_size = VTD_PAGE_SIZE;
 936
 937         if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
 938                 pr_err("Can't reserve memory\n");
 939                 err = -EBUSY;
 940                 goto out;
 941         }
 942
 943         iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
 944         if (!iommu->reg) {
 945                 pr_err("Can't map the region\n");
 946                 err = -ENOMEM;
 947                 goto release;
 948         }
 949
 950         iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
 951         iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
 952
 953         if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
 954                 err = -EINVAL;
 955                 warn_invalid_dmar(phys_addr, " returns all ones");
 956                 goto unmap;
 957         }
 958
 959         /* the registers might be more than one page */
 960         map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
 961                          cap_max_fault_reg_offset(iommu->cap));
 962         map_size = VTD_PAGE_ALIGN(map_size);
 963         if (map_size > iommu->reg_size) {
 964                 iounmap(iommu->reg);
 965                 release_mem_region(iommu->reg_phys, iommu->reg_size);
 966                 iommu->reg_size = map_size;
 967                 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
 968                                         iommu->name)) {
 969                         pr_err("Can't reserve memory\n");
 970                         err = -EBUSY;
 971                         goto out;
 972                 }
 973                 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
 974                 if (!iommu->reg) {
 975                         pr_err("Can't map the region\n");
 976                         err = -ENOMEM;
 977                         goto release;
 978                 }
 979         }
 980         err = 0;
 981         goto out;
 982
 983 unmap:
 984         iounmap(iommu->reg);
 985 release:
 986         release_mem_region(iommu->reg_phys, iommu->reg_size);
 987 out:
 988         return err;
 989 }
 990
 991 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
 992 {
 993         iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
 994                                             DMAR_UNITS_SUPPORTED);
 995         if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
 996                 iommu->seq_id = -1;
 997         } else {
 998                 set_bit(iommu->seq_id, dmar_seq_ids);
 999                 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1000         }
1001
1002         return iommu->seq_id;
1003 }
1004
1005 static void dmar_free_seq_id(struct intel_iommu *iommu)
1006 {
1007         if (iommu->seq_id >= 0) {
1008                 clear_bit(iommu->seq_id, dmar_seq_ids);
1009                 iommu->seq_id = -1;
1010         }
1011 }
1012
1013 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1014 {
1015         struct intel_iommu *iommu;
1016         u32 ver, sts;
1017         int agaw = 0;
1018         int msagaw = 0;
1019         int err;
1020
1021         if (!drhd->reg_base_addr) {
1022                 warn_invalid_dmar(0, "");
1023                 return -EINVAL;
1024         }
1025
1026         iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1027         if (!iommu)
1028                 return -ENOMEM;
1029
1030         if (dmar_alloc_seq_id(iommu) < 0) {
1031                 pr_err("Failed to allocate seq_id\n");
1032                 err = -ENOSPC;
1033                 goto error;
1034         }
1035
1036         err = map_iommu(iommu, drhd->reg_base_addr);
1037         if (err) {
1038                 pr_err("Failed to map %s\n", iommu->name);
1039                 goto error_free_seq_id;
1040         }
1041
1042         err = -EINVAL;
1043         agaw = iommu_calculate_agaw(iommu);
1044         if (agaw < 0) {
1045                 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1046                         iommu->seq_id);
1047                 goto err_unmap;
1048         }
1049         msagaw = iommu_calculate_max_sagaw(iommu);
1050         if (msagaw < 0) {
1051                 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1052                         iommu->seq_id);
1053                 goto err_unmap;
1054         }
1055         iommu->agaw = agaw;
1056         iommu->msagaw = msagaw;
1057         iommu->segment = drhd->segment;
1058
1059         iommu->node = -1;
1060
1061         ver = readl(iommu->reg + DMAR_VER_REG);
1062         pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1063                 iommu->name,
1064                 (unsigned long long)drhd->reg_base_addr,
1065                 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1066                 (unsigned long long)iommu->cap,
1067                 (unsigned long long)iommu->ecap);
1068
1069         /* Reflect status in gcmd */
1070         sts = readl(iommu->reg + DMAR_GSTS_REG);
1071         if (sts & DMA_GSTS_IRES)
1072                 iommu->gcmd |= DMA_GCMD_IRE;
1073         if (sts & DMA_GSTS_TES)
1074                 iommu->gcmd |= DMA_GCMD_TE;
1075         if (sts & DMA_GSTS_QIES)
1076                 iommu->gcmd |= DMA_GCMD_QIE;
1077
1078         raw_spin_lock_init(&iommu->register_lock);
1079
1080         if (intel_iommu_enabled) {
1081                 iommu->iommu_dev = iommu_device_create(NULL, iommu,
1082                                                        intel_iommu_groups,
1083                                                        "%s", iommu->name);
1084
1085                 if (IS_ERR(iommu->iommu_dev)) {
1086                         err = PTR_ERR(iommu->iommu_dev);
1087                         goto err_unmap;
1088                 }
1089
1090                 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
1091
1092                 err = iommu_device_register(&iommu->iommu);
1093                 if (err)
1094                         goto err_unmap;
1095         }
1096
1097         drhd->iommu = iommu;
1098
1099         return 0;
1100
1101 err_unmap:
1102         unmap_iommu(iommu);
1103 error_free_seq_id:
1104         dmar_free_seq_id(iommu);
1105 error:
1106         kfree(iommu);
1107         return err;
1108 }
1109
1110 static void free_iommu(struct intel_iommu *iommu)
1111 {
1112         iommu_device_destroy(iommu->iommu_dev);
1113         iommu_device_unregister(&iommu->iommu);
1114
1115         if (iommu->irq) {
1116                 if (iommu->pr_irq) {
1117                         free_irq(iommu->pr_irq, iommu);
1118                         dmar_free_hwirq(iommu->pr_irq);
1119                         iommu->pr_irq = 0;
1120                 }
1121                 free_irq(iommu->irq, iommu);
1122                 dmar_free_hwirq(iommu->irq);
1123                 iommu->irq = 0;
1124         }
1125
1126         if (iommu->qi) {
1127                 free_page((unsigned long)iommu->qi->desc);
1128                 kfree(iommu->qi->desc_status);
1129                 kfree(iommu->qi);
1130         }
1131
1132         if (iommu->reg)
1133                 unmap_iommu(iommu);
1134
1135         dmar_free_seq_id(iommu);
1136         kfree(iommu);
1137 }
1138
1139 /*
1140  * Reclaim all the submitted descriptors which have completed its work.
1141  */
1142 static inline void reclaim_free_desc(struct q_inval *qi)
1143 {
1144         while (qi->desc_status[qi->free_tail] == QI_DONE ||
1145                qi->desc_status[qi->free_tail] == QI_ABORT) {
1146                 qi->desc_status[qi->free_tail] = QI_FREE;
1147                 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1148                 qi->free_cnt++;
1149         }
1150 }
1151
1152 static int qi_check_fault(struct intel_iommu *iommu, int index)
1153 {
1154         u32 fault;
1155         int head, tail;
1156         struct q_inval *qi = iommu->qi;
1157         int wait_index = (index + 1) % QI_LENGTH;
1158
1159         if (qi->desc_status[wait_index] == QI_ABORT)
1160                 return -EAGAIN;
1161
1162         fault = readl(iommu->reg + DMAR_FSTS_REG);
1163
1164         /*
1165          * If IQE happens, the head points to the descriptor associated
1166          * with the error. No new descriptors are fetched until the IQE
1167          * is cleared.
1168          */
1169         if (fault & DMA_FSTS_IQE) {
1170                 head = readl(iommu->reg + DMAR_IQH_REG);
1171                 if ((head >> DMAR_IQ_SHIFT) == index) {
1172                         pr_err("VT-d detected invalid descriptor: "
1173                                 "low=%llx, high=%llx\n",
1174                                 (unsigned long long)qi->desc[index].low,
1175                                 (unsigned long long)qi->desc[index].high);
1176                         memcpy(&qi->desc[index], &qi->desc[wait_index],
1177                                         sizeof(struct qi_desc));
1178                         writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1179                         return -EINVAL;
1180                 }
1181         }
1182
1183         /*
1184          * If ITE happens, all pending wait_desc commands are aborted.
1185          * No new descriptors are fetched until the ITE is cleared.
1186          */
1187         if (fault & DMA_FSTS_ITE) {
1188                 head = readl(iommu->reg + DMAR_IQH_REG);
1189                 head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1190                 head |= 1;
1191                 tail = readl(iommu->reg + DMAR_IQT_REG);
1192                 tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH;
1193
1194                 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1195
1196                 do {
1197                         if (qi->desc_status[head] == QI_IN_USE)
1198                                 qi->desc_status[head] = QI_ABORT;
1199                         head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1200                 } while (head != tail);
1201
1202                 if (qi->desc_status[wait_index] == QI_ABORT)
1203                         return -EAGAIN;
1204         }
1205
1206         if (fault & DMA_FSTS_ICE)
1207                 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1208
1209         return 0;
1210 }
1211
1212 /*
1213  * Submit the queued invalidation descriptor to the remapping
1214  * hardware unit and wait for its completion.
1215  */
1216 int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
1217 {
1218         int rc;
1219         struct q_inval *qi = iommu->qi;
1220         struct qi_desc *hw, wait_desc;
1221         int wait_index, index;
1222         unsigned long flags;
1223
1224         if (!qi)
1225                 return 0;
1226
1227         hw = qi->desc;
1228
1229 restart:
1230         rc = 0;
1231
1232         raw_spin_lock_irqsave(&qi->q_lock, flags);
1233         while (qi->free_cnt < 3) {
1234                 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1235                 cpu_relax();
1236                 raw_spin_lock_irqsave(&qi->q_lock, flags);
1237         }
1238
1239         index = qi->free_head;
1240         wait_index = (index + 1) % QI_LENGTH;
1241
1242         qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
1243
1244         hw[index] = *desc;
1245
1246         wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) |
1247                         QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1248         wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
1249
1250         hw[wait_index] = wait_desc;
1251
1252         qi->free_head = (qi->free_head + 2) % QI_LENGTH;
1253         qi->free_cnt -= 2;
1254
1255         /*
1256          * update the HW tail register indicating the presence of
1257          * new descriptors.
1258          */
1259         writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG);
1260
1261         while (qi->desc_status[wait_index] != QI_DONE) {
1262                 /*
1263                  * We will leave the interrupts disabled, to prevent interrupt
1264                  * context to queue another cmd while a cmd is already submitted
1265                  * and waiting for completion on this cpu. This is to avoid
1266                  * a deadlock where the interrupt context can wait indefinitely
1267                  * for free slots in the queue.
1268                  */
1269                 rc = qi_check_fault(iommu, index);
1270                 if (rc)
1271                         break;
1272
1273                 raw_spin_unlock(&qi->q_lock);
1274                 cpu_relax();
1275                 raw_spin_lock(&qi->q_lock);
1276         }
1277
1278         qi->desc_status[index] = QI_DONE;
1279
1280         reclaim_free_desc(qi);
1281         raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1282
1283         if (rc == -EAGAIN)
1284                 goto restart;
1285
1286         return rc;
1287 }
1288
1289 /*
1290  * Flush the global interrupt entry cache.
1291  */
1292 void qi_global_iec(struct intel_iommu *iommu)
1293 {
1294         struct qi_desc desc;
1295
1296         desc.low = QI_IEC_TYPE;
1297         desc.high = 0;
1298
1299         /* should never fail */
1300         qi_submit_sync(&desc, iommu);
1301 }
1302
1303 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1304                       u64 type)
1305 {
1306         struct qi_desc desc;
1307
1308         desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1309                         | QI_CC_GRAN(type) | QI_CC_TYPE;
1310         desc.high = 0;
1311
1312         qi_submit_sync(&desc, iommu);
1313 }
1314
1315 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1316                     unsigned int size_order, u64 type)
1317 {
1318         u8 dw = 0, dr = 0;
1319
1320         struct qi_desc desc;
1321         int ih = 0;
1322
1323         if (cap_write_drain(iommu->cap))
1324                 dw = 1;
1325
1326         if (cap_read_drain(iommu->cap))
1327                 dr = 1;
1328
1329         desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1330                 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1331         desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1332                 | QI_IOTLB_AM(size_order);
1333
1334         qi_submit_sync(&desc, iommu);
1335 }
1336
1337 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
1338                         u64 addr, unsigned mask)
1339 {
1340         struct qi_desc desc;
1341
1342         if (mask) {
1343                 BUG_ON(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1));
1344                 addr |= (1 << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1345                 desc.high = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1346         } else
1347                 desc.high = QI_DEV_IOTLB_ADDR(addr);
1348
1349         if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1350                 qdep = 0;
1351
1352         desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1353                    QI_DIOTLB_TYPE;
1354
1355         qi_submit_sync(&desc, iommu);
1356 }
1357
1358 /*
1359  * Disable Queued Invalidation interface.
1360  */
1361 void dmar_disable_qi(struct intel_iommu *iommu)
1362 {
1363         unsigned long flags;
1364         u32 sts;
1365         cycles_t start_time = get_cycles();
1366
1367         if (!ecap_qis(iommu->ecap))
1368                 return;
1369
1370         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1371
1372         sts =  readl(iommu->reg + DMAR_GSTS_REG);
1373         if (!(sts & DMA_GSTS_QIES))
1374                 goto end;
1375
1376         /*
1377          * Give a chance to HW to complete the pending invalidation requests.
1378          */
1379         while ((readl(iommu->reg + DMAR_IQT_REG) !=
1380                 readl(iommu->reg + DMAR_IQH_REG)) &&
1381                 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1382                 cpu_relax();
1383
1384         iommu->gcmd &= ~DMA_GCMD_QIE;
1385         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1386
1387         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1388                       !(sts & DMA_GSTS_QIES), sts);
1389 end:
1390         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1391 }
1392
1393 /*
1394  * Enable queued invalidation.
1395  */
1396 static void __dmar_enable_qi(struct intel_iommu *iommu)
1397 {
1398         u32 sts;
1399         unsigned long flags;
1400         struct q_inval *qi = iommu->qi;
1401
1402         qi->free_head = qi->free_tail = 0;
1403         qi->free_cnt = QI_LENGTH;
1404
1405         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1406
1407         /* write zero to the tail reg */
1408         writel(0, iommu->reg + DMAR_IQT_REG);
1409
1410         dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
1411
1412         iommu->gcmd |= DMA_GCMD_QIE;
1413         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1414
1415         /* Make sure hardware complete it */
1416         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1417
1418         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1419 }
1420
1421 /*
1422  * Enable Queued Invalidation interface. This is a must to support
1423  * interrupt-remapping. Also used by DMA-remapping, which replaces
1424  * register based IOTLB invalidation.
1425  */
1426 int dmar_enable_qi(struct intel_iommu *iommu)
1427 {
1428         struct q_inval *qi;
1429         struct page *desc_page;
1430
1431         if (!ecap_qis(iommu->ecap))
1432                 return -ENOENT;
1433
1434         /*
1435          * queued invalidation is already setup and enabled.
1436          */
1437         if (iommu->qi)
1438                 return 0;
1439
1440         iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1441         if (!iommu->qi)
1442                 return -ENOMEM;
1443
1444         qi = iommu->qi;
1445
1446
1447         desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0);
1448         if (!desc_page) {
1449                 kfree(qi);
1450                 iommu->qi = NULL;
1451                 return -ENOMEM;
1452         }
1453
1454         qi->desc = page_address(desc_page);
1455
1456         qi->desc_status = kzalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC);
1457         if (!qi->desc_status) {
1458                 free_page((unsigned long) qi->desc);
1459                 kfree(qi);
1460                 iommu->qi = NULL;
1461                 return -ENOMEM;
1462         }
1463
1464         raw_spin_lock_init(&qi->q_lock);
1465
1466         __dmar_enable_qi(iommu);
1467
1468         return 0;
1469 }
1470
1471 /* iommu interrupt handling. Most stuff are MSI-like. */
1472
1473 enum faulttype {
1474         DMA_REMAP,
1475         INTR_REMAP,
1476         UNKNOWN,
1477 };
1478
1479 static const char *dma_remap_fault_reasons[] =
1480 {
1481         "Software",
1482         "Present bit in root entry is clear",
1483         "Present bit in context entry is clear",
1484         "Invalid context entry",
1485         "Access beyond MGAW",
1486         "PTE Write access is not set",
1487         "PTE Read access is not set",
1488         "Next page table ptr is invalid",
1489         "Root table address invalid",
1490         "Context table ptr is invalid",
1491         "non-zero reserved fields in RTP",
1492         "non-zero reserved fields in CTP",
1493         "non-zero reserved fields in PTE",
1494         "PCE for translation request specifies blocking",
1495 };
1496
1497 static const char *irq_remap_fault_reasons[] =
1498 {
1499         "Detected reserved fields in the decoded interrupt-remapped request",
1500         "Interrupt index exceeded the interrupt-remapping table size",
1501         "Present field in the IRTE entry is clear",
1502         "Error accessing interrupt-remapping table pointed by IRTA_REG",
1503         "Detected reserved fields in the IRTE entry",
1504         "Blocked a compatibility format interrupt request",
1505         "Blocked an interrupt request due to source-id verification failure",
1506 };
1507
1508 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1509 {
1510         if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1511                                         ARRAY_SIZE(irq_remap_fault_reasons))) {
1512                 *fault_type = INTR_REMAP;
1513                 return irq_remap_fault_reasons[fault_reason - 0x20];
1514         } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1515                 *fault_type = DMA_REMAP;
1516                 return dma_remap_fault_reasons[fault_reason];
1517         } else {
1518                 *fault_type = UNKNOWN;
1519                 return "Unknown";
1520         }
1521 }
1522
1523
1524 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1525 {
1526         if (iommu->irq == irq)
1527                 return DMAR_FECTL_REG;
1528         else if (iommu->pr_irq == irq)
1529                 return DMAR_PECTL_REG;
1530         else
1531                 BUG();
1532 }
1533
1534 void dmar_msi_unmask(struct irq_data *data)
1535 {
1536         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1537         int reg = dmar_msi_reg(iommu, data->irq);
1538         unsigned long flag;
1539
1540         /* unmask it */
1541         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1542         writel(0, iommu->reg + reg);
1543         /* Read a reg to force flush the post write */
1544         readl(iommu->reg + reg);
1545         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1546 }
1547
1548 void dmar_msi_mask(struct irq_data *data)
1549 {
1550         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1551         int reg = dmar_msi_reg(iommu, data->irq);
1552         unsigned long flag;
1553
1554         /* mask it */
1555         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1556         writel(DMA_FECTL_IM, iommu->reg + reg);
1557         /* Read a reg to force flush the post write */
1558         readl(iommu->reg + reg);
1559         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1560 }
1561
1562 void dmar_msi_write(int irq, struct msi_msg *msg)
1563 {
1564         struct intel_iommu *iommu = irq_get_handler_data(irq);
1565         int reg = dmar_msi_reg(iommu, irq);
1566         unsigned long flag;
1567
1568         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1569         writel(msg->data, iommu->reg + reg + 4);
1570         writel(msg->address_lo, iommu->reg + reg + 8);
1571         writel(msg->address_hi, iommu->reg + reg + 12);
1572         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1573 }
1574
1575 void dmar_msi_read(int irq, struct msi_msg *msg)
1576 {
1577         struct intel_iommu *iommu = irq_get_handler_data(irq);
1578         int reg = dmar_msi_reg(iommu, irq);
1579         unsigned long flag;
1580
1581         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1582         msg->data = readl(iommu->reg + reg + 4);
1583         msg->address_lo = readl(iommu->reg + reg + 8);
1584         msg->address_hi = readl(iommu->reg + reg + 12);
1585         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1586 }
1587
1588 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1589                 u8 fault_reason, u16 source_id, unsigned long long addr)
1590 {
1591         const char *reason;
1592         int fault_type;
1593
1594         reason = dmar_get_fault_reason(fault_reason, &fault_type);
1595
1596         if (fault_type == INTR_REMAP)
1597                 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n",
1598                         source_id >> 8, PCI_SLOT(source_id & 0xFF),
1599                         PCI_FUNC(source_id & 0xFF), addr >> 48,
1600                         fault_reason, reason);
1601         else
1602                 pr_err("[%s] Request device [%02x:%02x.%d] fault addr %llx [fault reason %02d] %s\n",
1603                        type ? "DMA Read" : "DMA Write",
1604                        source_id >> 8, PCI_SLOT(source_id & 0xFF),
1605                        PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
1606         return 0;
1607 }
1608
1609 #define PRIMARY_FAULT_REG_LEN (16)
1610 irqreturn_t dmar_fault(int irq, void *dev_id)
1611 {
1612         struct intel_iommu *iommu = dev_id;
1613         int reg, fault_index;
1614         u32 fault_status;
1615         unsigned long flag;
1616         bool ratelimited;
1617         static DEFINE_RATELIMIT_STATE(rs,
1618                                       DEFAULT_RATELIMIT_INTERVAL,
1619                                       DEFAULT_RATELIMIT_BURST);
1620
1621         /* Disable printing, simply clear the fault when ratelimited */
1622         ratelimited = !__ratelimit(&rs);
1623
1624         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1625         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1626         if (fault_status && !ratelimited)
1627                 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1628
1629         /* TBD: ignore advanced fault log currently */
1630         if (!(fault_status & DMA_FSTS_PPF))
1631                 goto unlock_exit;
1632
1633         fault_index = dma_fsts_fault_record_index(fault_status);
1634         reg = cap_fault_reg_offset(iommu->cap);
1635         while (1) {
1636                 u8 fault_reason;
1637                 u16 source_id;
1638                 u64 guest_addr;
1639                 int type;
1640                 u32 data;
1641
1642                 /* highest 32 bits */
1643                 data = readl(iommu->reg + reg +
1644                                 fault_index * PRIMARY_FAULT_REG_LEN + 12);
1645                 if (!(data & DMA_FRCD_F))
1646                         break;
1647
1648                 if (!ratelimited) {
1649                         fault_reason = dma_frcd_fault_reason(data);
1650                         type = dma_frcd_type(data);
1651
1652                         data = readl(iommu->reg + reg +
1653                                      fault_index * PRIMARY_FAULT_REG_LEN + 8);
1654                         source_id = dma_frcd_source_id(data);
1655
1656                         guest_addr = dmar_readq(iommu->reg + reg +
1657                                         fault_index * PRIMARY_FAULT_REG_LEN);
1658                         guest_addr = dma_frcd_page_addr(guest_addr);
1659                 }
1660
1661                 /* clear the fault */
1662                 writel(DMA_FRCD_F, iommu->reg + reg +
1663                         fault_index * PRIMARY_FAULT_REG_LEN + 12);
1664
1665                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1666
1667                 if (!ratelimited)
1668                         dmar_fault_do_one(iommu, type, fault_reason,
1669                                           source_id, guest_addr);
1670
1671                 fault_index++;
1672                 if (fault_index >= cap_num_fault_regs(iommu->cap))
1673                         fault_index = 0;
1674                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1675         }
1676
1677         writel(DMA_FSTS_PFO | DMA_FSTS_PPF, iommu->reg + DMAR_FSTS_REG);
1678
1679 unlock_exit:
1680         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1681         return IRQ_HANDLED;
1682 }
1683
1684 int dmar_set_interrupt(struct intel_iommu *iommu)
1685 {
1686         int irq, ret;
1687
1688         /*
1689          * Check if the fault interrupt is already initialized.
1690          */
1691         if (iommu->irq)
1692                 return 0;
1693
1694         irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
1695         if (irq > 0) {
1696                 iommu->irq = irq;
1697         } else {
1698                 pr_err("No free IRQ vectors\n");
1699                 return -EINVAL;
1700         }
1701
1702         ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
1703         if (ret)
1704                 pr_err("Can't request irq\n");
1705         return ret;
1706 }
1707
1708 int __init enable_drhd_fault_handling(void)
1709 {
1710         struct dmar_drhd_unit *drhd;
1711         struct intel_iommu *iommu;
1712
1713         /*
1714          * Enable fault control interrupt.
1715          */
1716         for_each_iommu(iommu, drhd) {
1717                 u32 fault_status;
1718                 int ret = dmar_set_interrupt(iommu);
1719
1720                 if (ret) {
1721                         pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
1722                                (unsigned long long)drhd->reg_base_addr, ret);
1723                         return -1;
1724                 }
1725
1726                 /*
1727                  * Clear any previous faults.
1728                  */
1729                 dmar_fault(iommu->irq, iommu);
1730                 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1731                 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
1732         }
1733
1734         return 0;
1735 }
1736
1737 /*
1738  * Re-enable Queued Invalidation interface.
1739  */
1740 int dmar_reenable_qi(struct intel_iommu *iommu)
1741 {
1742         if (!ecap_qis(iommu->ecap))
1743                 return -ENOENT;
1744
1745         if (!iommu->qi)
1746                 return -ENOENT;
1747
1748         /*
1749          * First disable queued invalidation.
1750          */
1751         dmar_disable_qi(iommu);
1752         /*
1753          * Then enable queued invalidation again. Since there is no pending
1754          * invalidation requests now, it's safe to re-enable queued
1755          * invalidation.
1756          */
1757         __dmar_enable_qi(iommu);
1758
1759         return 0;
1760 }
1761
1762 /*
1763  * Check interrupt remapping support in DMAR table description.
1764  */
1765 int __init dmar_ir_support(void)
1766 {
1767         struct acpi_table_dmar *dmar;
1768         dmar = (struct acpi_table_dmar *)dmar_tbl;
1769         if (!dmar)
1770                 return 0;
1771         return dmar->flags & 0x1;
1772 }
1773
1774 /* Check whether DMAR units are in use */
1775 static inline bool dmar_in_use(void)
1776 {
1777         return irq_remapping_enabled || intel_iommu_enabled;
1778 }
1779
1780 static int __init dmar_free_unused_resources(void)
1781 {
1782         struct dmar_drhd_unit *dmaru, *dmaru_n;
1783
1784         if (dmar_in_use())
1785                 return 0;
1786
1787         if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
1788                 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
1789
1790         down_write(&dmar_global_lock);
1791         list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
1792                 list_del(&dmaru->list);
1793                 dmar_free_drhd(dmaru);
1794         }
1795         up_write(&dmar_global_lock);
1796
1797         return 0;
1798 }
1799
1800 late_initcall(dmar_free_unused_resources);
1801 IOMMU_INIT_POST(detect_intel_iommu);
1802
1803 /*
1804  * DMAR Hotplug Support
1805  * For more details, please refer to Intel(R) Virtualization Technology
1806  * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
1807  * "Remapping Hardware Unit Hot Plug".
1808  */
1809 static u8 dmar_hp_uuid[] = {
1810         /* 0000 */    0xA6, 0xA3, 0xC1, 0xD8, 0x9B, 0xBE, 0x9B, 0x4C,
1811         /* 0008 */    0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF
1812 };
1813
1814 /*
1815  * Currently there's only one revision and BIOS will not check the revision id,
1816  * so use 0 for safety.
1817  */
1818 #define DMAR_DSM_REV_ID                 0
1819 #define DMAR_DSM_FUNC_DRHD              1
1820 #define DMAR_DSM_FUNC_ATSR              2
1821 #define DMAR_DSM_FUNC_RHSA              3
1822
1823 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
1824 {
1825         return acpi_check_dsm(handle, dmar_hp_uuid, DMAR_DSM_REV_ID, 1 << func);
1826 }
1827
1828 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
1829                                   dmar_res_handler_t handler, void *arg)
1830 {
1831         int ret = -ENODEV;
1832         union acpi_object *obj;
1833         struct acpi_dmar_header *start;
1834         struct dmar_res_callback callback;
1835         static int res_type[] = {
1836                 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
1837                 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
1838                 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
1839         };
1840
1841         if (!dmar_detect_dsm(handle, func))
1842                 return 0;
1843
1844         obj = acpi_evaluate_dsm_typed(handle, dmar_hp_uuid, DMAR_DSM_REV_ID,
1845                                       func, NULL, ACPI_TYPE_BUFFER);
1846         if (!obj)
1847                 return -ENODEV;
1848
1849         memset(&callback, 0, sizeof(callback));
1850         callback.cb[res_type[func]] = handler;
1851         callback.arg[res_type[func]] = arg;
1852         start = (struct acpi_dmar_header *)obj->buffer.pointer;
1853         ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
1854
1855         ACPI_FREE(obj);
1856
1857         return ret;
1858 }
1859
1860 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
1861 {
1862         int ret;
1863         struct dmar_drhd_unit *dmaru;
1864
1865         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1866         if (!dmaru)
1867                 return -ENODEV;
1868
1869         ret = dmar_ir_hotplug(dmaru, true);
1870         if (ret == 0)
1871                 ret = dmar_iommu_hotplug(dmaru, true);
1872
1873         return ret;
1874 }
1875
1876 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
1877 {
1878         int i, ret;
1879         struct device *dev;
1880         struct dmar_drhd_unit *dmaru;
1881
1882         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1883         if (!dmaru)
1884                 return 0;
1885
1886         /*
1887          * All PCI devices managed by this unit should have been destroyed.
1888          */
1889         if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
1890                 for_each_active_dev_scope(dmaru->devices,
1891                                           dmaru->devices_cnt, i, dev)
1892                         return -EBUSY;
1893         }
1894
1895         ret = dmar_ir_hotplug(dmaru, false);
1896         if (ret == 0)
1897                 ret = dmar_iommu_hotplug(dmaru, false);
1898
1899         return ret;
1900 }
1901
1902 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
1903 {
1904         struct dmar_drhd_unit *dmaru;
1905
1906         dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
1907         if (dmaru) {
1908                 list_del_rcu(&dmaru->list);
1909                 synchronize_rcu();
1910                 dmar_free_drhd(dmaru);
1911         }
1912
1913         return 0;
1914 }
1915
1916 static int dmar_hotplug_insert(acpi_handle handle)
1917 {
1918         int ret;
1919         int drhd_count = 0;
1920
1921         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1922                                      &dmar_validate_one_drhd, (void *)1);
1923         if (ret)
1924                 goto out;
1925
1926         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1927                                      &dmar_parse_one_drhd, (void *)&drhd_count);
1928         if (ret == 0 && drhd_count == 0) {
1929                 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
1930                 goto out;
1931         } else if (ret) {
1932                 goto release_drhd;
1933         }
1934
1935         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
1936                                      &dmar_parse_one_rhsa, NULL);
1937         if (ret)
1938                 goto release_drhd;
1939
1940         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1941                                      &dmar_parse_one_atsr, NULL);
1942         if (ret)
1943                 goto release_atsr;
1944
1945         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1946                                      &dmar_hp_add_drhd, NULL);
1947         if (!ret)
1948                 return 0;
1949
1950         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1951                                &dmar_hp_remove_drhd, NULL);
1952 release_atsr:
1953         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1954                                &dmar_release_one_atsr, NULL);
1955 release_drhd:
1956         dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1957                                &dmar_hp_release_drhd, NULL);
1958 out:
1959         return ret;
1960 }
1961
1962 static int dmar_hotplug_remove(acpi_handle handle)
1963 {
1964         int ret;
1965
1966         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1967                                      &dmar_check_one_atsr, NULL);
1968         if (ret)
1969                 return ret;
1970
1971         ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1972                                      &dmar_hp_remove_drhd, NULL);
1973         if (ret == 0) {
1974                 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
1975                                                &dmar_release_one_atsr, NULL));
1976                 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1977                                                &dmar_hp_release_drhd, NULL));
1978         } else {
1979                 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
1980                                        &dmar_hp_add_drhd, NULL);
1981         }
1982
1983         return ret;
1984 }
1985
1986 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
1987                                        void *context, void **retval)
1988 {
1989         acpi_handle *phdl = retval;
1990
1991         if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
1992                 *phdl = handle;
1993                 return AE_CTRL_TERMINATE;
1994         }
1995
1996         return AE_OK;
1997 }
1998
1999 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2000 {
2001         int ret;
2002         acpi_handle tmp = NULL;
2003         acpi_status status;
2004
2005         if (!dmar_in_use())
2006                 return 0;
2007
2008         if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2009                 tmp = handle;
2010         } else {
2011                 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2012                                              ACPI_UINT32_MAX,
2013                                              dmar_get_dsm_handle,
2014                                              NULL, NULL, &tmp);
2015                 if (ACPI_FAILURE(status)) {
2016                         pr_warn("Failed to locate _DSM method.\n");
2017                         return -ENXIO;
2018                 }
2019         }
2020         if (tmp == NULL)
2021                 return 0;
2022
2023         down_write(&dmar_global_lock);
2024         if (insert)
2025                 ret = dmar_hotplug_insert(tmp);
2026         else
2027                 ret = dmar_hotplug_remove(tmp);
2028         up_write(&dmar_global_lock);
2029
2030         return ret;
2031 }
2032
2033 int dmar_device_add(acpi_handle handle)
2034 {
2035         return dmar_device_hotplug(handle, true);
2036 }
2037
2038 int dmar_device_remove(acpi_handle handle)
2039 {
2040         return dmar_device_hotplug(handle, false);
2041 }