drivers/iommu/exynos-iommu.c

   1 /*
   2  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  11 #define DEBUG
  12 #endif
  13
  14 #include <linux/clk.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/iommu.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/of.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/slab.h>
  27 #include <linux/dma-iommu.h>
  28
  29 typedef u32 sysmmu_iova_t;
  30 typedef u32 sysmmu_pte_t;
  31
  32 /* We do not consider super section mapping (16MB) */
  33 #define SECT_ORDER 20
  34 #define LPAGE_ORDER 16
  35 #define SPAGE_ORDER 12
  36
  37 #define SECT_SIZE (1 << SECT_ORDER)
  38 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  39 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  40
  41 #define SECT_MASK (~(SECT_SIZE - 1))
  42 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  43 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  44
  45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  46                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  50                           ((*(sent) & 3) == 1))
  51 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  52
  53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  54 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  55 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  56
  57 #ifdef CONFIG_BIG_ENDIAN
  58 #warning "revisit driver if we can enable big-endian ptes"
  59 #endif
  60
  61 /*
  62  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  63  * v5.0 introduced support for 36bit physical address space by shifting
  64  * all page entry values by 4 bits.
  65  * All SYSMMU controllers in the system support the address spaces of the same
  66  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  67  * value (0 or 4).
  68  */
  69 static short PG_ENT_SHIFT = -1;
  70 #define SYSMMU_PG_ENT_SHIFT 0
  71 #define SYSMMU_V5_PG_ENT_SHIFT 4
  72
  73 static const sysmmu_pte_t *LV1_PROT;
  74 static const sysmmu_pte_t SYSMMU_LV1_PROT[] = {
  75         ((0 << 15) | (0 << 10)), /* no access */
  76         ((1 << 15) | (1 << 10)), /* IOMMU_READ only */
  77         ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
  78         ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
  79 };
  80 static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = {
  81         (0 << 4), /* no access */
  82         (1 << 4), /* IOMMU_READ only */
  83         (2 << 4), /* IOMMU_WRITE only */
  84         (3 << 4), /* IOMMU_READ | IOMMU_WRITE */
  85 };
  86
  87 static const sysmmu_pte_t *LV2_PROT;
  88 static const sysmmu_pte_t SYSMMU_LV2_PROT[] = {
  89         ((0 << 9) | (0 << 4)), /* no access */
  90         ((1 << 9) | (1 << 4)), /* IOMMU_READ only */
  91         ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
  92         ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
  93 };
  94 static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = {
  95         (0 << 2), /* no access */
  96         (1 << 2), /* IOMMU_READ only */
  97         (2 << 2), /* IOMMU_WRITE only */
  98         (3 << 2), /* IOMMU_READ | IOMMU_WRITE */
  99 };
 100
 101 #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE)
 102
 103 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
 104 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
 105 #define section_offs(iova) (iova & (SECT_SIZE - 1))
 106 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
 107 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
 108 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
 109 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
 110
 111 #define NUM_LV1ENTRIES 4096
 112 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
 113
 114 static u32 lv1ent_offset(sysmmu_iova_t iova)
 115 {
 116         return iova >> SECT_ORDER;
 117 }
 118
 119 static u32 lv2ent_offset(sysmmu_iova_t iova)
 120 {
 121         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
 122 }
 123
 124 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
 125 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
 126
 127 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
 128 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
 129
 130 #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2)
 131 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
 132 #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1)
 133 #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2)
 134
 135 #define CTRL_ENABLE     0x5
 136 #define CTRL_BLOCK      0x7
 137 #define CTRL_DISABLE    0x0
 138
 139 #define CFG_LRU         0x1
 140 #define CFG_EAP         (1 << 2)
 141 #define CFG_QOS(n)      ((n & 0xF) << 7)
 142 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 143 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 144 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 145
 146 /* common registers */
 147 #define REG_MMU_CTRL            0x000
 148 #define REG_MMU_CFG             0x004
 149 #define REG_MMU_STATUS          0x008
 150 #define REG_MMU_VERSION         0x034
 151
 152 #define MMU_MAJ_VER(val)        ((val) >> 7)
 153 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 154 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 155
 156 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 157
 158 /* v1.x - v3.x registers */
 159 #define REG_MMU_FLUSH           0x00C
 160 #define REG_MMU_FLUSH_ENTRY     0x010
 161 #define REG_PT_BASE_ADDR        0x014
 162 #define REG_INT_STATUS          0x018
 163 #define REG_INT_CLEAR           0x01C
 164
 165 #define REG_PAGE_FAULT_ADDR     0x024
 166 #define REG_AW_FAULT_ADDR       0x028
 167 #define REG_AR_FAULT_ADDR       0x02C
 168 #define REG_DEFAULT_SLAVE_ADDR  0x030
 169
 170 /* v5.x registers */
 171 #define REG_V5_PT_BASE_PFN      0x00C
 172 #define REG_V5_MMU_FLUSH_ALL    0x010
 173 #define REG_V5_MMU_FLUSH_ENTRY  0x014
 174 #define REG_V5_INT_STATUS       0x060
 175 #define REG_V5_INT_CLEAR        0x064
 176 #define REG_V5_FAULT_AR_VA      0x070
 177 #define REG_V5_FAULT_AW_VA      0x080
 178
 179 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 180
 181 static struct device *dma_dev;
 182 static struct kmem_cache *lv2table_kmem_cache;
 183 static sysmmu_pte_t *zero_lv2_table;
 184 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 185
 186 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 187 {
 188         return pgtable + lv1ent_offset(iova);
 189 }
 190
 191 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 192 {
 193         return (sysmmu_pte_t *)phys_to_virt(
 194                                 lv2table_base(sent)) + lv2ent_offset(iova);
 195 }
 196
 197 /*
 198  * IOMMU fault information register
 199  */
 200 struct sysmmu_fault_info {
 201         unsigned int bit;       /* bit number in STATUS register */
 202         unsigned short addr_reg; /* register to read VA fault address */
 203         const char *name;       /* human readable fault name */
 204         unsigned int type;      /* fault type for report_iommu_fault */
 205 };
 206
 207 static const struct sysmmu_fault_info sysmmu_faults[] = {
 208         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 209         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 210         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 211         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 212         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 213         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 214         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 215         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 216 };
 217
 218 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
 219         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
 220         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
 221         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
 222         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 223         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 224         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
 225         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
 226         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 227         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 228         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 229 };
 230
 231 /*
 232  * This structure is attached to dev.archdata.iommu of the master device
 233  * on device add, contains a list of SYSMMU controllers defined by device tree,
 234  * which are bound to given master device. It is usually referenced by 'owner'
 235  * pointer.
 236 */
 237 struct exynos_iommu_owner {
 238         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 239         struct iommu_domain *domain;    /* domain this device is attached */
 240         struct mutex rpm_lock;          /* for runtime pm of all sysmmus */
 241 };
 242
 243 /*
 244  * This structure exynos specific generalization of struct iommu_domain.
 245  * It contains list of SYSMMU controllers from all master devices, which has
 246  * been attached to this domain and page tables of IO address space defined by
 247  * it. It is usually referenced by 'domain' pointer.
 248  */
 249 struct exynos_iommu_domain {
 250         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 251         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 252         short *lv2entcnt;       /* free lv2 entry counter for each section */
 253         spinlock_t lock;        /* lock for modyfying list of clients */
 254         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 255         struct iommu_domain domain; /* generic domain data structure */
 256 };
 257
 258 /*
 259  * This structure hold all data of a single SYSMMU controller, this includes
 260  * hw resources like registers and clocks, pointers and list nodes to connect
 261  * it to all other structures, internal state and parameters read from device
 262  * tree. It is usually referenced by 'data' pointer.
 263  */
 264 struct sysmmu_drvdata {
 265         struct device *sysmmu;          /* SYSMMU controller device */
 266         struct device *master;          /* master device (owner) */
 267         void __iomem *sfrbase;          /* our registers */
 268         struct clk *clk;                /* SYSMMU's clock */
 269         struct clk *aclk;               /* SYSMMU's aclk clock */
 270         struct clk *pclk;               /* SYSMMU's pclk clock */
 271         struct clk *clk_master;         /* master's device clock */
 272         spinlock_t lock;                /* lock for modyfying state */
 273         bool active;                    /* current status */
 274         struct exynos_iommu_domain *domain; /* domain we belong to */
 275         struct list_head domain_node;   /* node for domain clients list */
 276         struct list_head owner_node;    /* node for owner controllers list */
 277         phys_addr_t pgtable;            /* assigned page table structure */
 278         unsigned int version;           /* our version */
 279 };
 280
 281 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 282 {
 283         return container_of(dom, struct exynos_iommu_domain, domain);
 284 }
 285
 286 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 287 {
 288         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 289 }
 290
 291 static bool sysmmu_block(struct sysmmu_drvdata *data)
 292 {
 293         int i = 120;
 294
 295         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 296         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
 297                 --i;
 298
 299         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 300                 sysmmu_unblock(data);
 301                 return false;
 302         }
 303
 304         return true;
 305 }
 306
 307 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 308 {
 309         if (MMU_MAJ_VER(data->version) < 5)
 310                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 311         else
 312                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
 313 }
 314
 315 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 316                                 sysmmu_iova_t iova, unsigned int num_inv)
 317 {
 318         unsigned int i;
 319
 320         for (i = 0; i < num_inv; i++) {
 321                 if (MMU_MAJ_VER(data->version) < 5)
 322                         writel((iova & SPAGE_MASK) | 1,
 323                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
 324                 else
 325                         writel((iova & SPAGE_MASK) | 1,
 326                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
 327                 iova += SPAGE_SIZE;
 328         }
 329 }
 330
 331 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 332 {
 333         if (MMU_MAJ_VER(data->version) < 5)
 334                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 335         else
 336                 writel(pgd >> PAGE_SHIFT,
 337                              data->sfrbase + REG_V5_PT_BASE_PFN);
 338
 339         __sysmmu_tlb_invalidate(data);
 340 }
 341
 342 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
 343 {
 344         BUG_ON(clk_prepare_enable(data->clk_master));
 345         BUG_ON(clk_prepare_enable(data->clk));
 346         BUG_ON(clk_prepare_enable(data->pclk));
 347         BUG_ON(clk_prepare_enable(data->aclk));
 348 }
 349
 350 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
 351 {
 352         clk_disable_unprepare(data->aclk);
 353         clk_disable_unprepare(data->pclk);
 354         clk_disable_unprepare(data->clk);
 355         clk_disable_unprepare(data->clk_master);
 356 }
 357
 358 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
 359 {
 360         u32 ver;
 361
 362         __sysmmu_enable_clocks(data);
 363
 364         ver = readl(data->sfrbase + REG_MMU_VERSION);
 365
 366         /* controllers on some SoCs don't report proper version */
 367         if (ver == 0x80000001u)
 368                 data->version = MAKE_MMU_VER(1, 0);
 369         else
 370                 data->version = MMU_RAW_VER(ver);
 371
 372         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
 373                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
 374
 375         __sysmmu_disable_clocks(data);
 376 }
 377
 378 static void show_fault_information(struct sysmmu_drvdata *data,
 379                                    const struct sysmmu_fault_info *finfo,
 380                                    sysmmu_iova_t fault_addr)
 381 {
 382         sysmmu_pte_t *ent;
 383
 384         dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n",
 385                 dev_name(data->master), finfo->name, fault_addr);
 386         dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable);
 387         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 388         dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 389         if (lv1ent_page(ent)) {
 390                 ent = page_entry(ent, fault_addr);
 391                 dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 392         }
 393 }
 394
 395 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 396 {
 397         /* SYSMMU is in blocked state when interrupt occurred. */
 398         struct sysmmu_drvdata *data = dev_id;
 399         const struct sysmmu_fault_info *finfo;
 400         unsigned int i, n, itype;
 401         sysmmu_iova_t fault_addr = -1;
 402         unsigned short reg_status, reg_clear;
 403         int ret = -ENOSYS;
 404
 405         WARN_ON(!data->active);
 406
 407         if (MMU_MAJ_VER(data->version) < 5) {
 408                 reg_status = REG_INT_STATUS;
 409                 reg_clear = REG_INT_CLEAR;
 410                 finfo = sysmmu_faults;
 411                 n = ARRAY_SIZE(sysmmu_faults);
 412         } else {
 413                 reg_status = REG_V5_INT_STATUS;
 414                 reg_clear = REG_V5_INT_CLEAR;
 415                 finfo = sysmmu_v5_faults;
 416                 n = ARRAY_SIZE(sysmmu_v5_faults);
 417         }
 418
 419         spin_lock(&data->lock);
 420
 421         clk_enable(data->clk_master);
 422
 423         itype = __ffs(readl(data->sfrbase + reg_status));
 424         for (i = 0; i < n; i++, finfo++)
 425                 if (finfo->bit == itype)
 426                         break;
 427         /* unknown/unsupported fault */
 428         BUG_ON(i == n);
 429
 430         /* print debug message */
 431         fault_addr = readl(data->sfrbase + finfo->addr_reg);
 432         show_fault_information(data, finfo, fault_addr);
 433
 434         if (data->domain)
 435                 ret = report_iommu_fault(&data->domain->domain,
 436                                         data->master, fault_addr, finfo->type);
 437         /* fault is not recovered by fault handler */
 438         BUG_ON(ret != 0);
 439
 440         writel(1 << itype, data->sfrbase + reg_clear);
 441
 442         sysmmu_unblock(data);
 443
 444         clk_disable(data->clk_master);
 445
 446         spin_unlock(&data->lock);
 447
 448         return IRQ_HANDLED;
 449 }
 450
 451 static void __sysmmu_disable(struct sysmmu_drvdata *data)
 452 {
 453         unsigned long flags;
 454
 455         clk_enable(data->clk_master);
 456
 457         spin_lock_irqsave(&data->lock, flags);
 458         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 459         writel(0, data->sfrbase + REG_MMU_CFG);
 460         data->active = false;
 461         spin_unlock_irqrestore(&data->lock, flags);
 462
 463         __sysmmu_disable_clocks(data);
 464 }
 465
 466 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 467 {
 468         unsigned int cfg;
 469
 470         if (data->version <= MAKE_MMU_VER(3, 1))
 471                 cfg = CFG_LRU | CFG_QOS(15);
 472         else if (data->version <= MAKE_MMU_VER(3, 2))
 473                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
 474         else
 475                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
 476
 477         cfg |= CFG_EAP; /* enable access protection bits check */
 478
 479         writel(cfg, data->sfrbase + REG_MMU_CFG);
 480 }
 481
 482 static void __sysmmu_enable(struct sysmmu_drvdata *data)
 483 {
 484         unsigned long flags;
 485
 486         __sysmmu_enable_clocks(data);
 487
 488         spin_lock_irqsave(&data->lock, flags);
 489         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 490         __sysmmu_init_config(data);
 491         __sysmmu_set_ptbase(data, data->pgtable);
 492         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 493         data->active = true;
 494         spin_unlock_irqrestore(&data->lock, flags);
 495
 496         /*
 497          * SYSMMU driver keeps master's clock enabled only for the short
 498          * time, while accessing the registers. For performing address
 499          * translation during DMA transaction it relies on the client
 500          * driver to enable it.
 501          */
 502         clk_disable(data->clk_master);
 503 }
 504
 505 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 506                                             sysmmu_iova_t iova)
 507 {
 508         unsigned long flags;
 509
 510         spin_lock_irqsave(&data->lock, flags);
 511         if (data->active && data->version >= MAKE_MMU_VER(3, 3)) {
 512                 clk_enable(data->clk_master);
 513                 __sysmmu_tlb_invalidate_entry(data, iova, 1);
 514                 clk_disable(data->clk_master);
 515         }
 516         spin_unlock_irqrestore(&data->lock, flags);
 517 }
 518
 519 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 520                                         sysmmu_iova_t iova, size_t size)
 521 {
 522         unsigned long flags;
 523
 524         spin_lock_irqsave(&data->lock, flags);
 525         if (data->active) {
 526                 unsigned int num_inv = 1;
 527
 528                 clk_enable(data->clk_master);
 529
 530                 /*
 531                  * L2TLB invalidation required
 532                  * 4KB page: 1 invalidation
 533                  * 64KB page: 16 invalidations
 534                  * 1MB page: 64 invalidations
 535                  * because it is set-associative TLB
 536                  * with 8-way and 64 sets.
 537                  * 1MB page can be cached in one of all sets.
 538                  * 64KB page can be one of 16 consecutive sets.
 539                  */
 540                 if (MMU_MAJ_VER(data->version) == 2)
 541                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 542
 543                 if (sysmmu_block(data)) {
 544                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 545                         sysmmu_unblock(data);
 546                 }
 547                 clk_disable(data->clk_master);
 548         }
 549         spin_unlock_irqrestore(&data->lock, flags);
 550 }
 551
 552 static struct iommu_ops exynos_iommu_ops;
 553
 554 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 555 {
 556         int irq, ret;
 557         struct device *dev = &pdev->dev;
 558         struct sysmmu_drvdata *data;
 559         struct resource *res;
 560
 561         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 562         if (!data)
 563                 return -ENOMEM;
 564
 565         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 566         data->sfrbase = devm_ioremap_resource(dev, res);
 567         if (IS_ERR(data->sfrbase))
 568                 return PTR_ERR(data->sfrbase);
 569
 570         irq = platform_get_irq(pdev, 0);
 571         if (irq <= 0) {
 572                 dev_err(dev, "Unable to find IRQ resource\n");
 573                 return irq;
 574         }
 575
 576         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 577                                 dev_name(dev), data);
 578         if (ret) {
 579                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 580                 return ret;
 581         }
 582
 583         data->clk = devm_clk_get(dev, "sysmmu");
 584         if (PTR_ERR(data->clk) == -ENOENT)
 585                 data->clk = NULL;
 586         else if (IS_ERR(data->clk))
 587                 return PTR_ERR(data->clk);
 588
 589         data->aclk = devm_clk_get(dev, "aclk");
 590         if (PTR_ERR(data->aclk) == -ENOENT)
 591                 data->aclk = NULL;
 592         else if (IS_ERR(data->aclk))
 593                 return PTR_ERR(data->aclk);
 594
 595         data->pclk = devm_clk_get(dev, "pclk");
 596         if (PTR_ERR(data->pclk) == -ENOENT)
 597                 data->pclk = NULL;
 598         else if (IS_ERR(data->pclk))
 599                 return PTR_ERR(data->pclk);
 600
 601         if (!data->clk && (!data->aclk || !data->pclk)) {
 602                 dev_err(dev, "Failed to get device clock(s)!\n");
 603                 return -ENOSYS;
 604         }
 605
 606         data->clk_master = devm_clk_get(dev, "master");
 607         if (PTR_ERR(data->clk_master) == -ENOENT)
 608                 data->clk_master = NULL;
 609         else if (IS_ERR(data->clk_master))
 610                 return PTR_ERR(data->clk_master);
 611
 612         data->sysmmu = dev;
 613         spin_lock_init(&data->lock);
 614
 615         platform_set_drvdata(pdev, data);
 616
 617         __sysmmu_get_version(data);
 618         if (PG_ENT_SHIFT < 0) {
 619                 if (MMU_MAJ_VER(data->version) < 5) {
 620                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
 621                         LV1_PROT = SYSMMU_LV1_PROT;
 622                         LV2_PROT = SYSMMU_LV2_PROT;
 623                 } else {
 624                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
 625                         LV1_PROT = SYSMMU_V5_LV1_PROT;
 626                         LV2_PROT = SYSMMU_V5_LV2_PROT;
 627                 }
 628         }
 629
 630         pm_runtime_enable(dev);
 631
 632         of_iommu_set_ops(dev->of_node, &exynos_iommu_ops);
 633
 634         return 0;
 635 }
 636
 637 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev)
 638 {
 639         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 640         struct device *master = data->master;
 641
 642         if (master) {
 643                 struct exynos_iommu_owner *owner = master->archdata.iommu;
 644
 645                 mutex_lock(&owner->rpm_lock);
 646                 if (data->domain) {
 647                         dev_dbg(data->sysmmu, "saving state\n");
 648                         __sysmmu_disable(data);
 649                 }
 650                 mutex_unlock(&owner->rpm_lock);
 651         }
 652         return 0;
 653 }
 654
 655 static int __maybe_unused exynos_sysmmu_resume(struct device *dev)
 656 {
 657         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 658         struct device *master = data->master;
 659
 660         if (master) {
 661                 struct exynos_iommu_owner *owner = master->archdata.iommu;
 662
 663                 mutex_lock(&owner->rpm_lock);
 664                 if (data->domain) {
 665                         dev_dbg(data->sysmmu, "restoring state\n");
 666                         __sysmmu_enable(data);
 667                 }
 668                 mutex_unlock(&owner->rpm_lock);
 669         }
 670         return 0;
 671 }
 672
 673 static const struct dev_pm_ops sysmmu_pm_ops = {
 674         SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL)
 675         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 676                                 pm_runtime_force_resume)
 677 };
 678
 679 static const struct of_device_id sysmmu_of_match[] __initconst = {
 680         { .compatible   = "samsung,exynos-sysmmu", },
 681         { },
 682 };
 683
 684 static struct platform_driver exynos_sysmmu_driver __refdata = {
 685         .probe  = exynos_sysmmu_probe,
 686         .driver = {
 687                 .name           = "exynos-sysmmu",
 688                 .of_match_table = sysmmu_of_match,
 689                 .pm             = &sysmmu_pm_ops,
 690                 .suppress_bind_attrs = true,
 691         }
 692 };
 693
 694 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 695 {
 696         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 697                                 DMA_TO_DEVICE);
 698         *ent = cpu_to_le32(val);
 699         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 700                                    DMA_TO_DEVICE);
 701 }
 702
 703 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 704 {
 705         struct exynos_iommu_domain *domain;
 706         dma_addr_t handle;
 707         int i;
 708
 709         /* Check if correct PTE offsets are initialized */
 710         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
 711
 712         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 713         if (!domain)
 714                 return NULL;
 715
 716         if (type == IOMMU_DOMAIN_DMA) {
 717                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 718                         goto err_pgtable;
 719         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 720                 goto err_pgtable;
 721         }
 722
 723         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 724         if (!domain->pgtable)
 725                 goto err_dma_cookie;
 726
 727         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 728         if (!domain->lv2entcnt)
 729                 goto err_counter;
 730
 731         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 732         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 733                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 734                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 735                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 736                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 737                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 738                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 739                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 740                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 741         }
 742
 743         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 744                                 DMA_TO_DEVICE);
 745         /* For mapping page table entries we rely on dma == phys */
 746         BUG_ON(handle != virt_to_phys(domain->pgtable));
 747         if (dma_mapping_error(dma_dev, handle))
 748                 goto err_lv2ent;
 749
 750         spin_lock_init(&domain->lock);
 751         spin_lock_init(&domain->pgtablelock);
 752         INIT_LIST_HEAD(&domain->clients);
 753
 754         domain->domain.geometry.aperture_start = 0;
 755         domain->domain.geometry.aperture_end   = ~0UL;
 756         domain->domain.geometry.force_aperture = true;
 757
 758         return &domain->domain;
 759
 760 err_lv2ent:
 761         free_pages((unsigned long)domain->lv2entcnt, 1);
 762 err_counter:
 763         free_pages((unsigned long)domain->pgtable, 2);
 764 err_dma_cookie:
 765         if (type == IOMMU_DOMAIN_DMA)
 766                 iommu_put_dma_cookie(&domain->domain);
 767 err_pgtable:
 768         kfree(domain);
 769         return NULL;
 770 }
 771
 772 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 773 {
 774         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 775         struct sysmmu_drvdata *data, *next;
 776         unsigned long flags;
 777         int i;
 778
 779         WARN_ON(!list_empty(&domain->clients));
 780
 781         spin_lock_irqsave(&domain->lock, flags);
 782
 783         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 784                 spin_lock(&data->lock);
 785                 __sysmmu_disable(data);
 786                 data->pgtable = 0;
 787                 data->domain = NULL;
 788                 list_del_init(&data->domain_node);
 789                 spin_unlock(&data->lock);
 790         }
 791
 792         spin_unlock_irqrestore(&domain->lock, flags);
 793
 794         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 795                 iommu_put_dma_cookie(iommu_domain);
 796
 797         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 798                          DMA_TO_DEVICE);
 799
 800         for (i = 0; i < NUM_LV1ENTRIES; i++)
 801                 if (lv1ent_page(domain->pgtable + i)) {
 802                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 803
 804                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 805                                          DMA_TO_DEVICE);
 806                         kmem_cache_free(lv2table_kmem_cache,
 807                                         phys_to_virt(base));
 808                 }
 809
 810         free_pages((unsigned long)domain->pgtable, 2);
 811         free_pages((unsigned long)domain->lv2entcnt, 1);
 812         kfree(domain);
 813 }
 814
 815 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 816                                     struct device *dev)
 817 {
 818         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 819         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 820         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 821         struct sysmmu_drvdata *data, *next;
 822         unsigned long flags;
 823
 824         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
 825                 return;
 826
 827         mutex_lock(&owner->rpm_lock);
 828
 829         list_for_each_entry(data, &owner->controllers, owner_node) {
 830                 pm_runtime_get_noresume(data->sysmmu);
 831                 if (pm_runtime_active(data->sysmmu))
 832                         __sysmmu_disable(data);
 833                 pm_runtime_put(data->sysmmu);
 834         }
 835
 836         spin_lock_irqsave(&domain->lock, flags);
 837         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 838                 spin_lock(&data->lock);
 839                 data->pgtable = 0;
 840                 data->domain = NULL;
 841                 list_del_init(&data->domain_node);
 842                 spin_unlock(&data->lock);
 843         }
 844         owner->domain = NULL;
 845         spin_unlock_irqrestore(&domain->lock, flags);
 846
 847         mutex_unlock(&owner->rpm_lock);
 848
 849         dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__,
 850                 &pagetable);
 851 }
 852
 853 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 854                                    struct device *dev)
 855 {
 856         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 857         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 858         struct sysmmu_drvdata *data;
 859         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 860         unsigned long flags;
 861
 862         if (!has_sysmmu(dev))
 863                 return -ENODEV;
 864
 865         if (owner->domain)
 866                 exynos_iommu_detach_device(owner->domain, dev);
 867
 868         mutex_lock(&owner->rpm_lock);
 869
 870         spin_lock_irqsave(&domain->lock, flags);
 871         list_for_each_entry(data, &owner->controllers, owner_node) {
 872                 spin_lock(&data->lock);
 873                 data->pgtable = pagetable;
 874                 data->domain = domain;
 875                 list_add_tail(&data->domain_node, &domain->clients);
 876                 spin_unlock(&data->lock);
 877         }
 878         owner->domain = iommu_domain;
 879         spin_unlock_irqrestore(&domain->lock, flags);
 880
 881         list_for_each_entry(data, &owner->controllers, owner_node) {
 882                 pm_runtime_get_noresume(data->sysmmu);
 883                 if (pm_runtime_active(data->sysmmu))
 884                         __sysmmu_enable(data);
 885                 pm_runtime_put(data->sysmmu);
 886         }
 887
 888         mutex_unlock(&owner->rpm_lock);
 889
 890         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__,
 891                 &pagetable);
 892
 893         return 0;
 894 }
 895
 896 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 897                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 898 {
 899         if (lv1ent_section(sent)) {
 900                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 901                 return ERR_PTR(-EADDRINUSE);
 902         }
 903
 904         if (lv1ent_fault(sent)) {
 905                 dma_addr_t handle;
 906                 sysmmu_pte_t *pent;
 907                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 908
 909                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 910                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
 911                 if (!pent)
 912                         return ERR_PTR(-ENOMEM);
 913
 914                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 915                 kmemleak_ignore(pent);
 916                 *pgcounter = NUM_LV2ENTRIES;
 917                 handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE,
 918                                         DMA_TO_DEVICE);
 919                 if (dma_mapping_error(dma_dev, handle)) {
 920                         kmem_cache_free(lv2table_kmem_cache, pent);
 921                         return ERR_PTR(-EADDRINUSE);
 922                 }
 923
 924                 /*
 925                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 926                  * FLPD cache may cache the address of zero_l2_table. This
 927                  * function replaces the zero_l2_table with new L2 page table
 928                  * to write valid mappings.
 929                  * Accessing the valid area may cause page fault since FLPD
 930                  * cache may still cache zero_l2_table for the valid area
 931                  * instead of new L2 page table that has the mapping
 932                  * information of the valid area.
 933                  * Thus any replacement of zero_l2_table with other valid L2
 934                  * page table must involve FLPD cache invalidation for System
 935                  * MMU v3.3.
 936                  * FLPD cache invalidation is performed with TLB invalidation
 937                  * by VPN without blocking. It is safe to invalidate TLB without
 938                  * blocking because the target address of TLB invalidation is
 939                  * not currently mapped.
 940                  */
 941                 if (need_flush_flpd_cache) {
 942                         struct sysmmu_drvdata *data;
 943
 944                         spin_lock(&domain->lock);
 945                         list_for_each_entry(data, &domain->clients, domain_node)
 946                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 947                         spin_unlock(&domain->lock);
 948                 }
 949         }
 950
 951         return page_entry(sent, iova);
 952 }
 953
 954 static int lv1set_section(struct exynos_iommu_domain *domain,
 955                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 956                           phys_addr_t paddr, int prot, short *pgcnt)
 957 {
 958         if (lv1ent_section(sent)) {
 959                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 960                         iova);
 961                 return -EADDRINUSE;
 962         }
 963
 964         if (lv1ent_page(sent)) {
 965                 if (*pgcnt != NUM_LV2ENTRIES) {
 966                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 967                                 iova);
 968                         return -EADDRINUSE;
 969                 }
 970
 971                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 972                 *pgcnt = 0;
 973         }
 974
 975         update_pte(sent, mk_lv1ent_sect(paddr, prot));
 976
 977         spin_lock(&domain->lock);
 978         if (lv1ent_page_zero(sent)) {
 979                 struct sysmmu_drvdata *data;
 980                 /*
 981                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 982                  * entry by speculative prefetch of SLPD which has no mapping.
 983                  */
 984                 list_for_each_entry(data, &domain->clients, domain_node)
 985                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 986         }
 987         spin_unlock(&domain->lock);
 988
 989         return 0;
 990 }
 991
 992 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 993                        int prot, short *pgcnt)
 994 {
 995         if (size == SPAGE_SIZE) {
 996                 if (WARN_ON(!lv2ent_fault(pent)))
 997                         return -EADDRINUSE;
 998
 999                 update_pte(pent, mk_lv2ent_spage(paddr, prot));
1000                 *pgcnt -= 1;
1001         } else { /* size == LPAGE_SIZE */
1002                 int i;
1003                 dma_addr_t pent_base = virt_to_phys(pent);
1004
1005                 dma_sync_single_for_cpu(dma_dev, pent_base,
1006                                         sizeof(*pent) * SPAGES_PER_LPAGE,
1007                                         DMA_TO_DEVICE);
1008                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
1009                         if (WARN_ON(!lv2ent_fault(pent))) {
1010                                 if (i > 0)
1011                                         memset(pent - i, 0, sizeof(*pent) * i);
1012                                 return -EADDRINUSE;
1013                         }
1014
1015                         *pent = mk_lv2ent_lpage(paddr, prot);
1016                 }
1017                 dma_sync_single_for_device(dma_dev, pent_base,
1018                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1019                                            DMA_TO_DEVICE);
1020                 *pgcnt -= SPAGES_PER_LPAGE;
1021         }
1022
1023         return 0;
1024 }
1025
1026 /*
1027  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1028  *
1029  * System MMU v3.x has advanced logic to improve address translation
1030  * performance with caching more page table entries by a page table walk.
1031  * However, the logic has a bug that while caching faulty page table entries,
1032  * System MMU reports page fault if the cached fault entry is hit even though
1033  * the fault entry is updated to a valid entry after the entry is cached.
1034  * To prevent caching faulty page table entries which may be updated to valid
1035  * entries later, the virtual memory manager should care about the workaround
1036  * for the problem. The following describes the workaround.
1037  *
1038  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1039  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1040  *
1041  * Precisely, any start address of I/O virtual region must be aligned with
1042  * the following sizes for System MMU v3.1 and v3.2.
1043  * System MMU v3.1: 128KiB
1044  * System MMU v3.2: 256KiB
1045  *
1046  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1047  * more workarounds.
1048  * - Any two consecutive I/O virtual regions must have a hole of size larger
1049  *   than or equal to 128KiB.
1050  * - Start address of an I/O virtual region must be aligned by 128KiB.
1051  */
1052 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1053                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1054                             int prot)
1055 {
1056         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1057         sysmmu_pte_t *entry;
1058         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1059         unsigned long flags;
1060         int ret = -ENOMEM;
1061
1062         BUG_ON(domain->pgtable == NULL);
1063         prot &= SYSMMU_SUPPORTED_PROT_BITS;
1064
1065         spin_lock_irqsave(&domain->pgtablelock, flags);
1066
1067         entry = section_entry(domain->pgtable, iova);
1068
1069         if (size == SECT_SIZE) {
1070                 ret = lv1set_section(domain, entry, iova, paddr, prot,
1071                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1072         } else {
1073                 sysmmu_pte_t *pent;
1074
1075                 pent = alloc_lv2entry(domain, entry, iova,
1076                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1077
1078                 if (IS_ERR(pent))
1079                         ret = PTR_ERR(pent);
1080                 else
1081                         ret = lv2set_page(pent, paddr, size, prot,
1082                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1083         }
1084
1085         if (ret)
1086                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1087                         __func__, ret, size, iova);
1088
1089         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1090
1091         return ret;
1092 }
1093
1094 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1095                                               sysmmu_iova_t iova, size_t size)
1096 {
1097         struct sysmmu_drvdata *data;
1098         unsigned long flags;
1099
1100         spin_lock_irqsave(&domain->lock, flags);
1101
1102         list_for_each_entry(data, &domain->clients, domain_node)
1103                 sysmmu_tlb_invalidate_entry(data, iova, size);
1104
1105         spin_unlock_irqrestore(&domain->lock, flags);
1106 }
1107
1108 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1109                                  unsigned long l_iova, size_t size)
1110 {
1111         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1112         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1113         sysmmu_pte_t *ent;
1114         size_t err_pgsize;
1115         unsigned long flags;
1116
1117         BUG_ON(domain->pgtable == NULL);
1118
1119         spin_lock_irqsave(&domain->pgtablelock, flags);
1120
1121         ent = section_entry(domain->pgtable, iova);
1122
1123         if (lv1ent_section(ent)) {
1124                 if (WARN_ON(size < SECT_SIZE)) {
1125                         err_pgsize = SECT_SIZE;
1126                         goto err;
1127                 }
1128
1129                 /* workaround for h/w bug in System MMU v3.3 */
1130                 update_pte(ent, ZERO_LV2LINK);
1131                 size = SECT_SIZE;
1132                 goto done;
1133         }
1134
1135         if (unlikely(lv1ent_fault(ent))) {
1136                 if (size > SECT_SIZE)
1137                         size = SECT_SIZE;
1138                 goto done;
1139         }
1140
1141         /* lv1ent_page(sent) == true here */
1142
1143         ent = page_entry(ent, iova);
1144
1145         if (unlikely(lv2ent_fault(ent))) {
1146                 size = SPAGE_SIZE;
1147                 goto done;
1148         }
1149
1150         if (lv2ent_small(ent)) {
1151                 update_pte(ent, 0);
1152                 size = SPAGE_SIZE;
1153                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1154                 goto done;
1155         }
1156
1157         /* lv1ent_large(ent) == true here */
1158         if (WARN_ON(size < LPAGE_SIZE)) {
1159                 err_pgsize = LPAGE_SIZE;
1160                 goto err;
1161         }
1162
1163         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1164                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1165                                 DMA_TO_DEVICE);
1166         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1167         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1168                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1169                                    DMA_TO_DEVICE);
1170         size = LPAGE_SIZE;
1171         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1172 done:
1173         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1174
1175         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1176
1177         return size;
1178 err:
1179         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1180
1181         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1182                 __func__, size, iova, err_pgsize);
1183
1184         return 0;
1185 }
1186
1187 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1188                                           dma_addr_t iova)
1189 {
1190         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1191         sysmmu_pte_t *entry;
1192         unsigned long flags;
1193         phys_addr_t phys = 0;
1194
1195         spin_lock_irqsave(&domain->pgtablelock, flags);
1196
1197         entry = section_entry(domain->pgtable, iova);
1198
1199         if (lv1ent_section(entry)) {
1200                 phys = section_phys(entry) + section_offs(iova);
1201         } else if (lv1ent_page(entry)) {
1202                 entry = page_entry(entry, iova);
1203
1204                 if (lv2ent_large(entry))
1205                         phys = lpage_phys(entry) + lpage_offs(iova);
1206                 else if (lv2ent_small(entry))
1207                         phys = spage_phys(entry) + spage_offs(iova);
1208         }
1209
1210         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1211
1212         return phys;
1213 }
1214
1215 static struct iommu_group *get_device_iommu_group(struct device *dev)
1216 {
1217         struct iommu_group *group;
1218
1219         group = iommu_group_get(dev);
1220         if (!group)
1221                 group = iommu_group_alloc();
1222
1223         return group;
1224 }
1225
1226 static int exynos_iommu_add_device(struct device *dev)
1227 {
1228         struct iommu_group *group;
1229
1230         if (!has_sysmmu(dev))
1231                 return -ENODEV;
1232
1233         group = iommu_group_get_for_dev(dev);
1234
1235         if (IS_ERR(group))
1236                 return PTR_ERR(group);
1237
1238         iommu_group_put(group);
1239
1240         return 0;
1241 }
1242
1243 static void exynos_iommu_remove_device(struct device *dev)
1244 {
1245         if (!has_sysmmu(dev))
1246                 return;
1247
1248         iommu_group_remove_device(dev);
1249 }
1250
1251 static int exynos_iommu_of_xlate(struct device *dev,
1252                                  struct of_phandle_args *spec)
1253 {
1254         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1255         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1256         struct sysmmu_drvdata *data;
1257
1258         if (!sysmmu)
1259                 return -ENODEV;
1260
1261         data = platform_get_drvdata(sysmmu);
1262         if (!data)
1263                 return -ENODEV;
1264
1265         if (!owner) {
1266                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1267                 if (!owner)
1268                         return -ENOMEM;
1269
1270                 INIT_LIST_HEAD(&owner->controllers);
1271                 mutex_init(&owner->rpm_lock);
1272                 dev->archdata.iommu = owner;
1273         }
1274
1275         list_add_tail(&data->owner_node, &owner->controllers);
1276         data->master = dev;
1277
1278         /*
1279          * SYSMMU will be runtime activated via device link (dependency) to its
1280          * master device, so there are no direct calls to pm_runtime_get/put
1281          * in this driver.
1282          */
1283         device_link_add(dev, data->sysmmu, DL_FLAG_PM_RUNTIME);
1284
1285         return 0;
1286 }
1287
1288 static struct iommu_ops exynos_iommu_ops = {
1289         .domain_alloc = exynos_iommu_domain_alloc,
1290         .domain_free = exynos_iommu_domain_free,
1291         .attach_dev = exynos_iommu_attach_device,
1292         .detach_dev = exynos_iommu_detach_device,
1293         .map = exynos_iommu_map,
1294         .unmap = exynos_iommu_unmap,
1295         .map_sg = default_iommu_map_sg,
1296         .iova_to_phys = exynos_iommu_iova_to_phys,
1297         .device_group = get_device_iommu_group,
1298         .add_device = exynos_iommu_add_device,
1299         .remove_device = exynos_iommu_remove_device,
1300         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1301         .of_xlate = exynos_iommu_of_xlate,
1302 };
1303
1304 static bool init_done;
1305
1306 static int __init exynos_iommu_init(void)
1307 {
1308         int ret;
1309
1310         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1311                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1312         if (!lv2table_kmem_cache) {
1313                 pr_err("%s: Failed to create kmem cache\n", __func__);
1314                 return -ENOMEM;
1315         }
1316
1317         ret = platform_driver_register(&exynos_sysmmu_driver);
1318         if (ret) {
1319                 pr_err("%s: Failed to register driver\n", __func__);
1320                 goto err_reg_driver;
1321         }
1322
1323         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1324         if (zero_lv2_table == NULL) {
1325                 pr_err("%s: Failed to allocate zero level2 page table\n",
1326                         __func__);
1327                 ret = -ENOMEM;
1328                 goto err_zero_lv2;
1329         }
1330
1331         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1332         if (ret) {
1333                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1334                                                                 __func__);
1335                 goto err_set_iommu;
1336         }
1337
1338         init_done = true;
1339
1340         return 0;
1341 err_set_iommu:
1342         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1343 err_zero_lv2:
1344         platform_driver_unregister(&exynos_sysmmu_driver);
1345 err_reg_driver:
1346         kmem_cache_destroy(lv2table_kmem_cache);
1347         return ret;
1348 }
1349
1350 static int __init exynos_iommu_of_setup(struct device_node *np)
1351 {
1352         struct platform_device *pdev;
1353
1354         if (!init_done)
1355                 exynos_iommu_init();
1356
1357         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1358         if (!pdev)
1359                 return -ENODEV;
1360
1361         /*
1362          * use the first registered sysmmu device for performing
1363          * dma mapping operations on iommu page tables (cpu cache flush)
1364          */
1365         if (!dma_dev)
1366                 dma_dev = &pdev->dev;
1367
1368         return 0;
1369 }
1370
1371 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1372                  exynos_iommu_of_setup);