drivers/iommu/exynos-iommu.c

   1 /*
   2  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  11 #define DEBUG
  12 #endif
  13
  14 #include <linux/clk.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/iommu.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/of.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/slab.h>
  27 #include <linux/dma-iommu.h>
  28
  29 typedef u32 sysmmu_iova_t;
  30 typedef u32 sysmmu_pte_t;
  31
  32 /* We do not consider super section mapping (16MB) */
  33 #define SECT_ORDER 20
  34 #define LPAGE_ORDER 16
  35 #define SPAGE_ORDER 12
  36
  37 #define SECT_SIZE (1 << SECT_ORDER)
  38 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  39 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  40
  41 #define SECT_MASK (~(SECT_SIZE - 1))
  42 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  43 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  44
  45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  46                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  50                           ((*(sent) & 3) == 1))
  51 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  52
  53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  54 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  55 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  56
  57 #ifdef CONFIG_BIG_ENDIAN
  58 #warning "revisit driver if we can enable big-endian ptes"
  59 #endif
  60
  61 /*
  62  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  63  * v5.0 introduced support for 36bit physical address space by shifting
  64  * all page entry values by 4 bits.
  65  * All SYSMMU controllers in the system support the address spaces of the same
  66  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  67  * value (0 or 4).
  68  */
  69 static short PG_ENT_SHIFT = -1;
  70 #define SYSMMU_PG_ENT_SHIFT 0
  71 #define SYSMMU_V5_PG_ENT_SHIFT 4
  72
  73 static const sysmmu_pte_t *LV1_PROT;
  74 static const sysmmu_pte_t SYSMMU_LV1_PROT[] = {
  75         ((0 << 15) | (0 << 10)), /* no access */
  76         ((1 << 15) | (1 << 10)), /* IOMMU_READ only */
  77         ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
  78         ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
  79 };
  80 static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = {
  81         (0 << 4), /* no access */
  82         (1 << 4), /* IOMMU_READ only */
  83         (2 << 4), /* IOMMU_WRITE only */
  84         (3 << 4), /* IOMMU_READ | IOMMU_WRITE */
  85 };
  86
  87 static const sysmmu_pte_t *LV2_PROT;
  88 static const sysmmu_pte_t SYSMMU_LV2_PROT[] = {
  89         ((0 << 9) | (0 << 4)), /* no access */
  90         ((1 << 9) | (1 << 4)), /* IOMMU_READ only */
  91         ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
  92         ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
  93 };
  94 static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = {
  95         (0 << 2), /* no access */
  96         (1 << 2), /* IOMMU_READ only */
  97         (2 << 2), /* IOMMU_WRITE only */
  98         (3 << 2), /* IOMMU_READ | IOMMU_WRITE */
  99 };
 100
 101 #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE)
 102
 103 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
 104 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
 105 #define section_offs(iova) (iova & (SECT_SIZE - 1))
 106 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
 107 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
 108 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
 109 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
 110
 111 #define NUM_LV1ENTRIES 4096
 112 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
 113
 114 static u32 lv1ent_offset(sysmmu_iova_t iova)
 115 {
 116         return iova >> SECT_ORDER;
 117 }
 118
 119 static u32 lv2ent_offset(sysmmu_iova_t iova)
 120 {
 121         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
 122 }
 123
 124 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
 125 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
 126
 127 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
 128 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
 129
 130 #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2)
 131 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
 132 #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1)
 133 #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2)
 134
 135 #define CTRL_ENABLE     0x5
 136 #define CTRL_BLOCK      0x7
 137 #define CTRL_DISABLE    0x0
 138
 139 #define CFG_LRU         0x1
 140 #define CFG_EAP         (1 << 2)
 141 #define CFG_QOS(n)      ((n & 0xF) << 7)
 142 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 143 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 144 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 145
 146 /* common registers */
 147 #define REG_MMU_CTRL            0x000
 148 #define REG_MMU_CFG             0x004
 149 #define REG_MMU_STATUS          0x008
 150 #define REG_MMU_VERSION         0x034
 151
 152 #define MMU_MAJ_VER(val)        ((val) >> 7)
 153 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 154 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 155
 156 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 157
 158 /* v1.x - v3.x registers */
 159 #define REG_MMU_FLUSH           0x00C
 160 #define REG_MMU_FLUSH_ENTRY     0x010
 161 #define REG_PT_BASE_ADDR        0x014
 162 #define REG_INT_STATUS          0x018
 163 #define REG_INT_CLEAR           0x01C
 164
 165 #define REG_PAGE_FAULT_ADDR     0x024
 166 #define REG_AW_FAULT_ADDR       0x028
 167 #define REG_AR_FAULT_ADDR       0x02C
 168 #define REG_DEFAULT_SLAVE_ADDR  0x030
 169
 170 /* v5.x registers */
 171 #define REG_V5_PT_BASE_PFN      0x00C
 172 #define REG_V5_MMU_FLUSH_ALL    0x010
 173 #define REG_V5_MMU_FLUSH_ENTRY  0x014
 174 #define REG_V5_INT_STATUS       0x060
 175 #define REG_V5_INT_CLEAR        0x064
 176 #define REG_V5_FAULT_AR_VA      0x070
 177 #define REG_V5_FAULT_AW_VA      0x080
 178
 179 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 180
 181 static struct device *dma_dev;
 182 static struct kmem_cache *lv2table_kmem_cache;
 183 static sysmmu_pte_t *zero_lv2_table;
 184 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 185
 186 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 187 {
 188         return pgtable + lv1ent_offset(iova);
 189 }
 190
 191 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 192 {
 193         return (sysmmu_pte_t *)phys_to_virt(
 194                                 lv2table_base(sent)) + lv2ent_offset(iova);
 195 }
 196
 197 /*
 198  * IOMMU fault information register
 199  */
 200 struct sysmmu_fault_info {
 201         unsigned int bit;       /* bit number in STATUS register */
 202         unsigned short addr_reg; /* register to read VA fault address */
 203         const char *name;       /* human readable fault name */
 204         unsigned int type;      /* fault type for report_iommu_fault */
 205 };
 206
 207 static const struct sysmmu_fault_info sysmmu_faults[] = {
 208         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 209         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 210         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 211         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 212         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 213         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 214         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 215         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 216 };
 217
 218 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
 219         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
 220         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
 221         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
 222         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 223         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 224         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
 225         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
 226         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 227         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 228         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 229 };
 230
 231 /*
 232  * This structure is attached to dev.archdata.iommu of the master device
 233  * on device add, contains a list of SYSMMU controllers defined by device tree,
 234  * which are bound to given master device. It is usually referenced by 'owner'
 235  * pointer.
 236 */
 237 struct exynos_iommu_owner {
 238         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 239         struct iommu_domain *domain;    /* domain this device is attached */
 240         struct mutex rpm_lock;          /* for runtime pm of all sysmmus */
 241 };
 242
 243 /*
 244  * This structure exynos specific generalization of struct iommu_domain.
 245  * It contains list of SYSMMU controllers from all master devices, which has
 246  * been attached to this domain and page tables of IO address space defined by
 247  * it. It is usually referenced by 'domain' pointer.
 248  */
 249 struct exynos_iommu_domain {
 250         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 251         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 252         short *lv2entcnt;       /* free lv2 entry counter for each section */
 253         spinlock_t lock;        /* lock for modyfying list of clients */
 254         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 255         struct iommu_domain domain; /* generic domain data structure */
 256 };
 257
 258 /*
 259  * This structure hold all data of a single SYSMMU controller, this includes
 260  * hw resources like registers and clocks, pointers and list nodes to connect
 261  * it to all other structures, internal state and parameters read from device
 262  * tree. It is usually referenced by 'data' pointer.
 263  */
 264 struct sysmmu_drvdata {
 265         struct device *sysmmu;          /* SYSMMU controller device */
 266         struct device *master;          /* master device (owner) */
 267         void __iomem *sfrbase;          /* our registers */
 268         struct clk *clk;                /* SYSMMU's clock */
 269         struct clk *aclk;               /* SYSMMU's aclk clock */
 270         struct clk *pclk;               /* SYSMMU's pclk clock */
 271         struct clk *clk_master;         /* master's device clock */
 272         spinlock_t lock;                /* lock for modyfying state */
 273         bool active;                    /* current status */
 274         struct exynos_iommu_domain *domain; /* domain we belong to */
 275         struct list_head domain_node;   /* node for domain clients list */
 276         struct list_head owner_node;    /* node for owner controllers list */
 277         phys_addr_t pgtable;            /* assigned page table structure */
 278         unsigned int version;           /* our version */
 279 };
 280
 281 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 282 {
 283         return container_of(dom, struct exynos_iommu_domain, domain);
 284 }
 285
 286 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 287 {
 288         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 289 }
 290
 291 static bool sysmmu_block(struct sysmmu_drvdata *data)
 292 {
 293         int i = 120;
 294
 295         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 296         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
 297                 --i;
 298
 299         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 300                 sysmmu_unblock(data);
 301                 return false;
 302         }
 303
 304         return true;
 305 }
 306
 307 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 308 {
 309         if (MMU_MAJ_VER(data->version) < 5)
 310                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 311         else
 312                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
 313 }
 314
 315 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 316                                 sysmmu_iova_t iova, unsigned int num_inv)
 317 {
 318         unsigned int i;
 319
 320         for (i = 0; i < num_inv; i++) {
 321                 if (MMU_MAJ_VER(data->version) < 5)
 322                         writel((iova & SPAGE_MASK) | 1,
 323                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
 324                 else
 325                         writel((iova & SPAGE_MASK) | 1,
 326                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
 327                 iova += SPAGE_SIZE;
 328         }
 329 }
 330
 331 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 332 {
 333         if (MMU_MAJ_VER(data->version) < 5)
 334                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 335         else
 336                 writel(pgd >> PAGE_SHIFT,
 337                              data->sfrbase + REG_V5_PT_BASE_PFN);
 338
 339         __sysmmu_tlb_invalidate(data);
 340 }
 341
 342 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
 343 {
 344         BUG_ON(clk_prepare_enable(data->clk_master));
 345         BUG_ON(clk_prepare_enable(data->clk));
 346         BUG_ON(clk_prepare_enable(data->pclk));
 347         BUG_ON(clk_prepare_enable(data->aclk));
 348 }
 349
 350 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
 351 {
 352         clk_disable_unprepare(data->aclk);
 353         clk_disable_unprepare(data->pclk);
 354         clk_disable_unprepare(data->clk);
 355         clk_disable_unprepare(data->clk_master);
 356 }
 357
 358 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
 359 {
 360         u32 ver;
 361
 362         __sysmmu_enable_clocks(data);
 363
 364         ver = readl(data->sfrbase + REG_MMU_VERSION);
 365
 366         /* controllers on some SoCs don't report proper version */
 367         if (ver == 0x80000001u)
 368                 data->version = MAKE_MMU_VER(1, 0);
 369         else
 370                 data->version = MMU_RAW_VER(ver);
 371
 372         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
 373                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
 374
 375         __sysmmu_disable_clocks(data);
 376 }
 377
 378 static void show_fault_information(struct sysmmu_drvdata *data,
 379                                    const struct sysmmu_fault_info *finfo,
 380                                    sysmmu_iova_t fault_addr)
 381 {
 382         sysmmu_pte_t *ent;
 383
 384         dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n",
 385                 dev_name(data->master), finfo->name, fault_addr);
 386         dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable);
 387         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 388         dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 389         if (lv1ent_page(ent)) {
 390                 ent = page_entry(ent, fault_addr);
 391                 dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 392         }
 393 }
 394
 395 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 396 {
 397         /* SYSMMU is in blocked state when interrupt occurred. */
 398         struct sysmmu_drvdata *data = dev_id;
 399         const struct sysmmu_fault_info *finfo;
 400         unsigned int i, n, itype;
 401         sysmmu_iova_t fault_addr = -1;
 402         unsigned short reg_status, reg_clear;
 403         int ret = -ENOSYS;
 404
 405         WARN_ON(!data->active);
 406
 407         if (MMU_MAJ_VER(data->version) < 5) {
 408                 reg_status = REG_INT_STATUS;
 409                 reg_clear = REG_INT_CLEAR;
 410                 finfo = sysmmu_faults;
 411                 n = ARRAY_SIZE(sysmmu_faults);
 412         } else {
 413                 reg_status = REG_V5_INT_STATUS;
 414                 reg_clear = REG_V5_INT_CLEAR;
 415                 finfo = sysmmu_v5_faults;
 416                 n = ARRAY_SIZE(sysmmu_v5_faults);
 417         }
 418
 419         spin_lock(&data->lock);
 420
 421         clk_enable(data->clk_master);
 422
 423         itype = __ffs(readl(data->sfrbase + reg_status));
 424         for (i = 0; i < n; i++, finfo++)
 425                 if (finfo->bit == itype)
 426                         break;
 427         /* unknown/unsupported fault */
 428         BUG_ON(i == n);
 429
 430         /* print debug message */
 431         fault_addr = readl(data->sfrbase + finfo->addr_reg);
 432         show_fault_information(data, finfo, fault_addr);
 433
 434         if (data->domain)
 435                 ret = report_iommu_fault(&data->domain->domain,
 436                                         data->master, fault_addr, finfo->type);
 437         /* fault is not recovered by fault handler */
 438         BUG_ON(ret != 0);
 439
 440         writel(1 << itype, data->sfrbase + reg_clear);
 441
 442         sysmmu_unblock(data);
 443
 444         clk_disable(data->clk_master);
 445
 446         spin_unlock(&data->lock);
 447
 448         return IRQ_HANDLED;
 449 }
 450
 451 static void __sysmmu_disable(struct sysmmu_drvdata *data)
 452 {
 453         unsigned long flags;
 454
 455         clk_enable(data->clk_master);
 456
 457         spin_lock_irqsave(&data->lock, flags);
 458         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 459         writel(0, data->sfrbase + REG_MMU_CFG);
 460         data->active = false;
 461         spin_unlock_irqrestore(&data->lock, flags);
 462
 463         __sysmmu_disable_clocks(data);
 464 }
 465
 466 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 467 {
 468         unsigned int cfg;
 469
 470         if (data->version <= MAKE_MMU_VER(3, 1))
 471                 cfg = CFG_LRU | CFG_QOS(15);
 472         else if (data->version <= MAKE_MMU_VER(3, 2))
 473                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
 474         else
 475                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
 476
 477         cfg |= CFG_EAP; /* enable access protection bits check */
 478
 479         writel(cfg, data->sfrbase + REG_MMU_CFG);
 480 }
 481
 482 static void __sysmmu_enable(struct sysmmu_drvdata *data)
 483 {
 484         unsigned long flags;
 485
 486         __sysmmu_enable_clocks(data);
 487
 488         spin_lock_irqsave(&data->lock, flags);
 489         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 490         __sysmmu_init_config(data);
 491         __sysmmu_set_ptbase(data, data->pgtable);
 492         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 493         data->active = true;
 494         spin_unlock_irqrestore(&data->lock, flags);
 495
 496         /*
 497          * SYSMMU driver keeps master's clock enabled only for the short
 498          * time, while accessing the registers. For performing address
 499          * translation during DMA transaction it relies on the client
 500          * driver to enable it.
 501          */
 502         clk_disable(data->clk_master);
 503 }
 504
 505 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 506                                             sysmmu_iova_t iova)
 507 {
 508         unsigned long flags;
 509
 510         spin_lock_irqsave(&data->lock, flags);
 511         if (data->active && data->version >= MAKE_MMU_VER(3, 3)) {
 512                 clk_enable(data->clk_master);
 513                 __sysmmu_tlb_invalidate_entry(data, iova, 1);
 514                 clk_disable(data->clk_master);
 515         }
 516         spin_unlock_irqrestore(&data->lock, flags);
 517 }
 518
 519 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 520                                         sysmmu_iova_t iova, size_t size)
 521 {
 522         unsigned long flags;
 523
 524         spin_lock_irqsave(&data->lock, flags);
 525         if (data->active) {
 526                 unsigned int num_inv = 1;
 527
 528                 clk_enable(data->clk_master);
 529
 530                 /*
 531                  * L2TLB invalidation required
 532                  * 4KB page: 1 invalidation
 533                  * 64KB page: 16 invalidations
 534                  * 1MB page: 64 invalidations
 535                  * because it is set-associative TLB
 536                  * with 8-way and 64 sets.
 537                  * 1MB page can be cached in one of all sets.
 538                  * 64KB page can be one of 16 consecutive sets.
 539                  */
 540                 if (MMU_MAJ_VER(data->version) == 2)
 541                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 542
 543                 if (sysmmu_block(data)) {
 544                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 545                         sysmmu_unblock(data);
 546                 }
 547                 clk_disable(data->clk_master);
 548         }
 549         spin_unlock_irqrestore(&data->lock, flags);
 550 }
 551
 552 static struct iommu_ops exynos_iommu_ops;
 553
 554 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 555 {
 556         int irq, ret;
 557         struct device *dev = &pdev->dev;
 558         struct sysmmu_drvdata *data;
 559         struct resource *res;
 560
 561         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 562         if (!data)
 563                 return -ENOMEM;
 564
 565         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 566         data->sfrbase = devm_ioremap_resource(dev, res);
 567         if (IS_ERR(data->sfrbase))
 568                 return PTR_ERR(data->sfrbase);
 569
 570         irq = platform_get_irq(pdev, 0);
 571         if (irq <= 0) {
 572                 dev_err(dev, "Unable to find IRQ resource\n");
 573                 return irq;
 574         }
 575
 576         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 577                                 dev_name(dev), data);
 578         if (ret) {
 579                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 580                 return ret;
 581         }
 582
 583         data->clk = devm_clk_get(dev, "sysmmu");
 584         if (PTR_ERR(data->clk) == -ENOENT)
 585                 data->clk = NULL;
 586         else if (IS_ERR(data->clk))
 587                 return PTR_ERR(data->clk);
 588
 589         data->aclk = devm_clk_get(dev, "aclk");
 590         if (PTR_ERR(data->aclk) == -ENOENT)
 591                 data->aclk = NULL;
 592         else if (IS_ERR(data->aclk))
 593                 return PTR_ERR(data->aclk);
 594
 595         data->pclk = devm_clk_get(dev, "pclk");
 596         if (PTR_ERR(data->pclk) == -ENOENT)
 597                 data->pclk = NULL;
 598         else if (IS_ERR(data->pclk))
 599                 return PTR_ERR(data->pclk);
 600
 601         if (!data->clk && (!data->aclk || !data->pclk)) {
 602                 dev_err(dev, "Failed to get device clock(s)!\n");
 603                 return -ENOSYS;
 604         }
 605
 606         data->clk_master = devm_clk_get(dev, "master");
 607         if (PTR_ERR(data->clk_master) == -ENOENT)
 608                 data->clk_master = NULL;
 609         else if (IS_ERR(data->clk_master))
 610                 return PTR_ERR(data->clk_master);
 611
 612         data->sysmmu = dev;
 613         spin_lock_init(&data->lock);
 614
 615         platform_set_drvdata(pdev, data);
 616
 617         __sysmmu_get_version(data);
 618         if (PG_ENT_SHIFT < 0) {
 619                 if (MMU_MAJ_VER(data->version) < 5) {
 620                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
 621                         LV1_PROT = SYSMMU_LV1_PROT;
 622                         LV2_PROT = SYSMMU_LV2_PROT;
 623                 } else {
 624                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
 625                         LV1_PROT = SYSMMU_V5_LV1_PROT;
 626                         LV2_PROT = SYSMMU_V5_LV2_PROT;
 627                 }
 628         }
 629
 630         pm_runtime_enable(dev);
 631
 632         of_iommu_set_ops(dev->of_node, &exynos_iommu_ops);
 633
 634         return 0;
 635 }
 636
 637 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev)
 638 {
 639         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 640         struct device *master = data->master;
 641
 642         if (master) {
 643                 struct exynos_iommu_owner *owner = master->archdata.iommu;
 644
 645                 mutex_lock(&owner->rpm_lock);
 646                 if (data->domain) {
 647                         dev_dbg(data->sysmmu, "saving state\n");
 648                         __sysmmu_disable(data);
 649                 }
 650                 mutex_unlock(&owner->rpm_lock);
 651         }
 652         return 0;
 653 }
 654
 655 static int __maybe_unused exynos_sysmmu_resume(struct device *dev)
 656 {
 657         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 658         struct device *master = data->master;
 659
 660         if (master) {
 661                 struct exynos_iommu_owner *owner = master->archdata.iommu;
 662
 663                 mutex_lock(&owner->rpm_lock);
 664                 if (data->domain) {
 665                         dev_dbg(data->sysmmu, "restoring state\n");
 666                         __sysmmu_enable(data);
 667                 }
 668                 mutex_unlock(&owner->rpm_lock);
 669         }
 670         return 0;
 671 }
 672
 673 static const struct dev_pm_ops sysmmu_pm_ops = {
 674         SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL)
 675         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 676                                 pm_runtime_force_resume)
 677 };
 678
 679 static const struct of_device_id sysmmu_of_match[] __initconst = {
 680         { .compatible   = "samsung,exynos-sysmmu", },
 681         { },
 682 };
 683
 684 static struct platform_driver exynos_sysmmu_driver __refdata = {
 685         .probe  = exynos_sysmmu_probe,
 686         .driver = {
 687                 .name           = "exynos-sysmmu",
 688                 .of_match_table = sysmmu_of_match,
 689                 .pm             = &sysmmu_pm_ops,
 690                 .suppress_bind_attrs = true,
 691         }
 692 };
 693
 694 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 695 {
 696         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 697                                 DMA_TO_DEVICE);
 698         *ent = cpu_to_le32(val);
 699         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 700                                    DMA_TO_DEVICE);
 701 }
 702
 703 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 704 {
 705         struct exynos_iommu_domain *domain;
 706         dma_addr_t handle;
 707         int i;
 708
 709         /* Check if correct PTE offsets are initialized */
 710         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
 711
 712         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 713         if (!domain)
 714                 return NULL;
 715
 716         if (type == IOMMU_DOMAIN_DMA) {
 717                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 718                         goto err_pgtable;
 719         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 720                 goto err_pgtable;
 721         }
 722
 723         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 724         if (!domain->pgtable)
 725                 goto err_dma_cookie;
 726
 727         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 728         if (!domain->lv2entcnt)
 729                 goto err_counter;
 730
 731         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 732         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 733                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 734                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 735                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 736                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 737                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 738                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 739                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 740                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 741         }
 742
 743         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 744                                 DMA_TO_DEVICE);
 745         /* For mapping page table entries we rely on dma == phys */
 746         BUG_ON(handle != virt_to_phys(domain->pgtable));
 747
 748         spin_lock_init(&domain->lock);
 749         spin_lock_init(&domain->pgtablelock);
 750         INIT_LIST_HEAD(&domain->clients);
 751
 752         domain->domain.geometry.aperture_start = 0;
 753         domain->domain.geometry.aperture_end   = ~0UL;
 754         domain->domain.geometry.force_aperture = true;
 755
 756         return &domain->domain;
 757
 758 err_counter:
 759         free_pages((unsigned long)domain->pgtable, 2);
 760 err_dma_cookie:
 761         if (type == IOMMU_DOMAIN_DMA)
 762                 iommu_put_dma_cookie(&domain->domain);
 763 err_pgtable:
 764         kfree(domain);
 765         return NULL;
 766 }
 767
 768 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 769 {
 770         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 771         struct sysmmu_drvdata *data, *next;
 772         unsigned long flags;
 773         int i;
 774
 775         WARN_ON(!list_empty(&domain->clients));
 776
 777         spin_lock_irqsave(&domain->lock, flags);
 778
 779         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 780                 spin_lock(&data->lock);
 781                 __sysmmu_disable(data);
 782                 data->pgtable = 0;
 783                 data->domain = NULL;
 784                 list_del_init(&data->domain_node);
 785                 spin_unlock(&data->lock);
 786         }
 787
 788         spin_unlock_irqrestore(&domain->lock, flags);
 789
 790         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 791                 iommu_put_dma_cookie(iommu_domain);
 792
 793         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 794                          DMA_TO_DEVICE);
 795
 796         for (i = 0; i < NUM_LV1ENTRIES; i++)
 797                 if (lv1ent_page(domain->pgtable + i)) {
 798                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 799
 800                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 801                                          DMA_TO_DEVICE);
 802                         kmem_cache_free(lv2table_kmem_cache,
 803                                         phys_to_virt(base));
 804                 }
 805
 806         free_pages((unsigned long)domain->pgtable, 2);
 807         free_pages((unsigned long)domain->lv2entcnt, 1);
 808         kfree(domain);
 809 }
 810
 811 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 812                                     struct device *dev)
 813 {
 814         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 815         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 816         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 817         struct sysmmu_drvdata *data, *next;
 818         unsigned long flags;
 819
 820         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
 821                 return;
 822
 823         mutex_lock(&owner->rpm_lock);
 824
 825         list_for_each_entry(data, &owner->controllers, owner_node) {
 826                 pm_runtime_get_noresume(data->sysmmu);
 827                 if (pm_runtime_active(data->sysmmu))
 828                         __sysmmu_disable(data);
 829                 pm_runtime_put(data->sysmmu);
 830         }
 831
 832         spin_lock_irqsave(&domain->lock, flags);
 833         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 834                 spin_lock(&data->lock);
 835                 data->pgtable = 0;
 836                 data->domain = NULL;
 837                 list_del_init(&data->domain_node);
 838                 spin_unlock(&data->lock);
 839         }
 840         owner->domain = NULL;
 841         spin_unlock_irqrestore(&domain->lock, flags);
 842
 843         mutex_unlock(&owner->rpm_lock);
 844
 845         dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__,
 846                 &pagetable);
 847 }
 848
 849 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 850                                    struct device *dev)
 851 {
 852         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 853         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 854         struct sysmmu_drvdata *data;
 855         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 856         unsigned long flags;
 857
 858         if (!has_sysmmu(dev))
 859                 return -ENODEV;
 860
 861         if (owner->domain)
 862                 exynos_iommu_detach_device(owner->domain, dev);
 863
 864         mutex_lock(&owner->rpm_lock);
 865
 866         spin_lock_irqsave(&domain->lock, flags);
 867         list_for_each_entry(data, &owner->controllers, owner_node) {
 868                 spin_lock(&data->lock);
 869                 data->pgtable = pagetable;
 870                 data->domain = domain;
 871                 list_add_tail(&data->domain_node, &domain->clients);
 872                 spin_unlock(&data->lock);
 873         }
 874         owner->domain = iommu_domain;
 875         spin_unlock_irqrestore(&domain->lock, flags);
 876
 877         list_for_each_entry(data, &owner->controllers, owner_node) {
 878                 pm_runtime_get_noresume(data->sysmmu);
 879                 if (pm_runtime_active(data->sysmmu))
 880                         __sysmmu_enable(data);
 881                 pm_runtime_put(data->sysmmu);
 882         }
 883
 884         mutex_unlock(&owner->rpm_lock);
 885
 886         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__,
 887                 &pagetable);
 888
 889         return 0;
 890 }
 891
 892 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 893                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 894 {
 895         if (lv1ent_section(sent)) {
 896                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 897                 return ERR_PTR(-EADDRINUSE);
 898         }
 899
 900         if (lv1ent_fault(sent)) {
 901                 sysmmu_pte_t *pent;
 902                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 903
 904                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 905                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
 906                 if (!pent)
 907                         return ERR_PTR(-ENOMEM);
 908
 909                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 910                 kmemleak_ignore(pent);
 911                 *pgcounter = NUM_LV2ENTRIES;
 912                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
 913
 914                 /*
 915                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 916                  * FLPD cache may cache the address of zero_l2_table. This
 917                  * function replaces the zero_l2_table with new L2 page table
 918                  * to write valid mappings.
 919                  * Accessing the valid area may cause page fault since FLPD
 920                  * cache may still cache zero_l2_table for the valid area
 921                  * instead of new L2 page table that has the mapping
 922                  * information of the valid area.
 923                  * Thus any replacement of zero_l2_table with other valid L2
 924                  * page table must involve FLPD cache invalidation for System
 925                  * MMU v3.3.
 926                  * FLPD cache invalidation is performed with TLB invalidation
 927                  * by VPN without blocking. It is safe to invalidate TLB without
 928                  * blocking because the target address of TLB invalidation is
 929                  * not currently mapped.
 930                  */
 931                 if (need_flush_flpd_cache) {
 932                         struct sysmmu_drvdata *data;
 933
 934                         spin_lock(&domain->lock);
 935                         list_for_each_entry(data, &domain->clients, domain_node)
 936                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 937                         spin_unlock(&domain->lock);
 938                 }
 939         }
 940
 941         return page_entry(sent, iova);
 942 }
 943
 944 static int lv1set_section(struct exynos_iommu_domain *domain,
 945                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 946                           phys_addr_t paddr, int prot, short *pgcnt)
 947 {
 948         if (lv1ent_section(sent)) {
 949                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 950                         iova);
 951                 return -EADDRINUSE;
 952         }
 953
 954         if (lv1ent_page(sent)) {
 955                 if (*pgcnt != NUM_LV2ENTRIES) {
 956                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 957                                 iova);
 958                         return -EADDRINUSE;
 959                 }
 960
 961                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 962                 *pgcnt = 0;
 963         }
 964
 965         update_pte(sent, mk_lv1ent_sect(paddr, prot));
 966
 967         spin_lock(&domain->lock);
 968         if (lv1ent_page_zero(sent)) {
 969                 struct sysmmu_drvdata *data;
 970                 /*
 971                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 972                  * entry by speculative prefetch of SLPD which has no mapping.
 973                  */
 974                 list_for_each_entry(data, &domain->clients, domain_node)
 975                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 976         }
 977         spin_unlock(&domain->lock);
 978
 979         return 0;
 980 }
 981
 982 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 983                        int prot, short *pgcnt)
 984 {
 985         if (size == SPAGE_SIZE) {
 986                 if (WARN_ON(!lv2ent_fault(pent)))
 987                         return -EADDRINUSE;
 988
 989                 update_pte(pent, mk_lv2ent_spage(paddr, prot));
 990                 *pgcnt -= 1;
 991         } else { /* size == LPAGE_SIZE */
 992                 int i;
 993                 dma_addr_t pent_base = virt_to_phys(pent);
 994
 995                 dma_sync_single_for_cpu(dma_dev, pent_base,
 996                                         sizeof(*pent) * SPAGES_PER_LPAGE,
 997                                         DMA_TO_DEVICE);
 998                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
 999                         if (WARN_ON(!lv2ent_fault(pent))) {
1000                                 if (i > 0)
1001                                         memset(pent - i, 0, sizeof(*pent) * i);
1002                                 return -EADDRINUSE;
1003                         }
1004
1005                         *pent = mk_lv2ent_lpage(paddr, prot);
1006                 }
1007                 dma_sync_single_for_device(dma_dev, pent_base,
1008                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1009                                            DMA_TO_DEVICE);
1010                 *pgcnt -= SPAGES_PER_LPAGE;
1011         }
1012
1013         return 0;
1014 }
1015
1016 /*
1017  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1018  *
1019  * System MMU v3.x has advanced logic to improve address translation
1020  * performance with caching more page table entries by a page table walk.
1021  * However, the logic has a bug that while caching faulty page table entries,
1022  * System MMU reports page fault if the cached fault entry is hit even though
1023  * the fault entry is updated to a valid entry after the entry is cached.
1024  * To prevent caching faulty page table entries which may be updated to valid
1025  * entries later, the virtual memory manager should care about the workaround
1026  * for the problem. The following describes the workaround.
1027  *
1028  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1029  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1030  *
1031  * Precisely, any start address of I/O virtual region must be aligned with
1032  * the following sizes for System MMU v3.1 and v3.2.
1033  * System MMU v3.1: 128KiB
1034  * System MMU v3.2: 256KiB
1035  *
1036  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1037  * more workarounds.
1038  * - Any two consecutive I/O virtual regions must have a hole of size larger
1039  *   than or equal to 128KiB.
1040  * - Start address of an I/O virtual region must be aligned by 128KiB.
1041  */
1042 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1043                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1044                             int prot)
1045 {
1046         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1047         sysmmu_pte_t *entry;
1048         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1049         unsigned long flags;
1050         int ret = -ENOMEM;
1051
1052         BUG_ON(domain->pgtable == NULL);
1053         prot &= SYSMMU_SUPPORTED_PROT_BITS;
1054
1055         spin_lock_irqsave(&domain->pgtablelock, flags);
1056
1057         entry = section_entry(domain->pgtable, iova);
1058
1059         if (size == SECT_SIZE) {
1060                 ret = lv1set_section(domain, entry, iova, paddr, prot,
1061                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1062         } else {
1063                 sysmmu_pte_t *pent;
1064
1065                 pent = alloc_lv2entry(domain, entry, iova,
1066                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1067
1068                 if (IS_ERR(pent))
1069                         ret = PTR_ERR(pent);
1070                 else
1071                         ret = lv2set_page(pent, paddr, size, prot,
1072                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1073         }
1074
1075         if (ret)
1076                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1077                         __func__, ret, size, iova);
1078
1079         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1080
1081         return ret;
1082 }
1083
1084 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1085                                               sysmmu_iova_t iova, size_t size)
1086 {
1087         struct sysmmu_drvdata *data;
1088         unsigned long flags;
1089
1090         spin_lock_irqsave(&domain->lock, flags);
1091
1092         list_for_each_entry(data, &domain->clients, domain_node)
1093                 sysmmu_tlb_invalidate_entry(data, iova, size);
1094
1095         spin_unlock_irqrestore(&domain->lock, flags);
1096 }
1097
1098 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1099                                  unsigned long l_iova, size_t size)
1100 {
1101         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1102         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1103         sysmmu_pte_t *ent;
1104         size_t err_pgsize;
1105         unsigned long flags;
1106
1107         BUG_ON(domain->pgtable == NULL);
1108
1109         spin_lock_irqsave(&domain->pgtablelock, flags);
1110
1111         ent = section_entry(domain->pgtable, iova);
1112
1113         if (lv1ent_section(ent)) {
1114                 if (WARN_ON(size < SECT_SIZE)) {
1115                         err_pgsize = SECT_SIZE;
1116                         goto err;
1117                 }
1118
1119                 /* workaround for h/w bug in System MMU v3.3 */
1120                 update_pte(ent, ZERO_LV2LINK);
1121                 size = SECT_SIZE;
1122                 goto done;
1123         }
1124
1125         if (unlikely(lv1ent_fault(ent))) {
1126                 if (size > SECT_SIZE)
1127                         size = SECT_SIZE;
1128                 goto done;
1129         }
1130
1131         /* lv1ent_page(sent) == true here */
1132
1133         ent = page_entry(ent, iova);
1134
1135         if (unlikely(lv2ent_fault(ent))) {
1136                 size = SPAGE_SIZE;
1137                 goto done;
1138         }
1139
1140         if (lv2ent_small(ent)) {
1141                 update_pte(ent, 0);
1142                 size = SPAGE_SIZE;
1143                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1144                 goto done;
1145         }
1146
1147         /* lv1ent_large(ent) == true here */
1148         if (WARN_ON(size < LPAGE_SIZE)) {
1149                 err_pgsize = LPAGE_SIZE;
1150                 goto err;
1151         }
1152
1153         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1154                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1155                                 DMA_TO_DEVICE);
1156         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1157         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1158                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1159                                    DMA_TO_DEVICE);
1160         size = LPAGE_SIZE;
1161         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1162 done:
1163         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1164
1165         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1166
1167         return size;
1168 err:
1169         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1170
1171         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1172                 __func__, size, iova, err_pgsize);
1173
1174         return 0;
1175 }
1176
1177 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1178                                           dma_addr_t iova)
1179 {
1180         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1181         sysmmu_pte_t *entry;
1182         unsigned long flags;
1183         phys_addr_t phys = 0;
1184
1185         spin_lock_irqsave(&domain->pgtablelock, flags);
1186
1187         entry = section_entry(domain->pgtable, iova);
1188
1189         if (lv1ent_section(entry)) {
1190                 phys = section_phys(entry) + section_offs(iova);
1191         } else if (lv1ent_page(entry)) {
1192                 entry = page_entry(entry, iova);
1193
1194                 if (lv2ent_large(entry))
1195                         phys = lpage_phys(entry) + lpage_offs(iova);
1196                 else if (lv2ent_small(entry))
1197                         phys = spage_phys(entry) + spage_offs(iova);
1198         }
1199
1200         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1201
1202         return phys;
1203 }
1204
1205 static struct iommu_group *get_device_iommu_group(struct device *dev)
1206 {
1207         struct iommu_group *group;
1208
1209         group = iommu_group_get(dev);
1210         if (!group)
1211                 group = iommu_group_alloc();
1212
1213         return group;
1214 }
1215
1216 static int exynos_iommu_add_device(struct device *dev)
1217 {
1218         struct iommu_group *group;
1219
1220         if (!has_sysmmu(dev))
1221                 return -ENODEV;
1222
1223         group = iommu_group_get_for_dev(dev);
1224
1225         if (IS_ERR(group))
1226                 return PTR_ERR(group);
1227
1228         iommu_group_put(group);
1229
1230         return 0;
1231 }
1232
1233 static void exynos_iommu_remove_device(struct device *dev)
1234 {
1235         if (!has_sysmmu(dev))
1236                 return;
1237
1238         iommu_group_remove_device(dev);
1239 }
1240
1241 static int exynos_iommu_of_xlate(struct device *dev,
1242                                  struct of_phandle_args *spec)
1243 {
1244         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1245         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1246         struct sysmmu_drvdata *data;
1247
1248         if (!sysmmu)
1249                 return -ENODEV;
1250
1251         data = platform_get_drvdata(sysmmu);
1252         if (!data)
1253                 return -ENODEV;
1254
1255         if (!owner) {
1256                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1257                 if (!owner)
1258                         return -ENOMEM;
1259
1260                 INIT_LIST_HEAD(&owner->controllers);
1261                 mutex_init(&owner->rpm_lock);
1262                 dev->archdata.iommu = owner;
1263         }
1264
1265         list_add_tail(&data->owner_node, &owner->controllers);
1266         data->master = dev;
1267
1268         /*
1269          * SYSMMU will be runtime activated via device link (dependency) to its
1270          * master device, so there are no direct calls to pm_runtime_get/put
1271          * in this driver.
1272          */
1273         device_link_add(dev, data->sysmmu, DL_FLAG_PM_RUNTIME);
1274
1275         return 0;
1276 }
1277
1278 static struct iommu_ops exynos_iommu_ops = {
1279         .domain_alloc = exynos_iommu_domain_alloc,
1280         .domain_free = exynos_iommu_domain_free,
1281         .attach_dev = exynos_iommu_attach_device,
1282         .detach_dev = exynos_iommu_detach_device,
1283         .map = exynos_iommu_map,
1284         .unmap = exynos_iommu_unmap,
1285         .map_sg = default_iommu_map_sg,
1286         .iova_to_phys = exynos_iommu_iova_to_phys,
1287         .device_group = get_device_iommu_group,
1288         .add_device = exynos_iommu_add_device,
1289         .remove_device = exynos_iommu_remove_device,
1290         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1291         .of_xlate = exynos_iommu_of_xlate,
1292 };
1293
1294 static bool init_done;
1295
1296 static int __init exynos_iommu_init(void)
1297 {
1298         int ret;
1299
1300         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1301                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1302         if (!lv2table_kmem_cache) {
1303                 pr_err("%s: Failed to create kmem cache\n", __func__);
1304                 return -ENOMEM;
1305         }
1306
1307         ret = platform_driver_register(&exynos_sysmmu_driver);
1308         if (ret) {
1309                 pr_err("%s: Failed to register driver\n", __func__);
1310                 goto err_reg_driver;
1311         }
1312
1313         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1314         if (zero_lv2_table == NULL) {
1315                 pr_err("%s: Failed to allocate zero level2 page table\n",
1316                         __func__);
1317                 ret = -ENOMEM;
1318                 goto err_zero_lv2;
1319         }
1320
1321         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1322         if (ret) {
1323                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1324                                                                 __func__);
1325                 goto err_set_iommu;
1326         }
1327
1328         init_done = true;
1329
1330         return 0;
1331 err_set_iommu:
1332         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1333 err_zero_lv2:
1334         platform_driver_unregister(&exynos_sysmmu_driver);
1335 err_reg_driver:
1336         kmem_cache_destroy(lv2table_kmem_cache);
1337         return ret;
1338 }
1339
1340 static int __init exynos_iommu_of_setup(struct device_node *np)
1341 {
1342         struct platform_device *pdev;
1343
1344         if (!init_done)
1345                 exynos_iommu_init();
1346
1347         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1348         if (!pdev)
1349                 return -ENODEV;
1350
1351         /*
1352          * use the first registered sysmmu device for performing
1353          * dma mapping operations on iommu page tables (cpu cache flush)
1354          */
1355         if (!dma_dev)
1356                 dma_dev = &pdev->dev;
1357
1358         return 0;
1359 }
1360
1361 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1362                  exynos_iommu_of_setup);