drivers/iommu/intel-iommu-debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright © 2018 Intel Corporation.
   4  *
   5  * Authors: Gayatri Kammela <gayatri.kammela@intel.com>
   6  *          Sohil Mehta <sohil.mehta@intel.com>
   7  *          Jacob Pan <jacob.jun.pan@linux.intel.com>
   8  *          Lu Baolu <baolu.lu@linux.intel.com>
   9  */
  10
  11 #include <linux/debugfs.h>
  12 #include <linux/dmar.h>
  13 #include <linux/intel-iommu.h>
  14 #include <linux/pci.h>
  15
  16 #include <asm/irq_remapping.h>
  17
  18 #include "intel-pasid.h"
  19
  20 struct tbl_walk {
  21         u16 bus;
  22         u16 devfn;
  23         u32 pasid;
  24         struct root_entry *rt_entry;
  25         struct context_entry *ctx_entry;
  26         struct pasid_entry *pasid_tbl_entry;
  27 };
  28
  29 struct iommu_regset {
  30         int offset;
  31         const char *regs;
  32 };
  33
  34 #define IOMMU_REGSET_ENTRY(_reg_)                                       \
  35         { DMAR_##_reg_##_REG, __stringify(_reg_) }
  36 static const struct iommu_regset iommu_regs[] = {
  37         IOMMU_REGSET_ENTRY(VER),
  38         IOMMU_REGSET_ENTRY(CAP),
  39         IOMMU_REGSET_ENTRY(ECAP),
  40         IOMMU_REGSET_ENTRY(GCMD),
  41         IOMMU_REGSET_ENTRY(GSTS),
  42         IOMMU_REGSET_ENTRY(RTADDR),
  43         IOMMU_REGSET_ENTRY(CCMD),
  44         IOMMU_REGSET_ENTRY(FSTS),
  45         IOMMU_REGSET_ENTRY(FECTL),
  46         IOMMU_REGSET_ENTRY(FEDATA),
  47         IOMMU_REGSET_ENTRY(FEADDR),
  48         IOMMU_REGSET_ENTRY(FEUADDR),
  49         IOMMU_REGSET_ENTRY(AFLOG),
  50         IOMMU_REGSET_ENTRY(PMEN),
  51         IOMMU_REGSET_ENTRY(PLMBASE),
  52         IOMMU_REGSET_ENTRY(PLMLIMIT),
  53         IOMMU_REGSET_ENTRY(PHMBASE),
  54         IOMMU_REGSET_ENTRY(PHMLIMIT),
  55         IOMMU_REGSET_ENTRY(IQH),
  56         IOMMU_REGSET_ENTRY(IQT),
  57         IOMMU_REGSET_ENTRY(IQA),
  58         IOMMU_REGSET_ENTRY(ICS),
  59         IOMMU_REGSET_ENTRY(IRTA),
  60         IOMMU_REGSET_ENTRY(PQH),
  61         IOMMU_REGSET_ENTRY(PQT),
  62         IOMMU_REGSET_ENTRY(PQA),
  63         IOMMU_REGSET_ENTRY(PRS),
  64         IOMMU_REGSET_ENTRY(PECTL),
  65         IOMMU_REGSET_ENTRY(PEDATA),
  66         IOMMU_REGSET_ENTRY(PEADDR),
  67         IOMMU_REGSET_ENTRY(PEUADDR),
  68         IOMMU_REGSET_ENTRY(MTRRCAP),
  69         IOMMU_REGSET_ENTRY(MTRRDEF),
  70         IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
  71         IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000),
  72         IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000),
  73         IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000),
  74         IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000),
  75         IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000),
  76         IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000),
  77         IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000),
  78         IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000),
  79         IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000),
  80         IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000),
  81         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0),
  82         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0),
  83         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1),
  84         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1),
  85         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2),
  86         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2),
  87         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3),
  88         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3),
  89         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4),
  90         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4),
  91         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5),
  92         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5),
  93         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6),
  94         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6),
  95         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7),
  96         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7),
  97         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8),
  98         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),
  99         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),
 100         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),
 101         IOMMU_REGSET_ENTRY(VCCAP),
 102         IOMMU_REGSET_ENTRY(VCMD),
 103         IOMMU_REGSET_ENTRY(VCRSP),
 104 };
 105
 106 static int iommu_regset_show(struct seq_file *m, void *unused)
 107 {
 108         struct dmar_drhd_unit *drhd;
 109         struct intel_iommu *iommu;
 110         unsigned long flag;
 111         int i, ret = 0;
 112         u64 value;
 113
 114         rcu_read_lock();
 115         for_each_active_iommu(iommu, drhd) {
 116                 if (!drhd->reg_base_addr) {
 117                         seq_puts(m, "IOMMU: Invalid base address\n");
 118                         ret = -EINVAL;
 119                         goto out;
 120                 }
 121
 122                 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
 123                            iommu->name, drhd->reg_base_addr);
 124                 seq_puts(m, "Name\t\t\tOffset\t\tContents\n");
 125                 /*
 126                  * Publish the contents of the 64-bit hardware registers
 127                  * by adding the offset to the pointer (virtual address).
 128                  */
 129                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
 130                 for (i = 0 ; i < ARRAY_SIZE(iommu_regs); i++) {
 131                         value = dmar_readq(iommu->reg + iommu_regs[i].offset);
 132                         seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
 133                                    iommu_regs[i].regs, iommu_regs[i].offset,
 134                                    value);
 135                 }
 136                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 137                 seq_putc(m, '\n');
 138         }
 139 out:
 140         rcu_read_unlock();
 141
 142         return ret;
 143 }
 144 DEFINE_SHOW_ATTRIBUTE(iommu_regset);
 145
 146 static inline void print_tbl_walk(struct seq_file *m)
 147 {
 148         struct tbl_walk *tbl_wlk = m->private;
 149
 150         seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t",
 151                    tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn),
 152                    PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi,
 153                    tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi,
 154                    tbl_wlk->ctx_entry->lo);
 155
 156         /*
 157          * A legacy mode DMAR doesn't support PASID, hence default it to -1
 158          * indicating that it's invalid. Also, default all PASID related fields
 159          * to 0.
 160          */
 161         if (!tbl_wlk->pasid_tbl_entry)
 162                 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1,
 163                            (u64)0, (u64)0, (u64)0);
 164         else
 165                 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",
 166                            tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],
 167                            tbl_wlk->pasid_tbl_entry->val[1],
 168                            tbl_wlk->pasid_tbl_entry->val[0]);
 169 }
 170
 171 static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry,
 172                            u16 dir_idx)
 173 {
 174         struct tbl_walk *tbl_wlk = m->private;
 175         u8 tbl_idx;
 176
 177         for (tbl_idx = 0; tbl_idx < PASID_TBL_ENTRIES; tbl_idx++) {
 178                 if (pasid_pte_is_present(tbl_entry)) {
 179                         tbl_wlk->pasid_tbl_entry = tbl_entry;
 180                         tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx;
 181                         print_tbl_walk(m);
 182                 }
 183
 184                 tbl_entry++;
 185         }
 186 }
 187
 188 static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr,
 189                            u16 pasid_dir_size)
 190 {
 191         struct pasid_dir_entry *dir_entry = phys_to_virt(pasid_dir_ptr);
 192         struct pasid_entry *pasid_tbl;
 193         u16 dir_idx;
 194
 195         for (dir_idx = 0; dir_idx < pasid_dir_size; dir_idx++) {
 196                 pasid_tbl = get_pasid_table_from_pde(dir_entry);
 197                 if (pasid_tbl)
 198                         pasid_tbl_walk(m, pasid_tbl, dir_idx);
 199
 200                 dir_entry++;
 201         }
 202 }
 203
 204 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
 205 {
 206         struct context_entry *context;
 207         u16 devfn, pasid_dir_size;
 208         u64 pasid_dir_ptr;
 209
 210         for (devfn = 0; devfn < 256; devfn++) {
 211                 struct tbl_walk tbl_wlk = {0};
 212
 213                 /*
 214                  * Scalable mode root entry points to upper scalable mode
 215                  * context table and lower scalable mode context table. Each
 216                  * scalable mode context table has 128 context entries where as
 217                  * legacy mode context table has 256 context entries. So in
 218                  * scalable mode, the context entries for former 128 devices are
 219                  * in the lower scalable mode context table, while the latter
 220                  * 128 devices are in the upper scalable mode context table.
 221                  * In scalable mode, when devfn > 127, iommu_context_addr()
 222                  * automatically refers to upper scalable mode context table and
 223                  * hence the caller doesn't have to worry about differences
 224                  * between scalable mode and non scalable mode.
 225                  */
 226                 context = iommu_context_addr(iommu, bus, devfn, 0);
 227                 if (!context)
 228                         return;
 229
 230                 if (!context_present(context))
 231                         continue;
 232
 233                 tbl_wlk.bus = bus;
 234                 tbl_wlk.devfn = devfn;
 235                 tbl_wlk.rt_entry = &iommu->root_entry[bus];
 236                 tbl_wlk.ctx_entry = context;
 237                 m->private = &tbl_wlk;
 238
 239                 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
 240                         pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
 241                         pasid_dir_size = get_pasid_dir_size(context);
 242                         pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
 243                         continue;
 244                 }
 245
 246                 print_tbl_walk(m);
 247         }
 248 }
 249
 250 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)
 251 {
 252         unsigned long flags;
 253         u16 bus;
 254
 255         spin_lock_irqsave(&iommu->lock, flags);
 256         seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,
 257                    (u64)virt_to_phys(iommu->root_entry));
 258         seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n");
 259
 260         /*
 261          * No need to check if the root entry is present or not because
 262          * iommu_context_addr() performs the same check before returning
 263          * context entry.
 264          */
 265         for (bus = 0; bus < 256; bus++)
 266                 ctx_tbl_walk(m, iommu, bus);
 267
 268         spin_unlock_irqrestore(&iommu->lock, flags);
 269 }
 270
 271 static int dmar_translation_struct_show(struct seq_file *m, void *unused)
 272 {
 273         struct dmar_drhd_unit *drhd;
 274         struct intel_iommu *iommu;
 275
 276         rcu_read_lock();
 277         for_each_active_iommu(iommu, drhd) {
 278                 root_tbl_walk(m, iommu);
 279                 seq_putc(m, '\n');
 280         }
 281         rcu_read_unlock();
 282
 283         return 0;
 284 }
 285 DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct);
 286
 287 static inline unsigned long level_to_directory_size(int level)
 288 {
 289         return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));
 290 }
 291
 292 static inline void
 293 dump_page_info(struct seq_file *m, unsigned long iova, u64 *path)
 294 {
 295         seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\n",
 296                    iova >> VTD_PAGE_SHIFT, path[5], path[4],
 297                    path[3], path[2], path[1]);
 298 }
 299
 300 static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde,
 301                                int level, unsigned long start,
 302                                u64 *path)
 303 {
 304         int i;
 305
 306         if (level > 5 || level < 1)
 307                 return;
 308
 309         for (i = 0; i < BIT_ULL(VTD_STRIDE_SHIFT);
 310                         i++, pde++, start += level_to_directory_size(level)) {
 311                 if (!dma_pte_present(pde))
 312                         continue;
 313
 314                 path[level] = pde->val;
 315                 if (dma_pte_superpage(pde) || level == 1)
 316                         dump_page_info(m, start, path);
 317                 else
 318                         pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)),
 319                                            level - 1, start, path);
 320                 path[level] = 0;
 321         }
 322 }
 323
 324 static int show_device_domain_translation(struct device *dev, void *data)
 325 {
 326         struct dmar_domain *domain = find_domain(dev);
 327         struct seq_file *m = data;
 328         u64 path[6] = { 0 };
 329
 330         if (!domain)
 331                 return 0;
 332
 333         seq_printf(m, "Device %s with pasid %d @0x%llx\n",
 334                    dev_name(dev), domain->default_pasid,
 335                    (u64)virt_to_phys(domain->pgd));
 336         seq_puts(m, "IOVA_PFN\t\tPML5E\t\t\tPML4E\t\t\tPDPE\t\t\tPDE\t\t\tPTE\n");
 337
 338         pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path);
 339         seq_putc(m, '\n');
 340
 341         return 0;
 342 }
 343
 344 static int domain_translation_struct_show(struct seq_file *m, void *unused)
 345 {
 346         unsigned long flags;
 347         int ret;
 348
 349         spin_lock_irqsave(&device_domain_lock, flags);
 350         ret = bus_for_each_dev(&pci_bus_type, NULL, m,
 351                                show_device_domain_translation);
 352         spin_unlock_irqrestore(&device_domain_lock, flags);
 353
 354         return ret;
 355 }
 356 DEFINE_SHOW_ATTRIBUTE(domain_translation_struct);
 357
 358 #ifdef CONFIG_IRQ_REMAP
 359 static void ir_tbl_remap_entry_show(struct seq_file *m,
 360                                     struct intel_iommu *iommu)
 361 {
 362         struct irte *ri_entry;
 363         unsigned long flags;
 364         int idx;
 365
 366         seq_puts(m, " Entry SrcID   DstID    Vct IRTE_high\t\tIRTE_low\n");
 367
 368         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 369         for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
 370                 ri_entry = &iommu->ir_table->base[idx];
 371                 if (!ri_entry->present || ri_entry->p_pst)
 372                         continue;
 373
 374                 seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x  %016llx\t%016llx\n",
 375                            idx, PCI_BUS_NUM(ri_entry->sid),
 376                            PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),
 377                            ri_entry->dest_id, ri_entry->vector,
 378                            ri_entry->high, ri_entry->low);
 379         }
 380         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 381 }
 382
 383 static void ir_tbl_posted_entry_show(struct seq_file *m,
 384                                      struct intel_iommu *iommu)
 385 {
 386         struct irte *pi_entry;
 387         unsigned long flags;
 388         int idx;
 389
 390         seq_puts(m, " Entry SrcID   PDA_high PDA_low  Vct IRTE_high\t\tIRTE_low\n");
 391
 392         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 393         for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
 394                 pi_entry = &iommu->ir_table->base[idx];
 395                 if (!pi_entry->present || !pi_entry->p_pst)
 396                         continue;
 397
 398                 seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x  %016llx\t%016llx\n",
 399                            idx, PCI_BUS_NUM(pi_entry->sid),
 400                            PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),
 401                            pi_entry->pda_h, pi_entry->pda_l << 6,
 402                            pi_entry->vector, pi_entry->high,
 403                            pi_entry->low);
 404         }
 405         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 406 }
 407
 408 /*
 409  * For active IOMMUs go through the Interrupt remapping
 410  * table and print valid entries in a table format for
 411  * Remapped and Posted Interrupts.
 412  */
 413 static int ir_translation_struct_show(struct seq_file *m, void *unused)
 414 {
 415         struct dmar_drhd_unit *drhd;
 416         struct intel_iommu *iommu;
 417         u64 irta;
 418
 419         rcu_read_lock();
 420         for_each_active_iommu(iommu, drhd) {
 421                 if (!ecap_ir_support(iommu->ecap))
 422                         continue;
 423
 424                 seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
 425                            iommu->name);
 426
 427                 if (iommu->ir_table) {
 428                         irta = virt_to_phys(iommu->ir_table->base);
 429                         seq_printf(m, " IR table address:%llx\n", irta);
 430                         ir_tbl_remap_entry_show(m, iommu);
 431                 } else {
 432                         seq_puts(m, "Interrupt Remapping is not enabled\n");
 433                 }
 434                 seq_putc(m, '\n');
 435         }
 436
 437         seq_puts(m, "****\n\n");
 438
 439         for_each_active_iommu(iommu, drhd) {
 440                 if (!cap_pi_support(iommu->cap))
 441                         continue;
 442
 443                 seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",
 444                            iommu->name);
 445
 446                 if (iommu->ir_table) {
 447                         irta = virt_to_phys(iommu->ir_table->base);
 448                         seq_printf(m, " IR table address:%llx\n", irta);
 449                         ir_tbl_posted_entry_show(m, iommu);
 450                 } else {
 451                         seq_puts(m, "Interrupt Remapping is not enabled\n");
 452                 }
 453                 seq_putc(m, '\n');
 454         }
 455         rcu_read_unlock();
 456
 457         return 0;
 458 }
 459 DEFINE_SHOW_ATTRIBUTE(ir_translation_struct);
 460 #endif
 461
 462 void __init intel_iommu_debugfs_init(void)
 463 {
 464         struct dentry *intel_iommu_debug = debugfs_create_dir("intel",
 465                                                 iommu_debugfs_dir);
 466
 467         debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL,
 468                             &iommu_regset_fops);
 469         debugfs_create_file("dmar_translation_struct", 0444, intel_iommu_debug,
 470                             NULL, &dmar_translation_struct_fops);
 471         debugfs_create_file("domain_translation_struct", 0444,
 472                             intel_iommu_debug, NULL,
 473                             &domain_translation_struct_fops);
 474 #ifdef CONFIG_IRQ_REMAP
 475         debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug,
 476                             NULL, &ir_translation_struct_fops);
 477 #endif
 478 }