drivers/iommu/intel-svm.c

   1 /*
   2  * Copyright © 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * Authors: David Woodhouse <dwmw2@infradead.org>
  14  */
  15
  16 #include <linux/intel-iommu.h>
  17 #include <linux/mmu_notifier.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/mm.h>
  20 #include <linux/slab.h>
  21 #include <linux/intel-svm.h>
  22 #include <linux/rculist.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-ats.h>
  25 #include <linux/dmar.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mm_types.h>
  28 #include <asm/page.h>
  29
  30 #include "intel-pasid.h"
  31
  32 static irqreturn_t prq_event_thread(int irq, void *d);
  33
  34 int intel_svm_init(struct intel_iommu *iommu)
  35 {
  36         if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
  37                         !cap_fl1gp_support(iommu->cap))
  38                 return -EINVAL;
  39
  40         if (cpu_feature_enabled(X86_FEATURE_LA57) &&
  41                         !cap_5lp_support(iommu->cap))
  42                 return -EINVAL;
  43
  44         return 0;
  45 }
  46
  47 #define PRQ_ORDER 0
  48
  49 int intel_svm_enable_prq(struct intel_iommu *iommu)
  50 {
  51         struct page *pages;
  52         int irq, ret;
  53
  54         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
  55         if (!pages) {
  56                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
  57                         iommu->name);
  58                 return -ENOMEM;
  59         }
  60         iommu->prq = page_address(pages);
  61
  62         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
  63         if (irq <= 0) {
  64                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
  65                        iommu->name);
  66                 ret = -EINVAL;
  67         err:
  68                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
  69                 iommu->prq = NULL;
  70                 return ret;
  71         }
  72         iommu->pr_irq = irq;
  73
  74         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
  75
  76         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
  77                                    iommu->prq_name, iommu);
  78         if (ret) {
  79                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
  80                        iommu->name);
  81                 dmar_free_hwirq(irq);
  82                 iommu->pr_irq = 0;
  83                 goto err;
  84         }
  85         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  86         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  87         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
  88
  89         return 0;
  90 }
  91
  92 int intel_svm_finish_prq(struct intel_iommu *iommu)
  93 {
  94         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  95         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  96         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
  97
  98         if (iommu->pr_irq) {
  99                 free_irq(iommu->pr_irq, iommu);
 100                 dmar_free_hwirq(iommu->pr_irq);
 101                 iommu->pr_irq = 0;
 102         }
 103
 104         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 105         iommu->prq = NULL;
 106
 107         return 0;
 108 }
 109
 110 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 111                                        unsigned long address, unsigned long pages, int ih, int gl)
 112 {
 113         struct qi_desc desc;
 114
 115         if (pages == -1) {
 116                 /* For global kernel pages we have to flush them in *all* PASIDs
 117                  * because that's the only option the hardware gives us. Despite
 118                  * the fact that they are actually only accessible through one. */
 119                 if (gl)
 120                         desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 121                                         QI_EIOTLB_DID(sdev->did) |
 122                                         QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) |
 123                                         QI_EIOTLB_TYPE;
 124                 else
 125                         desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 126                                         QI_EIOTLB_DID(sdev->did) |
 127                                         QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
 128                                         QI_EIOTLB_TYPE;
 129                 desc.qw1 = 0;
 130         } else {
 131                 int mask = ilog2(__roundup_pow_of_two(pages));
 132
 133                 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 134                                 QI_EIOTLB_DID(sdev->did) |
 135                                 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
 136                                 QI_EIOTLB_TYPE;
 137                 desc.qw1 = QI_EIOTLB_ADDR(address) |
 138                                 QI_EIOTLB_GL(gl) |
 139                                 QI_EIOTLB_IH(ih) |
 140                                 QI_EIOTLB_AM(mask);
 141         }
 142         desc.qw2 = 0;
 143         desc.qw3 = 0;
 144         qi_submit_sync(&desc, svm->iommu);
 145
 146         if (sdev->dev_iotlb) {
 147                 desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
 148                                 QI_DEV_EIOTLB_SID(sdev->sid) |
 149                                 QI_DEV_EIOTLB_QDEP(sdev->qdep) |
 150                                 QI_DEIOTLB_TYPE;
 151                 if (pages == -1) {
 152                         desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) |
 153                                         QI_DEV_EIOTLB_SIZE;
 154                 } else if (pages > 1) {
 155                         /* The least significant zero bit indicates the size. So,
 156                          * for example, an "address" value of 0x12345f000 will
 157                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 158                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 159                         unsigned long mask = __rounddown_pow_of_two(address ^ last);
 160
 161                         desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) |
 162                                         (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 163                 } else {
 164                         desc.qw1 = QI_DEV_EIOTLB_ADDR(address);
 165                 }
 166                 desc.qw2 = 0;
 167                 desc.qw3 = 0;
 168                 qi_submit_sync(&desc, svm->iommu);
 169         }
 170 }
 171
 172 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 173                                   unsigned long pages, int ih, int gl)
 174 {
 175         struct intel_svm_dev *sdev;
 176
 177         rcu_read_lock();
 178         list_for_each_entry_rcu(sdev, &svm->devs, list)
 179                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
 180         rcu_read_unlock();
 181 }
 182
 183 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
 184                              unsigned long address, pte_t pte)
 185 {
 186         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 187
 188         intel_flush_svm_range(svm, address, 1, 1, 0);
 189 }
 190
 191 /* Pages have been freed at this point */
 192 static void intel_invalidate_range(struct mmu_notifier *mn,
 193                                    struct mm_struct *mm,
 194                                    unsigned long start, unsigned long end)
 195 {
 196         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 197
 198         intel_flush_svm_range(svm, start,
 199                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
 200 }
 201
 202 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 203 {
 204         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 205         struct intel_svm_dev *sdev;
 206
 207         /* This might end up being called from exit_mmap(), *before* the page
 208          * tables are cleared. And __mmu_notifier_release() will delete us from
 209          * the list of notifiers so that our invalidate_range() callback doesn't
 210          * get called when the page tables are cleared. So we need to protect
 211          * against hardware accessing those page tables.
 212          *
 213          * We do it by clearing the entry in the PASID table and then flushing
 214          * the IOTLB and the PASID table caches. This might upset hardware;
 215          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 216          * page) so that we end up taking a fault that the hardware really
 217          * *has* to handle gracefully without affecting other processes.
 218          */
 219         rcu_read_lock();
 220         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 221                 intel_pasid_tear_down_entry(svm->iommu, sdev->dev, svm->pasid);
 222                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 223         }
 224         rcu_read_unlock();
 225
 226 }
 227
 228 static const struct mmu_notifier_ops intel_mmuops = {
 229         .release = intel_mm_release,
 230         .change_pte = intel_change_pte,
 231         .invalidate_range = intel_invalidate_range,
 232 };
 233
 234 static DEFINE_MUTEX(pasid_mutex);
 235 static LIST_HEAD(global_svm_list);
 236
 237 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 238 {
 239         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 240         struct intel_svm_dev *sdev;
 241         struct intel_svm *svm = NULL;
 242         struct mm_struct *mm = NULL;
 243         int pasid_max;
 244         int ret;
 245
 246         if (!iommu)
 247                 return -EINVAL;
 248
 249         if (dev_is_pci(dev)) {
 250                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 251                 if (pasid_max < 0)
 252                         return -EINVAL;
 253         } else
 254                 pasid_max = 1 << 20;
 255
 256         if (flags & SVM_FLAG_SUPERVISOR_MODE) {
 257                 if (!ecap_srs(iommu->ecap))
 258                         return -EINVAL;
 259         } else if (pasid) {
 260                 mm = get_task_mm(current);
 261                 BUG_ON(!mm);
 262         }
 263
 264         mutex_lock(&pasid_mutex);
 265         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 266                 struct intel_svm *t;
 267
 268                 list_for_each_entry(t, &global_svm_list, list) {
 269                         if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
 270                                 continue;
 271
 272                         svm = t;
 273                         if (svm->pasid >= pasid_max) {
 274                                 dev_warn(dev,
 275                                          "Limited PASID width. Cannot use existing PASID %d\n",
 276                                          svm->pasid);
 277                                 ret = -ENOSPC;
 278                                 goto out;
 279                         }
 280
 281                         list_for_each_entry(sdev, &svm->devs, list) {
 282                                 if (dev == sdev->dev) {
 283                                         if (sdev->ops != ops) {
 284                                                 ret = -EBUSY;
 285                                                 goto out;
 286                                         }
 287                                         sdev->users++;
 288                                         goto success;
 289                                 }
 290                         }
 291
 292                         break;
 293                 }
 294         }
 295
 296         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 297         if (!sdev) {
 298                 ret = -ENOMEM;
 299                 goto out;
 300         }
 301         sdev->dev = dev;
 302
 303         ret = intel_iommu_enable_pasid(iommu, sdev);
 304         if (ret || !pasid) {
 305                 /* If they don't actually want to assign a PASID, this is
 306                  * just an enabling check/preparation. */
 307                 kfree(sdev);
 308                 goto out;
 309         }
 310         /* Finish the setup now we know we're keeping it */
 311         sdev->users = 1;
 312         sdev->ops = ops;
 313         init_rcu_head(&sdev->rcu);
 314
 315         if (!svm) {
 316                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 317                 if (!svm) {
 318                         ret = -ENOMEM;
 319                         kfree(sdev);
 320                         goto out;
 321                 }
 322                 svm->iommu = iommu;
 323
 324                 if (pasid_max > intel_pasid_max_id)
 325                         pasid_max = intel_pasid_max_id;
 326
 327                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 328                 ret = intel_pasid_alloc_id(svm,
 329                                            !!cap_caching_mode(iommu->cap),
 330                                            pasid_max - 1, GFP_KERNEL);
 331                 if (ret < 0) {
 332                         kfree(svm);
 333                         kfree(sdev);
 334                         goto out;
 335                 }
 336                 svm->pasid = ret;
 337                 svm->notifier.ops = &intel_mmuops;
 338                 svm->mm = mm;
 339                 svm->flags = flags;
 340                 INIT_LIST_HEAD_RCU(&svm->devs);
 341                 INIT_LIST_HEAD(&svm->list);
 342                 ret = -ENOMEM;
 343                 if (mm) {
 344                         ret = mmu_notifier_register(&svm->notifier, mm);
 345                         if (ret) {
 346                                 intel_pasid_free_id(svm->pasid);
 347                                 kfree(svm);
 348                                 kfree(sdev);
 349                                 goto out;
 350                         }
 351                 }
 352
 353                 spin_lock(&iommu->lock);
 354                 ret = intel_pasid_setup_first_level(iommu, dev,
 355                                 mm ? mm->pgd : init_mm.pgd,
 356                                 svm->pasid, FLPT_DEFAULT_DID,
 357                                 mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
 358                 spin_unlock(&iommu->lock);
 359                 if (ret) {
 360                         if (mm)
 361                                 mmu_notifier_unregister(&svm->notifier, mm);
 362                         intel_pasid_free_id(svm->pasid);
 363                         kfree(svm);
 364                         kfree(sdev);
 365                         goto out;
 366                 }
 367
 368                 list_add_tail(&svm->list, &global_svm_list);
 369         }
 370         list_add_rcu(&sdev->list, &svm->devs);
 371
 372  success:
 373         *pasid = svm->pasid;
 374         ret = 0;
 375  out:
 376         mutex_unlock(&pasid_mutex);
 377         if (mm)
 378                 mmput(mm);
 379         return ret;
 380 }
 381 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 382
 383 int intel_svm_unbind_mm(struct device *dev, int pasid)
 384 {
 385         struct intel_svm_dev *sdev;
 386         struct intel_iommu *iommu;
 387         struct intel_svm *svm;
 388         int ret = -EINVAL;
 389
 390         mutex_lock(&pasid_mutex);
 391         iommu = intel_svm_device_to_iommu(dev);
 392         if (!iommu)
 393                 goto out;
 394
 395         svm = intel_pasid_lookup_id(pasid);
 396         if (!svm)
 397                 goto out;
 398
 399         list_for_each_entry(sdev, &svm->devs, list) {
 400                 if (dev == sdev->dev) {
 401                         ret = 0;
 402                         sdev->users--;
 403                         if (!sdev->users) {
 404                                 list_del_rcu(&sdev->list);
 405                                 /* Flush the PASID cache and IOTLB for this device.
 406                                  * Note that we do depend on the hardware *not* using
 407                                  * the PASID any more. Just as we depend on other
 408                                  * devices never using PASIDs that they have no right
 409                                  * to use. We have a *shared* PASID table, because it's
 410                                  * large and has to be physically contiguous. So it's
 411                                  * hard to be as defensive as we might like. */
 412                                 intel_pasid_tear_down_entry(iommu, dev, svm->pasid);
 413                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 414                                 kfree_rcu(sdev, rcu);
 415
 416                                 if (list_empty(&svm->devs)) {
 417                                         intel_pasid_free_id(svm->pasid);
 418                                         if (svm->mm)
 419                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 420
 421                                         list_del(&svm->list);
 422
 423                                         /* We mandate that no page faults may be outstanding
 424                                          * for the PASID when intel_svm_unbind_mm() is called.
 425                                          * If that is not obeyed, subtle errors will happen.
 426                                          * Let's make them less subtle... */
 427                                         memset(svm, 0x6b, sizeof(*svm));
 428                                         kfree(svm);
 429                                 }
 430                         }
 431                         break;
 432                 }
 433         }
 434  out:
 435         mutex_unlock(&pasid_mutex);
 436
 437         return ret;
 438 }
 439 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 440
 441 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 442 {
 443         struct intel_iommu *iommu;
 444         struct intel_svm *svm;
 445         int ret = -EINVAL;
 446
 447         mutex_lock(&pasid_mutex);
 448         iommu = intel_svm_device_to_iommu(dev);
 449         if (!iommu)
 450                 goto out;
 451
 452         svm = intel_pasid_lookup_id(pasid);
 453         if (!svm)
 454                 goto out;
 455
 456         /* init_mm is used in this case */
 457         if (!svm->mm)
 458                 ret = 1;
 459         else if (atomic_read(&svm->mm->mm_users) > 0)
 460                 ret = 1;
 461         else
 462                 ret = 0;
 463
 464  out:
 465         mutex_unlock(&pasid_mutex);
 466
 467         return ret;
 468 }
 469 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 470
 471 /* Page request queue descriptor */
 472 struct page_req_dsc {
 473         u64 srr:1;
 474         u64 bof:1;
 475         u64 pasid_present:1;
 476         u64 lpig:1;
 477         u64 pasid:20;
 478         u64 bus:8;
 479         u64 private:23;
 480         u64 prg_index:9;
 481         u64 rd_req:1;
 482         u64 wr_req:1;
 483         u64 exe_req:1;
 484         u64 priv_req:1;
 485         u64 devfn:8;
 486         u64 addr:52;
 487 };
 488
 489 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 490
 491 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 492 {
 493         unsigned long requested = 0;
 494
 495         if (req->exe_req)
 496                 requested |= VM_EXEC;
 497
 498         if (req->rd_req)
 499                 requested |= VM_READ;
 500
 501         if (req->wr_req)
 502                 requested |= VM_WRITE;
 503
 504         return (requested & ~vma->vm_flags) != 0;
 505 }
 506
 507 static bool is_canonical_address(u64 addr)
 508 {
 509         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 510         long saddr = (long) addr;
 511
 512         return (((saddr << shift) >> shift) == saddr);
 513 }
 514
 515 static irqreturn_t prq_event_thread(int irq, void *d)
 516 {
 517         struct intel_iommu *iommu = d;
 518         struct intel_svm *svm = NULL;
 519         int head, tail, handled = 0;
 520
 521         /* Clear PPR bit before reading head/tail registers, to
 522          * ensure that we get a new interrupt if needed. */
 523         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 524
 525         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 526         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 527         while (head != tail) {
 528                 struct intel_svm_dev *sdev;
 529                 struct vm_area_struct *vma;
 530                 struct page_req_dsc *req;
 531                 struct qi_desc resp;
 532                 int result;
 533                 vm_fault_t ret;
 534                 u64 address;
 535
 536                 handled = 1;
 537
 538                 req = &iommu->prq[head / sizeof(*req)];
 539
 540                 result = QI_RESP_FAILURE;
 541                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 542                 if (!req->pasid_present) {
 543                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 544                                iommu->name, ((unsigned long long *)req)[0],
 545                                ((unsigned long long *)req)[1]);
 546                         goto no_pasid;
 547                 }
 548
 549                 if (!svm || svm->pasid != req->pasid) {
 550                         rcu_read_lock();
 551                         svm = intel_pasid_lookup_id(req->pasid);
 552                         /* It *can't* go away, because the driver is not permitted
 553                          * to unbind the mm while any page faults are outstanding.
 554                          * So we only need RCU to protect the internal idr code. */
 555                         rcu_read_unlock();
 556
 557                         if (!svm) {
 558                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 559                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 560                                        ((unsigned long long *)req)[1]);
 561                                 goto no_pasid;
 562                         }
 563                 }
 564
 565                 result = QI_RESP_INVALID;
 566                 /* Since we're using init_mm.pgd directly, we should never take
 567                  * any faults on kernel addresses. */
 568                 if (!svm->mm)
 569                         goto bad_req;
 570                 /* If the mm is already defunct, don't handle faults. */
 571                 if (!mmget_not_zero(svm->mm))
 572                         goto bad_req;
 573
 574                 /* If address is not canonical, return invalid response */
 575                 if (!is_canonical_address(address))
 576                         goto bad_req;
 577
 578                 down_read(&svm->mm->mmap_sem);
 579                 vma = find_extend_vma(svm->mm, address);
 580                 if (!vma || address < vma->vm_start)
 581                         goto invalid;
 582
 583                 if (access_error(vma, req))
 584                         goto invalid;
 585
 586                 ret = handle_mm_fault(vma, address,
 587                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 588                 if (ret & VM_FAULT_ERROR)
 589                         goto invalid;
 590
 591                 result = QI_RESP_SUCCESS;
 592         invalid:
 593                 up_read(&svm->mm->mmap_sem);
 594                 mmput(svm->mm);
 595         bad_req:
 596                 /* Accounting for major/minor faults? */
 597                 rcu_read_lock();
 598                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 599                         if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
 600                                 break;
 601                 }
 602                 /* Other devices can go away, but the drivers are not permitted
 603                  * to unbind while any page faults might be in flight. So it's
 604                  * OK to drop the 'lock' here now we have it. */
 605                 rcu_read_unlock();
 606
 607                 if (WARN_ON(&sdev->list == &svm->devs))
 608                         sdev = NULL;
 609
 610                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 611                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 612                                 (req->exe_req << 1) | (req->priv_req);
 613                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
 614                 }
 615                 /* We get here in the error case where the PASID lookup failed,
 616                    and these can be NULL. Do not use them below this point! */
 617                 sdev = NULL;
 618                 svm = NULL;
 619         no_pasid:
 620                 if (req->lpig) {
 621                         /* Page Group Response */
 622                         resp.qw0 = QI_PGRP_PASID(req->pasid) |
 623                                 QI_PGRP_DID((req->bus << 8) | req->devfn) |
 624                                 QI_PGRP_PASID_P(req->pasid_present) |
 625                                 QI_PGRP_RESP_TYPE;
 626                         resp.qw1 = QI_PGRP_IDX(req->prg_index) |
 627                                 QI_PGRP_PRIV(req->private) |
 628                                 QI_PGRP_RESP_CODE(result);
 629                 } else if (req->srr) {
 630                         /* Page Stream Response */
 631                         resp.qw0 = QI_PSTRM_IDX(req->prg_index) |
 632                                 QI_PSTRM_PRIV(req->private) |
 633                                 QI_PSTRM_BUS(req->bus) |
 634                                 QI_PSTRM_PASID(req->pasid) |
 635                                 QI_PSTRM_RESP_TYPE;
 636                         resp.qw1 = QI_PSTRM_ADDR(address) |
 637                                 QI_PSTRM_DEVFN(req->devfn) |
 638                                 QI_PSTRM_RESP_CODE(result);
 639                 }
 640                 resp.qw2 = 0;
 641                 resp.qw3 = 0;
 642                 qi_submit_sync(&resp, iommu);
 643
 644                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 645         }
 646
 647         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 648
 649         return IRQ_RETVAL(handled);
 650 }