1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU-agnostic ARM page table allocator.
5 * ARMv7 Short-descriptor format, supporting
6 * - Basic memory attributes
7 * - Simplified access permissions (AP[2:1] model)
8 * - Backwards-compatible TEX remap
9 * - Large pages/supersections (if indicated by the caller)
12 * - Legacy access permissions (AP[2:0] model)
14 * Almost certainly never supporting:
18 * Copyright (C) 2014-2015 ARM Limited
19 * Copyright (c) 2014-2015 MediaTek Inc.
22 #define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
24 #include <linux/atomic.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/gfp.h>
27 #include <linux/io-pgtable.h>
28 #include <linux/iommu.h>
29 #include <linux/kernel.h>
30 #include <linux/kmemleak.h>
31 #include <linux/sizes.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/types.h>
36 #include <asm/barrier.h>
38 /* Struct accessors */
39 #define io_pgtable_to_data(x) \
40 container_of((x), struct arm_v7s_io_pgtable, iop)
42 #define io_pgtable_ops_to_data(x) \
43 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
46 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
47 * and 12 bits in a page. With some carefully-chosen coefficients we can
48 * hide the ugly inconsistencies behind these macros and at least let the
49 * rest of the code pretend to be somewhat sane.
51 #define ARM_V7S_ADDR_BITS 32
52 #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
53 #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
54 #define ARM_V7S_TABLE_SHIFT 10
56 #define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl))
57 #define ARM_V7S_TABLE_SIZE(lvl) \
58 (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte))
60 #define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl))
61 #define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
62 #define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
63 #define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1)
64 #define ARM_V7S_LVL_IDX(addr, lvl) ({ \
66 ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \
70 * Large page/supersection entries are effectively a block of 16 page/section
71 * entries, along the lines of the LPAE contiguous hint, but all with the
72 * same output address. For want of a better common name we'll call them
73 * "contiguous" versions of their respective page/section entries here, but
74 * noting the distinction (WRT to TLB maintenance) that they represent *one*
75 * entry repeated 16 times, not 16 separate entries (as in the LPAE case).
77 #define ARM_V7S_CONT_PAGES 16
79 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
80 #define ARM_V7S_PTE_TYPE_TABLE 0x1
81 #define ARM_V7S_PTE_TYPE_PAGE 0x2
82 #define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1
84 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0)
85 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) \
86 ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE))
89 #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl)))
90 #define ARM_V7S_ATTR_B BIT(2)
91 #define ARM_V7S_ATTR_C BIT(3)
92 #define ARM_V7S_ATTR_NS_TABLE BIT(3)
93 #define ARM_V7S_ATTR_NS_SECTION BIT(19)
95 #define ARM_V7S_CONT_SECTION BIT(18)
96 #define ARM_V7S_CONT_PAGE_XN_SHIFT 15
99 * The attribute bits are consistently ordered*, but occupy bits [17:10] of
100 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
101 * fields relative to that 8-bit block, plus a total shift relative to the PTE.
103 #define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6)
105 #define ARM_V7S_ATTR_MASK 0xff
106 #define ARM_V7S_ATTR_AP0 BIT(0)
107 #define ARM_V7S_ATTR_AP1 BIT(1)
108 #define ARM_V7S_ATTR_AP2 BIT(5)
109 #define ARM_V7S_ATTR_S BIT(6)
110 #define ARM_V7S_ATTR_NG BIT(7)
111 #define ARM_V7S_TEX_SHIFT 2
112 #define ARM_V7S_TEX_MASK 0x7
113 #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
115 #define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
117 /* *well, except for TEX on level 2 large pages, of course :( */
118 #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
119 #define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
121 /* Simplified access permissions */
122 #define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0
123 #define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1
124 #define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2
127 #define ARM_V7S_RGN_NC 0
128 #define ARM_V7S_RGN_WBWA 1
129 #define ARM_V7S_RGN_WT 2
130 #define ARM_V7S_RGN_WB 3
132 #define ARM_V7S_PRRR_TYPE_DEVICE 1
133 #define ARM_V7S_PRRR_TYPE_NORMAL 2
134 #define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2))
135 #define ARM_V7S_PRRR_DS0 BIT(16)
136 #define ARM_V7S_PRRR_DS1 BIT(17)
137 #define ARM_V7S_PRRR_NS0 BIT(18)
138 #define ARM_V7S_PRRR_NS1 BIT(19)
139 #define ARM_V7S_PRRR_NOS(n) BIT((n) + 24)
141 #define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2))
142 #define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16))
144 #define ARM_V7S_TTBR_S BIT(1)
145 #define ARM_V7S_TTBR_NOS BIT(5)
146 #define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3)
147 #define ARM_V7S_TTBR_IRGN_ATTR(attr) \
148 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1))
150 #define ARM_V7S_TCR_PD1 BIT(5)
152 #ifdef CONFIG_ZONE_DMA32
153 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA32
154 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA32
156 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA
157 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA
160 typedef u32 arm_v7s_iopte;
162 static bool selftest_running;
164 struct arm_v7s_io_pgtable {
165 struct io_pgtable iop;
168 struct kmem_cache *l2_tables;
169 spinlock_t split_lock;
172 static dma_addr_t __arm_v7s_dma_addr(void *pages)
174 return (dma_addr_t)virt_to_phys(pages);
177 static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl)
179 if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
180 pte &= ARM_V7S_TABLE_MASK;
182 pte &= ARM_V7S_LVL_MASK(lvl);
183 return phys_to_virt(pte);
186 static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
187 struct arm_v7s_io_pgtable *data)
189 struct io_pgtable_cfg *cfg = &data->iop.cfg;
190 struct device *dev = cfg->iommu_dev;
193 size_t size = ARM_V7S_TABLE_SIZE(lvl);
197 table = (void *)__get_free_pages(
198 __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size));
200 table = kmem_cache_zalloc(data->l2_tables, gfp);
201 phys = virt_to_phys(table);
202 if (phys != (arm_v7s_iopte)phys) {
203 /* Doesn't fit in PTE */
204 dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
207 if (table && !cfg->coherent_walk) {
208 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE);
209 if (dma_mapping_error(dev, dma))
212 * We depend on the IOMMU being able to work with any physical
213 * address directly, so if the DMA layer suggests otherwise by
214 * translating or truncating them, that bodes very badly...
220 kmemleak_ignore(table);
224 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
225 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
228 free_pages((unsigned long)table, get_order(size));
230 kmem_cache_free(data->l2_tables, table);
234 static void __arm_v7s_free_table(void *table, int lvl,
235 struct arm_v7s_io_pgtable *data)
237 struct io_pgtable_cfg *cfg = &data->iop.cfg;
238 struct device *dev = cfg->iommu_dev;
239 size_t size = ARM_V7S_TABLE_SIZE(lvl);
241 if (!cfg->coherent_walk)
242 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
245 free_pages((unsigned long)table, get_order(size));
247 kmem_cache_free(data->l2_tables, table);
250 static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
251 struct io_pgtable_cfg *cfg)
253 if (cfg->coherent_walk)
256 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),
257 num_entries * sizeof(*ptep), DMA_TO_DEVICE);
259 static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
260 int num_entries, struct io_pgtable_cfg *cfg)
264 for (i = 0; i < num_entries; i++)
267 __arm_v7s_pte_sync(ptep, num_entries, cfg);
270 static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
271 struct io_pgtable_cfg *cfg)
273 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
274 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
276 if (!(prot & IOMMU_MMIO))
277 pte |= ARM_V7S_ATTR_TEX(1);
279 pte |= ARM_V7S_PTE_AF;
280 if (!(prot & IOMMU_PRIV))
281 pte |= ARM_V7S_PTE_AP_UNPRIV;
282 if (!(prot & IOMMU_WRITE))
283 pte |= ARM_V7S_PTE_AP_RDONLY;
285 pte <<= ARM_V7S_ATTR_SHIFT(lvl);
287 if ((prot & IOMMU_NOEXEC) && ap)
288 pte |= ARM_V7S_ATTR_XN(lvl);
289 if (prot & IOMMU_MMIO)
290 pte |= ARM_V7S_ATTR_B;
291 else if (prot & IOMMU_CACHE)
292 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C;
294 pte |= ARM_V7S_PTE_TYPE_PAGE;
295 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
296 pte |= ARM_V7S_ATTR_NS_SECTION;
298 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
299 pte |= ARM_V7S_ATTR_MTK_4GB;
304 static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl)
306 int prot = IOMMU_READ;
307 arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
309 if (!(attr & ARM_V7S_PTE_AP_RDONLY))
311 if (!(attr & ARM_V7S_PTE_AP_UNPRIV))
313 if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
315 else if (pte & ARM_V7S_ATTR_C)
317 if (pte & ARM_V7S_ATTR_XN(lvl))
318 prot |= IOMMU_NOEXEC;
323 static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl)
326 pte |= ARM_V7S_CONT_SECTION;
327 } else if (lvl == 2) {
328 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl);
329 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK;
331 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE;
332 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) |
333 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) |
334 ARM_V7S_PTE_TYPE_CONT_PAGE;
339 static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl)
342 pte &= ~ARM_V7S_CONT_SECTION;
343 } else if (lvl == 2) {
344 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT);
345 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK <<
346 ARM_V7S_CONT_PAGE_TEX_SHIFT);
348 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE;
349 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) |
350 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) |
351 ARM_V7S_PTE_TYPE_PAGE;
356 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl)
358 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl))
359 return pte & ARM_V7S_CONT_SECTION;
361 return !(pte & ARM_V7S_PTE_TYPE_PAGE);
365 static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *, unsigned long,
366 size_t, int, arm_v7s_iopte *);
368 static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
369 unsigned long iova, phys_addr_t paddr, int prot,
370 int lvl, int num_entries, arm_v7s_iopte *ptep)
372 struct io_pgtable_cfg *cfg = &data->iop.cfg;
376 for (i = 0; i < num_entries; i++)
377 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) {
379 * We need to unmap and free the old table before
380 * overwriting it with a block entry.
383 size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
385 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl);
386 if (WARN_ON(__arm_v7s_unmap(data, iova + i * sz,
387 sz, lvl, tblp) != sz))
389 } else if (ptep[i]) {
390 /* We require an unmap first */
391 WARN_ON(!selftest_running);
395 pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
397 pte = arm_v7s_pte_to_cont(pte, lvl);
399 pte |= paddr & ARM_V7S_LVL_MASK(lvl);
401 __arm_v7s_set_pte(ptep, pte, num_entries, cfg);
405 static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
408 struct io_pgtable_cfg *cfg)
410 arm_v7s_iopte old, new;
412 new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
413 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
414 new |= ARM_V7S_ATTR_NS_TABLE;
417 * Ensure the table itself is visible before its PTE can be.
418 * Whilst we could get away with cmpxchg64_release below, this
419 * doesn't have any ordering semantics when !CONFIG_SMP.
423 old = cmpxchg_relaxed(ptep, curr, new);
424 __arm_v7s_pte_sync(ptep, 1, cfg);
429 static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
430 phys_addr_t paddr, size_t size, int prot,
431 int lvl, arm_v7s_iopte *ptep)
433 struct io_pgtable_cfg *cfg = &data->iop.cfg;
434 arm_v7s_iopte pte, *cptep;
435 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
437 /* Find our entry at the current level */
438 ptep += ARM_V7S_LVL_IDX(iova, lvl);
440 /* If we can install a leaf entry at this level, then do so */
442 return arm_v7s_init_pte(data, iova, paddr, prot,
443 lvl, num_entries, ptep);
445 /* We can't allocate tables at the final level */
446 if (WARN_ON(lvl == 2))
449 /* Grab a pointer to the next level */
450 pte = READ_ONCE(*ptep);
452 cptep = __arm_v7s_alloc_table(lvl + 1, GFP_ATOMIC, data);
456 pte = arm_v7s_install_table(cptep, ptep, 0, cfg);
458 __arm_v7s_free_table(cptep, lvl + 1, data);
460 /* We've no easy way of knowing if it's synced yet, so... */
461 __arm_v7s_pte_sync(ptep, 1, cfg);
464 if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
465 cptep = iopte_deref(pte, lvl);
467 /* We require an unmap first */
468 WARN_ON(!selftest_running);
473 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep);
476 static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
477 phys_addr_t paddr, size_t size, int prot)
479 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
480 struct io_pgtable *iop = &data->iop;
483 /* If no access, then nothing to do */
484 if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
487 if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr)))
490 ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
492 * Synchronise all PTE updates for the new mapping before there's
493 * a chance for anything to kick off a table walk for the new iova.
495 if (iop->cfg.quirks & IO_PGTABLE_QUIRK_TLBI_ON_MAP) {
496 io_pgtable_tlb_flush_walk(iop, iova, size,
497 ARM_V7S_BLOCK_SIZE(2));
505 static void arm_v7s_free_pgtable(struct io_pgtable *iop)
507 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
510 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) {
511 arm_v7s_iopte pte = data->pgd[i];
513 if (ARM_V7S_PTE_IS_TABLE(pte, 1))
514 __arm_v7s_free_table(iopte_deref(pte, 1), 2, data);
516 __arm_v7s_free_table(data->pgd, 1, data);
517 kmem_cache_destroy(data->l2_tables);
521 static arm_v7s_iopte arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
522 unsigned long iova, int idx, int lvl,
525 struct io_pgtable *iop = &data->iop;
527 size_t size = ARM_V7S_BLOCK_SIZE(lvl);
530 /* Check that we didn't lose a race to get the lock */
532 if (!arm_v7s_pte_is_cont(pte, lvl))
535 ptep -= idx & (ARM_V7S_CONT_PAGES - 1);
536 pte = arm_v7s_cont_to_pte(pte, lvl);
537 for (i = 0; i < ARM_V7S_CONT_PAGES; i++)
538 ptep[i] = pte + i * size;
540 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg);
542 size *= ARM_V7S_CONT_PAGES;
543 io_pgtable_tlb_flush_leaf(iop, iova, size, size);
547 static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
548 unsigned long iova, size_t size,
549 arm_v7s_iopte blk_pte,
552 struct io_pgtable_cfg *cfg = &data->iop.cfg;
553 arm_v7s_iopte pte, *tablep;
554 int i, unmap_idx, num_entries, num_ptes;
556 tablep = __arm_v7s_alloc_table(2, GFP_ATOMIC, data);
558 return 0; /* Bytes unmapped */
560 num_ptes = ARM_V7S_PTES_PER_LVL(2);
561 num_entries = size >> ARM_V7S_LVL_SHIFT(2);
562 unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
564 pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
566 pte = arm_v7s_pte_to_cont(pte, 2);
568 for (i = 0; i < num_ptes; i += num_entries, pte += size) {
573 __arm_v7s_set_pte(&tablep[i], pte, num_entries, cfg);
576 pte = arm_v7s_install_table(tablep, ptep, blk_pte, cfg);
577 if (pte != blk_pte) {
578 __arm_v7s_free_table(tablep, 2, data);
580 if (!ARM_V7S_PTE_IS_TABLE(pte, 1))
583 tablep = iopte_deref(pte, 1);
584 return __arm_v7s_unmap(data, iova, size, 2, tablep);
587 io_pgtable_tlb_add_flush(&data->iop, iova, size, size, true);
591 static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
592 unsigned long iova, size_t size, int lvl,
595 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES];
596 struct io_pgtable *iop = &data->iop;
597 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
599 /* Something went horribly wrong and we ran out of page table */
600 if (WARN_ON(lvl > 2))
603 idx = ARM_V7S_LVL_IDX(iova, lvl);
606 pte[i] = READ_ONCE(ptep[i]);
607 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(pte[i])))
609 } while (++i < num_entries);
612 * If we've hit a contiguous 'large page' entry at this level, it
613 * needs splitting first, unless we're unmapping the whole lot.
615 * For splitting, we can't rewrite 16 PTEs atomically, and since we
616 * can't necessarily assume TEX remap we don't have a software bit to
617 * mark live entries being split. In practice (i.e. DMA API code), we
618 * will never be splitting large pages anyway, so just wrap this edge
619 * case in a lock for the sake of correctness and be done with it.
621 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) {
624 spin_lock_irqsave(&data->split_lock, flags);
625 pte[0] = arm_v7s_split_cont(data, iova, idx, lvl, ptep);
626 spin_unlock_irqrestore(&data->split_lock, flags);
629 /* If the size matches this level, we're in the right place */
631 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl);
633 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg);
635 for (i = 0; i < num_entries; i++) {
636 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) {
637 /* Also flush any partial walks */
638 io_pgtable_tlb_flush_walk(iop, iova, blk_size,
639 ARM_V7S_BLOCK_SIZE(lvl + 1));
640 ptep = iopte_deref(pte[i], lvl);
641 __arm_v7s_free_table(ptep, lvl + 1, data);
642 } else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) {
644 * Order the PTE update against queueing the IOVA, to
645 * guarantee that a flush callback from a different CPU
646 * has observed it before the TLBIALL can be issued.
650 io_pgtable_tlb_add_flush(iop, iova, blk_size,
656 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) {
658 * Insert a table at the next level to map the old region,
659 * minus the part we want to unmap
661 return arm_v7s_split_blk_unmap(data, iova, size, pte[0], ptep);
664 /* Keep on walkin' */
665 ptep = iopte_deref(pte[0], lvl);
666 return __arm_v7s_unmap(data, iova, size, lvl + 1, ptep);
669 static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
672 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
674 if (WARN_ON(upper_32_bits(iova)))
677 return __arm_v7s_unmap(data, iova, size, 1, data->pgd);
680 static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
683 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
684 arm_v7s_iopte *ptep = data->pgd, pte;
689 ptep += ARM_V7S_LVL_IDX(iova, ++lvl);
690 pte = READ_ONCE(*ptep);
691 ptep = iopte_deref(pte, lvl);
692 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
694 if (!ARM_V7S_PTE_IS_VALID(pte))
697 mask = ARM_V7S_LVL_MASK(lvl);
698 if (arm_v7s_pte_is_cont(pte, lvl))
699 mask *= ARM_V7S_CONT_PAGES;
700 return (pte & mask) | (iova & ~mask);
703 static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
706 struct arm_v7s_io_pgtable *data;
708 if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS)
711 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
712 IO_PGTABLE_QUIRK_NO_PERMS |
713 IO_PGTABLE_QUIRK_TLBI_ON_MAP |
714 IO_PGTABLE_QUIRK_ARM_MTK_4GB |
715 IO_PGTABLE_QUIRK_NON_STRICT))
718 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
719 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB &&
720 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
723 data = kmalloc(sizeof(*data), GFP_KERNEL);
727 spin_lock_init(&data->split_lock);
728 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
729 ARM_V7S_TABLE_SIZE(2),
730 ARM_V7S_TABLE_SIZE(2),
731 ARM_V7S_TABLE_SLAB_FLAGS, NULL);
732 if (!data->l2_tables)
735 data->iop.ops = (struct io_pgtable_ops) {
737 .unmap = arm_v7s_unmap,
738 .iova_to_phys = arm_v7s_iova_to_phys,
741 /* We have to do this early for __arm_v7s_alloc_table to work... */
742 data->iop.cfg = *cfg;
745 * Unless the IOMMU driver indicates supersection support by
746 * having SZ_16M set in the initial bitmap, they won't be used.
748 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
750 /* TCR: T0SZ=0, disable TTBR1 */
751 cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1;
754 * TEX remap: the indices used map to the closest equivalent types
755 * under the non-TEX-remap interpretation of those attribute bits,
756 * excepting various implementation-defined aspects of shareability.
758 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) |
759 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) |
760 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) |
761 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 |
762 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7);
763 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) |
764 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA);
766 /* Looking good; allocate a pgd */
767 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data);
771 /* Ensure the empty pgd is visible before any actual TTBR write */
775 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) |
776 ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS |
777 (cfg->coherent_walk ?
778 (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
779 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
780 (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
781 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
782 cfg->arm_v7s_cfg.ttbr[1] = 0;
786 kmem_cache_destroy(data->l2_tables);
791 struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = {
792 .alloc = arm_v7s_alloc_pgtable,
793 .free = arm_v7s_free_pgtable,
796 #ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST
798 static struct io_pgtable_cfg *cfg_cookie;
800 static void dummy_tlb_flush_all(void *cookie)
802 WARN_ON(cookie != cfg_cookie);
805 static void dummy_tlb_flush(unsigned long iova, size_t size, size_t granule,
808 WARN_ON(cookie != cfg_cookie);
809 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
812 static void dummy_tlb_add_flush(unsigned long iova, size_t size,
813 size_t granule, bool leaf, void *cookie)
815 dummy_tlb_flush(iova, size, granule, cookie);
818 static void dummy_tlb_sync(void *cookie)
820 WARN_ON(cookie != cfg_cookie);
823 static const struct iommu_flush_ops dummy_tlb_ops = {
824 .tlb_flush_all = dummy_tlb_flush_all,
825 .tlb_flush_walk = dummy_tlb_flush,
826 .tlb_flush_leaf = dummy_tlb_flush,
827 .tlb_add_flush = dummy_tlb_add_flush,
828 .tlb_sync = dummy_tlb_sync,
831 #define __FAIL(ops) ({ \
832 WARN(1, "selftest: test failed\n"); \
833 selftest_running = false; \
837 static int __init arm_v7s_do_selftests(void)
839 struct io_pgtable_ops *ops;
840 struct io_pgtable_cfg cfg = {
841 .tlb = &dummy_tlb_ops,
844 .coherent_walk = true,
845 .quirks = IO_PGTABLE_QUIRK_ARM_NS,
846 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
848 unsigned int iova, size, iova_start;
849 unsigned int i, loopnr = 0;
851 selftest_running = true;
855 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg);
857 pr_err("selftest: failed to allocate io pgtable ops\n");
862 * Initial sanity checks.
863 * Empty page tables shouldn't provide any translations.
865 if (ops->iova_to_phys(ops, 42))
868 if (ops->iova_to_phys(ops, SZ_1G + 42))
871 if (ops->iova_to_phys(ops, SZ_2G + 42))
875 * Distinct mappings of different granule sizes.
878 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
880 if (ops->map(ops, iova, iova, size, IOMMU_READ |
886 /* Overlapping mappings */
887 if (!ops->map(ops, iova, iova + size, size,
888 IOMMU_READ | IOMMU_NOEXEC))
891 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
900 size = 1UL << __ffs(cfg.pgsize_bitmap);
902 iova_start = i * SZ_16M;
903 if (ops->unmap(ops, iova_start + size, size) != size)
906 /* Remap of partial unmap */
907 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ))
910 if (ops->iova_to_phys(ops, iova_start + size + 42)
918 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
921 if (ops->unmap(ops, iova, size) != size)
924 if (ops->iova_to_phys(ops, iova + 42))
927 /* Remap full block */
928 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
931 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
937 free_io_pgtable_ops(ops);
939 selftest_running = false;
941 pr_info("self test ok\n");
944 subsys_initcall(arm_v7s_do_selftests);