drivers/iommu/ipmmu-vmsa.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * IOMMU API for Renesas VMSA-compatible IPMMU
   4  * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   5  *
   6  * Copyright (C) 2014 Renesas Electronics Corporation
   7  */
   8
   9 #include <linux/bitmap.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-iommu.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/export.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/io-pgtable.h>
  19 #include <linux/iommu.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sizes.h>
  26 #include <linux/slab.h>
  27 #include <linux/sys_soc.h>
  28
  29 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
  30 #include <asm/dma-iommu.h>
  31 #include <asm/pgalloc.h>
  32 #else
  33 #define arm_iommu_create_mapping(...)   NULL
  34 #define arm_iommu_attach_device(...)    -ENODEV
  35 #define arm_iommu_release_mapping(...)  do {} while (0)
  36 #define arm_iommu_detach_device(...)    do {} while (0)
  37 #endif
  38
  39 #define IPMMU_CTX_MAX           8U
  40 #define IPMMU_CTX_INVALID       -1
  41
  42 #define IPMMU_UTLB_MAX          48U
  43
  44 struct ipmmu_features {
  45         bool use_ns_alias_offset;
  46         bool has_cache_leaf_nodes;
  47         unsigned int number_of_contexts;
  48         unsigned int num_utlbs;
  49         bool setup_imbuscr;
  50         bool twobit_imttbcr_sl0;
  51         bool reserved_context;
  52 };
  53
  54 struct ipmmu_vmsa_device {
  55         struct device *dev;
  56         void __iomem *base;
  57         struct iommu_device iommu;
  58         struct ipmmu_vmsa_device *root;
  59         const struct ipmmu_features *features;
  60         unsigned int num_ctx;
  61         spinlock_t lock;                        /* Protects ctx and domains[] */
  62         DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
  63         struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
  64         s8 utlb_ctx[IPMMU_UTLB_MAX];
  65
  66         struct iommu_group *group;
  67         struct dma_iommu_mapping *mapping;
  68 };
  69
  70 struct ipmmu_vmsa_domain {
  71         struct ipmmu_vmsa_device *mmu;
  72         struct iommu_domain io_domain;
  73
  74         struct io_pgtable_cfg cfg;
  75         struct io_pgtable_ops *iop;
  76
  77         unsigned int context_id;
  78         struct mutex mutex;                     /* Protects mappings */
  79 };
  80
  81 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
  82 {
  83         return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
  84 }
  85
  86 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
  87 {
  88         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
  89
  90         return fwspec ? fwspec->iommu_priv : NULL;
  91 }
  92
  93 #define TLB_LOOP_TIMEOUT                100     /* 100us */
  94
  95 /* -----------------------------------------------------------------------------
  96  * Registers Definition
  97  */
  98
  99 #define IM_NS_ALIAS_OFFSET              0x800
 100
 101 #define IM_CTX_SIZE                     0x40
 102
 103 #define IMCTR                           0x0000
 104 #define IMCTR_TRE                       (1 << 17)
 105 #define IMCTR_AFE                       (1 << 16)
 106 #define IMCTR_RTSEL_MASK                (3 << 4)
 107 #define IMCTR_RTSEL_SHIFT               4
 108 #define IMCTR_TREN                      (1 << 3)
 109 #define IMCTR_INTEN                     (1 << 2)
 110 #define IMCTR_FLUSH                     (1 << 1)
 111 #define IMCTR_MMUEN                     (1 << 0)
 112
 113 #define IMCAAR                          0x0004
 114
 115 #define IMTTBCR                         0x0008
 116 #define IMTTBCR_EAE                     (1 << 31)
 117 #define IMTTBCR_PMB                     (1 << 30)
 118 #define IMTTBCR_SH1_NON_SHAREABLE       (0 << 28)
 119 #define IMTTBCR_SH1_OUTER_SHAREABLE     (2 << 28)
 120 #define IMTTBCR_SH1_INNER_SHAREABLE     (3 << 28)
 121 #define IMTTBCR_SH1_MASK                (3 << 28)
 122 #define IMTTBCR_ORGN1_NC                (0 << 26)
 123 #define IMTTBCR_ORGN1_WB_WA             (1 << 26)
 124 #define IMTTBCR_ORGN1_WT                (2 << 26)
 125 #define IMTTBCR_ORGN1_WB                (3 << 26)
 126 #define IMTTBCR_ORGN1_MASK              (3 << 26)
 127 #define IMTTBCR_IRGN1_NC                (0 << 24)
 128 #define IMTTBCR_IRGN1_WB_WA             (1 << 24)
 129 #define IMTTBCR_IRGN1_WT                (2 << 24)
 130 #define IMTTBCR_IRGN1_WB                (3 << 24)
 131 #define IMTTBCR_IRGN1_MASK              (3 << 24)
 132 #define IMTTBCR_TSZ1_MASK               (7 << 16)
 133 #define IMTTBCR_TSZ1_SHIFT              16
 134 #define IMTTBCR_SH0_NON_SHAREABLE       (0 << 12)
 135 #define IMTTBCR_SH0_OUTER_SHAREABLE     (2 << 12)
 136 #define IMTTBCR_SH0_INNER_SHAREABLE     (3 << 12)
 137 #define IMTTBCR_SH0_MASK                (3 << 12)
 138 #define IMTTBCR_ORGN0_NC                (0 << 10)
 139 #define IMTTBCR_ORGN0_WB_WA             (1 << 10)
 140 #define IMTTBCR_ORGN0_WT                (2 << 10)
 141 #define IMTTBCR_ORGN0_WB                (3 << 10)
 142 #define IMTTBCR_ORGN0_MASK              (3 << 10)
 143 #define IMTTBCR_IRGN0_NC                (0 << 8)
 144 #define IMTTBCR_IRGN0_WB_WA             (1 << 8)
 145 #define IMTTBCR_IRGN0_WT                (2 << 8)
 146 #define IMTTBCR_IRGN0_WB                (3 << 8)
 147 #define IMTTBCR_IRGN0_MASK              (3 << 8)
 148 #define IMTTBCR_SL0_LVL_2               (0 << 4)
 149 #define IMTTBCR_SL0_LVL_1               (1 << 4)
 150 #define IMTTBCR_TSZ0_MASK               (7 << 0)
 151 #define IMTTBCR_TSZ0_SHIFT              O
 152
 153 #define IMTTBCR_SL0_TWOBIT_LVL_3        (0 << 6)
 154 #define IMTTBCR_SL0_TWOBIT_LVL_2        (1 << 6)
 155 #define IMTTBCR_SL0_TWOBIT_LVL_1        (2 << 6)
 156
 157 #define IMBUSCR                         0x000c
 158 #define IMBUSCR_DVM                     (1 << 2)
 159 #define IMBUSCR_BUSSEL_SYS              (0 << 0)
 160 #define IMBUSCR_BUSSEL_CCI              (1 << 0)
 161 #define IMBUSCR_BUSSEL_IMCAAR           (2 << 0)
 162 #define IMBUSCR_BUSSEL_CCI_IMCAAR       (3 << 0)
 163 #define IMBUSCR_BUSSEL_MASK             (3 << 0)
 164
 165 #define IMTTLBR0                        0x0010
 166 #define IMTTUBR0                        0x0014
 167 #define IMTTLBR1                        0x0018
 168 #define IMTTUBR1                        0x001c
 169
 170 #define IMSTR                           0x0020
 171 #define IMSTR_ERRLVL_MASK               (3 << 12)
 172 #define IMSTR_ERRLVL_SHIFT              12
 173 #define IMSTR_ERRCODE_TLB_FORMAT        (1 << 8)
 174 #define IMSTR_ERRCODE_ACCESS_PERM       (4 << 8)
 175 #define IMSTR_ERRCODE_SECURE_ACCESS     (5 << 8)
 176 #define IMSTR_ERRCODE_MASK              (7 << 8)
 177 #define IMSTR_MHIT                      (1 << 4)
 178 #define IMSTR_ABORT                     (1 << 2)
 179 #define IMSTR_PF                        (1 << 1)
 180 #define IMSTR_TF                        (1 << 0)
 181
 182 #define IMMAIR0                         0x0028
 183 #define IMMAIR1                         0x002c
 184 #define IMMAIR_ATTR_MASK                0xff
 185 #define IMMAIR_ATTR_DEVICE              0x04
 186 #define IMMAIR_ATTR_NC                  0x44
 187 #define IMMAIR_ATTR_WBRWA               0xff
 188 #define IMMAIR_ATTR_SHIFT(n)            ((n) << 3)
 189 #define IMMAIR_ATTR_IDX_NC              0
 190 #define IMMAIR_ATTR_IDX_WBRWA           1
 191 #define IMMAIR_ATTR_IDX_DEV             2
 192
 193 #define IMELAR                          0x0030  /* IMEAR on R-Car Gen2 */
 194 #define IMEUAR                          0x0034  /* R-Car Gen3 only */
 195
 196 #define IMPCTR                          0x0200
 197 #define IMPSTR                          0x0208
 198 #define IMPEAR                          0x020c
 199 #define IMPMBA(n)                       (0x0280 + ((n) * 4))
 200 #define IMPMBD(n)                       (0x02c0 + ((n) * 4))
 201
 202 #define IMUCTR(n)                       ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n))
 203 #define IMUCTR0(n)                      (0x0300 + ((n) * 16))
 204 #define IMUCTR32(n)                     (0x0600 + (((n) - 32) * 16))
 205 #define IMUCTR_FIXADDEN                 (1 << 31)
 206 #define IMUCTR_FIXADD_MASK              (0xff << 16)
 207 #define IMUCTR_FIXADD_SHIFT             16
 208 #define IMUCTR_TTSEL_MMU(n)             ((n) << 4)
 209 #define IMUCTR_TTSEL_PMB                (8 << 4)
 210 #define IMUCTR_TTSEL_MASK               (15 << 4)
 211 #define IMUCTR_FLUSH                    (1 << 1)
 212 #define IMUCTR_MMUEN                    (1 << 0)
 213
 214 #define IMUASID(n)                      ((n) < 32 ? IMUASID0(n) : IMUASID32(n))
 215 #define IMUASID0(n)                     (0x0308 + ((n) * 16))
 216 #define IMUASID32(n)                    (0x0608 + (((n) - 32) * 16))
 217 #define IMUASID_ASID8_MASK              (0xff << 8)
 218 #define IMUASID_ASID8_SHIFT             8
 219 #define IMUASID_ASID0_MASK              (0xff << 0)
 220 #define IMUASID_ASID0_SHIFT             0
 221
 222 /* -----------------------------------------------------------------------------
 223  * Root device handling
 224  */
 225
 226 static struct platform_driver ipmmu_driver;
 227
 228 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu)
 229 {
 230         return mmu->root == mmu;
 231 }
 232
 233 static int __ipmmu_check_device(struct device *dev, void *data)
 234 {
 235         struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
 236         struct ipmmu_vmsa_device **rootp = data;
 237
 238         if (ipmmu_is_root(mmu))
 239                 *rootp = mmu;
 240
 241         return 0;
 242 }
 243
 244 static struct ipmmu_vmsa_device *ipmmu_find_root(void)
 245 {
 246         struct ipmmu_vmsa_device *root = NULL;
 247
 248         return driver_for_each_device(&ipmmu_driver.driver, NULL, &root,
 249                                       __ipmmu_check_device) == 0 ? root : NULL;
 250 }
 251
 252 /* -----------------------------------------------------------------------------
 253  * Read/Write Access
 254  */
 255
 256 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
 257 {
 258         return ioread32(mmu->base + offset);
 259 }
 260
 261 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
 262                         u32 data)
 263 {
 264         iowrite32(data, mmu->base + offset);
 265 }
 266
 267 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain,
 268                                unsigned int reg)
 269 {
 270         return ipmmu_read(domain->mmu->root,
 271                           domain->context_id * IM_CTX_SIZE + reg);
 272 }
 273
 274 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain,
 275                                  unsigned int reg, u32 data)
 276 {
 277         ipmmu_write(domain->mmu->root,
 278                     domain->context_id * IM_CTX_SIZE + reg, data);
 279 }
 280
 281 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain,
 282                                 unsigned int reg, u32 data)
 283 {
 284         if (domain->mmu != domain->mmu->root)
 285                 ipmmu_write(domain->mmu,
 286                             domain->context_id * IM_CTX_SIZE + reg, data);
 287
 288         ipmmu_write(domain->mmu->root,
 289                     domain->context_id * IM_CTX_SIZE + reg, data);
 290 }
 291
 292 /* -----------------------------------------------------------------------------
 293  * TLB and microTLB Management
 294  */
 295
 296 /* Wait for any pending TLB invalidations to complete */
 297 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
 298 {
 299         unsigned int count = 0;
 300
 301         while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) {
 302                 cpu_relax();
 303                 if (++count == TLB_LOOP_TIMEOUT) {
 304                         dev_err_ratelimited(domain->mmu->dev,
 305                         "TLB sync timed out -- MMU may be deadlocked\n");
 306                         return;
 307                 }
 308                 udelay(1);
 309         }
 310 }
 311
 312 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
 313 {
 314         u32 reg;
 315
 316         reg = ipmmu_ctx_read_root(domain, IMCTR);
 317         reg |= IMCTR_FLUSH;
 318         ipmmu_ctx_write_all(domain, IMCTR, reg);
 319
 320         ipmmu_tlb_sync(domain);
 321 }
 322
 323 /*
 324  * Enable MMU translation for the microTLB.
 325  */
 326 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
 327                               unsigned int utlb)
 328 {
 329         struct ipmmu_vmsa_device *mmu = domain->mmu;
 330
 331         /*
 332          * TODO: Reference-count the microTLB as several bus masters can be
 333          * connected to the same microTLB.
 334          */
 335
 336         /* TODO: What should we set the ASID to ? */
 337         ipmmu_write(mmu, IMUASID(utlb), 0);
 338         /* TODO: Do we need to flush the microTLB ? */
 339         ipmmu_write(mmu, IMUCTR(utlb),
 340                     IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH |
 341                     IMUCTR_MMUEN);
 342         mmu->utlb_ctx[utlb] = domain->context_id;
 343 }
 344
 345 /*
 346  * Disable MMU translation for the microTLB.
 347  */
 348 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
 349                                unsigned int utlb)
 350 {
 351         struct ipmmu_vmsa_device *mmu = domain->mmu;
 352
 353         ipmmu_write(mmu, IMUCTR(utlb), 0);
 354         mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID;
 355 }
 356
 357 static void ipmmu_tlb_flush_all(void *cookie)
 358 {
 359         struct ipmmu_vmsa_domain *domain = cookie;
 360
 361         ipmmu_tlb_invalidate(domain);
 362 }
 363
 364 static void ipmmu_tlb_add_flush(unsigned long iova, size_t size,
 365                                 size_t granule, bool leaf, void *cookie)
 366 {
 367         /* The hardware doesn't support selective TLB flush. */
 368 }
 369
 370 static const struct iommu_gather_ops ipmmu_gather_ops = {
 371         .tlb_flush_all = ipmmu_tlb_flush_all,
 372         .tlb_add_flush = ipmmu_tlb_add_flush,
 373         .tlb_sync = ipmmu_tlb_flush_all,
 374 };
 375
 376 /* -----------------------------------------------------------------------------
 377  * Domain/Context Management
 378  */
 379
 380 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu,
 381                                          struct ipmmu_vmsa_domain *domain)
 382 {
 383         unsigned long flags;
 384         int ret;
 385
 386         spin_lock_irqsave(&mmu->lock, flags);
 387
 388         ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx);
 389         if (ret != mmu->num_ctx) {
 390                 mmu->domains[ret] = domain;
 391                 set_bit(ret, mmu->ctx);
 392         } else
 393                 ret = -EBUSY;
 394
 395         spin_unlock_irqrestore(&mmu->lock, flags);
 396
 397         return ret;
 398 }
 399
 400 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
 401                                       unsigned int context_id)
 402 {
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&mmu->lock, flags);
 406
 407         clear_bit(context_id, mmu->ctx);
 408         mmu->domains[context_id] = NULL;
 409
 410         spin_unlock_irqrestore(&mmu->lock, flags);
 411 }
 412
 413 static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain)
 414 {
 415         u64 ttbr;
 416         u32 tmp;
 417
 418         /* TTBR0 */
 419         ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];
 420         ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);
 421         ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);
 422
 423         /*
 424          * TTBCR
 425          * We use long descriptors with inner-shareable WBWA tables and allocate
 426          * the whole 32-bit VA space to TTBR0.
 427          */
 428         if (domain->mmu->features->twobit_imttbcr_sl0)
 429                 tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
 430         else
 431                 tmp = IMTTBCR_SL0_LVL_1;
 432
 433         ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE |
 434                              IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
 435                              IMTTBCR_IRGN0_WB_WA | tmp);
 436
 437         /* MAIR0 */
 438         ipmmu_ctx_write_root(domain, IMMAIR0,
 439                              domain->cfg.arm_lpae_s1_cfg.mair[0]);
 440
 441         /* IMBUSCR */
 442         if (domain->mmu->features->setup_imbuscr)
 443                 ipmmu_ctx_write_root(domain, IMBUSCR,
 444                                      ipmmu_ctx_read_root(domain, IMBUSCR) &
 445                                      ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
 446
 447         /*
 448          * IMSTR
 449          * Clear all interrupt flags.
 450          */
 451         ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR));
 452
 453         /*
 454          * IMCTR
 455          * Enable the MMU and interrupt generation. The long-descriptor
 456          * translation table format doesn't use TEX remapping. Don't enable AF
 457          * software management as we have no use for it. Flush the TLB as
 458          * required when modifying the context registers.
 459          */
 460         ipmmu_ctx_write_all(domain, IMCTR,
 461                             IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
 462 }
 463
 464 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
 465 {
 466         int ret;
 467
 468         /*
 469          * Allocate the page table operations.
 470          *
 471          * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
 472          * access, Long-descriptor format" that the NStable bit being set in a
 473          * table descriptor will result in the NStable and NS bits of all child
 474          * entries being ignored and considered as being set. The IPMMU seems
 475          * not to comply with this, as it generates a secure access page fault
 476          * if any of the NStable and NS bits isn't set when running in
 477          * non-secure mode.
 478          */
 479         domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
 480         domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
 481         domain->cfg.ias = 32;
 482         domain->cfg.oas = 40;
 483         domain->cfg.tlb = &ipmmu_gather_ops;
 484         domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
 485         domain->io_domain.geometry.force_aperture = true;
 486         /*
 487          * TODO: Add support for coherent walk through CCI with DVM and remove
 488          * cache handling. For now, delegate it to the io-pgtable code.
 489          */
 490         domain->cfg.iommu_dev = domain->mmu->root->dev;
 491
 492         /*
 493          * Find an unused context.
 494          */
 495         ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
 496         if (ret < 0)
 497                 return ret;
 498
 499         domain->context_id = ret;
 500
 501         domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
 502                                            domain);
 503         if (!domain->iop) {
 504                 ipmmu_domain_free_context(domain->mmu->root,
 505                                           domain->context_id);
 506                 return -EINVAL;
 507         }
 508
 509         ipmmu_domain_setup_context(domain);
 510         return 0;
 511 }
 512
 513 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
 514 {
 515         if (!domain->mmu)
 516                 return;
 517
 518         /*
 519          * Disable the context. Flush the TLB as required when modifying the
 520          * context registers.
 521          *
 522          * TODO: Is TLB flush really needed ?
 523          */
 524         ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH);
 525         ipmmu_tlb_sync(domain);
 526         ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
 527 }
 528
 529 /* -----------------------------------------------------------------------------
 530  * Fault Handling
 531  */
 532
 533 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
 534 {
 535         const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
 536         struct ipmmu_vmsa_device *mmu = domain->mmu;
 537         unsigned long iova;
 538         u32 status;
 539
 540         status = ipmmu_ctx_read_root(domain, IMSTR);
 541         if (!(status & err_mask))
 542                 return IRQ_NONE;
 543
 544         iova = ipmmu_ctx_read_root(domain, IMELAR);
 545         if (IS_ENABLED(CONFIG_64BIT))
 546                 iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32;
 547
 548         /*
 549          * Clear the error status flags. Unlike traditional interrupt flag
 550          * registers that must be cleared by writing 1, this status register
 551          * seems to require 0. The error address register must be read before,
 552          * otherwise its value will be 0.
 553          */
 554         ipmmu_ctx_write_root(domain, IMSTR, 0);
 555
 556         /* Log fatal errors. */
 557         if (status & IMSTR_MHIT)
 558                 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n",
 559                                     iova);
 560         if (status & IMSTR_ABORT)
 561                 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n",
 562                                     iova);
 563
 564         if (!(status & (IMSTR_PF | IMSTR_TF)))
 565                 return IRQ_NONE;
 566
 567         /*
 568          * Try to handle page faults and translation faults.
 569          *
 570          * TODO: We need to look up the faulty device based on the I/O VA. Use
 571          * the IOMMU device for now.
 572          */
 573         if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
 574                 return IRQ_HANDLED;
 575
 576         dev_err_ratelimited(mmu->dev,
 577                             "Unhandled fault: status 0x%08x iova 0x%lx\n",
 578                             status, iova);
 579
 580         return IRQ_HANDLED;
 581 }
 582
 583 static irqreturn_t ipmmu_irq(int irq, void *dev)
 584 {
 585         struct ipmmu_vmsa_device *mmu = dev;
 586         irqreturn_t status = IRQ_NONE;
 587         unsigned int i;
 588         unsigned long flags;
 589
 590         spin_lock_irqsave(&mmu->lock, flags);
 591
 592         /*
 593          * Check interrupts for all active contexts.
 594          */
 595         for (i = 0; i < mmu->num_ctx; i++) {
 596                 if (!mmu->domains[i])
 597                         continue;
 598                 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED)
 599                         status = IRQ_HANDLED;
 600         }
 601
 602         spin_unlock_irqrestore(&mmu->lock, flags);
 603
 604         return status;
 605 }
 606
 607 /* -----------------------------------------------------------------------------
 608  * IOMMU Operations
 609  */
 610
 611 static struct iommu_domain *__ipmmu_domain_alloc(unsigned type)
 612 {
 613         struct ipmmu_vmsa_domain *domain;
 614
 615         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 616         if (!domain)
 617                 return NULL;
 618
 619         mutex_init(&domain->mutex);
 620
 621         return &domain->io_domain;
 622 }
 623
 624 static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
 625 {
 626         struct iommu_domain *io_domain = NULL;
 627
 628         switch (type) {
 629         case IOMMU_DOMAIN_UNMANAGED:
 630                 io_domain = __ipmmu_domain_alloc(type);
 631                 break;
 632
 633         case IOMMU_DOMAIN_DMA:
 634                 io_domain = __ipmmu_domain_alloc(type);
 635                 if (io_domain && iommu_get_dma_cookie(io_domain)) {
 636                         kfree(io_domain);
 637                         io_domain = NULL;
 638                 }
 639                 break;
 640         }
 641
 642         return io_domain;
 643 }
 644
 645 static void ipmmu_domain_free(struct iommu_domain *io_domain)
 646 {
 647         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 648
 649         /*
 650          * Free the domain resources. We assume that all devices have already
 651          * been detached.
 652          */
 653         iommu_put_dma_cookie(io_domain);
 654         ipmmu_domain_destroy_context(domain);
 655         free_io_pgtable_ops(domain->iop);
 656         kfree(domain);
 657 }
 658
 659 static int ipmmu_attach_device(struct iommu_domain *io_domain,
 660                                struct device *dev)
 661 {
 662         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 663         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 664         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 665         unsigned int i;
 666         int ret = 0;
 667
 668         if (!mmu) {
 669                 dev_err(dev, "Cannot attach to IPMMU\n");
 670                 return -ENXIO;
 671         }
 672
 673         mutex_lock(&domain->mutex);
 674
 675         if (!domain->mmu) {
 676                 /* The domain hasn't been used yet, initialize it. */
 677                 domain->mmu = mmu;
 678                 ret = ipmmu_domain_init_context(domain);
 679                 if (ret < 0) {
 680                         dev_err(dev, "Unable to initialize IPMMU context\n");
 681                         domain->mmu = NULL;
 682                 } else {
 683                         dev_info(dev, "Using IPMMU context %u\n",
 684                                  domain->context_id);
 685                 }
 686         } else if (domain->mmu != mmu) {
 687                 /*
 688                  * Something is wrong, we can't attach two devices using
 689                  * different IOMMUs to the same domain.
 690                  */
 691                 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n",
 692                         dev_name(mmu->dev), dev_name(domain->mmu->dev));
 693                 ret = -EINVAL;
 694         } else
 695                 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id);
 696
 697         mutex_unlock(&domain->mutex);
 698
 699         if (ret < 0)
 700                 return ret;
 701
 702         for (i = 0; i < fwspec->num_ids; ++i)
 703                 ipmmu_utlb_enable(domain, fwspec->ids[i]);
 704
 705         return 0;
 706 }
 707
 708 static void ipmmu_detach_device(struct iommu_domain *io_domain,
 709                                 struct device *dev)
 710 {
 711         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 712         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 713         unsigned int i;
 714
 715         for (i = 0; i < fwspec->num_ids; ++i)
 716                 ipmmu_utlb_disable(domain, fwspec->ids[i]);
 717
 718         /*
 719          * TODO: Optimize by disabling the context when no device is attached.
 720          */
 721 }
 722
 723 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
 724                      phys_addr_t paddr, size_t size, int prot)
 725 {
 726         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 727
 728         if (!domain)
 729                 return -ENODEV;
 730
 731         return domain->iop->map(domain->iop, iova, paddr, size, prot);
 732 }
 733
 734 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
 735                           size_t size)
 736 {
 737         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 738
 739         return domain->iop->unmap(domain->iop, iova, size);
 740 }
 741
 742 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain)
 743 {
 744         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 745
 746         if (domain->mmu)
 747                 ipmmu_tlb_flush_all(domain);
 748 }
 749
 750 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
 751                                       dma_addr_t iova)
 752 {
 753         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 754
 755         /* TODO: Is locking needed ? */
 756
 757         return domain->iop->iova_to_phys(domain->iop, iova);
 758 }
 759
 760 static int ipmmu_init_platform_device(struct device *dev,
 761                                       struct of_phandle_args *args)
 762 {
 763         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 764         struct platform_device *ipmmu_pdev;
 765
 766         ipmmu_pdev = of_find_device_by_node(args->np);
 767         if (!ipmmu_pdev)
 768                 return -ENODEV;
 769
 770         fwspec->iommu_priv = platform_get_drvdata(ipmmu_pdev);
 771
 772         return 0;
 773 }
 774
 775 static const struct soc_device_attribute soc_rcar_gen3[] = {
 776         { .soc_id = "r8a774a1", },
 777         { .soc_id = "r8a774c0", },
 778         { .soc_id = "r8a7795", },
 779         { .soc_id = "r8a7796", },
 780         { .soc_id = "r8a77965", },
 781         { .soc_id = "r8a77970", },
 782         { .soc_id = "r8a77990", },
 783         { .soc_id = "r8a77995", },
 784         { /* sentinel */ }
 785 };
 786
 787 static const struct soc_device_attribute soc_rcar_gen3_whitelist[] = {
 788         { .soc_id = "r8a774c0", },
 789         { .soc_id = "r8a7795", .revision = "ES3.*" },
 790         { .soc_id = "r8a77965", },
 791         { .soc_id = "r8a77990", },
 792         { .soc_id = "r8a77995", },
 793         { /* sentinel */ }
 794 };
 795
 796 static const char * const rcar_gen3_slave_whitelist[] = {
 797 };
 798
 799 static bool ipmmu_slave_whitelist(struct device *dev)
 800 {
 801         unsigned int i;
 802
 803         /*
 804          * For R-Car Gen3 use a white list to opt-in slave devices.
 805          * For Other SoCs, this returns true anyway.
 806          */
 807         if (!soc_device_match(soc_rcar_gen3))
 808                 return true;
 809
 810         /* Check whether this R-Car Gen3 can use the IPMMU correctly or not */
 811         if (!soc_device_match(soc_rcar_gen3_whitelist))
 812                 return false;
 813
 814         /* Check whether this slave device can work with the IPMMU */
 815         for (i = 0; i < ARRAY_SIZE(rcar_gen3_slave_whitelist); i++) {
 816                 if (!strcmp(dev_name(dev), rcar_gen3_slave_whitelist[i]))
 817                         return true;
 818         }
 819
 820         /* Otherwise, do not allow use of IPMMU */
 821         return false;
 822 }
 823
 824 static int ipmmu_of_xlate(struct device *dev,
 825                           struct of_phandle_args *spec)
 826 {
 827         if (!ipmmu_slave_whitelist(dev))
 828                 return -ENODEV;
 829
 830         iommu_fwspec_add_ids(dev, spec->args, 1);
 831
 832         /* Initialize once - xlate() will call multiple times */
 833         if (to_ipmmu(dev))
 834                 return 0;
 835
 836         return ipmmu_init_platform_device(dev, spec);
 837 }
 838
 839 static int ipmmu_init_arm_mapping(struct device *dev)
 840 {
 841         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 842         struct iommu_group *group;
 843         int ret;
 844
 845         /* Create a device group and add the device to it. */
 846         group = iommu_group_alloc();
 847         if (IS_ERR(group)) {
 848                 dev_err(dev, "Failed to allocate IOMMU group\n");
 849                 return PTR_ERR(group);
 850         }
 851
 852         ret = iommu_group_add_device(group, dev);
 853         iommu_group_put(group);
 854
 855         if (ret < 0) {
 856                 dev_err(dev, "Failed to add device to IPMMU group\n");
 857                 return ret;
 858         }
 859
 860         /*
 861          * Create the ARM mapping, used by the ARM DMA mapping core to allocate
 862          * VAs. This will allocate a corresponding IOMMU domain.
 863          *
 864          * TODO:
 865          * - Create one mapping per context (TLB).
 866          * - Make the mapping size configurable ? We currently use a 2GB mapping
 867          *   at a 1GB offset to ensure that NULL VAs will fault.
 868          */
 869         if (!mmu->mapping) {
 870                 struct dma_iommu_mapping *mapping;
 871
 872                 mapping = arm_iommu_create_mapping(&platform_bus_type,
 873                                                    SZ_1G, SZ_2G);
 874                 if (IS_ERR(mapping)) {
 875                         dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
 876                         ret = PTR_ERR(mapping);
 877                         goto error;
 878                 }
 879
 880                 mmu->mapping = mapping;
 881         }
 882
 883         /* Attach the ARM VA mapping to the device. */
 884         ret = arm_iommu_attach_device(dev, mmu->mapping);
 885         if (ret < 0) {
 886                 dev_err(dev, "Failed to attach device to VA mapping\n");
 887                 goto error;
 888         }
 889
 890         return 0;
 891
 892 error:
 893         iommu_group_remove_device(dev);
 894         if (mmu->mapping)
 895                 arm_iommu_release_mapping(mmu->mapping);
 896
 897         return ret;
 898 }
 899
 900 static int ipmmu_add_device(struct device *dev)
 901 {
 902         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 903         struct iommu_group *group;
 904         int ret;
 905
 906         /*
 907          * Only let through devices that have been verified in xlate()
 908          */
 909         if (!mmu)
 910                 return -ENODEV;
 911
 912         if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)) {
 913                 ret = ipmmu_init_arm_mapping(dev);
 914                 if (ret)
 915                         return ret;
 916         } else {
 917                 group = iommu_group_get_for_dev(dev);
 918                 if (IS_ERR(group))
 919                         return PTR_ERR(group);
 920
 921                 iommu_group_put(group);
 922         }
 923
 924         iommu_device_link(&mmu->iommu, dev);
 925         return 0;
 926 }
 927
 928 static void ipmmu_remove_device(struct device *dev)
 929 {
 930         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 931
 932         iommu_device_unlink(&mmu->iommu, dev);
 933         arm_iommu_detach_device(dev);
 934         iommu_group_remove_device(dev);
 935 }
 936
 937 static struct iommu_group *ipmmu_find_group(struct device *dev)
 938 {
 939         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 940         struct iommu_group *group;
 941
 942         if (mmu->group)
 943                 return iommu_group_ref_get(mmu->group);
 944
 945         group = iommu_group_alloc();
 946         if (!IS_ERR(group))
 947                 mmu->group = group;
 948
 949         return group;
 950 }
 951
 952 static const struct iommu_ops ipmmu_ops = {
 953         .domain_alloc = ipmmu_domain_alloc,
 954         .domain_free = ipmmu_domain_free,
 955         .attach_dev = ipmmu_attach_device,
 956         .detach_dev = ipmmu_detach_device,
 957         .map = ipmmu_map,
 958         .unmap = ipmmu_unmap,
 959         .flush_iotlb_all = ipmmu_iotlb_sync,
 960         .iotlb_sync = ipmmu_iotlb_sync,
 961         .iova_to_phys = ipmmu_iova_to_phys,
 962         .add_device = ipmmu_add_device,
 963         .remove_device = ipmmu_remove_device,
 964         .device_group = ipmmu_find_group,
 965         .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
 966         .of_xlate = ipmmu_of_xlate,
 967 };
 968
 969 /* -----------------------------------------------------------------------------
 970  * Probe/remove and init
 971  */
 972
 973 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
 974 {
 975         unsigned int i;
 976
 977         /* Disable all contexts. */
 978         for (i = 0; i < mmu->num_ctx; ++i)
 979                 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
 980 }
 981
 982 static const struct ipmmu_features ipmmu_features_default = {
 983         .use_ns_alias_offset = true,
 984         .has_cache_leaf_nodes = false,
 985         .number_of_contexts = 1, /* software only tested with one context */
 986         .num_utlbs = 32,
 987         .setup_imbuscr = true,
 988         .twobit_imttbcr_sl0 = false,
 989         .reserved_context = false,
 990 };
 991
 992 static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
 993         .use_ns_alias_offset = false,
 994         .has_cache_leaf_nodes = true,
 995         .number_of_contexts = 8,
 996         .num_utlbs = 48,
 997         .setup_imbuscr = false,
 998         .twobit_imttbcr_sl0 = true,
 999         .reserved_context = true,
1000 };
1001
1002 static const struct of_device_id ipmmu_of_ids[] = {
1003         {
1004                 .compatible = "renesas,ipmmu-vmsa",
1005                 .data = &ipmmu_features_default,
1006         }, {
1007                 .compatible = "renesas,ipmmu-r8a774a1",
1008                 .data = &ipmmu_features_rcar_gen3,
1009         }, {
1010                 .compatible = "renesas,ipmmu-r8a774c0",
1011                 .data = &ipmmu_features_rcar_gen3,
1012         }, {
1013                 .compatible = "renesas,ipmmu-r8a7795",
1014                 .data = &ipmmu_features_rcar_gen3,
1015         }, {
1016                 .compatible = "renesas,ipmmu-r8a7796",
1017                 .data = &ipmmu_features_rcar_gen3,
1018         }, {
1019                 .compatible = "renesas,ipmmu-r8a77965",
1020                 .data = &ipmmu_features_rcar_gen3,
1021         }, {
1022                 .compatible = "renesas,ipmmu-r8a77970",
1023                 .data = &ipmmu_features_rcar_gen3,
1024         }, {
1025                 .compatible = "renesas,ipmmu-r8a77990",
1026                 .data = &ipmmu_features_rcar_gen3,
1027         }, {
1028                 .compatible = "renesas,ipmmu-r8a77995",
1029                 .data = &ipmmu_features_rcar_gen3,
1030         }, {
1031                 /* Terminator */
1032         },
1033 };
1034
1035 static int ipmmu_probe(struct platform_device *pdev)
1036 {
1037         struct ipmmu_vmsa_device *mmu;
1038         struct resource *res;
1039         int irq;
1040         int ret;
1041
1042         mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
1043         if (!mmu) {
1044                 dev_err(&pdev->dev, "cannot allocate device data\n");
1045                 return -ENOMEM;
1046         }
1047
1048         mmu->dev = &pdev->dev;
1049         spin_lock_init(&mmu->lock);
1050         bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
1051         mmu->features = of_device_get_match_data(&pdev->dev);
1052         memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs);
1053         dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
1054
1055         /* Map I/O memory and request IRQ. */
1056         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1057         mmu->base = devm_ioremap_resource(&pdev->dev, res);
1058         if (IS_ERR(mmu->base))
1059                 return PTR_ERR(mmu->base);
1060
1061         /*
1062          * The IPMMU has two register banks, for secure and non-secure modes.
1063          * The bank mapped at the beginning of the IPMMU address space
1064          * corresponds to the running mode of the CPU. When running in secure
1065          * mode the non-secure register bank is also available at an offset.
1066          *
1067          * Secure mode operation isn't clearly documented and is thus currently
1068          * not implemented in the driver. Furthermore, preliminary tests of
1069          * non-secure operation with the main register bank were not successful.
1070          * Offset the registers base unconditionally to point to the non-secure
1071          * alias space for now.
1072          */
1073         if (mmu->features->use_ns_alias_offset)
1074                 mmu->base += IM_NS_ALIAS_OFFSET;
1075
1076         mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts);
1077
1078         irq = platform_get_irq(pdev, 0);
1079
1080         /*
1081          * Determine if this IPMMU instance is a root device by checking for
1082          * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
1083          */
1084         if (!mmu->features->has_cache_leaf_nodes ||
1085             !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL))
1086                 mmu->root = mmu;
1087         else
1088                 mmu->root = ipmmu_find_root();
1089
1090         /*
1091          * Wait until the root device has been registered for sure.
1092          */
1093         if (!mmu->root)
1094                 return -EPROBE_DEFER;
1095
1096         /* Root devices have mandatory IRQs */
1097         if (ipmmu_is_root(mmu)) {
1098                 if (irq < 0) {
1099                         dev_err(&pdev->dev, "no IRQ found\n");
1100                         return irq;
1101                 }
1102
1103                 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
1104                                        dev_name(&pdev->dev), mmu);
1105                 if (ret < 0) {
1106                         dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
1107                         return ret;
1108                 }
1109
1110                 ipmmu_device_reset(mmu);
1111
1112                 if (mmu->features->reserved_context) {
1113                         dev_info(&pdev->dev, "IPMMU context 0 is reserved\n");
1114                         set_bit(0, mmu->ctx);
1115                 }
1116         }
1117
1118         /*
1119          * Register the IPMMU to the IOMMU subsystem in the following cases:
1120          * - R-Car Gen2 IPMMU (all devices registered)
1121          * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device)
1122          */
1123         if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) {
1124                 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
1125                                              dev_name(&pdev->dev));
1126                 if (ret)
1127                         return ret;
1128
1129                 iommu_device_set_ops(&mmu->iommu, &ipmmu_ops);
1130                 iommu_device_set_fwnode(&mmu->iommu,
1131                                         &pdev->dev.of_node->fwnode);
1132
1133                 ret = iommu_device_register(&mmu->iommu);
1134                 if (ret)
1135                         return ret;
1136
1137 #if defined(CONFIG_IOMMU_DMA)
1138                 if (!iommu_present(&platform_bus_type))
1139                         bus_set_iommu(&platform_bus_type, &ipmmu_ops);
1140 #endif
1141         }
1142
1143         /*
1144          * We can't create the ARM mapping here as it requires the bus to have
1145          * an IOMMU, which only happens when bus_set_iommu() is called in
1146          * ipmmu_init() after the probe function returns.
1147          */
1148
1149         platform_set_drvdata(pdev, mmu);
1150
1151         return 0;
1152 }
1153
1154 static int ipmmu_remove(struct platform_device *pdev)
1155 {
1156         struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
1157
1158         iommu_device_sysfs_remove(&mmu->iommu);
1159         iommu_device_unregister(&mmu->iommu);
1160
1161         arm_iommu_release_mapping(mmu->mapping);
1162
1163         ipmmu_device_reset(mmu);
1164
1165         return 0;
1166 }
1167
1168 #ifdef CONFIG_PM_SLEEP
1169 static int ipmmu_resume_noirq(struct device *dev)
1170 {
1171         struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
1172         unsigned int i;
1173
1174         /* Reset root MMU and restore contexts */
1175         if (ipmmu_is_root(mmu)) {
1176                 ipmmu_device_reset(mmu);
1177
1178                 for (i = 0; i < mmu->num_ctx; i++) {
1179                         if (!mmu->domains[i])
1180                                 continue;
1181
1182                         ipmmu_domain_setup_context(mmu->domains[i]);
1183                 }
1184         }
1185
1186         /* Re-enable active micro-TLBs */
1187         for (i = 0; i < mmu->features->num_utlbs; i++) {
1188                 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID)
1189                         continue;
1190
1191                 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i);
1192         }
1193
1194         return 0;
1195 }
1196
1197 static const struct dev_pm_ops ipmmu_pm  = {
1198         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq)
1199 };
1200 #define DEV_PM_OPS      &ipmmu_pm
1201 #else
1202 #define DEV_PM_OPS      NULL
1203 #endif /* CONFIG_PM_SLEEP */
1204
1205 static struct platform_driver ipmmu_driver = {
1206         .driver = {
1207                 .name = "ipmmu-vmsa",
1208                 .of_match_table = of_match_ptr(ipmmu_of_ids),
1209                 .pm = DEV_PM_OPS,
1210         },
1211         .probe = ipmmu_probe,
1212         .remove = ipmmu_remove,
1213 };
1214
1215 static int __init ipmmu_init(void)
1216 {
1217         struct device_node *np;
1218         static bool setup_done;
1219         int ret;
1220
1221         if (setup_done)
1222                 return 0;
1223
1224         np = of_find_matching_node(NULL, ipmmu_of_ids);
1225         if (!np)
1226                 return 0;
1227
1228         of_node_put(np);
1229
1230         ret = platform_driver_register(&ipmmu_driver);
1231         if (ret < 0)
1232                 return ret;
1233
1234 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
1235         if (!iommu_present(&platform_bus_type))
1236                 bus_set_iommu(&platform_bus_type, &ipmmu_ops);
1237 #endif
1238
1239         setup_done = true;
1240         return 0;
1241 }
1242 subsys_initcall(ipmmu_init);