1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap iommu: tlb and pagetable primitives
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
8 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
9 * Paul Mundt and Toshihiro Kobayashi
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/slab.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/platform_device.h>
18 #include <linux/iommu.h>
19 #include <linux/omap-iommu.h>
20 #include <linux/mutex.h>
21 #include <linux/spinlock.h>
23 #include <linux/pm_runtime.h>
25 #include <linux/of_iommu.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_platform.h>
28 #include <linux/regmap.h>
29 #include <linux/mfd/syscon.h>
31 #include <linux/platform_data/iommu-omap.h>
33 #include "omap-iopgtable.h"
34 #include "omap-iommu.h"
36 static const struct iommu_ops omap_iommu_ops;
38 #define to_iommu(dev) ((struct omap_iommu *)dev_get_drvdata(dev))
40 /* bitmap of the page sizes currently supported */
41 #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
43 #define MMU_LOCK_BASE_SHIFT 10
44 #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
45 #define MMU_LOCK_BASE(x) \
46 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
48 #define MMU_LOCK_VICT_SHIFT 4
49 #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
50 #define MMU_LOCK_VICT(x) \
51 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
53 static struct platform_driver omap_iommu_driver;
54 static struct kmem_cache *iopte_cachep;
57 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain
58 * @dom: generic iommu domain handle
60 static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom)
62 return container_of(dom, struct omap_iommu_domain, domain);
66 * omap_iommu_save_ctx - Save registers for pm off-mode support
69 void omap_iommu_save_ctx(struct device *dev)
71 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
72 struct omap_iommu *obj;
79 while (arch_data->iommu_dev) {
80 obj = arch_data->iommu_dev;
82 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
83 p[i] = iommu_read_reg(obj, i * sizeof(u32));
84 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i,
90 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
93 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
96 void omap_iommu_restore_ctx(struct device *dev)
98 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
99 struct omap_iommu *obj;
106 while (arch_data->iommu_dev) {
107 obj = arch_data->iommu_dev;
109 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
110 iommu_write_reg(obj, p[i], i * sizeof(u32));
111 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i,
117 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
119 static void dra7_cfg_dspsys_mmu(struct omap_iommu *obj, bool enable)
126 mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT));
127 val = enable ? mask : 0;
128 regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val);
131 static void __iommu_set_twl(struct omap_iommu *obj, bool on)
133 u32 l = iommu_read_reg(obj, MMU_CNTL);
136 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
138 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
142 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
144 l |= (MMU_CNTL_MMU_EN);
146 iommu_write_reg(obj, l, MMU_CNTL);
149 static int omap2_iommu_enable(struct omap_iommu *obj)
153 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
156 pa = virt_to_phys(obj->iopgd);
157 if (!IS_ALIGNED(pa, SZ_16K))
160 l = iommu_read_reg(obj, MMU_REVISION);
161 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
162 (l >> 4) & 0xf, l & 0xf);
164 iommu_write_reg(obj, pa, MMU_TTB);
166 dra7_cfg_dspsys_mmu(obj, true);
168 if (obj->has_bus_err_back)
169 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
171 __iommu_set_twl(obj, true);
176 static void omap2_iommu_disable(struct omap_iommu *obj)
178 u32 l = iommu_read_reg(obj, MMU_CNTL);
181 iommu_write_reg(obj, l, MMU_CNTL);
182 dra7_cfg_dspsys_mmu(obj, false);
184 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
187 static int iommu_enable(struct omap_iommu *obj)
190 struct platform_device *pdev = to_platform_device(obj->dev);
191 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
193 if (pdata && pdata->deassert_reset) {
194 err = pdata->deassert_reset(pdev, pdata->reset_name);
196 dev_err(obj->dev, "deassert_reset failed: %d\n", err);
201 pm_runtime_get_sync(obj->dev);
203 err = omap2_iommu_enable(obj);
208 static void iommu_disable(struct omap_iommu *obj)
210 struct platform_device *pdev = to_platform_device(obj->dev);
211 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
213 omap2_iommu_disable(obj);
215 pm_runtime_put_sync(obj->dev);
217 if (pdata && pdata->assert_reset)
218 pdata->assert_reset(pdev, pdata->reset_name);
224 static u32 iotlb_cr_to_virt(struct cr_regs *cr)
226 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
227 u32 mask = get_cam_va_mask(cr->cam & page_size);
229 return cr->cam & mask;
232 static u32 get_iopte_attr(struct iotlb_entry *e)
236 attr = e->mixed << 5;
238 attr |= e->elsz >> 3;
239 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
240 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
244 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
246 u32 status, fault_addr;
248 status = iommu_read_reg(obj, MMU_IRQSTATUS);
249 status &= MMU_IRQ_MASK;
255 fault_addr = iommu_read_reg(obj, MMU_FAULT_AD);
258 iommu_write_reg(obj, status, MMU_IRQSTATUS);
263 void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
267 val = iommu_read_reg(obj, MMU_LOCK);
269 l->base = MMU_LOCK_BASE(val);
270 l->vict = MMU_LOCK_VICT(val);
273 void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
277 val = (l->base << MMU_LOCK_BASE_SHIFT);
278 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
280 iommu_write_reg(obj, val, MMU_LOCK);
283 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
285 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
286 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
289 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
291 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
292 iommu_write_reg(obj, cr->ram, MMU_RAM);
294 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
295 iommu_write_reg(obj, 1, MMU_LD_TLB);
298 /* only used in iotlb iteration for-loop */
299 struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
304 iotlb_lock_get(obj, &l);
306 iotlb_lock_set(obj, &l);
307 iotlb_read_cr(obj, &cr);
312 #ifdef PREFETCH_IOTLB
313 static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
314 struct iotlb_entry *e)
321 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
322 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
324 return ERR_PTR(-EINVAL);
327 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
329 return ERR_PTR(-ENOMEM);
331 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
332 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
338 * load_iotlb_entry - Set an iommu tlb entry
340 * @e: an iommu tlb entry info
342 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
348 if (!obj || !obj->nr_tlb_entries || !e)
351 pm_runtime_get_sync(obj->dev);
353 iotlb_lock_get(obj, &l);
354 if (l.base == obj->nr_tlb_entries) {
355 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
363 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
364 if (!iotlb_cr_valid(&tmp))
367 if (i == obj->nr_tlb_entries) {
368 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
373 iotlb_lock_get(obj, &l);
376 iotlb_lock_set(obj, &l);
379 cr = iotlb_alloc_cr(obj, e);
381 pm_runtime_put_sync(obj->dev);
385 iotlb_load_cr(obj, cr);
390 /* increment victim for next tlb load */
391 if (++l.vict == obj->nr_tlb_entries)
393 iotlb_lock_set(obj, &l);
395 pm_runtime_put_sync(obj->dev);
399 #else /* !PREFETCH_IOTLB */
401 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
406 #endif /* !PREFETCH_IOTLB */
408 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
410 return load_iotlb_entry(obj, e);
414 * flush_iotlb_page - Clear an iommu tlb entry
416 * @da: iommu device virtual address
418 * Clear an iommu tlb entry which includes 'da' address.
420 static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
425 pm_runtime_get_sync(obj->dev);
427 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
431 if (!iotlb_cr_valid(&cr))
434 start = iotlb_cr_to_virt(&cr);
435 bytes = iopgsz_to_bytes(cr.cam & 3);
437 if ((start <= da) && (da < start + bytes)) {
438 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
439 __func__, start, da, bytes);
440 iotlb_load_cr(obj, &cr);
441 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
445 pm_runtime_put_sync(obj->dev);
447 if (i == obj->nr_tlb_entries)
448 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
452 * flush_iotlb_all - Clear all iommu tlb entries
455 static void flush_iotlb_all(struct omap_iommu *obj)
459 pm_runtime_get_sync(obj->dev);
463 iotlb_lock_set(obj, &l);
465 iommu_write_reg(obj, 1, MMU_GFLUSH);
467 pm_runtime_put_sync(obj->dev);
471 * H/W pagetable operations
473 static void flush_iopte_range(struct device *dev, dma_addr_t dma,
474 unsigned long offset, int num_entries)
476 size_t size = num_entries * sizeof(u32);
478 dma_sync_single_range_for_device(dev, dma, offset, size, DMA_TO_DEVICE);
481 static void iopte_free(struct omap_iommu *obj, u32 *iopte, bool dma_valid)
485 /* Note: freed iopte's must be clean ready for re-use */
488 pt_dma = virt_to_phys(iopte);
489 dma_unmap_single(obj->dev, pt_dma, IOPTE_TABLE_SIZE,
493 kmem_cache_free(iopte_cachep, iopte);
497 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd,
498 dma_addr_t *pt_dma, u32 da)
501 unsigned long offset = iopgd_index(da) * sizeof(da);
503 /* a table has already existed */
508 * do the allocation outside the page table lock
510 spin_unlock(&obj->page_table_lock);
511 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
512 spin_lock(&obj->page_table_lock);
516 return ERR_PTR(-ENOMEM);
518 *pt_dma = dma_map_single(obj->dev, iopte, IOPTE_TABLE_SIZE,
520 if (dma_mapping_error(obj->dev, *pt_dma)) {
521 dev_err(obj->dev, "DMA map error for L2 table\n");
522 iopte_free(obj, iopte, false);
523 return ERR_PTR(-ENOMEM);
527 * we rely on dma address and the physical address to be
528 * the same for mapping the L2 table
530 if (WARN_ON(*pt_dma != virt_to_phys(iopte))) {
531 dev_err(obj->dev, "DMA translation error for L2 table\n");
532 dma_unmap_single(obj->dev, *pt_dma, IOPTE_TABLE_SIZE,
534 iopte_free(obj, iopte, false);
535 return ERR_PTR(-ENOMEM);
538 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
540 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
541 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
543 /* We raced, free the reduniovant table */
544 iopte_free(obj, iopte, false);
548 iopte = iopte_offset(iopgd, da);
549 *pt_dma = iopgd_page_paddr(iopgd);
551 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
552 __func__, da, iopgd, *iopgd, iopte, *iopte);
557 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
559 u32 *iopgd = iopgd_offset(obj, da);
560 unsigned long offset = iopgd_index(da) * sizeof(da);
562 if ((da | pa) & ~IOSECTION_MASK) {
563 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
564 __func__, da, pa, IOSECTION_SIZE);
568 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
569 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
573 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
575 u32 *iopgd = iopgd_offset(obj, da);
576 unsigned long offset = iopgd_index(da) * sizeof(da);
579 if ((da | pa) & ~IOSUPER_MASK) {
580 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
581 __func__, da, pa, IOSUPER_SIZE);
585 for (i = 0; i < 16; i++)
586 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
587 flush_iopte_range(obj->dev, obj->pd_dma, offset, 16);
591 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
593 u32 *iopgd = iopgd_offset(obj, da);
595 u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da);
596 unsigned long offset = iopte_index(da) * sizeof(da);
599 return PTR_ERR(iopte);
601 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
602 flush_iopte_range(obj->dev, pt_dma, offset, 1);
604 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
605 __func__, da, pa, iopte, *iopte);
610 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
612 u32 *iopgd = iopgd_offset(obj, da);
614 u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da);
615 unsigned long offset = iopte_index(da) * sizeof(da);
618 if ((da | pa) & ~IOLARGE_MASK) {
619 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
620 __func__, da, pa, IOLARGE_SIZE);
625 return PTR_ERR(iopte);
627 for (i = 0; i < 16; i++)
628 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
629 flush_iopte_range(obj->dev, pt_dma, offset, 16);
634 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
636 int (*fn)(struct omap_iommu *, u32, u32, u32);
644 case MMU_CAM_PGSZ_16M:
645 fn = iopgd_alloc_super;
647 case MMU_CAM_PGSZ_1M:
648 fn = iopgd_alloc_section;
650 case MMU_CAM_PGSZ_64K:
651 fn = iopte_alloc_large;
653 case MMU_CAM_PGSZ_4K:
654 fn = iopte_alloc_page;
664 prot = get_iopte_attr(e);
666 spin_lock(&obj->page_table_lock);
667 err = fn(obj, e->da, e->pa, prot);
668 spin_unlock(&obj->page_table_lock);
674 * omap_iopgtable_store_entry - Make an iommu pte entry
676 * @e: an iommu tlb entry info
679 omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
683 flush_iotlb_page(obj, e->da);
684 err = iopgtable_store_entry_core(obj, e);
686 prefetch_iotlb_entry(obj, e);
691 * iopgtable_lookup_entry - Lookup an iommu pte entry
693 * @da: iommu device virtual address
694 * @ppgd: iommu pgd entry pointer to be returned
695 * @ppte: iommu pte entry pointer to be returned
698 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
700 u32 *iopgd, *iopte = NULL;
702 iopgd = iopgd_offset(obj, da);
706 if (iopgd_is_table(*iopgd))
707 iopte = iopte_offset(iopgd, da);
713 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
716 u32 *iopgd = iopgd_offset(obj, da);
719 unsigned long pd_offset = iopgd_index(da) * sizeof(da);
720 unsigned long pt_offset = iopte_index(da) * sizeof(da);
725 if (iopgd_is_table(*iopgd)) {
727 u32 *iopte = iopte_offset(iopgd, da);
730 if (*iopte & IOPTE_LARGE) {
732 /* rewind to the 1st entry */
733 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
736 memset(iopte, 0, nent * sizeof(*iopte));
737 pt_dma = iopgd_page_paddr(iopgd);
738 flush_iopte_range(obj->dev, pt_dma, pt_offset, nent);
741 * do table walk to check if this table is necessary or not
743 iopte = iopte_offset(iopgd, 0);
744 for (i = 0; i < PTRS_PER_IOPTE; i++)
748 iopte_free(obj, iopte, true);
749 nent = 1; /* for the next L1 entry */
752 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
754 /* rewind to the 1st entry */
755 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
759 memset(iopgd, 0, nent * sizeof(*iopgd));
760 flush_iopte_range(obj->dev, obj->pd_dma, pd_offset, nent);
766 * iopgtable_clear_entry - Remove an iommu pte entry
768 * @da: iommu device virtual address
770 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
774 spin_lock(&obj->page_table_lock);
776 bytes = iopgtable_clear_entry_core(obj, da);
777 flush_iotlb_page(obj, da);
779 spin_unlock(&obj->page_table_lock);
784 static void iopgtable_clear_entry_all(struct omap_iommu *obj)
786 unsigned long offset;
789 spin_lock(&obj->page_table_lock);
791 for (i = 0; i < PTRS_PER_IOPGD; i++) {
795 da = i << IOPGD_SHIFT;
796 iopgd = iopgd_offset(obj, da);
797 offset = iopgd_index(da) * sizeof(da);
802 if (iopgd_is_table(*iopgd))
803 iopte_free(obj, iopte_offset(iopgd, 0), true);
806 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
809 flush_iotlb_all(obj);
811 spin_unlock(&obj->page_table_lock);
815 * Device IOMMU generic operations
817 static irqreturn_t iommu_fault_handler(int irq, void *data)
821 struct omap_iommu *obj = data;
822 struct iommu_domain *domain = obj->domain;
823 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
825 if (!omap_domain->dev)
828 errs = iommu_report_fault(obj, &da);
832 /* Fault callback or TLB/PTE Dynamic loading */
833 if (!report_iommu_fault(domain, obj->dev, da, 0))
836 iommu_write_reg(obj, 0, MMU_IRQENABLE);
838 iopgd = iopgd_offset(obj, da);
840 if (!iopgd_is_table(*iopgd)) {
841 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
842 obj->name, errs, da, iopgd, *iopgd);
846 iopte = iopte_offset(iopgd, da);
848 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
849 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
855 * omap_iommu_attach() - attach iommu device to an iommu domain
856 * @obj: target omap iommu device
859 static int omap_iommu_attach(struct omap_iommu *obj, u32 *iopgd)
863 spin_lock(&obj->iommu_lock);
865 obj->pd_dma = dma_map_single(obj->dev, iopgd, IOPGD_TABLE_SIZE,
867 if (dma_mapping_error(obj->dev, obj->pd_dma)) {
868 dev_err(obj->dev, "DMA map error for L1 table\n");
874 err = iommu_enable(obj);
877 flush_iotlb_all(obj);
879 spin_unlock(&obj->iommu_lock);
881 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
886 spin_unlock(&obj->iommu_lock);
892 * omap_iommu_detach - release iommu device
895 static void omap_iommu_detach(struct omap_iommu *obj)
897 if (!obj || IS_ERR(obj))
900 spin_lock(&obj->iommu_lock);
902 dma_unmap_single(obj->dev, obj->pd_dma, IOPGD_TABLE_SIZE,
908 spin_unlock(&obj->iommu_lock);
910 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
913 static bool omap_iommu_can_register(struct platform_device *pdev)
915 struct device_node *np = pdev->dev.of_node;
917 if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
921 * restrict IOMMU core registration only for processor-port MDMA MMUs
924 if ((!strcmp(dev_name(&pdev->dev), "40d01000.mmu")) ||
925 (!strcmp(dev_name(&pdev->dev), "41501000.mmu")))
931 static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev,
932 struct omap_iommu *obj)
934 struct device_node *np = pdev->dev.of_node;
937 if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
940 if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) {
941 dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n");
946 syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig");
947 if (IS_ERR(obj->syscfg)) {
948 /* can fail with -EPROBE_DEFER */
949 ret = PTR_ERR(obj->syscfg);
953 if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1,
955 dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n");
959 if (obj->id != 0 && obj->id != 1) {
960 dev_err(&pdev->dev, "invalid IOMMU instance id\n");
968 * OMAP Device MMU(IOMMU) detection
970 static int omap_iommu_probe(struct platform_device *pdev)
974 struct omap_iommu *obj;
975 struct resource *res;
976 struct device_node *of = pdev->dev.of_node;
979 pr_err("%s: only DT-based devices are supported\n", __func__);
983 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
987 obj->name = dev_name(&pdev->dev);
988 obj->nr_tlb_entries = 32;
989 err = of_property_read_u32(of, "ti,#tlb-entries", &obj->nr_tlb_entries);
990 if (err && err != -EINVAL)
992 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
994 if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
995 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
997 obj->dev = &pdev->dev;
998 obj->ctx = (void *)obj + sizeof(*obj);
1000 spin_lock_init(&obj->iommu_lock);
1001 spin_lock_init(&obj->page_table_lock);
1003 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004 obj->regbase = devm_ioremap_resource(obj->dev, res);
1005 if (IS_ERR(obj->regbase))
1006 return PTR_ERR(obj->regbase);
1008 err = omap_iommu_dra7_get_dsp_system_cfg(pdev, obj);
1012 irq = platform_get_irq(pdev, 0);
1016 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
1017 dev_name(obj->dev), obj);
1020 platform_set_drvdata(pdev, obj);
1022 if (omap_iommu_can_register(pdev)) {
1023 obj->group = iommu_group_alloc();
1024 if (IS_ERR(obj->group))
1025 return PTR_ERR(obj->group);
1027 err = iommu_device_sysfs_add(&obj->iommu, obj->dev, NULL,
1032 iommu_device_set_ops(&obj->iommu, &omap_iommu_ops);
1034 err = iommu_device_register(&obj->iommu);
1039 pm_runtime_irq_safe(obj->dev);
1040 pm_runtime_enable(obj->dev);
1042 omap_iommu_debugfs_add(obj);
1044 dev_info(&pdev->dev, "%s registered\n", obj->name);
1049 iommu_device_sysfs_remove(&obj->iommu);
1051 iommu_group_put(obj->group);
1055 static int omap_iommu_remove(struct platform_device *pdev)
1057 struct omap_iommu *obj = platform_get_drvdata(pdev);
1060 iommu_group_put(obj->group);
1063 iommu_device_sysfs_remove(&obj->iommu);
1064 iommu_device_unregister(&obj->iommu);
1067 omap_iommu_debugfs_remove(obj);
1069 pm_runtime_disable(obj->dev);
1071 dev_info(&pdev->dev, "%s removed\n", obj->name);
1075 static const struct of_device_id omap_iommu_of_match[] = {
1076 { .compatible = "ti,omap2-iommu" },
1077 { .compatible = "ti,omap4-iommu" },
1078 { .compatible = "ti,dra7-iommu" },
1079 { .compatible = "ti,dra7-dsp-iommu" },
1083 static struct platform_driver omap_iommu_driver = {
1084 .probe = omap_iommu_probe,
1085 .remove = omap_iommu_remove,
1087 .name = "omap-iommu",
1088 .of_match_table = of_match_ptr(omap_iommu_of_match),
1092 static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz)
1094 memset(e, 0, sizeof(*e));
1098 e->valid = MMU_CAM_V;
1100 e->endian = MMU_RAM_ENDIAN_LITTLE;
1101 e->elsz = MMU_RAM_ELSZ_8;
1104 return iopgsz_to_bytes(e->pgsz);
1107 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1108 phys_addr_t pa, size_t bytes, int prot)
1110 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1111 struct device *dev = omap_domain->dev;
1112 struct omap_iommu_device *iommu;
1113 struct omap_iommu *oiommu;
1114 struct iotlb_entry e;
1119 omap_pgsz = bytes_to_iopgsz(bytes);
1120 if (omap_pgsz < 0) {
1121 dev_err(dev, "invalid size to map: %d\n", bytes);
1125 dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes);
1127 iotlb_init_entry(&e, da, pa, omap_pgsz);
1129 iommu = omap_domain->iommus;
1130 for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1131 oiommu = iommu->iommu_dev;
1132 ret = omap_iopgtable_store_entry(oiommu, &e);
1134 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n",
1143 oiommu = iommu->iommu_dev;
1144 iopgtable_clear_entry(oiommu, da);
1151 static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1154 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1155 struct device *dev = omap_domain->dev;
1156 struct omap_iommu_device *iommu;
1157 struct omap_iommu *oiommu;
1162 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1164 iommu = omap_domain->iommus;
1165 for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1166 oiommu = iommu->iommu_dev;
1167 bytes = iopgtable_clear_entry(oiommu, da);
1173 * simplify return - we are only checking if any of the iommus
1174 * reported an error, but not if all of them are unmapping the
1175 * same number of entries. This should not occur due to the
1176 * mirror programming.
1178 return error ? 0 : bytes;
1181 static int omap_iommu_count(struct device *dev)
1183 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1186 while (arch_data->iommu_dev) {
1194 /* caller should call cleanup if this function fails */
1195 static int omap_iommu_attach_init(struct device *dev,
1196 struct omap_iommu_domain *odomain)
1198 struct omap_iommu_device *iommu;
1201 odomain->num_iommus = omap_iommu_count(dev);
1202 if (!odomain->num_iommus)
1205 odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu),
1207 if (!odomain->iommus)
1210 iommu = odomain->iommus;
1211 for (i = 0; i < odomain->num_iommus; i++, iommu++) {
1212 iommu->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_ATOMIC);
1213 if (!iommu->pgtable)
1217 * should never fail, but please keep this around to ensure
1218 * we keep the hardware happy
1220 if (WARN_ON(!IS_ALIGNED((long)iommu->pgtable,
1228 static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain)
1231 struct omap_iommu_device *iommu = odomain->iommus;
1233 for (i = 0; iommu && i < odomain->num_iommus; i++, iommu++)
1234 kfree(iommu->pgtable);
1236 kfree(odomain->iommus);
1237 odomain->num_iommus = 0;
1238 odomain->iommus = NULL;
1242 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1244 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1245 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1246 struct omap_iommu_device *iommu;
1247 struct omap_iommu *oiommu;
1251 if (!arch_data || !arch_data->iommu_dev) {
1252 dev_err(dev, "device doesn't have an associated iommu\n");
1256 spin_lock(&omap_domain->lock);
1258 /* only a single client device can be attached to a domain */
1259 if (omap_domain->dev) {
1260 dev_err(dev, "iommu domain is already attached\n");
1265 ret = omap_iommu_attach_init(dev, omap_domain);
1267 dev_err(dev, "failed to allocate required iommu data %d\n",
1272 iommu = omap_domain->iommus;
1273 for (i = 0; i < omap_domain->num_iommus; i++, iommu++, arch_data++) {
1274 /* configure and enable the omap iommu */
1275 oiommu = arch_data->iommu_dev;
1276 ret = omap_iommu_attach(oiommu, iommu->pgtable);
1278 dev_err(dev, "can't get omap iommu: %d\n", ret);
1282 oiommu->domain = domain;
1283 iommu->iommu_dev = oiommu;
1286 omap_domain->dev = dev;
1294 oiommu = iommu->iommu_dev;
1295 omap_iommu_detach(oiommu);
1296 iommu->iommu_dev = NULL;
1297 oiommu->domain = NULL;
1300 omap_iommu_detach_fini(omap_domain);
1302 spin_unlock(&omap_domain->lock);
1306 static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1309 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1310 struct omap_iommu_device *iommu = omap_domain->iommus;
1311 struct omap_iommu *oiommu;
1314 if (!omap_domain->dev) {
1315 dev_err(dev, "domain has no attached device\n");
1319 /* only a single device is supported per domain for now */
1320 if (omap_domain->dev != dev) {
1321 dev_err(dev, "invalid attached device\n");
1326 * cleanup in the reverse order of attachment - this addresses
1327 * any h/w dependencies between multiple instances, if any
1329 iommu += (omap_domain->num_iommus - 1);
1330 arch_data += (omap_domain->num_iommus - 1);
1331 for (i = 0; i < omap_domain->num_iommus; i++, iommu--, arch_data--) {
1332 oiommu = iommu->iommu_dev;
1333 iopgtable_clear_entry_all(oiommu);
1335 omap_iommu_detach(oiommu);
1336 iommu->iommu_dev = NULL;
1337 oiommu->domain = NULL;
1340 omap_iommu_detach_fini(omap_domain);
1342 omap_domain->dev = NULL;
1345 static void omap_iommu_detach_dev(struct iommu_domain *domain,
1348 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1350 spin_lock(&omap_domain->lock);
1351 _omap_iommu_detach_dev(omap_domain, dev);
1352 spin_unlock(&omap_domain->lock);
1355 static struct iommu_domain *omap_iommu_domain_alloc(unsigned type)
1357 struct omap_iommu_domain *omap_domain;
1359 if (type != IOMMU_DOMAIN_UNMANAGED)
1362 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1366 spin_lock_init(&omap_domain->lock);
1368 omap_domain->domain.geometry.aperture_start = 0;
1369 omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1;
1370 omap_domain->domain.geometry.force_aperture = true;
1372 return &omap_domain->domain;
1375 static void omap_iommu_domain_free(struct iommu_domain *domain)
1377 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1380 * An iommu device is still attached
1381 * (currently, only one device can be attached) ?
1383 if (omap_domain->dev)
1384 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1389 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1392 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1393 struct omap_iommu_device *iommu = omap_domain->iommus;
1394 struct omap_iommu *oiommu = iommu->iommu_dev;
1395 struct device *dev = oiommu->dev;
1397 phys_addr_t ret = 0;
1400 * all the iommus within the domain will have identical programming,
1401 * so perform the lookup using just the first iommu
1403 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1406 if (iopte_is_small(*pte))
1407 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1408 else if (iopte_is_large(*pte))
1409 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1411 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
1412 (unsigned long long)da);
1414 if (iopgd_is_section(*pgd))
1415 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1416 else if (iopgd_is_super(*pgd))
1417 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1419 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
1420 (unsigned long long)da);
1426 static int omap_iommu_add_device(struct device *dev)
1428 struct omap_iommu_arch_data *arch_data, *tmp;
1429 struct omap_iommu *oiommu;
1430 struct iommu_group *group;
1431 struct device_node *np;
1432 struct platform_device *pdev;
1437 * Allocate the archdata iommu structure for DT-based devices.
1439 * TODO: Simplify this when removing non-DT support completely from the
1446 * retrieve the count of IOMMU nodes using phandle size as element size
1447 * since #iommu-cells = 0 for OMAP
1449 num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus",
1454 arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL);
1458 for (i = 0, tmp = arch_data; i < num_iommus; i++, tmp++) {
1459 np = of_parse_phandle(dev->of_node, "iommus", i);
1465 pdev = of_find_device_by_node(np);
1466 if (WARN_ON(!pdev)) {
1472 oiommu = platform_get_drvdata(pdev);
1479 tmp->iommu_dev = oiommu;
1485 * use the first IOMMU alone for the sysfs device linking.
1486 * TODO: Evaluate if a single iommu_group needs to be
1487 * maintained for both IOMMUs
1489 oiommu = arch_data->iommu_dev;
1490 ret = iommu_device_link(&oiommu->iommu, dev);
1496 dev->archdata.iommu = arch_data;
1499 * IOMMU group initialization calls into omap_iommu_device_group, which
1500 * needs a valid dev->archdata.iommu pointer
1502 group = iommu_group_get_for_dev(dev);
1503 if (IS_ERR(group)) {
1504 iommu_device_unlink(&oiommu->iommu, dev);
1505 dev->archdata.iommu = NULL;
1507 return PTR_ERR(group);
1509 iommu_group_put(group);
1514 static void omap_iommu_remove_device(struct device *dev)
1516 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1518 if (!dev->of_node || !arch_data)
1521 iommu_device_unlink(&arch_data->iommu_dev->iommu, dev);
1522 iommu_group_remove_device(dev);
1524 dev->archdata.iommu = NULL;
1529 static struct iommu_group *omap_iommu_device_group(struct device *dev)
1531 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1532 struct iommu_group *group = ERR_PTR(-EINVAL);
1534 if (arch_data->iommu_dev)
1535 group = iommu_group_ref_get(arch_data->iommu_dev->group);
1540 static const struct iommu_ops omap_iommu_ops = {
1541 .domain_alloc = omap_iommu_domain_alloc,
1542 .domain_free = omap_iommu_domain_free,
1543 .attach_dev = omap_iommu_attach_dev,
1544 .detach_dev = omap_iommu_detach_dev,
1545 .map = omap_iommu_map,
1546 .unmap = omap_iommu_unmap,
1547 .iova_to_phys = omap_iommu_iova_to_phys,
1548 .add_device = omap_iommu_add_device,
1549 .remove_device = omap_iommu_remove_device,
1550 .device_group = omap_iommu_device_group,
1551 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
1554 static int __init omap_iommu_init(void)
1556 struct kmem_cache *p;
1557 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1558 size_t align = 1 << 10; /* L2 pagetable alignement */
1559 struct device_node *np;
1562 np = of_find_matching_node(NULL, omap_iommu_of_match);
1568 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1574 omap_iommu_debugfs_init();
1576 ret = platform_driver_register(&omap_iommu_driver);
1578 pr_err("%s: failed to register driver\n", __func__);
1582 ret = bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1589 platform_driver_unregister(&omap_iommu_driver);
1591 kmem_cache_destroy(iopte_cachep);
1594 subsys_initcall(omap_iommu_init);
1595 /* must be ready before omap3isp is probed */